| blob | eb8ffe75ef769797584fffada7fadb7efd57ce4d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64IZFINXZDINX %s
10 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV32I %s
12 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64I %s
15 define float @fcvt_s_d(double %a) nounwind {
16 ; CHECKIFD-LABEL: fcvt_s_d:
17 ; CHECKIFD: # %bb.0:
18 ; CHECKIFD-NEXT: fcvt.s.d fa0, fa0
19 ; CHECKIFD-NEXT: ret
20 ;
21 ; RV32IZFINXZDINX-LABEL: fcvt_s_d:
22 ; RV32IZFINXZDINX: # %bb.0:
23 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
24 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
25 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
26 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
27 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
28 ; RV32IZFINXZDINX-NEXT: fcvt.s.d a0, a0
29 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
30 ; RV32IZFINXZDINX-NEXT: ret
31 ;
32 ; RV64IZFINXZDINX-LABEL: fcvt_s_d:
33 ; RV64IZFINXZDINX: # %bb.0:
34 ; RV64IZFINXZDINX-NEXT: fcvt.s.d a0, a0
35 ; RV64IZFINXZDINX-NEXT: ret
36 ;
37 ; RV32I-LABEL: fcvt_s_d:
38 ; RV32I: # %bb.0:
39 ; RV32I-NEXT: addi sp, sp, -16
40 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
41 ; RV32I-NEXT: call __truncdfsf2
42 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
43 ; RV32I-NEXT: addi sp, sp, 16
44 ; RV32I-NEXT: ret
45 ;
46 ; RV64I-LABEL: fcvt_s_d:
47 ; RV64I: # %bb.0:
48 ; RV64I-NEXT: addi sp, sp, -16
49 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
50 ; RV64I-NEXT: call __truncdfsf2
51 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
52 ; RV64I-NEXT: addi sp, sp, 16
53 ; RV64I-NEXT: ret
54 %1 = fptrunc double %a to float
55 ret float %1
56 }
58 define double @fcvt_d_s(float %a) nounwind {
59 ; CHECKIFD-LABEL: fcvt_d_s:
60 ; CHECKIFD: # %bb.0:
61 ; CHECKIFD-NEXT: fcvt.d.s fa0, fa0
62 ; CHECKIFD-NEXT: ret
63 ;
64 ; RV32IZFINXZDINX-LABEL: fcvt_d_s:
65 ; RV32IZFINXZDINX: # %bb.0:
66 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
67 ; RV32IZFINXZDINX-NEXT: fcvt.d.s a0, a0
68 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
69 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
70 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
71 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
72 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
73 ; RV32IZFINXZDINX-NEXT: ret
74 ;
75 ; RV64IZFINXZDINX-LABEL: fcvt_d_s:
76 ; RV64IZFINXZDINX: # %bb.0:
77 ; RV64IZFINXZDINX-NEXT: fcvt.d.s a0, a0
78 ; RV64IZFINXZDINX-NEXT: ret
79 ;
80 ; RV32I-LABEL: fcvt_d_s:
81 ; RV32I: # %bb.0:
82 ; RV32I-NEXT: addi sp, sp, -16
83 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
84 ; RV32I-NEXT: call __extendsfdf2
85 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
86 ; RV32I-NEXT: addi sp, sp, 16
87 ; RV32I-NEXT: ret
88 ;
89 ; RV64I-LABEL: fcvt_d_s:
90 ; RV64I: # %bb.0:
91 ; RV64I-NEXT: addi sp, sp, -16
92 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
93 ; RV64I-NEXT: call __extendsfdf2
94 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
95 ; RV64I-NEXT: addi sp, sp, 16
96 ; RV64I-NEXT: ret
97 %1 = fpext float %a to double
98 ret double %1
99 }
101 define i32 @fcvt_w_d(double %a) nounwind {
102 ; CHECKIFD-LABEL: fcvt_w_d:
103 ; CHECKIFD: # %bb.0:
104 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
105 ; CHECKIFD-NEXT: ret
106 ;
107 ; RV32IZFINXZDINX-LABEL: fcvt_w_d:
108 ; RV32IZFINXZDINX: # %bb.0:
109 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
110 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
111 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
112 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
113 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
114 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
115 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
116 ; RV32IZFINXZDINX-NEXT: ret
117 ;
118 ; RV64IZFINXZDINX-LABEL: fcvt_w_d:
119 ; RV64IZFINXZDINX: # %bb.0:
120 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
121 ; RV64IZFINXZDINX-NEXT: ret
122 ;
123 ; RV32I-LABEL: fcvt_w_d:
124 ; RV32I: # %bb.0:
125 ; RV32I-NEXT: addi sp, sp, -16
126 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
127 ; RV32I-NEXT: call __fixdfsi
128 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
129 ; RV32I-NEXT: addi sp, sp, 16
130 ; RV32I-NEXT: ret
131 ;
132 ; RV64I-LABEL: fcvt_w_d:
133 ; RV64I: # %bb.0:
134 ; RV64I-NEXT: addi sp, sp, -16
135 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
136 ; RV64I-NEXT: call __fixdfsi
137 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
138 ; RV64I-NEXT: addi sp, sp, 16
139 ; RV64I-NEXT: ret
140 %1 = fptosi double %a to i32
141 ret i32 %1
142 }
144 define i32 @fcvt_w_d_sat(double %a) nounwind {
145 ; CHECKIFD-LABEL: fcvt_w_d_sat:
146 ; CHECKIFD: # %bb.0: # %start
147 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
148 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
149 ; CHECKIFD-NEXT: seqz a1, a1
150 ; CHECKIFD-NEXT: addi a1, a1, -1
151 ; CHECKIFD-NEXT: and a0, a1, a0
152 ; CHECKIFD-NEXT: ret
153 ;
154 ; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat:
155 ; RV32IZFINXZDINX: # %bb.0: # %start
156 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
157 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
158 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
159 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
160 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
161 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
162 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
163 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
164 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
165 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
166 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
167 ; RV32IZFINXZDINX-NEXT: ret
168 ;
169 ; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat:
170 ; RV64IZFINXZDINX: # %bb.0: # %start
171 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a1, a0, rtz
172 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
173 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
174 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
175 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
176 ; RV64IZFINXZDINX-NEXT: ret
177 ;
178 ; RV32I-LABEL: fcvt_w_d_sat:
179 ; RV32I: # %bb.0: # %start
180 ; RV32I-NEXT: addi sp, sp, -32
181 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
182 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
183 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
184 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
185 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
186 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
187 ; RV32I-NEXT: mv s0, a1
188 ; RV32I-NEXT: mv s1, a0
189 ; RV32I-NEXT: lui a3, 269824
190 ; RV32I-NEXT: addi a3, a3, -1
191 ; RV32I-NEXT: lui a2, 1047552
192 ; RV32I-NEXT: call __gtdf2
193 ; RV32I-NEXT: mv s2, a0
194 ; RV32I-NEXT: lui a3, 794112
195 ; RV32I-NEXT: mv a0, s1
196 ; RV32I-NEXT: mv a1, s0
197 ; RV32I-NEXT: li a2, 0
198 ; RV32I-NEXT: call __gedf2
199 ; RV32I-NEXT: mv s4, a0
200 ; RV32I-NEXT: mv a0, s1
201 ; RV32I-NEXT: mv a1, s0
202 ; RV32I-NEXT: call __fixdfsi
203 ; RV32I-NEXT: mv s3, a0
204 ; RV32I-NEXT: lui a0, 524288
205 ; RV32I-NEXT: bgez s4, .LBB3_2
206 ; RV32I-NEXT: # %bb.1: # %start
207 ; RV32I-NEXT: lui s3, 524288
208 ; RV32I-NEXT: .LBB3_2: # %start
209 ; RV32I-NEXT: blez s2, .LBB3_4
210 ; RV32I-NEXT: # %bb.3: # %start
211 ; RV32I-NEXT: addi s3, a0, -1
212 ; RV32I-NEXT: .LBB3_4: # %start
213 ; RV32I-NEXT: mv a0, s1
214 ; RV32I-NEXT: mv a1, s0
215 ; RV32I-NEXT: mv a2, s1
216 ; RV32I-NEXT: mv a3, s0
217 ; RV32I-NEXT: call __unorddf2
218 ; RV32I-NEXT: snez a0, a0
219 ; RV32I-NEXT: addi a0, a0, -1
220 ; RV32I-NEXT: and a0, a0, s3
221 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
222 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
223 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
224 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
225 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
226 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
227 ; RV32I-NEXT: addi sp, sp, 32
228 ; RV32I-NEXT: ret
229 ;
230 ; RV64I-LABEL: fcvt_w_d_sat:
231 ; RV64I: # %bb.0: # %start
232 ; RV64I-NEXT: addi sp, sp, -48
233 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
234 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
235 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
236 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
237 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
238 ; RV64I-NEXT: mv s0, a0
239 ; RV64I-NEXT: li a1, -497
240 ; RV64I-NEXT: slli a1, a1, 53
241 ; RV64I-NEXT: call __gedf2
242 ; RV64I-NEXT: mv s2, a0
243 ; RV64I-NEXT: mv a0, s0
244 ; RV64I-NEXT: call __fixdfdi
245 ; RV64I-NEXT: mv s1, a0
246 ; RV64I-NEXT: lui s3, 524288
247 ; RV64I-NEXT: bgez s2, .LBB3_2
248 ; RV64I-NEXT: # %bb.1: # %start
249 ; RV64I-NEXT: lui s1, 524288
250 ; RV64I-NEXT: .LBB3_2: # %start
251 ; RV64I-NEXT: li a0, 527
252 ; RV64I-NEXT: slli a0, a0, 31
253 ; RV64I-NEXT: addi a0, a0, -1
254 ; RV64I-NEXT: slli a1, a0, 22
255 ; RV64I-NEXT: mv a0, s0
256 ; RV64I-NEXT: call __gtdf2
257 ; RV64I-NEXT: blez a0, .LBB3_4
258 ; RV64I-NEXT: # %bb.3: # %start
259 ; RV64I-NEXT: addiw s1, s3, -1
260 ; RV64I-NEXT: .LBB3_4: # %start
261 ; RV64I-NEXT: mv a0, s0
262 ; RV64I-NEXT: mv a1, s0
263 ; RV64I-NEXT: call __unorddf2
264 ; RV64I-NEXT: snez a0, a0
265 ; RV64I-NEXT: addi a0, a0, -1
266 ; RV64I-NEXT: and a0, a0, s1
267 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
268 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
269 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
270 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
271 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
272 ; RV64I-NEXT: addi sp, sp, 48
273 ; RV64I-NEXT: ret
274 start:
275 %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
276 ret i32 %0
277 }
278 declare i32 @llvm.fptosi.sat.i32.f64(double)
280 ; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
281 ; because fptosi will produce poison if the result doesn't fit into an i32.
282 define i32 @fcvt_wu_d(double %a) nounwind {
283 ; CHECKIFD-LABEL: fcvt_wu_d:
284 ; CHECKIFD: # %bb.0:
285 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
286 ; CHECKIFD-NEXT: ret
287 ;
288 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d:
289 ; RV32IZFINXZDINX: # %bb.0:
290 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
291 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
292 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
293 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
294 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
295 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
296 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
297 ; RV32IZFINXZDINX-NEXT: ret
298 ;
299 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d:
300 ; RV64IZFINXZDINX: # %bb.0:
301 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
302 ; RV64IZFINXZDINX-NEXT: ret
303 ;
304 ; RV32I-LABEL: fcvt_wu_d:
305 ; RV32I: # %bb.0:
306 ; RV32I-NEXT: addi sp, sp, -16
307 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
308 ; RV32I-NEXT: call __fixunsdfsi
309 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
310 ; RV32I-NEXT: addi sp, sp, 16
311 ; RV32I-NEXT: ret
312 ;
313 ; RV64I-LABEL: fcvt_wu_d:
314 ; RV64I: # %bb.0:
315 ; RV64I-NEXT: addi sp, sp, -16
316 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
317 ; RV64I-NEXT: call __fixunsdfsi
318 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
319 ; RV64I-NEXT: addi sp, sp, 16
320 ; RV64I-NEXT: ret
321 %1 = fptoui double %a to i32
322 ret i32 %1
323 }
325 ; Test where the fptoui has multiple uses, one of which causes a sext to be
326 ; inserted on RV64.
327 define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
328 ; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
329 ; CHECKIFD: # %bb.0:
330 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
331 ; CHECKIFD-NEXT: seqz a1, a0
332 ; CHECKIFD-NEXT: add a0, a0, a1
333 ; CHECKIFD-NEXT: ret
334 ;
335 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
336 ; RV32IZFINXZDINX: # %bb.0:
337 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
338 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
339 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
340 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
341 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
342 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
343 ; RV32IZFINXZDINX-NEXT: seqz a1, a0
344 ; RV32IZFINXZDINX-NEXT: add a0, a0, a1
345 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
346 ; RV32IZFINXZDINX-NEXT: ret
347 ;
348 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
349 ; RV64IZFINXZDINX: # %bb.0:
350 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
351 ; RV64IZFINXZDINX-NEXT: seqz a1, a0
352 ; RV64IZFINXZDINX-NEXT: add a0, a0, a1
353 ; RV64IZFINXZDINX-NEXT: ret
354 ;
355 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
356 ; RV32I: # %bb.0:
357 ; RV32I-NEXT: addi sp, sp, -16
358 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
359 ; RV32I-NEXT: call __fixunsdfsi
360 ; RV32I-NEXT: seqz a1, a0
361 ; RV32I-NEXT: add a0, a0, a1
362 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
363 ; RV32I-NEXT: addi sp, sp, 16
364 ; RV32I-NEXT: ret
365 ;
366 ; RV64I-LABEL: fcvt_wu_d_multiple_use:
367 ; RV64I: # %bb.0:
368 ; RV64I-NEXT: addi sp, sp, -16
369 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
370 ; RV64I-NEXT: call __fixunsdfsi
371 ; RV64I-NEXT: seqz a1, a0
372 ; RV64I-NEXT: add a0, a0, a1
373 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
374 ; RV64I-NEXT: addi sp, sp, 16
375 ; RV64I-NEXT: ret
376 %a = fptoui double %x to i32
377 %b = icmp eq i32 %a, 0
378 %c = select i1 %b, i32 1, i32 %a
379 ret i32 %c
380 }
382 define i32 @fcvt_wu_d_sat(double %a) nounwind {
383 ; RV32IFD-LABEL: fcvt_wu_d_sat:
384 ; RV32IFD: # %bb.0: # %start
385 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
386 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
387 ; RV32IFD-NEXT: seqz a1, a1
388 ; RV32IFD-NEXT: addi a1, a1, -1
389 ; RV32IFD-NEXT: and a0, a1, a0
390 ; RV32IFD-NEXT: ret
391 ;
392 ; RV64IFD-LABEL: fcvt_wu_d_sat:
393 ; RV64IFD: # %bb.0: # %start
394 ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
395 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
396 ; RV64IFD-NEXT: seqz a1, a1
397 ; RV64IFD-NEXT: addi a1, a1, -1
398 ; RV64IFD-NEXT: and a0, a0, a1
399 ; RV64IFD-NEXT: slli a0, a0, 32
400 ; RV64IFD-NEXT: srli a0, a0, 32
401 ; RV64IFD-NEXT: ret
402 ;
403 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat:
404 ; RV32IZFINXZDINX: # %bb.0: # %start
405 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
406 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
407 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
408 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
409 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
410 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
411 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
412 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
413 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
414 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
415 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
416 ; RV32IZFINXZDINX-NEXT: ret
417 ;
418 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat:
419 ; RV64IZFINXZDINX: # %bb.0: # %start
420 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
421 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
422 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
423 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
424 ; RV64IZFINXZDINX-NEXT: and a0, a1, a0
425 ; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
426 ; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
427 ; RV64IZFINXZDINX-NEXT: ret
428 ;
429 ; RV32I-LABEL: fcvt_wu_d_sat:
430 ; RV32I: # %bb.0: # %start
431 ; RV32I-NEXT: addi sp, sp, -32
432 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
433 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
434 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
435 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
436 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
437 ; RV32I-NEXT: mv s0, a1
438 ; RV32I-NEXT: mv s1, a0
439 ; RV32I-NEXT: lui a3, 270080
440 ; RV32I-NEXT: addi a3, a3, -1
441 ; RV32I-NEXT: lui a2, 1048064
442 ; RV32I-NEXT: call __gtdf2
443 ; RV32I-NEXT: sgtz a0, a0
444 ; RV32I-NEXT: neg s2, a0
445 ; RV32I-NEXT: mv a0, s1
446 ; RV32I-NEXT: mv a1, s0
447 ; RV32I-NEXT: li a2, 0
448 ; RV32I-NEXT: li a3, 0
449 ; RV32I-NEXT: call __gedf2
450 ; RV32I-NEXT: slti a0, a0, 0
451 ; RV32I-NEXT: addi s3, a0, -1
452 ; RV32I-NEXT: mv a0, s1
453 ; RV32I-NEXT: mv a1, s0
454 ; RV32I-NEXT: call __fixunsdfsi
455 ; RV32I-NEXT: and a0, s3, a0
456 ; RV32I-NEXT: or a0, s2, a0
457 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
458 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
459 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
460 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
461 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
462 ; RV32I-NEXT: addi sp, sp, 32
463 ; RV32I-NEXT: ret
464 ;
465 ; RV64I-LABEL: fcvt_wu_d_sat:
466 ; RV64I: # %bb.0: # %start
467 ; RV64I-NEXT: addi sp, sp, -32
468 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
469 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
470 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
471 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
472 ; RV64I-NEXT: mv s2, a0
473 ; RV64I-NEXT: li a1, 0
474 ; RV64I-NEXT: call __gedf2
475 ; RV64I-NEXT: mv s0, a0
476 ; RV64I-NEXT: mv a0, s2
477 ; RV64I-NEXT: call __fixunsdfdi
478 ; RV64I-NEXT: mv s1, a0
479 ; RV64I-NEXT: li a0, 1055
480 ; RV64I-NEXT: slli a0, a0, 31
481 ; RV64I-NEXT: addi a0, a0, -1
482 ; RV64I-NEXT: slli a1, a0, 21
483 ; RV64I-NEXT: mv a0, s2
484 ; RV64I-NEXT: call __gtdf2
485 ; RV64I-NEXT: blez a0, .LBB6_2
486 ; RV64I-NEXT: # %bb.1: # %start
487 ; RV64I-NEXT: li a0, -1
488 ; RV64I-NEXT: srli a0, a0, 32
489 ; RV64I-NEXT: j .LBB6_3
490 ; RV64I-NEXT: .LBB6_2:
491 ; RV64I-NEXT: slti a0, s0, 0
492 ; RV64I-NEXT: addi a0, a0, -1
493 ; RV64I-NEXT: and a0, a0, s1
494 ; RV64I-NEXT: .LBB6_3: # %start
495 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
496 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
497 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
498 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
499 ; RV64I-NEXT: addi sp, sp, 32
500 ; RV64I-NEXT: ret
501 start:
502 %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
503 ret i32 %0
504 }
505 declare i32 @llvm.fptoui.sat.i32.f64(double)
507 define double @fcvt_d_w(i32 %a) nounwind {
508 ; CHECKIFD-LABEL: fcvt_d_w:
509 ; CHECKIFD: # %bb.0:
510 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
511 ; CHECKIFD-NEXT: ret
512 ;
513 ; RV32IZFINXZDINX-LABEL: fcvt_d_w:
514 ; RV32IZFINXZDINX: # %bb.0:
515 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
516 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
517 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
518 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
519 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
520 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
521 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
522 ; RV32IZFINXZDINX-NEXT: ret
523 ;
524 ; RV64IZFINXZDINX-LABEL: fcvt_d_w:
525 ; RV64IZFINXZDINX: # %bb.0:
526 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
527 ; RV64IZFINXZDINX-NEXT: ret
528 ;
529 ; RV32I-LABEL: fcvt_d_w:
530 ; RV32I: # %bb.0:
531 ; RV32I-NEXT: addi sp, sp, -16
532 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
533 ; RV32I-NEXT: call __floatsidf
534 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
535 ; RV32I-NEXT: addi sp, sp, 16
536 ; RV32I-NEXT: ret
537 ;
538 ; RV64I-LABEL: fcvt_d_w:
539 ; RV64I: # %bb.0:
540 ; RV64I-NEXT: addi sp, sp, -16
541 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
542 ; RV64I-NEXT: sext.w a0, a0
543 ; RV64I-NEXT: call __floatsidf
544 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
545 ; RV64I-NEXT: addi sp, sp, 16
546 ; RV64I-NEXT: ret
547 %1 = sitofp i32 %a to double
548 ret double %1
549 }
551 define double @fcvt_d_w_load(ptr %p) nounwind {
552 ; CHECKIFD-LABEL: fcvt_d_w_load:
553 ; CHECKIFD: # %bb.0:
554 ; CHECKIFD-NEXT: lw a0, 0(a0)
555 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
556 ; CHECKIFD-NEXT: ret
557 ;
558 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_load:
559 ; RV32IZFINXZDINX: # %bb.0:
560 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
561 ; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
562 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
563 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
564 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
565 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
566 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
567 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
568 ; RV32IZFINXZDINX-NEXT: ret
569 ;
570 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_load:
571 ; RV64IZFINXZDINX: # %bb.0:
572 ; RV64IZFINXZDINX-NEXT: lw a0, 0(a0)
573 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
574 ; RV64IZFINXZDINX-NEXT: ret
575 ;
576 ; RV32I-LABEL: fcvt_d_w_load:
577 ; RV32I: # %bb.0:
578 ; RV32I-NEXT: addi sp, sp, -16
579 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
580 ; RV32I-NEXT: lw a0, 0(a0)
581 ; RV32I-NEXT: call __floatsidf
582 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
583 ; RV32I-NEXT: addi sp, sp, 16
584 ; RV32I-NEXT: ret
585 ;
586 ; RV64I-LABEL: fcvt_d_w_load:
587 ; RV64I: # %bb.0:
588 ; RV64I-NEXT: addi sp, sp, -16
589 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
590 ; RV64I-NEXT: lw a0, 0(a0)
591 ; RV64I-NEXT: call __floatsidf
592 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
593 ; RV64I-NEXT: addi sp, sp, 16
594 ; RV64I-NEXT: ret
595 %a = load i32, ptr %p
596 %1 = sitofp i32 %a to double
597 ret double %1
598 }
600 define double @fcvt_d_wu(i32 %a) nounwind {
601 ; CHECKIFD-LABEL: fcvt_d_wu:
602 ; CHECKIFD: # %bb.0:
603 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
604 ; CHECKIFD-NEXT: ret
605 ;
606 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu:
607 ; RV32IZFINXZDINX: # %bb.0:
608 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
609 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
610 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
611 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
612 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
613 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
614 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
615 ; RV32IZFINXZDINX-NEXT: ret
616 ;
617 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu:
618 ; RV64IZFINXZDINX: # %bb.0:
619 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
620 ; RV64IZFINXZDINX-NEXT: ret
621 ;
622 ; RV32I-LABEL: fcvt_d_wu:
623 ; RV32I: # %bb.0:
624 ; RV32I-NEXT: addi sp, sp, -16
625 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
626 ; RV32I-NEXT: call __floatunsidf
627 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
628 ; RV32I-NEXT: addi sp, sp, 16
629 ; RV32I-NEXT: ret
630 ;
631 ; RV64I-LABEL: fcvt_d_wu:
632 ; RV64I: # %bb.0:
633 ; RV64I-NEXT: addi sp, sp, -16
634 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
635 ; RV64I-NEXT: sext.w a0, a0
636 ; RV64I-NEXT: call __floatunsidf
637 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
638 ; RV64I-NEXT: addi sp, sp, 16
639 ; RV64I-NEXT: ret
640 %1 = uitofp i32 %a to double
641 ret double %1
642 }
644 define double @fcvt_d_wu_load(ptr %p) nounwind {
645 ; RV32IFD-LABEL: fcvt_d_wu_load:
646 ; RV32IFD: # %bb.0:
647 ; RV32IFD-NEXT: lw a0, 0(a0)
648 ; RV32IFD-NEXT: fcvt.d.wu fa0, a0
649 ; RV32IFD-NEXT: ret
650 ;
651 ; RV64IFD-LABEL: fcvt_d_wu_load:
652 ; RV64IFD: # %bb.0:
653 ; RV64IFD-NEXT: lwu a0, 0(a0)
654 ; RV64IFD-NEXT: fcvt.d.wu fa0, a0
655 ; RV64IFD-NEXT: ret
656 ;
657 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_load:
658 ; RV32IZFINXZDINX: # %bb.0:
659 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
660 ; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
661 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
662 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
663 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
664 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
665 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
666 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
667 ; RV32IZFINXZDINX-NEXT: ret
668 ;
669 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_load:
670 ; RV64IZFINXZDINX: # %bb.0:
671 ; RV64IZFINXZDINX-NEXT: lwu a0, 0(a0)
672 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
673 ; RV64IZFINXZDINX-NEXT: ret
674 ;
675 ; RV32I-LABEL: fcvt_d_wu_load:
676 ; RV32I: # %bb.0:
677 ; RV32I-NEXT: addi sp, sp, -16
678 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
679 ; RV32I-NEXT: lw a0, 0(a0)
680 ; RV32I-NEXT: call __floatunsidf
681 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
682 ; RV32I-NEXT: addi sp, sp, 16
683 ; RV32I-NEXT: ret
684 ;
685 ; RV64I-LABEL: fcvt_d_wu_load:
686 ; RV64I: # %bb.0:
687 ; RV64I-NEXT: addi sp, sp, -16
688 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
689 ; RV64I-NEXT: lw a0, 0(a0)
690 ; RV64I-NEXT: call __floatunsidf
691 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
692 ; RV64I-NEXT: addi sp, sp, 16
693 ; RV64I-NEXT: ret
694 %a = load i32, ptr %p
695 %1 = uitofp i32 %a to double
696 ret double %1
697 }
699 define i64 @fcvt_l_d(double %a) nounwind {
700 ; RV32IFD-LABEL: fcvt_l_d:
701 ; RV32IFD: # %bb.0:
702 ; RV32IFD-NEXT: addi sp, sp, -16
703 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
704 ; RV32IFD-NEXT: call __fixdfdi
705 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
706 ; RV32IFD-NEXT: addi sp, sp, 16
707 ; RV32IFD-NEXT: ret
708 ;
709 ; RV64IFD-LABEL: fcvt_l_d:
710 ; RV64IFD: # %bb.0:
711 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
712 ; RV64IFD-NEXT: ret
713 ;
714 ; RV32IZFINXZDINX-LABEL: fcvt_l_d:
715 ; RV32IZFINXZDINX: # %bb.0:
716 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
717 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
718 ; RV32IZFINXZDINX-NEXT: call __fixdfdi
719 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
720 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
721 ; RV32IZFINXZDINX-NEXT: ret
722 ;
723 ; RV64IZFINXZDINX-LABEL: fcvt_l_d:
724 ; RV64IZFINXZDINX: # %bb.0:
725 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
726 ; RV64IZFINXZDINX-NEXT: ret
727 ;
728 ; RV32I-LABEL: fcvt_l_d:
729 ; RV32I: # %bb.0:
730 ; RV32I-NEXT: addi sp, sp, -16
731 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
732 ; RV32I-NEXT: call __fixdfdi
733 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
734 ; RV32I-NEXT: addi sp, sp, 16
735 ; RV32I-NEXT: ret
736 ;
737 ; RV64I-LABEL: fcvt_l_d:
738 ; RV64I: # %bb.0:
739 ; RV64I-NEXT: addi sp, sp, -16
740 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
741 ; RV64I-NEXT: call __fixdfdi
742 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
743 ; RV64I-NEXT: addi sp, sp, 16
744 ; RV64I-NEXT: ret
745 %1 = fptosi double %a to i64
746 ret i64 %1
747 }
749 define i64 @fcvt_l_d_sat(double %a) nounwind {
750 ; RV32IFD-LABEL: fcvt_l_d_sat:
751 ; RV32IFD: # %bb.0: # %start
752 ; RV32IFD-NEXT: addi sp, sp, -16
753 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
754 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
755 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
756 ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
757 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
758 ; RV32IFD-NEXT: fmv.d fs0, fa0
759 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
760 ; RV32IFD-NEXT: call __fixdfdi
761 ; RV32IFD-NEXT: lui a4, 524288
762 ; RV32IFD-NEXT: lui a2, 524288
763 ; RV32IFD-NEXT: beqz s0, .LBB12_2
764 ; RV32IFD-NEXT: # %bb.1: # %start
765 ; RV32IFD-NEXT: mv a2, a1
766 ; RV32IFD-NEXT: .LBB12_2: # %start
767 ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
768 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
769 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
770 ; RV32IFD-NEXT: beqz a3, .LBB12_4
771 ; RV32IFD-NEXT: # %bb.3:
772 ; RV32IFD-NEXT: addi a2, a4, -1
773 ; RV32IFD-NEXT: .LBB12_4: # %start
774 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
775 ; RV32IFD-NEXT: neg a4, a1
776 ; RV32IFD-NEXT: and a1, a4, a2
777 ; RV32IFD-NEXT: neg a2, a3
778 ; RV32IFD-NEXT: neg a3, s0
779 ; RV32IFD-NEXT: and a0, a3, a0
780 ; RV32IFD-NEXT: or a0, a2, a0
781 ; RV32IFD-NEXT: and a0, a4, a0
782 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
783 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
784 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
785 ; RV32IFD-NEXT: addi sp, sp, 16
786 ; RV32IFD-NEXT: ret
787 ;
788 ; RV64IFD-LABEL: fcvt_l_d_sat:
789 ; RV64IFD: # %bb.0: # %start
790 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
791 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
792 ; RV64IFD-NEXT: seqz a1, a1
793 ; RV64IFD-NEXT: addi a1, a1, -1
794 ; RV64IFD-NEXT: and a0, a1, a0
795 ; RV64IFD-NEXT: ret
796 ;
797 ; RV32IZFINXZDINX-LABEL: fcvt_l_d_sat:
798 ; RV32IZFINXZDINX: # %bb.0: # %start
799 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
800 ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
801 ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
802 ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
803 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
804 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
805 ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
806 ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
807 ; RV32IZFINXZDINX-NEXT: call __fixdfdi
808 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
809 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
810 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
811 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
812 ; RV32IZFINXZDINX-NEXT: lui a5, 524288
813 ; RV32IZFINXZDINX-NEXT: lui a3, 524288
814 ; RV32IZFINXZDINX-NEXT: beqz a2, .LBB12_2
815 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
816 ; RV32IZFINXZDINX-NEXT: mv a3, a1
817 ; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
818 ; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
819 ; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
820 ; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
821 ; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
822 ; RV32IZFINXZDINX-NEXT: beqz a4, .LBB12_4
823 ; RV32IZFINXZDINX-NEXT: # %bb.3:
824 ; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
825 ; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
826 ; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
827 ; RV32IZFINXZDINX-NEXT: neg a5, a1
828 ; RV32IZFINXZDINX-NEXT: and a1, a5, a3
829 ; RV32IZFINXZDINX-NEXT: neg a2, a2
830 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0
831 ; RV32IZFINXZDINX-NEXT: neg a2, a4
832 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0
833 ; RV32IZFINXZDINX-NEXT: and a0, a5, a0
834 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
835 ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
836 ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
837 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
838 ; RV32IZFINXZDINX-NEXT: ret
839 ;
840 ; RV64IZFINXZDINX-LABEL: fcvt_l_d_sat:
841 ; RV64IZFINXZDINX: # %bb.0: # %start
842 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rtz
843 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
844 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
845 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
846 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
847 ; RV64IZFINXZDINX-NEXT: ret
848 ;
849 ; RV32I-LABEL: fcvt_l_d_sat:
850 ; RV32I: # %bb.0: # %start
851 ; RV32I-NEXT: addi sp, sp, -32
852 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
853 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
854 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
855 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
856 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
857 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
858 ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
859 ; RV32I-NEXT: mv s0, a1
860 ; RV32I-NEXT: mv s1, a0
861 ; RV32I-NEXT: lui a3, 278016
862 ; RV32I-NEXT: addi a3, a3, -1
863 ; RV32I-NEXT: li a2, -1
864 ; RV32I-NEXT: call __gtdf2
865 ; RV32I-NEXT: mv s2, a0
866 ; RV32I-NEXT: lui a3, 802304
867 ; RV32I-NEXT: mv a0, s1
868 ; RV32I-NEXT: mv a1, s0
869 ; RV32I-NEXT: li a2, 0
870 ; RV32I-NEXT: call __gedf2
871 ; RV32I-NEXT: mv s3, a0
872 ; RV32I-NEXT: mv a0, s1
873 ; RV32I-NEXT: mv a1, s0
874 ; RV32I-NEXT: call __fixdfdi
875 ; RV32I-NEXT: mv s4, a0
876 ; RV32I-NEXT: mv s5, a1
877 ; RV32I-NEXT: lui a0, 524288
878 ; RV32I-NEXT: bgez s3, .LBB12_2
879 ; RV32I-NEXT: # %bb.1: # %start
880 ; RV32I-NEXT: lui s5, 524288
881 ; RV32I-NEXT: .LBB12_2: # %start
882 ; RV32I-NEXT: blez s2, .LBB12_4
883 ; RV32I-NEXT: # %bb.3: # %start
884 ; RV32I-NEXT: addi s5, a0, -1
885 ; RV32I-NEXT: .LBB12_4: # %start
886 ; RV32I-NEXT: mv a0, s1
887 ; RV32I-NEXT: mv a1, s0
888 ; RV32I-NEXT: mv a2, s1
889 ; RV32I-NEXT: mv a3, s0
890 ; RV32I-NEXT: call __unorddf2
891 ; RV32I-NEXT: snez a0, a0
892 ; RV32I-NEXT: addi a0, a0, -1
893 ; RV32I-NEXT: and a1, a0, s5
894 ; RV32I-NEXT: slti a2, s3, 0
895 ; RV32I-NEXT: addi a2, a2, -1
896 ; RV32I-NEXT: and a2, a2, s4
897 ; RV32I-NEXT: sgtz a3, s2
898 ; RV32I-NEXT: neg a3, a3
899 ; RV32I-NEXT: or a2, a3, a2
900 ; RV32I-NEXT: and a0, a0, a2
901 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
902 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
903 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
904 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
905 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
906 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
907 ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
908 ; RV32I-NEXT: addi sp, sp, 32
909 ; RV32I-NEXT: ret
910 ;
911 ; RV64I-LABEL: fcvt_l_d_sat:
912 ; RV64I: # %bb.0: # %start
913 ; RV64I-NEXT: addi sp, sp, -48
914 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
915 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
916 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
917 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
918 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
919 ; RV64I-NEXT: mv s0, a0
920 ; RV64I-NEXT: li a1, -481
921 ; RV64I-NEXT: slli a1, a1, 53
922 ; RV64I-NEXT: call __gedf2
923 ; RV64I-NEXT: mv s2, a0
924 ; RV64I-NEXT: mv a0, s0
925 ; RV64I-NEXT: call __fixdfdi
926 ; RV64I-NEXT: mv s1, a0
927 ; RV64I-NEXT: li s3, -1
928 ; RV64I-NEXT: bgez s2, .LBB12_2
929 ; RV64I-NEXT: # %bb.1: # %start
930 ; RV64I-NEXT: slli s1, s3, 63
931 ; RV64I-NEXT: .LBB12_2: # %start
932 ; RV64I-NEXT: li a0, 543
933 ; RV64I-NEXT: slli a0, a0, 53
934 ; RV64I-NEXT: addi a1, a0, -1
935 ; RV64I-NEXT: mv a0, s0
936 ; RV64I-NEXT: call __gtdf2
937 ; RV64I-NEXT: blez a0, .LBB12_4
938 ; RV64I-NEXT: # %bb.3: # %start
939 ; RV64I-NEXT: srli s1, s3, 1
940 ; RV64I-NEXT: .LBB12_4: # %start
941 ; RV64I-NEXT: mv a0, s0
942 ; RV64I-NEXT: mv a1, s0
943 ; RV64I-NEXT: call __unorddf2
944 ; RV64I-NEXT: snez a0, a0
945 ; RV64I-NEXT: addi a0, a0, -1
946 ; RV64I-NEXT: and a0, a0, s1
947 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
948 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
949 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
950 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
951 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
952 ; RV64I-NEXT: addi sp, sp, 48
953 ; RV64I-NEXT: ret
954 start:
955 %0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
956 ret i64 %0
957 }
958 declare i64 @llvm.fptosi.sat.i64.f64(double)
960 define i64 @fcvt_lu_d(double %a) nounwind {
961 ; RV32IFD-LABEL: fcvt_lu_d:
962 ; RV32IFD: # %bb.0:
963 ; RV32IFD-NEXT: addi sp, sp, -16
964 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
965 ; RV32IFD-NEXT: call __fixunsdfdi
966 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
967 ; RV32IFD-NEXT: addi sp, sp, 16
968 ; RV32IFD-NEXT: ret
969 ;
970 ; RV64IFD-LABEL: fcvt_lu_d:
971 ; RV64IFD: # %bb.0:
972 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
973 ; RV64IFD-NEXT: ret
974 ;
975 ; RV32IZFINXZDINX-LABEL: fcvt_lu_d:
976 ; RV32IZFINXZDINX: # %bb.0:
977 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
978 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
979 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
980 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
981 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
982 ; RV32IZFINXZDINX-NEXT: ret
983 ;
984 ; RV64IZFINXZDINX-LABEL: fcvt_lu_d:
985 ; RV64IZFINXZDINX: # %bb.0:
986 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
987 ; RV64IZFINXZDINX-NEXT: ret
988 ;
989 ; RV32I-LABEL: fcvt_lu_d:
990 ; RV32I: # %bb.0:
991 ; RV32I-NEXT: addi sp, sp, -16
992 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
993 ; RV32I-NEXT: call __fixunsdfdi
994 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
995 ; RV32I-NEXT: addi sp, sp, 16
996 ; RV32I-NEXT: ret
997 ;
998 ; RV64I-LABEL: fcvt_lu_d:
999 ; RV64I: # %bb.0:
1000 ; RV64I-NEXT: addi sp, sp, -16
1001 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1002 ; RV64I-NEXT: call __fixunsdfdi
1003 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1004 ; RV64I-NEXT: addi sp, sp, 16
1005 ; RV64I-NEXT: ret
1006 %1 = fptoui double %a to i64
1007 ret i64 %1
1008 }
1010 define i64 @fcvt_lu_d_sat(double %a) nounwind {
1011 ; RV32IFD-LABEL: fcvt_lu_d_sat:
1012 ; RV32IFD: # %bb.0: # %start
1013 ; RV32IFD-NEXT: addi sp, sp, -16
1014 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1015 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1016 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
1017 ; RV32IFD-NEXT: fmv.d fs0, fa0
1018 ; RV32IFD-NEXT: fcvt.d.w fa5, zero
1019 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
1020 ; RV32IFD-NEXT: neg s0, a0
1021 ; RV32IFD-NEXT: call __fixunsdfdi
1022 ; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0)
1023 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2)
1024 ; RV32IFD-NEXT: and a0, s0, a0
1025 ; RV32IFD-NEXT: flt.d a2, fa5, fs0
1026 ; RV32IFD-NEXT: neg a2, a2
1027 ; RV32IFD-NEXT: or a0, a2, a0
1028 ; RV32IFD-NEXT: and a1, s0, a1
1029 ; RV32IFD-NEXT: or a1, a2, a1
1030 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1031 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1032 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
1033 ; RV32IFD-NEXT: addi sp, sp, 16
1034 ; RV32IFD-NEXT: ret
1035 ;
1036 ; RV64IFD-LABEL: fcvt_lu_d_sat:
1037 ; RV64IFD: # %bb.0: # %start
1038 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
1039 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
1040 ; RV64IFD-NEXT: seqz a1, a1
1041 ; RV64IFD-NEXT: addi a1, a1, -1
1042 ; RV64IFD-NEXT: and a0, a1, a0
1043 ; RV64IFD-NEXT: ret
1044 ;
1045 ; RV32IZFINXZDINX-LABEL: fcvt_lu_d_sat:
1046 ; RV32IZFINXZDINX: # %bb.0: # %start
1047 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
1048 ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1049 ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1050 ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1051 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1052 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1053 ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
1054 ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
1055 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
1056 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
1057 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0)
1058 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4)
1059 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4)
1060 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
1061 ; RV32IZFINXZDINX-NEXT: neg a2, a2
1062 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0
1063 ; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
1064 ; RV32IZFINXZDINX-NEXT: neg a3, a3
1065 ; RV32IZFINXZDINX-NEXT: or a0, a3, a0
1066 ; RV32IZFINXZDINX-NEXT: and a1, a2, a1
1067 ; RV32IZFINXZDINX-NEXT: or a1, a3, a1
1068 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1069 ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1070 ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1071 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
1072 ; RV32IZFINXZDINX-NEXT: ret
1073 ;
1074 ; RV64IZFINXZDINX-LABEL: fcvt_lu_d_sat:
1075 ; RV64IZFINXZDINX: # %bb.0: # %start
1076 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a1, a0, rtz
1077 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
1078 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
1079 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
1080 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1081 ; RV64IZFINXZDINX-NEXT: ret
1082 ;
1083 ; RV32I-LABEL: fcvt_lu_d_sat:
1084 ; RV32I: # %bb.0: # %start
1085 ; RV32I-NEXT: addi sp, sp, -32
1086 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1087 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1088 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1089 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1090 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1091 ; RV32I-NEXT: mv s0, a1
1092 ; RV32I-NEXT: mv s1, a0
1093 ; RV32I-NEXT: lui a3, 278272
1094 ; RV32I-NEXT: addi a3, a3, -1
1095 ; RV32I-NEXT: li a2, -1
1096 ; RV32I-NEXT: call __gtdf2
1097 ; RV32I-NEXT: sgtz a0, a0
1098 ; RV32I-NEXT: neg s2, a0
1099 ; RV32I-NEXT: mv a0, s1
1100 ; RV32I-NEXT: mv a1, s0
1101 ; RV32I-NEXT: li a2, 0
1102 ; RV32I-NEXT: li a3, 0
1103 ; RV32I-NEXT: call __gedf2
1104 ; RV32I-NEXT: slti a0, a0, 0
1105 ; RV32I-NEXT: addi s3, a0, -1
1106 ; RV32I-NEXT: mv a0, s1
1107 ; RV32I-NEXT: mv a1, s0
1108 ; RV32I-NEXT: call __fixunsdfdi
1109 ; RV32I-NEXT: and a0, s3, a0
1110 ; RV32I-NEXT: or a0, s2, a0
1111 ; RV32I-NEXT: and a1, s3, a1
1112 ; RV32I-NEXT: or a1, s2, a1
1113 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1114 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1115 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1116 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1117 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1118 ; RV32I-NEXT: addi sp, sp, 32
1119 ; RV32I-NEXT: ret
1120 ;
1121 ; RV64I-LABEL: fcvt_lu_d_sat:
1122 ; RV64I: # %bb.0: # %start
1123 ; RV64I-NEXT: addi sp, sp, -32
1124 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1125 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1126 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1127 ; RV64I-NEXT: mv s0, a0
1128 ; RV64I-NEXT: li a1, 0
1129 ; RV64I-NEXT: call __gedf2
1130 ; RV64I-NEXT: slti a0, a0, 0
1131 ; RV64I-NEXT: addi s1, a0, -1
1132 ; RV64I-NEXT: mv a0, s0
1133 ; RV64I-NEXT: call __fixunsdfdi
1134 ; RV64I-NEXT: and s1, s1, a0
1135 ; RV64I-NEXT: li a0, 1087
1136 ; RV64I-NEXT: slli a0, a0, 52
1137 ; RV64I-NEXT: addi a1, a0, -1
1138 ; RV64I-NEXT: mv a0, s0
1139 ; RV64I-NEXT: call __gtdf2
1140 ; RV64I-NEXT: sgtz a0, a0
1141 ; RV64I-NEXT: neg a0, a0
1142 ; RV64I-NEXT: or a0, a0, s1
1143 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1144 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1145 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1146 ; RV64I-NEXT: addi sp, sp, 32
1147 ; RV64I-NEXT: ret
1148 start:
1149 %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
1150 ret i64 %0
1151 }
1152 declare i64 @llvm.fptoui.sat.i64.f64(double)
1154 define i64 @fmv_x_d(double %a, double %b) nounwind {
1155 ; RV32IFD-LABEL: fmv_x_d:
1156 ; RV32IFD: # %bb.0:
1157 ; RV32IFD-NEXT: addi sp, sp, -16
1158 ; RV32IFD-NEXT: fadd.d fa5, fa0, fa1
1159 ; RV32IFD-NEXT: fsd fa5, 8(sp)
1160 ; RV32IFD-NEXT: lw a0, 8(sp)
1161 ; RV32IFD-NEXT: lw a1, 12(sp)
1162 ; RV32IFD-NEXT: addi sp, sp, 16
1163 ; RV32IFD-NEXT: ret
1164 ;
1165 ; RV64IFD-LABEL: fmv_x_d:
1166 ; RV64IFD: # %bb.0:
1167 ; RV64IFD-NEXT: fadd.d fa5, fa0, fa1
1168 ; RV64IFD-NEXT: fmv.x.d a0, fa5
1169 ; RV64IFD-NEXT: ret
1170 ;
1171 ; RV32IZFINXZDINX-LABEL: fmv_x_d:
1172 ; RV32IZFINXZDINX: # %bb.0:
1173 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1174 ; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
1175 ; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
1176 ; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
1177 ; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
1178 ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
1179 ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
1180 ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
1181 ; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
1182 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
1183 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1184 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1185 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1186 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1187 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1188 ; RV32IZFINXZDINX-NEXT: ret
1189 ;
1190 ; RV64IZFINXZDINX-LABEL: fmv_x_d:
1191 ; RV64IZFINXZDINX: # %bb.0:
1192 ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
1193 ; RV64IZFINXZDINX-NEXT: ret
1194 ;
1195 ; RV32I-LABEL: fmv_x_d:
1196 ; RV32I: # %bb.0:
1197 ; RV32I-NEXT: addi sp, sp, -16
1198 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1199 ; RV32I-NEXT: call __adddf3
1200 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1201 ; RV32I-NEXT: addi sp, sp, 16
1202 ; RV32I-NEXT: ret
1203 ;
1204 ; RV64I-LABEL: fmv_x_d:
1205 ; RV64I: # %bb.0:
1206 ; RV64I-NEXT: addi sp, sp, -16
1207 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1208 ; RV64I-NEXT: call __adddf3
1209 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1210 ; RV64I-NEXT: addi sp, sp, 16
1211 ; RV64I-NEXT: ret
1212 %1 = fadd double %a, %b
1213 %2 = bitcast double %1 to i64
1214 ret i64 %2
1215 }
1217 define double @fcvt_d_l(i64 %a) nounwind {
1218 ; RV32IFD-LABEL: fcvt_d_l:
1219 ; RV32IFD: # %bb.0:
1220 ; RV32IFD-NEXT: addi sp, sp, -16
1221 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1222 ; RV32IFD-NEXT: call __floatdidf
1223 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1224 ; RV32IFD-NEXT: addi sp, sp, 16
1225 ; RV32IFD-NEXT: ret
1226 ;
1227 ; RV64IFD-LABEL: fcvt_d_l:
1228 ; RV64IFD: # %bb.0:
1229 ; RV64IFD-NEXT: fcvt.d.l fa0, a0
1230 ; RV64IFD-NEXT: ret
1231 ;
1232 ; RV32IZFINXZDINX-LABEL: fcvt_d_l:
1233 ; RV32IZFINXZDINX: # %bb.0:
1234 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1235 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1236 ; RV32IZFINXZDINX-NEXT: call __floatdidf
1237 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1238 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1239 ; RV32IZFINXZDINX-NEXT: ret
1240 ;
1241 ; RV64IZFINXZDINX-LABEL: fcvt_d_l:
1242 ; RV64IZFINXZDINX: # %bb.0:
1243 ; RV64IZFINXZDINX-NEXT: fcvt.d.l a0, a0
1244 ; RV64IZFINXZDINX-NEXT: ret
1245 ;
1246 ; RV32I-LABEL: fcvt_d_l:
1247 ; RV32I: # %bb.0:
1248 ; RV32I-NEXT: addi sp, sp, -16
1249 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1250 ; RV32I-NEXT: call __floatdidf
1251 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1252 ; RV32I-NEXT: addi sp, sp, 16
1253 ; RV32I-NEXT: ret
1254 ;
1255 ; RV64I-LABEL: fcvt_d_l:
1256 ; RV64I: # %bb.0:
1257 ; RV64I-NEXT: addi sp, sp, -16
1258 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1259 ; RV64I-NEXT: call __floatdidf
1260 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1261 ; RV64I-NEXT: addi sp, sp, 16
1262 ; RV64I-NEXT: ret
1263 %1 = sitofp i64 %a to double
1264 ret double %1
1265 }
1267 define double @fcvt_d_lu(i64 %a) nounwind {
1268 ; RV32IFD-LABEL: fcvt_d_lu:
1269 ; RV32IFD: # %bb.0:
1270 ; RV32IFD-NEXT: addi sp, sp, -16
1271 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1272 ; RV32IFD-NEXT: call __floatundidf
1273 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1274 ; RV32IFD-NEXT: addi sp, sp, 16
1275 ; RV32IFD-NEXT: ret
1276 ;
1277 ; RV64IFD-LABEL: fcvt_d_lu:
1278 ; RV64IFD: # %bb.0:
1279 ; RV64IFD-NEXT: fcvt.d.lu fa0, a0
1280 ; RV64IFD-NEXT: ret
1281 ;
1282 ; RV32IZFINXZDINX-LABEL: fcvt_d_lu:
1283 ; RV32IZFINXZDINX: # %bb.0:
1284 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1285 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1286 ; RV32IZFINXZDINX-NEXT: call __floatundidf
1287 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1288 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1289 ; RV32IZFINXZDINX-NEXT: ret
1290 ;
1291 ; RV64IZFINXZDINX-LABEL: fcvt_d_lu:
1292 ; RV64IZFINXZDINX: # %bb.0:
1293 ; RV64IZFINXZDINX-NEXT: fcvt.d.lu a0, a0
1294 ; RV64IZFINXZDINX-NEXT: ret
1295 ;
1296 ; RV32I-LABEL: fcvt_d_lu:
1297 ; RV32I: # %bb.0:
1298 ; RV32I-NEXT: addi sp, sp, -16
1299 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1300 ; RV32I-NEXT: call __floatundidf
1301 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1302 ; RV32I-NEXT: addi sp, sp, 16
1303 ; RV32I-NEXT: ret
1304 ;
1305 ; RV64I-LABEL: fcvt_d_lu:
1306 ; RV64I: # %bb.0:
1307 ; RV64I-NEXT: addi sp, sp, -16
1308 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1309 ; RV64I-NEXT: call __floatundidf
1310 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1311 ; RV64I-NEXT: addi sp, sp, 16
1312 ; RV64I-NEXT: ret
1313 %1 = uitofp i64 %a to double
1314 ret double %1
1315 }
1317 define double @fmv_d_x(i64 %a, i64 %b) nounwind {
1318 ; Ensure fmv.w.x is generated even for a soft double calling convention
1319 ; RV32IFD-LABEL: fmv_d_x:
1320 ; RV32IFD: # %bb.0:
1321 ; RV32IFD-NEXT: addi sp, sp, -16
1322 ; RV32IFD-NEXT: sw a3, 4(sp)
1323 ; RV32IFD-NEXT: sw a2, 0(sp)
1324 ; RV32IFD-NEXT: sw a1, 12(sp)
1325 ; RV32IFD-NEXT: sw a0, 8(sp)
1326 ; RV32IFD-NEXT: fld fa5, 0(sp)
1327 ; RV32IFD-NEXT: fld fa4, 8(sp)
1328 ; RV32IFD-NEXT: fadd.d fa0, fa4, fa5
1329 ; RV32IFD-NEXT: addi sp, sp, 16
1330 ; RV32IFD-NEXT: ret
1331 ;
1332 ; RV64IFD-LABEL: fmv_d_x:
1333 ; RV64IFD: # %bb.0:
1334 ; RV64IFD-NEXT: fmv.d.x fa5, a0
1335 ; RV64IFD-NEXT: fmv.d.x fa4, a1
1336 ; RV64IFD-NEXT: fadd.d fa0, fa5, fa4
1337 ; RV64IFD-NEXT: ret
1338 ;
1339 ; RV32IZFINXZDINX-LABEL: fmv_d_x:
1340 ; RV32IZFINXZDINX: # %bb.0:
1341 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
1342 ; RV32IZFINXZDINX-NEXT: sw a3, 20(sp)
1343 ; RV32IZFINXZDINX-NEXT: sw a2, 16(sp)
1344 ; RV32IZFINXZDINX-NEXT: sw a1, 28(sp)
1345 ; RV32IZFINXZDINX-NEXT: sw a0, 24(sp)
1346 ; RV32IZFINXZDINX-NEXT: lw a0, 16(sp)
1347 ; RV32IZFINXZDINX-NEXT: lw a1, 20(sp)
1348 ; RV32IZFINXZDINX-NEXT: lw a2, 24(sp)
1349 ; RV32IZFINXZDINX-NEXT: lw a3, 28(sp)
1350 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
1351 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1352 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1353 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1354 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1355 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
1356 ; RV32IZFINXZDINX-NEXT: ret
1357 ;
1358 ; RV64IZFINXZDINX-LABEL: fmv_d_x:
1359 ; RV64IZFINXZDINX: # %bb.0:
1360 ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
1361 ; RV64IZFINXZDINX-NEXT: ret
1362 ;
1363 ; RV32I-LABEL: fmv_d_x:
1364 ; RV32I: # %bb.0:
1365 ; RV32I-NEXT: addi sp, sp, -16
1366 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1367 ; RV32I-NEXT: call __adddf3
1368 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1369 ; RV32I-NEXT: addi sp, sp, 16
1370 ; RV32I-NEXT: ret
1371 ;
1372 ; RV64I-LABEL: fmv_d_x:
1373 ; RV64I: # %bb.0:
1374 ; RV64I-NEXT: addi sp, sp, -16
1375 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1376 ; RV64I-NEXT: call __adddf3
1377 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1378 ; RV64I-NEXT: addi sp, sp, 16
1379 ; RV64I-NEXT: ret
1380 %1 = bitcast i64 %a to double
1381 %2 = bitcast i64 %b to double
1382 %3 = fadd double %1, %2
1383 ret double %3
1384 }
1386 define double @fcvt_d_w_i8(i8 signext %a) nounwind {
1387 ; CHECKIFD-LABEL: fcvt_d_w_i8:
1388 ; CHECKIFD: # %bb.0:
1389 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
1390 ; CHECKIFD-NEXT: ret
1391 ;
1392 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_i8:
1393 ; RV32IZFINXZDINX: # %bb.0:
1394 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1395 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1396 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1397 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1398 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1399 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1400 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1401 ; RV32IZFINXZDINX-NEXT: ret
1402 ;
1403 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_i8:
1404 ; RV64IZFINXZDINX: # %bb.0:
1405 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1406 ; RV64IZFINXZDINX-NEXT: ret
1407 ;
1408 ; RV32I-LABEL: fcvt_d_w_i8:
1409 ; RV32I: # %bb.0:
1410 ; RV32I-NEXT: addi sp, sp, -16
1411 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1412 ; RV32I-NEXT: call __floatsidf
1413 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1414 ; RV32I-NEXT: addi sp, sp, 16
1415 ; RV32I-NEXT: ret
1416 ;
1417 ; RV64I-LABEL: fcvt_d_w_i8:
1418 ; RV64I: # %bb.0:
1419 ; RV64I-NEXT: addi sp, sp, -16
1420 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1421 ; RV64I-NEXT: call __floatsidf
1422 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1423 ; RV64I-NEXT: addi sp, sp, 16
1424 ; RV64I-NEXT: ret
1425 %1 = sitofp i8 %a to double
1426 ret double %1
1427 }
1429 define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
1430 ; CHECKIFD-LABEL: fcvt_d_wu_i8:
1431 ; CHECKIFD: # %bb.0:
1432 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
1433 ; CHECKIFD-NEXT: ret
1434 ;
1435 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i8:
1436 ; RV32IZFINXZDINX: # %bb.0:
1437 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1438 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1439 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1440 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1441 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1442 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1443 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1444 ; RV32IZFINXZDINX-NEXT: ret
1445 ;
1446 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i8:
1447 ; RV64IZFINXZDINX: # %bb.0:
1448 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1449 ; RV64IZFINXZDINX-NEXT: ret
1450 ;
1451 ; RV32I-LABEL: fcvt_d_wu_i8:
1452 ; RV32I: # %bb.0:
1453 ; RV32I-NEXT: addi sp, sp, -16
1454 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1455 ; RV32I-NEXT: call __floatunsidf
1456 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1457 ; RV32I-NEXT: addi sp, sp, 16
1458 ; RV32I-NEXT: ret
1459 ;
1460 ; RV64I-LABEL: fcvt_d_wu_i8:
1461 ; RV64I: # %bb.0:
1462 ; RV64I-NEXT: addi sp, sp, -16
1463 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1464 ; RV64I-NEXT: call __floatunsidf
1465 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1466 ; RV64I-NEXT: addi sp, sp, 16
1467 ; RV64I-NEXT: ret
1468 %1 = uitofp i8 %a to double
1469 ret double %1
1470 }
1472 define double @fcvt_d_w_i16(i16 signext %a) nounwind {
1473 ; CHECKIFD-LABEL: fcvt_d_w_i16:
1474 ; CHECKIFD: # %bb.0:
1475 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
1476 ; CHECKIFD-NEXT: ret
1477 ;
1478 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_i16:
1479 ; RV32IZFINXZDINX: # %bb.0:
1480 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1481 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1482 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1483 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1484 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1485 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1486 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1487 ; RV32IZFINXZDINX-NEXT: ret
1488 ;
1489 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_i16:
1490 ; RV64IZFINXZDINX: # %bb.0:
1491 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1492 ; RV64IZFINXZDINX-NEXT: ret
1493 ;
1494 ; RV32I-LABEL: fcvt_d_w_i16:
1495 ; RV32I: # %bb.0:
1496 ; RV32I-NEXT: addi sp, sp, -16
1497 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1498 ; RV32I-NEXT: call __floatsidf
1499 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1500 ; RV32I-NEXT: addi sp, sp, 16
1501 ; RV32I-NEXT: ret
1502 ;
1503 ; RV64I-LABEL: fcvt_d_w_i16:
1504 ; RV64I: # %bb.0:
1505 ; RV64I-NEXT: addi sp, sp, -16
1506 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1507 ; RV64I-NEXT: call __floatsidf
1508 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1509 ; RV64I-NEXT: addi sp, sp, 16
1510 ; RV64I-NEXT: ret
1511 %1 = sitofp i16 %a to double
1512 ret double %1
1513 }
1515 define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
1516 ; CHECKIFD-LABEL: fcvt_d_wu_i16:
1517 ; CHECKIFD: # %bb.0:
1518 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
1519 ; CHECKIFD-NEXT: ret
1520 ;
1521 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i16:
1522 ; RV32IZFINXZDINX: # %bb.0:
1523 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1524 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1525 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1526 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1527 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1528 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1529 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1530 ; RV32IZFINXZDINX-NEXT: ret
1531 ;
1532 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i16:
1533 ; RV64IZFINXZDINX: # %bb.0:
1534 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1535 ; RV64IZFINXZDINX-NEXT: ret
1536 ;
1537 ; RV32I-LABEL: fcvt_d_wu_i16:
1538 ; RV32I: # %bb.0:
1539 ; RV32I-NEXT: addi sp, sp, -16
1540 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1541 ; RV32I-NEXT: call __floatunsidf
1542 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1543 ; RV32I-NEXT: addi sp, sp, 16
1544 ; RV32I-NEXT: ret
1545 ;
1546 ; RV64I-LABEL: fcvt_d_wu_i16:
1547 ; RV64I: # %bb.0:
1548 ; RV64I-NEXT: addi sp, sp, -16
1549 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1550 ; RV64I-NEXT: call __floatunsidf
1551 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1552 ; RV64I-NEXT: addi sp, sp, 16
1553 ; RV64I-NEXT: ret
1554 %1 = uitofp i16 %a to double
1555 ret double %1
1556 }
1558 ; Make sure we select W version of addi on RV64.
1559 define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
1560 ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
1561 ; RV32IFD: # %bb.0:
1562 ; RV32IFD-NEXT: addi a0, a0, 1
1563 ; RV32IFD-NEXT: fcvt.d.w fa5, a0
1564 ; RV32IFD-NEXT: fsd fa5, 0(a1)
1565 ; RV32IFD-NEXT: ret
1566 ;
1567 ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
1568 ; RV64IFD: # %bb.0:
1569 ; RV64IFD-NEXT: addiw a0, a0, 1
1570 ; RV64IFD-NEXT: fcvt.d.w fa5, a0
1571 ; RV64IFD-NEXT: fsd fa5, 0(a1)
1572 ; RV64IFD-NEXT: ret
1573 ;
1574 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
1575 ; RV32IZFINXZDINX: # %bb.0:
1576 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 1
1577 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, a0
1578 ; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)
1579 ; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)
1580 ; RV32IZFINXZDINX-NEXT: ret
1581 ;
1582 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
1583 ; RV64IZFINXZDINX: # %bb.0:
1584 ; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
1585 ; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
1586 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1587 ; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
1588 ; RV64IZFINXZDINX-NEXT: mv a0, a2
1589 ; RV64IZFINXZDINX-NEXT: ret
1590 ;
1591 ; RV32I-LABEL: fcvt_d_w_demanded_bits:
1592 ; RV32I: # %bb.0:
1593 ; RV32I-NEXT: addi sp, sp, -16
1594 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1595 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1596 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1597 ; RV32I-NEXT: mv s0, a1
1598 ; RV32I-NEXT: addi s1, a0, 1
1599 ; RV32I-NEXT: mv a0, s1
1600 ; RV32I-NEXT: call __floatsidf
1601 ; RV32I-NEXT: sw a1, 4(s0)
1602 ; RV32I-NEXT: sw a0, 0(s0)
1603 ; RV32I-NEXT: mv a0, s1
1604 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1605 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1606 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1607 ; RV32I-NEXT: addi sp, sp, 16
1608 ; RV32I-NEXT: ret
1609 ;
1610 ; RV64I-LABEL: fcvt_d_w_demanded_bits:
1611 ; RV64I: # %bb.0:
1612 ; RV64I-NEXT: addi sp, sp, -32
1613 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1614 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1615 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1616 ; RV64I-NEXT: mv s0, a1
1617 ; RV64I-NEXT: addiw s1, a0, 1
1618 ; RV64I-NEXT: mv a0, s1
1619 ; RV64I-NEXT: call __floatsidf
1620 ; RV64I-NEXT: sd a0, 0(s0)
1621 ; RV64I-NEXT: mv a0, s1
1622 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1623 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1624 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1625 ; RV64I-NEXT: addi sp, sp, 32
1626 ; RV64I-NEXT: ret
1627 %3 = add i32 %0, 1
1628 %4 = sitofp i32 %3 to double
1629 store double %4, ptr %1, align 8
1630 ret i32 %3
1631 }
1633 ; Make sure we select W version of addi on RV64.
1634 define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
1635 ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
1636 ; RV32IFD: # %bb.0:
1637 ; RV32IFD-NEXT: addi a0, a0, 1
1638 ; RV32IFD-NEXT: fcvt.d.wu fa5, a0
1639 ; RV32IFD-NEXT: fsd fa5, 0(a1)
1640 ; RV32IFD-NEXT: ret
1641 ;
1642 ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
1643 ; RV64IFD: # %bb.0:
1644 ; RV64IFD-NEXT: addiw a0, a0, 1
1645 ; RV64IFD-NEXT: fcvt.d.wu fa5, a0
1646 ; RV64IFD-NEXT: fsd fa5, 0(a1)
1647 ; RV64IFD-NEXT: ret
1648 ;
1649 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:
1650 ; RV32IZFINXZDINX: # %bb.0:
1651 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 1
1652 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a2, a0
1653 ; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)
1654 ; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)
1655 ; RV32IZFINXZDINX-NEXT: ret
1656 ;
1657 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:
1658 ; RV64IZFINXZDINX: # %bb.0:
1659 ; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
1660 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a2, a0
1661 ; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
1662 ; RV64IZFINXZDINX-NEXT: ret
1663 ;
1664 ; RV32I-LABEL: fcvt_d_wu_demanded_bits:
1665 ; RV32I: # %bb.0:
1666 ; RV32I-NEXT: addi sp, sp, -16
1667 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1668 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1669 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1670 ; RV32I-NEXT: mv s0, a1
1671 ; RV32I-NEXT: addi s1, a0, 1
1672 ; RV32I-NEXT: mv a0, s1
1673 ; RV32I-NEXT: call __floatunsidf
1674 ; RV32I-NEXT: sw a1, 4(s0)
1675 ; RV32I-NEXT: sw a0, 0(s0)
1676 ; RV32I-NEXT: mv a0, s1
1677 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1678 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1679 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1680 ; RV32I-NEXT: addi sp, sp, 16
1681 ; RV32I-NEXT: ret
1682 ;
1683 ; RV64I-LABEL: fcvt_d_wu_demanded_bits:
1684 ; RV64I: # %bb.0:
1685 ; RV64I-NEXT: addi sp, sp, -32
1686 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1687 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1688 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1689 ; RV64I-NEXT: mv s0, a1
1690 ; RV64I-NEXT: addiw s1, a0, 1
1691 ; RV64I-NEXT: mv a0, s1
1692 ; RV64I-NEXT: call __floatunsidf
1693 ; RV64I-NEXT: sd a0, 0(s0)
1694 ; RV64I-NEXT: mv a0, s1
1695 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1696 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1697 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1698 ; RV64I-NEXT: addi sp, sp, 32
1699 ; RV64I-NEXT: ret
1700 %3 = add i32 %0, 1
1701 %4 = uitofp i32 %3 to double
1702 store double %4, ptr %1, align 8
1703 ret i32 %3
1704 }
1706 define signext i16 @fcvt_w_s_i16(double %a) nounwind {
1707 ; RV32IFD-LABEL: fcvt_w_s_i16:
1708 ; RV32IFD: # %bb.0:
1709 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
1710 ; RV32IFD-NEXT: ret
1711 ;
1712 ; RV64IFD-LABEL: fcvt_w_s_i16:
1713 ; RV64IFD: # %bb.0:
1714 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
1715 ; RV64IFD-NEXT: ret
1716 ;
1717 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_i16:
1718 ; RV32IZFINXZDINX: # %bb.0:
1719 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1720 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1721 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1722 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1723 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1724 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
1725 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1726 ; RV32IZFINXZDINX-NEXT: ret
1727 ;
1728 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_i16:
1729 ; RV64IZFINXZDINX: # %bb.0:
1730 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
1731 ; RV64IZFINXZDINX-NEXT: ret
1732 ;
1733 ; RV32I-LABEL: fcvt_w_s_i16:
1734 ; RV32I: # %bb.0:
1735 ; RV32I-NEXT: addi sp, sp, -16
1736 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1737 ; RV32I-NEXT: call __fixdfsi
1738 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1739 ; RV32I-NEXT: addi sp, sp, 16
1740 ; RV32I-NEXT: ret
1741 ;
1742 ; RV64I-LABEL: fcvt_w_s_i16:
1743 ; RV64I: # %bb.0:
1744 ; RV64I-NEXT: addi sp, sp, -16
1745 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1746 ; RV64I-NEXT: call __fixdfdi
1747 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1748 ; RV64I-NEXT: addi sp, sp, 16
1749 ; RV64I-NEXT: ret
1750 %1 = fptosi double %a to i16
1751 ret i16 %1
1752 }
1754 define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
1755 ; RV32IFD-LABEL: fcvt_w_s_sat_i16:
1756 ; RV32IFD: # %bb.0: # %start
1757 ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
1758 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
1759 ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
1760 ; RV32IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
1761 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
1762 ; RV32IFD-NEXT: neg a0, a0
1763 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
1764 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
1765 ; RV32IFD-NEXT: fcvt.w.d a1, fa5, rtz
1766 ; RV32IFD-NEXT: and a0, a0, a1
1767 ; RV32IFD-NEXT: ret
1768 ;
1769 ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
1770 ; RV64IFD: # %bb.0: # %start
1771 ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
1772 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
1773 ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
1774 ; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
1775 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
1776 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
1777 ; RV64IFD-NEXT: neg a0, a0
1778 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
1779 ; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
1780 ; RV64IFD-NEXT: and a0, a0, a1
1781 ; RV64IFD-NEXT: ret
1782 ;
1783 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
1784 ; RV32IZFINXZDINX: # %bb.0: # %start
1785 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1786 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1787 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1788 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1789 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1790 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
1791 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI26_0+4)(a2)
1792 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a2)
1793 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI26_1)
1794 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI26_1+4)(a4)
1795 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a4)
1796 ; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
1797 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
1798 ; RV32IZFINXZDINX-NEXT: neg a0, a0
1799 ; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
1800 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
1801 ; RV32IZFINXZDINX-NEXT: and a0, a0, a1
1802 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1803 ; RV32IZFINXZDINX-NEXT: ret
1804 ;
1805 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
1806 ; RV64IZFINXZDINX: # %bb.0: # %start
1807 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI26_0)
1808 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
1809 ; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
1810 ; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
1811 ; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
1812 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
1813 ; RV64IZFINXZDINX-NEXT: neg a0, a0
1814 ; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
1815 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
1816 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1817 ; RV64IZFINXZDINX-NEXT: ret
1818 ;
1819 ; RV32I-LABEL: fcvt_w_s_sat_i16:
1820 ; RV32I: # %bb.0: # %start
1821 ; RV32I-NEXT: addi sp, sp, -32
1822 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1823 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1824 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1825 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1826 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1827 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
1828 ; RV32I-NEXT: mv s0, a1
1829 ; RV32I-NEXT: mv s1, a0
1830 ; RV32I-NEXT: lui a0, 265728
1831 ; RV32I-NEXT: addi a3, a0, -64
1832 ; RV32I-NEXT: mv a0, s1
1833 ; RV32I-NEXT: li a2, 0
1834 ; RV32I-NEXT: call __gtdf2
1835 ; RV32I-NEXT: mv s2, a0
1836 ; RV32I-NEXT: lui a3, 790016
1837 ; RV32I-NEXT: mv a0, s1
1838 ; RV32I-NEXT: mv a1, s0
1839 ; RV32I-NEXT: li a2, 0
1840 ; RV32I-NEXT: call __gedf2
1841 ; RV32I-NEXT: mv s4, a0
1842 ; RV32I-NEXT: mv a0, s1
1843 ; RV32I-NEXT: mv a1, s0
1844 ; RV32I-NEXT: call __fixdfsi
1845 ; RV32I-NEXT: mv s3, a0
1846 ; RV32I-NEXT: bgez s4, .LBB26_2
1847 ; RV32I-NEXT: # %bb.1: # %start
1848 ; RV32I-NEXT: lui s3, 1048568
1849 ; RV32I-NEXT: .LBB26_2: # %start
1850 ; RV32I-NEXT: blez s2, .LBB26_4
1851 ; RV32I-NEXT: # %bb.3: # %start
1852 ; RV32I-NEXT: lui s3, 8
1853 ; RV32I-NEXT: addi s3, s3, -1
1854 ; RV32I-NEXT: .LBB26_4: # %start
1855 ; RV32I-NEXT: mv a0, s1
1856 ; RV32I-NEXT: mv a1, s0
1857 ; RV32I-NEXT: mv a2, s1
1858 ; RV32I-NEXT: mv a3, s0
1859 ; RV32I-NEXT: call __unorddf2
1860 ; RV32I-NEXT: snez a0, a0
1861 ; RV32I-NEXT: addi a0, a0, -1
1862 ; RV32I-NEXT: and a0, a0, s3
1863 ; RV32I-NEXT: slli a0, a0, 16
1864 ; RV32I-NEXT: srai a0, a0, 16
1865 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1866 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1867 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1868 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1869 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1870 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
1871 ; RV32I-NEXT: addi sp, sp, 32
1872 ; RV32I-NEXT: ret
1873 ;
1874 ; RV64I-LABEL: fcvt_w_s_sat_i16:
1875 ; RV64I: # %bb.0: # %start
1876 ; RV64I-NEXT: addi sp, sp, -32
1877 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1878 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1879 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1880 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1881 ; RV64I-NEXT: mv s0, a0
1882 ; RV64I-NEXT: li a1, -505
1883 ; RV64I-NEXT: slli a1, a1, 53
1884 ; RV64I-NEXT: call __gedf2
1885 ; RV64I-NEXT: mv s2, a0
1886 ; RV64I-NEXT: mv a0, s0
1887 ; RV64I-NEXT: call __fixdfdi
1888 ; RV64I-NEXT: mv s1, a0
1889 ; RV64I-NEXT: bgez s2, .LBB26_2
1890 ; RV64I-NEXT: # %bb.1: # %start
1891 ; RV64I-NEXT: lui s1, 1048568
1892 ; RV64I-NEXT: .LBB26_2: # %start
1893 ; RV64I-NEXT: lui a0, 4152
1894 ; RV64I-NEXT: addi a0, a0, -1
1895 ; RV64I-NEXT: slli a1, a0, 38
1896 ; RV64I-NEXT: mv a0, s0
1897 ; RV64I-NEXT: call __gtdf2
1898 ; RV64I-NEXT: blez a0, .LBB26_4
1899 ; RV64I-NEXT: # %bb.3: # %start
1900 ; RV64I-NEXT: lui s1, 8
1901 ; RV64I-NEXT: addi s1, s1, -1
1902 ; RV64I-NEXT: .LBB26_4: # %start
1903 ; RV64I-NEXT: mv a0, s0
1904 ; RV64I-NEXT: mv a1, s0
1905 ; RV64I-NEXT: call __unorddf2
1906 ; RV64I-NEXT: snez a0, a0
1907 ; RV64I-NEXT: addi a0, a0, -1
1908 ; RV64I-NEXT: and a0, a0, s1
1909 ; RV64I-NEXT: slli a0, a0, 48
1910 ; RV64I-NEXT: srai a0, a0, 48
1911 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1912 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1913 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1914 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1915 ; RV64I-NEXT: addi sp, sp, 32
1916 ; RV64I-NEXT: ret
1917 start:
1918 %0 = tail call i16 @llvm.fptosi.sat.i16.f64(double %a)
1919 ret i16 %0
1920 }
1921 declare i16 @llvm.fptosi.sat.i16.f64(double)
1923 define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
1924 ; RV32IFD-LABEL: fcvt_wu_s_i16:
1925 ; RV32IFD: # %bb.0:
1926 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
1927 ; RV32IFD-NEXT: ret
1928 ;
1929 ; RV64IFD-LABEL: fcvt_wu_s_i16:
1930 ; RV64IFD: # %bb.0:
1931 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
1932 ; RV64IFD-NEXT: ret
1933 ;
1934 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i16:
1935 ; RV32IZFINXZDINX: # %bb.0:
1936 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1937 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1938 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1939 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1940 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1941 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
1942 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1943 ; RV32IZFINXZDINX-NEXT: ret
1944 ;
1945 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i16:
1946 ; RV64IZFINXZDINX: # %bb.0:
1947 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
1948 ; RV64IZFINXZDINX-NEXT: ret
1949 ;
1950 ; RV32I-LABEL: fcvt_wu_s_i16:
1951 ; RV32I: # %bb.0:
1952 ; RV32I-NEXT: addi sp, sp, -16
1953 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1954 ; RV32I-NEXT: call __fixunsdfsi
1955 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1956 ; RV32I-NEXT: addi sp, sp, 16
1957 ; RV32I-NEXT: ret
1958 ;
1959 ; RV64I-LABEL: fcvt_wu_s_i16:
1960 ; RV64I: # %bb.0:
1961 ; RV64I-NEXT: addi sp, sp, -16
1962 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1963 ; RV64I-NEXT: call __fixunsdfdi
1964 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1965 ; RV64I-NEXT: addi sp, sp, 16
1966 ; RV64I-NEXT: ret
1967 %1 = fptoui double %a to i16
1968 ret i16 %1
1969 }
1971 define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
1972 ; RV32IFD-LABEL: fcvt_wu_s_sat_i16:
1973 ; RV32IFD: # %bb.0: # %start
1974 ; RV32IFD-NEXT: lui a0, %hi(.LCPI28_0)
1975 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI28_0)(a0)
1976 ; RV32IFD-NEXT: fcvt.d.w fa4, zero
1977 ; RV32IFD-NEXT: fmax.d fa4, fa0, fa4
1978 ; RV32IFD-NEXT: fmin.d fa5, fa4, fa5
1979 ; RV32IFD-NEXT: fcvt.wu.d a0, fa5, rtz
1980 ; RV32IFD-NEXT: ret
1981 ;
1982 ; RV64IFD-LABEL: fcvt_wu_s_sat_i16:
1983 ; RV64IFD: # %bb.0: # %start
1984 ; RV64IFD-NEXT: lui a0, %hi(.LCPI28_0)
1985 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI28_0)(a0)
1986 ; RV64IFD-NEXT: fmv.d.x fa4, zero
1987 ; RV64IFD-NEXT: fmax.d fa4, fa0, fa4
1988 ; RV64IFD-NEXT: fmin.d fa5, fa4, fa5
1989 ; RV64IFD-NEXT: fcvt.lu.d a0, fa5, rtz
1990 ; RV64IFD-NEXT: ret
1991 ;
1992 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
1993 ; RV32IZFINXZDINX: # %bb.0: # %start
1994 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1995 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1996 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1997 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1998 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1999 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
2000 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI28_0+4)(a2)
2001 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a2)
2002 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
2003 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
2004 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2005 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
2006 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2007 ; RV32IZFINXZDINX-NEXT: ret
2008 ;
2009 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
2010 ; RV64IZFINXZDINX: # %bb.0: # %start
2011 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI28_0)
2012 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI28_0)(a1)
2013 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
2014 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
2015 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
2016 ; RV64IZFINXZDINX-NEXT: ret
2017 ;
2018 ; RV32I-LABEL: fcvt_wu_s_sat_i16:
2019 ; RV32I: # %bb.0: # %start
2020 ; RV32I-NEXT: addi sp, sp, -32
2021 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2022 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2023 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2024 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2025 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2026 ; RV32I-NEXT: mv s1, a1
2027 ; RV32I-NEXT: mv s2, a0
2028 ; RV32I-NEXT: lui a3, 265984
2029 ; RV32I-NEXT: addi a3, a3, -32
2030 ; RV32I-NEXT: li a2, 0
2031 ; RV32I-NEXT: call __gtdf2
2032 ; RV32I-NEXT: mv s3, a0
2033 ; RV32I-NEXT: mv a0, s2
2034 ; RV32I-NEXT: mv a1, s1
2035 ; RV32I-NEXT: li a2, 0
2036 ; RV32I-NEXT: li a3, 0
2037 ; RV32I-NEXT: call __gedf2
2038 ; RV32I-NEXT: mv s0, a0
2039 ; RV32I-NEXT: mv a0, s2
2040 ; RV32I-NEXT: mv a1, s1
2041 ; RV32I-NEXT: call __fixunsdfsi
2042 ; RV32I-NEXT: lui a1, 16
2043 ; RV32I-NEXT: addi a1, a1, -1
2044 ; RV32I-NEXT: blez s3, .LBB28_2
2045 ; RV32I-NEXT: # %bb.1: # %start
2046 ; RV32I-NEXT: mv a0, a1
2047 ; RV32I-NEXT: j .LBB28_3
2048 ; RV32I-NEXT: .LBB28_2:
2049 ; RV32I-NEXT: slti a2, s0, 0
2050 ; RV32I-NEXT: addi a2, a2, -1
2051 ; RV32I-NEXT: and a0, a2, a0
2052 ; RV32I-NEXT: .LBB28_3: # %start
2053 ; RV32I-NEXT: and a0, a0, a1
2054 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2055 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2056 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2057 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2058 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2059 ; RV32I-NEXT: addi sp, sp, 32
2060 ; RV32I-NEXT: ret
2061 ;
2062 ; RV64I-LABEL: fcvt_wu_s_sat_i16:
2063 ; RV64I: # %bb.0: # %start
2064 ; RV64I-NEXT: addi sp, sp, -32
2065 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2066 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2067 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2068 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2069 ; RV64I-NEXT: mv s2, a0
2070 ; RV64I-NEXT: li a1, 0
2071 ; RV64I-NEXT: call __gedf2
2072 ; RV64I-NEXT: mv s0, a0
2073 ; RV64I-NEXT: mv a0, s2
2074 ; RV64I-NEXT: call __fixunsdfdi
2075 ; RV64I-NEXT: mv s1, a0
2076 ; RV64I-NEXT: lui a0, 8312
2077 ; RV64I-NEXT: addi a0, a0, -1
2078 ; RV64I-NEXT: slli a1, a0, 37
2079 ; RV64I-NEXT: mv a0, s2
2080 ; RV64I-NEXT: call __gtdf2
2081 ; RV64I-NEXT: lui a1, 16
2082 ; RV64I-NEXT: addiw a1, a1, -1
2083 ; RV64I-NEXT: blez a0, .LBB28_2
2084 ; RV64I-NEXT: # %bb.1: # %start
2085 ; RV64I-NEXT: mv a0, a1
2086 ; RV64I-NEXT: j .LBB28_3
2087 ; RV64I-NEXT: .LBB28_2:
2088 ; RV64I-NEXT: slti a0, s0, 0
2089 ; RV64I-NEXT: addi a0, a0, -1
2090 ; RV64I-NEXT: and a0, a0, s1
2091 ; RV64I-NEXT: .LBB28_3: # %start
2092 ; RV64I-NEXT: and a0, a0, a1
2093 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2094 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2095 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2096 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2097 ; RV64I-NEXT: addi sp, sp, 32
2098 ; RV64I-NEXT: ret
2099 start:
2100 %0 = tail call i16 @llvm.fptoui.sat.i16.f64(double %a)
2101 ret i16 %0
2102 }
2103 declare i16 @llvm.fptoui.sat.i16.f64(double)
2105 define signext i8 @fcvt_w_s_i8(double %a) nounwind {
2106 ; RV32IFD-LABEL: fcvt_w_s_i8:
2107 ; RV32IFD: # %bb.0:
2108 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
2109 ; RV32IFD-NEXT: ret
2110 ;
2111 ; RV64IFD-LABEL: fcvt_w_s_i8:
2112 ; RV64IFD: # %bb.0:
2113 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
2114 ; RV64IFD-NEXT: ret
2115 ;
2116 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_i8:
2117 ; RV32IZFINXZDINX: # %bb.0:
2118 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2119 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2120 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2121 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2122 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2123 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
2124 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2125 ; RV32IZFINXZDINX-NEXT: ret
2126 ;
2127 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_i8:
2128 ; RV64IZFINXZDINX: # %bb.0:
2129 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
2130 ; RV64IZFINXZDINX-NEXT: ret
2131 ;
2132 ; RV32I-LABEL: fcvt_w_s_i8:
2133 ; RV32I: # %bb.0:
2134 ; RV32I-NEXT: addi sp, sp, -16
2135 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2136 ; RV32I-NEXT: call __fixdfsi
2137 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2138 ; RV32I-NEXT: addi sp, sp, 16
2139 ; RV32I-NEXT: ret
2140 ;
2141 ; RV64I-LABEL: fcvt_w_s_i8:
2142 ; RV64I: # %bb.0:
2143 ; RV64I-NEXT: addi sp, sp, -16
2144 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2145 ; RV64I-NEXT: call __fixdfdi
2146 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2147 ; RV64I-NEXT: addi sp, sp, 16
2148 ; RV64I-NEXT: ret
2149 %1 = fptosi double %a to i8
2150 ret i8 %1
2151 }
2153 define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
2154 ; RV32IFD-LABEL: fcvt_w_s_sat_i8:
2155 ; RV32IFD: # %bb.0: # %start
2156 ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
2157 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
2158 ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
2159 ; RV32IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
2160 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
2161 ; RV32IFD-NEXT: neg a0, a0
2162 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
2163 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
2164 ; RV32IFD-NEXT: fcvt.w.d a1, fa5, rtz
2165 ; RV32IFD-NEXT: and a0, a0, a1
2166 ; RV32IFD-NEXT: ret
2167 ;
2168 ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
2169 ; RV64IFD: # %bb.0: # %start
2170 ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
2171 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
2172 ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
2173 ; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
2174 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
2175 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
2176 ; RV64IFD-NEXT: neg a0, a0
2177 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
2178 ; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
2179 ; RV64IFD-NEXT: and a0, a0, a1
2180 ; RV64IFD-NEXT: ret
2181 ;
2182 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
2183 ; RV32IZFINXZDINX: # %bb.0: # %start
2184 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2185 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2186 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2187 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2188 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2189 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
2190 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI30_0+4)(a2)
2191 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a2)
2192 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI30_1)
2193 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI30_1+4)(a4)
2194 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a4)
2195 ; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
2196 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
2197 ; RV32IZFINXZDINX-NEXT: neg a0, a0
2198 ; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
2199 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
2200 ; RV32IZFINXZDINX-NEXT: and a0, a0, a1
2201 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2202 ; RV32IZFINXZDINX-NEXT: ret
2203 ;
2204 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
2205 ; RV64IZFINXZDINX: # %bb.0: # %start
2206 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI30_0)
2207 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
2208 ; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
2209 ; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
2210 ; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
2211 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2212 ; RV64IZFINXZDINX-NEXT: neg a0, a0
2213 ; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
2214 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
2215 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
2216 ; RV64IZFINXZDINX-NEXT: ret
2217 ;
2218 ; RV32I-LABEL: fcvt_w_s_sat_i8:
2219 ; RV32I: # %bb.0: # %start
2220 ; RV32I-NEXT: addi sp, sp, -32
2221 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2222 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2223 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2224 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2225 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2226 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
2227 ; RV32I-NEXT: mv s0, a1
2228 ; RV32I-NEXT: mv s1, a0
2229 ; RV32I-NEXT: lui a3, 263676
2230 ; RV32I-NEXT: li a2, 0
2231 ; RV32I-NEXT: call __gtdf2
2232 ; RV32I-NEXT: mv s2, a0
2233 ; RV32I-NEXT: lui a3, 787968
2234 ; RV32I-NEXT: mv a0, s1
2235 ; RV32I-NEXT: mv a1, s0
2236 ; RV32I-NEXT: li a2, 0
2237 ; RV32I-NEXT: call __gedf2
2238 ; RV32I-NEXT: mv s4, a0
2239 ; RV32I-NEXT: mv a0, s1
2240 ; RV32I-NEXT: mv a1, s0
2241 ; RV32I-NEXT: call __fixdfsi
2242 ; RV32I-NEXT: mv s3, a0
2243 ; RV32I-NEXT: bgez s4, .LBB30_2
2244 ; RV32I-NEXT: # %bb.1: # %start
2245 ; RV32I-NEXT: li s3, -128
2246 ; RV32I-NEXT: .LBB30_2: # %start
2247 ; RV32I-NEXT: blez s2, .LBB30_4
2248 ; RV32I-NEXT: # %bb.3: # %start
2249 ; RV32I-NEXT: li s3, 127
2250 ; RV32I-NEXT: .LBB30_4: # %start
2251 ; RV32I-NEXT: mv a0, s1
2252 ; RV32I-NEXT: mv a1, s0
2253 ; RV32I-NEXT: mv a2, s1
2254 ; RV32I-NEXT: mv a3, s0
2255 ; RV32I-NEXT: call __unorddf2
2256 ; RV32I-NEXT: snez a0, a0
2257 ; RV32I-NEXT: addi a0, a0, -1
2258 ; RV32I-NEXT: and a0, a0, s3
2259 ; RV32I-NEXT: slli a0, a0, 24
2260 ; RV32I-NEXT: srai a0, a0, 24
2261 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2262 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2263 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2264 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2265 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2266 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
2267 ; RV32I-NEXT: addi sp, sp, 32
2268 ; RV32I-NEXT: ret
2269 ;
2270 ; RV64I-LABEL: fcvt_w_s_sat_i8:
2271 ; RV64I: # %bb.0: # %start
2272 ; RV64I-NEXT: addi sp, sp, -32
2273 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2274 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2275 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2276 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2277 ; RV64I-NEXT: mv s0, a0
2278 ; RV64I-NEXT: li a1, -509
2279 ; RV64I-NEXT: slli a1, a1, 53
2280 ; RV64I-NEXT: call __gedf2
2281 ; RV64I-NEXT: mv s2, a0
2282 ; RV64I-NEXT: mv a0, s0
2283 ; RV64I-NEXT: call __fixdfdi
2284 ; RV64I-NEXT: mv s1, a0
2285 ; RV64I-NEXT: bgez s2, .LBB30_2
2286 ; RV64I-NEXT: # %bb.1: # %start
2287 ; RV64I-NEXT: li s1, -128
2288 ; RV64I-NEXT: .LBB30_2: # %start
2289 ; RV64I-NEXT: lui a1, 65919
2290 ; RV64I-NEXT: slli a1, a1, 34
2291 ; RV64I-NEXT: mv a0, s0
2292 ; RV64I-NEXT: call __gtdf2
2293 ; RV64I-NEXT: blez a0, .LBB30_4
2294 ; RV64I-NEXT: # %bb.3: # %start
2295 ; RV64I-NEXT: li s1, 127
2296 ; RV64I-NEXT: .LBB30_4: # %start
2297 ; RV64I-NEXT: mv a0, s0
2298 ; RV64I-NEXT: mv a1, s0
2299 ; RV64I-NEXT: call __unorddf2
2300 ; RV64I-NEXT: snez a0, a0
2301 ; RV64I-NEXT: addi a0, a0, -1
2302 ; RV64I-NEXT: and a0, a0, s1
2303 ; RV64I-NEXT: slli a0, a0, 56
2304 ; RV64I-NEXT: srai a0, a0, 56
2305 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2306 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2307 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2308 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2309 ; RV64I-NEXT: addi sp, sp, 32
2310 ; RV64I-NEXT: ret
2311 start:
2312 %0 = tail call i8 @llvm.fptosi.sat.i8.f64(double %a)
2313 ret i8 %0
2314 }
2315 declare i8 @llvm.fptosi.sat.i8.f64(double)
2317 define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
2318 ;
2319 ;
2320 ; RV32IFD-LABEL: fcvt_wu_s_i8:
2321 ; RV32IFD: # %bb.0:
2322 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2323 ; RV32IFD-NEXT: ret
2324 ;
2325 ; RV64IFD-LABEL: fcvt_wu_s_i8:
2326 ; RV64IFD: # %bb.0:
2327 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
2328 ; RV64IFD-NEXT: ret
2329 ;
2330 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i8:
2331 ; RV32IZFINXZDINX: # %bb.0:
2332 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2333 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2334 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2335 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2336 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2337 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
2338 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2339 ; RV32IZFINXZDINX-NEXT: ret
2340 ;
2341 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i8:
2342 ; RV64IZFINXZDINX: # %bb.0:
2343 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
2344 ; RV64IZFINXZDINX-NEXT: ret
2345 ;
2346 ; RV32I-LABEL: fcvt_wu_s_i8:
2347 ; RV32I: # %bb.0:
2348 ; RV32I-NEXT: addi sp, sp, -16
2349 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2350 ; RV32I-NEXT: call __fixunsdfsi
2351 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2352 ; RV32I-NEXT: addi sp, sp, 16
2353 ; RV32I-NEXT: ret
2354 ;
2355 ; RV64I-LABEL: fcvt_wu_s_i8:
2356 ; RV64I: # %bb.0:
2357 ; RV64I-NEXT: addi sp, sp, -16
2358 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2359 ; RV64I-NEXT: call __fixunsdfdi
2360 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2361 ; RV64I-NEXT: addi sp, sp, 16
2362 ; RV64I-NEXT: ret
2363 %1 = fptoui double %a to i8
2364 ret i8 %1
2365 }
2367 define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
2368 ;
2369 ;
2370 ; RV32IFD-LABEL: fcvt_wu_s_sat_i8:
2371 ; RV32IFD: # %bb.0: # %start
2372 ; RV32IFD-NEXT: lui a0, %hi(.LCPI32_0)
2373 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI32_0)(a0)
2374 ; RV32IFD-NEXT: fcvt.d.w fa4, zero
2375 ; RV32IFD-NEXT: fmax.d fa4, fa0, fa4
2376 ; RV32IFD-NEXT: fmin.d fa5, fa4, fa5
2377 ; RV32IFD-NEXT: fcvt.wu.d a0, fa5, rtz
2378 ; RV32IFD-NEXT: ret
2379 ;
2380 ; RV64IFD-LABEL: fcvt_wu_s_sat_i8:
2381 ; RV64IFD: # %bb.0: # %start
2382 ; RV64IFD-NEXT: lui a0, %hi(.LCPI32_0)
2383 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI32_0)(a0)
2384 ; RV64IFD-NEXT: fmv.d.x fa4, zero
2385 ; RV64IFD-NEXT: fmax.d fa4, fa0, fa4
2386 ; RV64IFD-NEXT: fmin.d fa5, fa4, fa5
2387 ; RV64IFD-NEXT: fcvt.lu.d a0, fa5, rtz
2388 ; RV64IFD-NEXT: ret
2389 ;
2390 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
2391 ; RV32IZFINXZDINX: # %bb.0: # %start
2392 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2393 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2394 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2395 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2396 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2397 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
2398 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI32_0+4)(a2)
2399 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
2400 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
2401 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
2402 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2403 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
2404 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2405 ; RV32IZFINXZDINX-NEXT: ret
2406 ;
2407 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
2408 ; RV64IZFINXZDINX: # %bb.0: # %start
2409 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI32_0)
2410 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI32_0)(a1)
2411 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
2412 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
2413 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
2414 ; RV64IZFINXZDINX-NEXT: ret
2415 ;
2416 ; RV32I-LABEL: fcvt_wu_s_sat_i8:
2417 ; RV32I: # %bb.0: # %start
2418 ; RV32I-NEXT: addi sp, sp, -32
2419 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2420 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2421 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2422 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2423 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2424 ; RV32I-NEXT: mv s1, a1
2425 ; RV32I-NEXT: mv s2, a0
2426 ; RV32I-NEXT: lui a3, 263934
2427 ; RV32I-NEXT: li a2, 0
2428 ; RV32I-NEXT: call __gtdf2
2429 ; RV32I-NEXT: mv s3, a0
2430 ; RV32I-NEXT: mv a0, s2
2431 ; RV32I-NEXT: mv a1, s1
2432 ; RV32I-NEXT: li a2, 0
2433 ; RV32I-NEXT: li a3, 0
2434 ; RV32I-NEXT: call __gedf2
2435 ; RV32I-NEXT: mv s0, a0
2436 ; RV32I-NEXT: mv a0, s2
2437 ; RV32I-NEXT: mv a1, s1
2438 ; RV32I-NEXT: call __fixunsdfsi
2439 ; RV32I-NEXT: blez s3, .LBB32_2
2440 ; RV32I-NEXT: # %bb.1: # %start
2441 ; RV32I-NEXT: li a0, 255
2442 ; RV32I-NEXT: j .LBB32_3
2443 ; RV32I-NEXT: .LBB32_2:
2444 ; RV32I-NEXT: slti a1, s0, 0
2445 ; RV32I-NEXT: addi a1, a1, -1
2446 ; RV32I-NEXT: and a0, a1, a0
2447 ; RV32I-NEXT: .LBB32_3: # %start
2448 ; RV32I-NEXT: andi a0, a0, 255
2449 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2450 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2451 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2452 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2453 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2454 ; RV32I-NEXT: addi sp, sp, 32
2455 ; RV32I-NEXT: ret
2456 ;
2457 ; RV64I-LABEL: fcvt_wu_s_sat_i8:
2458 ; RV64I: # %bb.0: # %start
2459 ; RV64I-NEXT: addi sp, sp, -32
2460 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2461 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2462 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2463 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2464 ; RV64I-NEXT: mv s2, a0
2465 ; RV64I-NEXT: li a1, 0
2466 ; RV64I-NEXT: call __gedf2
2467 ; RV64I-NEXT: mv s0, a0
2468 ; RV64I-NEXT: mv a0, s2
2469 ; RV64I-NEXT: call __fixunsdfdi
2470 ; RV64I-NEXT: mv s1, a0
2471 ; RV64I-NEXT: lui a1, 131967
2472 ; RV64I-NEXT: slli a1, a1, 33
2473 ; RV64I-NEXT: mv a0, s2
2474 ; RV64I-NEXT: call __gtdf2
2475 ; RV64I-NEXT: blez a0, .LBB32_2
2476 ; RV64I-NEXT: # %bb.1: # %start
2477 ; RV64I-NEXT: li a0, 255
2478 ; RV64I-NEXT: j .LBB32_3
2479 ; RV64I-NEXT: .LBB32_2:
2480 ; RV64I-NEXT: slti a0, s0, 0
2481 ; RV64I-NEXT: addi a0, a0, -1
2482 ; RV64I-NEXT: and a0, a0, s1
2483 ; RV64I-NEXT: .LBB32_3: # %start
2484 ; RV64I-NEXT: andi a0, a0, 255
2485 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2486 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2487 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2488 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2489 ; RV64I-NEXT: addi sp, sp, 32
2490 ; RV64I-NEXT: ret
2491 start:
2492 %0 = tail call i8 @llvm.fptoui.sat.i8.f64(double %a)
2493 ret i8 %0
2494 }
2495 declare i8 @llvm.fptoui.sat.i8.f64(double)
2497 define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
2498 ; RV32IFD-LABEL: fcvt_wu_d_sat_zext:
2499 ; RV32IFD: # %bb.0: # %start
2500 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2501 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
2502 ; RV32IFD-NEXT: seqz a1, a1
2503 ; RV32IFD-NEXT: addi a1, a1, -1
2504 ; RV32IFD-NEXT: and a0, a1, a0
2505 ; RV32IFD-NEXT: ret
2506 ;
2507 ; RV64IFD-LABEL: fcvt_wu_d_sat_zext:
2508 ; RV64IFD: # %bb.0: # %start
2509 ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2510 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
2511 ; RV64IFD-NEXT: seqz a1, a1
2512 ; RV64IFD-NEXT: addi a1, a1, -1
2513 ; RV64IFD-NEXT: and a0, a0, a1
2514 ; RV64IFD-NEXT: slli a0, a0, 32
2515 ; RV64IFD-NEXT: srli a0, a0, 32
2516 ; RV64IFD-NEXT: ret
2517 ;
2518 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
2519 ; RV32IZFINXZDINX: # %bb.0: # %start
2520 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2521 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2522 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2523 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2524 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2525 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
2526 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
2527 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
2528 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
2529 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
2530 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2531 ; RV32IZFINXZDINX-NEXT: ret
2532 ;
2533 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
2534 ; RV64IZFINXZDINX: # %bb.0: # %start
2535 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
2536 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2537 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
2538 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
2539 ; RV64IZFINXZDINX-NEXT: and a0, a1, a0
2540 ; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
2541 ; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
2542 ; RV64IZFINXZDINX-NEXT: ret
2543 ;
2544 ; RV32I-LABEL: fcvt_wu_d_sat_zext:
2545 ; RV32I: # %bb.0: # %start
2546 ; RV32I-NEXT: addi sp, sp, -32
2547 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2548 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2549 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2550 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2551 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2552 ; RV32I-NEXT: mv s0, a1
2553 ; RV32I-NEXT: mv s1, a0
2554 ; RV32I-NEXT: lui a3, 270080
2555 ; RV32I-NEXT: addi a3, a3, -1
2556 ; RV32I-NEXT: lui a2, 1048064
2557 ; RV32I-NEXT: call __gtdf2
2558 ; RV32I-NEXT: sgtz a0, a0
2559 ; RV32I-NEXT: neg s2, a0
2560 ; RV32I-NEXT: mv a0, s1
2561 ; RV32I-NEXT: mv a1, s0
2562 ; RV32I-NEXT: li a2, 0
2563 ; RV32I-NEXT: li a3, 0
2564 ; RV32I-NEXT: call __gedf2
2565 ; RV32I-NEXT: slti a0, a0, 0
2566 ; RV32I-NEXT: addi s3, a0, -1
2567 ; RV32I-NEXT: mv a0, s1
2568 ; RV32I-NEXT: mv a1, s0
2569 ; RV32I-NEXT: call __fixunsdfsi
2570 ; RV32I-NEXT: and a0, s3, a0
2571 ; RV32I-NEXT: or a0, s2, a0
2572 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2573 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2574 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2575 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2576 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2577 ; RV32I-NEXT: addi sp, sp, 32
2578 ; RV32I-NEXT: ret
2579 ;
2580 ; RV64I-LABEL: fcvt_wu_d_sat_zext:
2581 ; RV64I: # %bb.0: # %start
2582 ; RV64I-NEXT: addi sp, sp, -32
2583 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2584 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2585 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2586 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2587 ; RV64I-NEXT: mv s2, a0
2588 ; RV64I-NEXT: li a1, 0
2589 ; RV64I-NEXT: call __gedf2
2590 ; RV64I-NEXT: mv s0, a0
2591 ; RV64I-NEXT: mv a0, s2
2592 ; RV64I-NEXT: call __fixunsdfdi
2593 ; RV64I-NEXT: mv s1, a0
2594 ; RV64I-NEXT: li a0, 1055
2595 ; RV64I-NEXT: slli a0, a0, 31
2596 ; RV64I-NEXT: addi a0, a0, -1
2597 ; RV64I-NEXT: slli a1, a0, 21
2598 ; RV64I-NEXT: mv a0, s2
2599 ; RV64I-NEXT: call __gtdf2
2600 ; RV64I-NEXT: blez a0, .LBB33_2
2601 ; RV64I-NEXT: # %bb.1: # %start
2602 ; RV64I-NEXT: li a0, -1
2603 ; RV64I-NEXT: srli a0, a0, 32
2604 ; RV64I-NEXT: j .LBB33_3
2605 ; RV64I-NEXT: .LBB33_2:
2606 ; RV64I-NEXT: slti a0, s0, 0
2607 ; RV64I-NEXT: addi a0, a0, -1
2608 ; RV64I-NEXT: and a0, a0, s1
2609 ; RV64I-NEXT: .LBB33_3: # %start
2610 ; RV64I-NEXT: slli a0, a0, 32
2611 ; RV64I-NEXT: srli a0, a0, 32
2612 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2613 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2614 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2615 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2616 ; RV64I-NEXT: addi sp, sp, 32
2617 ; RV64I-NEXT: ret
2618 start:
2619 %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
2620 ret i32 %0
2621 }
2623 define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
2624 ; CHECKIFD-LABEL: fcvt_w_d_sat_sext:
2625 ; CHECKIFD: # %bb.0: # %start
2626 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
2627 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
2628 ; CHECKIFD-NEXT: seqz a1, a1
2629 ; CHECKIFD-NEXT: addi a1, a1, -1
2630 ; CHECKIFD-NEXT: and a0, a1, a0
2631 ; CHECKIFD-NEXT: ret
2632 ;
2633 ; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
2634 ; RV32IZFINXZDINX: # %bb.0: # %start
2635 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2636 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
2637 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
2638 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
2639 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
2640 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
2641 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
2642 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
2643 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
2644 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
2645 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2646 ; RV32IZFINXZDINX-NEXT: ret
2647 ;
2648 ; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
2649 ; RV64IZFINXZDINX: # %bb.0: # %start
2650 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a1, a0, rtz
2651 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2652 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
2653 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
2654 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
2655 ; RV64IZFINXZDINX-NEXT: ret
2656 ;
2657 ; RV32I-LABEL: fcvt_w_d_sat_sext:
2658 ; RV32I: # %bb.0: # %start
2659 ; RV32I-NEXT: addi sp, sp, -32
2660 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2661 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2662 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2663 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2664 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2665 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
2666 ; RV32I-NEXT: mv s0, a1
2667 ; RV32I-NEXT: mv s1, a0
2668 ; RV32I-NEXT: lui a3, 269824
2669 ; RV32I-NEXT: addi a3, a3, -1
2670 ; RV32I-NEXT: lui a2, 1047552
2671 ; RV32I-NEXT: call __gtdf2
2672 ; RV32I-NEXT: mv s2, a0
2673 ; RV32I-NEXT: lui a3, 794112
2674 ; RV32I-NEXT: mv a0, s1
2675 ; RV32I-NEXT: mv a1, s0
2676 ; RV32I-NEXT: li a2, 0
2677 ; RV32I-NEXT: call __gedf2
2678 ; RV32I-NEXT: mv s4, a0
2679 ; RV32I-NEXT: mv a0, s1
2680 ; RV32I-NEXT: mv a1, s0
2681 ; RV32I-NEXT: call __fixdfsi
2682 ; RV32I-NEXT: mv s3, a0
2683 ; RV32I-NEXT: lui a0, 524288
2684 ; RV32I-NEXT: bgez s4, .LBB34_2
2685 ; RV32I-NEXT: # %bb.1: # %start
2686 ; RV32I-NEXT: lui s3, 524288
2687 ; RV32I-NEXT: .LBB34_2: # %start
2688 ; RV32I-NEXT: blez s2, .LBB34_4
2689 ; RV32I-NEXT: # %bb.3: # %start
2690 ; RV32I-NEXT: addi s3, a0, -1
2691 ; RV32I-NEXT: .LBB34_4: # %start
2692 ; RV32I-NEXT: mv a0, s1
2693 ; RV32I-NEXT: mv a1, s0
2694 ; RV32I-NEXT: mv a2, s1
2695 ; RV32I-NEXT: mv a3, s0
2696 ; RV32I-NEXT: call __unorddf2
2697 ; RV32I-NEXT: snez a0, a0
2698 ; RV32I-NEXT: addi a0, a0, -1
2699 ; RV32I-NEXT: and a0, a0, s3
2700 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2701 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2702 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2703 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2704 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2705 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
2706 ; RV32I-NEXT: addi sp, sp, 32
2707 ; RV32I-NEXT: ret
2708 ;
2709 ; RV64I-LABEL: fcvt_w_d_sat_sext:
2710 ; RV64I: # %bb.0: # %start
2711 ; RV64I-NEXT: addi sp, sp, -48
2712 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
2713 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
2714 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
2715 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
2716 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
2717 ; RV64I-NEXT: mv s0, a0
2718 ; RV64I-NEXT: li a1, -497
2719 ; RV64I-NEXT: slli a1, a1, 53
2720 ; RV64I-NEXT: call __gedf2
2721 ; RV64I-NEXT: mv s2, a0
2722 ; RV64I-NEXT: mv a0, s0
2723 ; RV64I-NEXT: call __fixdfdi
2724 ; RV64I-NEXT: mv s1, a0
2725 ; RV64I-NEXT: lui s3, 524288
2726 ; RV64I-NEXT: bgez s2, .LBB34_2
2727 ; RV64I-NEXT: # %bb.1: # %start
2728 ; RV64I-NEXT: lui s1, 524288
2729 ; RV64I-NEXT: .LBB34_2: # %start
2730 ; RV64I-NEXT: li a0, 527
2731 ; RV64I-NEXT: slli a0, a0, 31
2732 ; RV64I-NEXT: addi a0, a0, -1
2733 ; RV64I-NEXT: slli a1, a0, 22
2734 ; RV64I-NEXT: mv a0, s0
2735 ; RV64I-NEXT: call __gtdf2
2736 ; RV64I-NEXT: blez a0, .LBB34_4
2737 ; RV64I-NEXT: # %bb.3: # %start
2738 ; RV64I-NEXT: addi s1, s3, -1
2739 ; RV64I-NEXT: .LBB34_4: # %start
2740 ; RV64I-NEXT: mv a0, s0
2741 ; RV64I-NEXT: mv a1, s0
2742 ; RV64I-NEXT: call __unorddf2
2743 ; RV64I-NEXT: snez a0, a0
2744 ; RV64I-NEXT: addi a0, a0, -1
2745 ; RV64I-NEXT: and a0, a0, s1
2746 ; RV64I-NEXT: sext.w a0, a0
2747 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
2748 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
2749 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
2750 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
2751 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
2752 ; RV64I-NEXT: addi sp, sp, 48
2753 ; RV64I-NEXT: ret
2754 start:
2755 %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
2756 ret i32 %0
2757 }