| blob | 3ae2e997019caa138c71a3054d056514f2cfad9d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -disable-strictnode-mutation -target-abi=ilp32d \
4 ; RUN: | FileCheck -check-prefix=CHECKIFD %s
5 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
6 ; RUN: -disable-strictnode-mutation -target-abi=lp64d \
7 ; RUN: | FileCheck -check-prefix=CHECKIFD %s
8 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
9 ; RUN: -disable-strictnode-mutation -target-abi=ilp32 \
10 ; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
11 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
12 ; RUN: -disable-strictnode-mutation -target-abi=lp64 \
13 ; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
14 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
15 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
16 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
17 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
19 define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp {
20 ; CHECKIFD-LABEL: fcmp_oeq:
21 ; CHECKIFD: # %bb.0:
22 ; CHECKIFD-NEXT: feq.d a0, fa0, fa1
23 ; CHECKIFD-NEXT: ret
24 ;
25 ; RV32IZFINXZDINX-LABEL: fcmp_oeq:
26 ; RV32IZFINXZDINX: # %bb.0:
27 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
28 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
29 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
30 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
31 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
32 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
33 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
34 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
35 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
36 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
37 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
38 ; RV32IZFINXZDINX-NEXT: ret
39 ;
40 ; RV64IZFINXZDINX-LABEL: fcmp_oeq:
41 ; RV64IZFINXZDINX: # %bb.0:
42 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a1
43 ; RV64IZFINXZDINX-NEXT: ret
44 ;
45 ; RV32I-LABEL: fcmp_oeq:
46 ; RV32I: # %bb.0:
47 ; RV32I-NEXT: addi sp, sp, -16
48 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
49 ; RV32I-NEXT: call __eqdf2
50 ; RV32I-NEXT: seqz a0, a0
51 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
52 ; RV32I-NEXT: addi sp, sp, 16
53 ; RV32I-NEXT: ret
54 ;
55 ; RV64I-LABEL: fcmp_oeq:
56 ; RV64I: # %bb.0:
57 ; RV64I-NEXT: addi sp, sp, -16
58 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
59 ; RV64I-NEXT: call __eqdf2
60 ; RV64I-NEXT: seqz a0, a0
61 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
62 ; RV64I-NEXT: addi sp, sp, 16
63 ; RV64I-NEXT: ret
64 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
65 %2 = zext i1 %1 to i32
66 ret i32 %2
67 }
68 declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
70 define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
71 ; CHECKIFD-LABEL: fcmp_ogt:
72 ; CHECKIFD: # %bb.0:
73 ; CHECKIFD-NEXT: frflags a1
74 ; CHECKIFD-NEXT: flt.d a0, fa1, fa0
75 ; CHECKIFD-NEXT: fsflags a1
76 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
77 ; CHECKIFD-NEXT: ret
78 ;
79 ; RV32IZFINXZDINX-LABEL: fcmp_ogt:
80 ; RV32IZFINXZDINX: # %bb.0:
81 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
82 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
83 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
84 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
85 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
86 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
87 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
88 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
89 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
90 ; RV32IZFINXZDINX-NEXT: csrr a1, fflags
91 ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a4
92 ; RV32IZFINXZDINX-NEXT: csrw fflags, a1
93 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
94 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
95 ; RV32IZFINXZDINX-NEXT: ret
96 ;
97 ; RV64IZFINXZDINX-LABEL: fcmp_ogt:
98 ; RV64IZFINXZDINX: # %bb.0:
99 ; RV64IZFINXZDINX-NEXT: csrr a3, fflags
100 ; RV64IZFINXZDINX-NEXT: flt.d a2, a1, a0
101 ; RV64IZFINXZDINX-NEXT: csrw fflags, a3
102 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
103 ; RV64IZFINXZDINX-NEXT: mv a0, a2
104 ; RV64IZFINXZDINX-NEXT: ret
105 ;
106 ; RV32I-LABEL: fcmp_ogt:
107 ; RV32I: # %bb.0:
108 ; RV32I-NEXT: addi sp, sp, -16
109 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
110 ; RV32I-NEXT: call __gtdf2
111 ; RV32I-NEXT: sgtz a0, a0
112 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
113 ; RV32I-NEXT: addi sp, sp, 16
114 ; RV32I-NEXT: ret
115 ;
116 ; RV64I-LABEL: fcmp_ogt:
117 ; RV64I: # %bb.0:
118 ; RV64I-NEXT: addi sp, sp, -16
119 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
120 ; RV64I-NEXT: call __gtdf2
121 ; RV64I-NEXT: sgtz a0, a0
122 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
123 ; RV64I-NEXT: addi sp, sp, 16
124 ; RV64I-NEXT: ret
125 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
126 %2 = zext i1 %1 to i32
127 ret i32 %2
128 }
130 define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
131 ; CHECKIFD-LABEL: fcmp_oge:
132 ; CHECKIFD: # %bb.0:
133 ; CHECKIFD-NEXT: frflags a1
134 ; CHECKIFD-NEXT: fle.d a0, fa1, fa0
135 ; CHECKIFD-NEXT: fsflags a1
136 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
137 ; CHECKIFD-NEXT: ret
138 ;
139 ; RV32IZFINXZDINX-LABEL: fcmp_oge:
140 ; RV32IZFINXZDINX: # %bb.0:
141 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
142 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
143 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
144 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
145 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
146 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
147 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
148 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
149 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
150 ; RV32IZFINXZDINX-NEXT: csrr a1, fflags
151 ; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a4
152 ; RV32IZFINXZDINX-NEXT: csrw fflags, a1
153 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
154 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
155 ; RV32IZFINXZDINX-NEXT: ret
156 ;
157 ; RV64IZFINXZDINX-LABEL: fcmp_oge:
158 ; RV64IZFINXZDINX: # %bb.0:
159 ; RV64IZFINXZDINX-NEXT: csrr a3, fflags
160 ; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
161 ; RV64IZFINXZDINX-NEXT: csrw fflags, a3
162 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
163 ; RV64IZFINXZDINX-NEXT: mv a0, a2
164 ; RV64IZFINXZDINX-NEXT: ret
165 ;
166 ; RV32I-LABEL: fcmp_oge:
167 ; RV32I: # %bb.0:
168 ; RV32I-NEXT: addi sp, sp, -16
169 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
170 ; RV32I-NEXT: call __gedf2
171 ; RV32I-NEXT: slti a0, a0, 0
172 ; RV32I-NEXT: xori a0, a0, 1
173 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
174 ; RV32I-NEXT: addi sp, sp, 16
175 ; RV32I-NEXT: ret
176 ;
177 ; RV64I-LABEL: fcmp_oge:
178 ; RV64I: # %bb.0:
179 ; RV64I-NEXT: addi sp, sp, -16
180 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
181 ; RV64I-NEXT: call __gedf2
182 ; RV64I-NEXT: slti a0, a0, 0
183 ; RV64I-NEXT: xori a0, a0, 1
184 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
185 ; RV64I-NEXT: addi sp, sp, 16
186 ; RV64I-NEXT: ret
187 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
188 %2 = zext i1 %1 to i32
189 ret i32 %2
190 }
192 define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
193 ; CHECKIFD-LABEL: fcmp_olt:
194 ; CHECKIFD: # %bb.0:
195 ; CHECKIFD-NEXT: frflags a1
196 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
197 ; CHECKIFD-NEXT: fsflags a1
198 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
199 ; CHECKIFD-NEXT: ret
200 ;
201 ; RV32IZFINXZDINX-LABEL: fcmp_olt:
202 ; RV32IZFINXZDINX: # %bb.0:
203 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
204 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
205 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
206 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
207 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
208 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
209 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
210 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
211 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
212 ; RV32IZFINXZDINX-NEXT: csrr a1, fflags
213 ; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a2
214 ; RV32IZFINXZDINX-NEXT: csrw fflags, a1
215 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
216 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
217 ; RV32IZFINXZDINX-NEXT: ret
218 ;
219 ; RV64IZFINXZDINX-LABEL: fcmp_olt:
220 ; RV64IZFINXZDINX: # %bb.0:
221 ; RV64IZFINXZDINX-NEXT: csrr a3, fflags
222 ; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
223 ; RV64IZFINXZDINX-NEXT: csrw fflags, a3
224 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
225 ; RV64IZFINXZDINX-NEXT: mv a0, a2
226 ; RV64IZFINXZDINX-NEXT: ret
227 ;
228 ; RV32I-LABEL: fcmp_olt:
229 ; RV32I: # %bb.0:
230 ; RV32I-NEXT: addi sp, sp, -16
231 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
232 ; RV32I-NEXT: call __ltdf2
233 ; RV32I-NEXT: slti a0, a0, 0
234 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
235 ; RV32I-NEXT: addi sp, sp, 16
236 ; RV32I-NEXT: ret
237 ;
238 ; RV64I-LABEL: fcmp_olt:
239 ; RV64I: # %bb.0:
240 ; RV64I-NEXT: addi sp, sp, -16
241 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
242 ; RV64I-NEXT: call __ltdf2
243 ; RV64I-NEXT: slti a0, a0, 0
244 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
245 ; RV64I-NEXT: addi sp, sp, 16
246 ; RV64I-NEXT: ret
247 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
248 %2 = zext i1 %1 to i32
249 ret i32 %2
250 }
252 define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
253 ; CHECKIFD-LABEL: fcmp_ole:
254 ; CHECKIFD: # %bb.0:
255 ; CHECKIFD-NEXT: frflags a1
256 ; CHECKIFD-NEXT: fle.d a0, fa0, fa1
257 ; CHECKIFD-NEXT: fsflags a1
258 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
259 ; CHECKIFD-NEXT: ret
260 ;
261 ; RV32IZFINXZDINX-LABEL: fcmp_ole:
262 ; RV32IZFINXZDINX: # %bb.0:
263 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
264 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
265 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
266 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
267 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
268 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
269 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
270 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
271 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
272 ; RV32IZFINXZDINX-NEXT: csrr a1, fflags
273 ; RV32IZFINXZDINX-NEXT: fle.d a0, a4, a2
274 ; RV32IZFINXZDINX-NEXT: csrw fflags, a1
275 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
276 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
277 ; RV32IZFINXZDINX-NEXT: ret
278 ;
279 ; RV64IZFINXZDINX-LABEL: fcmp_ole:
280 ; RV64IZFINXZDINX: # %bb.0:
281 ; RV64IZFINXZDINX-NEXT: csrr a3, fflags
282 ; RV64IZFINXZDINX-NEXT: fle.d a2, a0, a1
283 ; RV64IZFINXZDINX-NEXT: csrw fflags, a3
284 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
285 ; RV64IZFINXZDINX-NEXT: mv a0, a2
286 ; RV64IZFINXZDINX-NEXT: ret
287 ;
288 ; RV32I-LABEL: fcmp_ole:
289 ; RV32I: # %bb.0:
290 ; RV32I-NEXT: addi sp, sp, -16
291 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
292 ; RV32I-NEXT: call __ledf2
293 ; RV32I-NEXT: slti a0, a0, 1
294 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
295 ; RV32I-NEXT: addi sp, sp, 16
296 ; RV32I-NEXT: ret
297 ;
298 ; RV64I-LABEL: fcmp_ole:
299 ; RV64I: # %bb.0:
300 ; RV64I-NEXT: addi sp, sp, -16
301 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
302 ; RV64I-NEXT: call __ledf2
303 ; RV64I-NEXT: slti a0, a0, 1
304 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
305 ; RV64I-NEXT: addi sp, sp, 16
306 ; RV64I-NEXT: ret
307 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
308 %2 = zext i1 %1 to i32
309 ret i32 %2
310 }
312 ; FIXME: We only need one frflags before the two flts and one fsflags after the
313 ; two flts.
314 define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
315 ; CHECKIFD-LABEL: fcmp_one:
316 ; CHECKIFD: # %bb.0:
317 ; CHECKIFD-NEXT: frflags a0
318 ; CHECKIFD-NEXT: flt.d a1, fa0, fa1
319 ; CHECKIFD-NEXT: fsflags a0
320 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
321 ; CHECKIFD-NEXT: frflags a0
322 ; CHECKIFD-NEXT: flt.d a2, fa1, fa0
323 ; CHECKIFD-NEXT: fsflags a0
324 ; CHECKIFD-NEXT: or a0, a2, a1
325 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
326 ; CHECKIFD-NEXT: ret
327 ;
328 ; RV32IZFINXZDINX-LABEL: fcmp_one:
329 ; RV32IZFINXZDINX: # %bb.0:
330 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
331 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
332 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
333 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
334 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
335 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
336 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
337 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
338 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
339 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
340 ; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
341 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
342 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
343 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
344 ; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a4
345 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
346 ; RV32IZFINXZDINX-NEXT: or a0, a6, a1
347 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
348 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
349 ; RV32IZFINXZDINX-NEXT: ret
350 ;
351 ; RV64IZFINXZDINX-LABEL: fcmp_one:
352 ; RV64IZFINXZDINX: # %bb.0:
353 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
354 ; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
355 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
356 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
357 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
358 ; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
359 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
360 ; RV64IZFINXZDINX-NEXT: or a2, a4, a3
361 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
362 ; RV64IZFINXZDINX-NEXT: mv a0, a2
363 ; RV64IZFINXZDINX-NEXT: ret
364 ;
365 ; RV32I-LABEL: fcmp_one:
366 ; RV32I: # %bb.0:
367 ; RV32I-NEXT: addi sp, sp, -32
368 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
369 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
370 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
371 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
372 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
373 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
374 ; RV32I-NEXT: mv s0, a3
375 ; RV32I-NEXT: mv s1, a2
376 ; RV32I-NEXT: mv s2, a1
377 ; RV32I-NEXT: mv s3, a0
378 ; RV32I-NEXT: call __eqdf2
379 ; RV32I-NEXT: snez s4, a0
380 ; RV32I-NEXT: mv a0, s3
381 ; RV32I-NEXT: mv a1, s2
382 ; RV32I-NEXT: mv a2, s1
383 ; RV32I-NEXT: mv a3, s0
384 ; RV32I-NEXT: call __unorddf2
385 ; RV32I-NEXT: seqz a0, a0
386 ; RV32I-NEXT: and a0, a0, s4
387 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
388 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
389 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
390 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
391 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
392 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
393 ; RV32I-NEXT: addi sp, sp, 32
394 ; RV32I-NEXT: ret
395 ;
396 ; RV64I-LABEL: fcmp_one:
397 ; RV64I: # %bb.0:
398 ; RV64I-NEXT: addi sp, sp, -32
399 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
400 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
401 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
402 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
403 ; RV64I-NEXT: mv s0, a1
404 ; RV64I-NEXT: mv s1, a0
405 ; RV64I-NEXT: call __eqdf2
406 ; RV64I-NEXT: snez s2, a0
407 ; RV64I-NEXT: mv a0, s1
408 ; RV64I-NEXT: mv a1, s0
409 ; RV64I-NEXT: call __unorddf2
410 ; RV64I-NEXT: seqz a0, a0
411 ; RV64I-NEXT: and a0, a0, s2
412 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
413 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
414 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
415 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
416 ; RV64I-NEXT: addi sp, sp, 32
417 ; RV64I-NEXT: ret
418 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"one", metadata !"fpexcept.strict") strictfp
419 %2 = zext i1 %1 to i32
420 ret i32 %2
421 }
423 define i32 @fcmp_ord(double %a, double %b) nounwind strictfp {
424 ; CHECKIFD-LABEL: fcmp_ord:
425 ; CHECKIFD: # %bb.0:
426 ; CHECKIFD-NEXT: feq.d a0, fa1, fa1
427 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
428 ; CHECKIFD-NEXT: and a0, a1, a0
429 ; CHECKIFD-NEXT: ret
430 ;
431 ; RV32IZFINXZDINX-LABEL: fcmp_ord:
432 ; RV32IZFINXZDINX: # %bb.0:
433 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
434 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
435 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
436 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
437 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
438 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
439 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
440 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
441 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
442 ; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
443 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
444 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
445 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
446 ; RV32IZFINXZDINX-NEXT: ret
447 ;
448 ; RV64IZFINXZDINX-LABEL: fcmp_ord:
449 ; RV64IZFINXZDINX: # %bb.0:
450 ; RV64IZFINXZDINX-NEXT: feq.d a1, a1, a1
451 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
452 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
453 ; RV64IZFINXZDINX-NEXT: ret
454 ;
455 ; RV32I-LABEL: fcmp_ord:
456 ; RV32I: # %bb.0:
457 ; RV32I-NEXT: addi sp, sp, -16
458 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
459 ; RV32I-NEXT: call __unorddf2
460 ; RV32I-NEXT: seqz a0, a0
461 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
462 ; RV32I-NEXT: addi sp, sp, 16
463 ; RV32I-NEXT: ret
464 ;
465 ; RV64I-LABEL: fcmp_ord:
466 ; RV64I: # %bb.0:
467 ; RV64I-NEXT: addi sp, sp, -16
468 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
469 ; RV64I-NEXT: call __unorddf2
470 ; RV64I-NEXT: seqz a0, a0
471 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
472 ; RV64I-NEXT: addi sp, sp, 16
473 ; RV64I-NEXT: ret
474 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
475 %2 = zext i1 %1 to i32
476 ret i32 %2
477 }
479 ; FIXME: We only need one frflags before the two flts and one fsflags after the
480 ; two flts.
481 define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
482 ; CHECKIFD-LABEL: fcmp_ueq:
483 ; CHECKIFD: # %bb.0:
484 ; CHECKIFD-NEXT: frflags a0
485 ; CHECKIFD-NEXT: flt.d a1, fa0, fa1
486 ; CHECKIFD-NEXT: fsflags a0
487 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
488 ; CHECKIFD-NEXT: frflags a0
489 ; CHECKIFD-NEXT: flt.d a2, fa1, fa0
490 ; CHECKIFD-NEXT: fsflags a0
491 ; CHECKIFD-NEXT: or a1, a2, a1
492 ; CHECKIFD-NEXT: xori a0, a1, 1
493 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
494 ; CHECKIFD-NEXT: ret
495 ;
496 ; RV32IZFINXZDINX-LABEL: fcmp_ueq:
497 ; RV32IZFINXZDINX: # %bb.0:
498 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
499 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
500 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
501 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
502 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
503 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
504 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
505 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
506 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
507 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
508 ; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
509 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
510 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
511 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
512 ; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a4
513 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
514 ; RV32IZFINXZDINX-NEXT: or a0, a6, a1
515 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
516 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
517 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
518 ; RV32IZFINXZDINX-NEXT: ret
519 ;
520 ; RV64IZFINXZDINX-LABEL: fcmp_ueq:
521 ; RV64IZFINXZDINX: # %bb.0:
522 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
523 ; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
524 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
525 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
526 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
527 ; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
528 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
529 ; RV64IZFINXZDINX-NEXT: or a3, a4, a3
530 ; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
531 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
532 ; RV64IZFINXZDINX-NEXT: mv a0, a2
533 ; RV64IZFINXZDINX-NEXT: ret
534 ;
535 ; RV32I-LABEL: fcmp_ueq:
536 ; RV32I: # %bb.0:
537 ; RV32I-NEXT: addi sp, sp, -32
538 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
539 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
540 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
541 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
542 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
543 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
544 ; RV32I-NEXT: mv s0, a3
545 ; RV32I-NEXT: mv s1, a2
546 ; RV32I-NEXT: mv s2, a1
547 ; RV32I-NEXT: mv s3, a0
548 ; RV32I-NEXT: call __eqdf2
549 ; RV32I-NEXT: seqz s4, a0
550 ; RV32I-NEXT: mv a0, s3
551 ; RV32I-NEXT: mv a1, s2
552 ; RV32I-NEXT: mv a2, s1
553 ; RV32I-NEXT: mv a3, s0
554 ; RV32I-NEXT: call __unorddf2
555 ; RV32I-NEXT: snez a0, a0
556 ; RV32I-NEXT: or a0, a0, s4
557 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
558 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
559 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
560 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
561 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
562 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
563 ; RV32I-NEXT: addi sp, sp, 32
564 ; RV32I-NEXT: ret
565 ;
566 ; RV64I-LABEL: fcmp_ueq:
567 ; RV64I: # %bb.0:
568 ; RV64I-NEXT: addi sp, sp, -32
569 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
570 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
571 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
572 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
573 ; RV64I-NEXT: mv s0, a1
574 ; RV64I-NEXT: mv s1, a0
575 ; RV64I-NEXT: call __eqdf2
576 ; RV64I-NEXT: seqz s2, a0
577 ; RV64I-NEXT: mv a0, s1
578 ; RV64I-NEXT: mv a1, s0
579 ; RV64I-NEXT: call __unorddf2
580 ; RV64I-NEXT: snez a0, a0
581 ; RV64I-NEXT: or a0, a0, s2
582 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
583 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
584 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
585 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
586 ; RV64I-NEXT: addi sp, sp, 32
587 ; RV64I-NEXT: ret
588 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
589 %2 = zext i1 %1 to i32
590 ret i32 %2
591 }
593 define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
594 ; CHECKIFD-LABEL: fcmp_ugt:
595 ; CHECKIFD: # %bb.0:
596 ; CHECKIFD-NEXT: frflags a0
597 ; CHECKIFD-NEXT: fle.d a1, fa0, fa1
598 ; CHECKIFD-NEXT: fsflags a0
599 ; CHECKIFD-NEXT: xori a0, a1, 1
600 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
601 ; CHECKIFD-NEXT: ret
602 ;
603 ; RV32IZFINXZDINX-LABEL: fcmp_ugt:
604 ; RV32IZFINXZDINX: # %bb.0:
605 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
606 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
607 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
608 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
609 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
610 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
611 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
612 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
613 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
614 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
615 ; RV32IZFINXZDINX-NEXT: fle.d a1, a4, a2
616 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
617 ; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
618 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
619 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
620 ; RV32IZFINXZDINX-NEXT: ret
621 ;
622 ; RV64IZFINXZDINX-LABEL: fcmp_ugt:
623 ; RV64IZFINXZDINX: # %bb.0:
624 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
625 ; RV64IZFINXZDINX-NEXT: fle.d a3, a0, a1
626 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
627 ; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
628 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
629 ; RV64IZFINXZDINX-NEXT: mv a0, a2
630 ; RV64IZFINXZDINX-NEXT: ret
631 ;
632 ; RV32I-LABEL: fcmp_ugt:
633 ; RV32I: # %bb.0:
634 ; RV32I-NEXT: addi sp, sp, -16
635 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
636 ; RV32I-NEXT: call __ledf2
637 ; RV32I-NEXT: sgtz a0, a0
638 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
639 ; RV32I-NEXT: addi sp, sp, 16
640 ; RV32I-NEXT: ret
641 ;
642 ; RV64I-LABEL: fcmp_ugt:
643 ; RV64I: # %bb.0:
644 ; RV64I-NEXT: addi sp, sp, -16
645 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
646 ; RV64I-NEXT: call __ledf2
647 ; RV64I-NEXT: sgtz a0, a0
648 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
649 ; RV64I-NEXT: addi sp, sp, 16
650 ; RV64I-NEXT: ret
651 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
652 %2 = zext i1 %1 to i32
653 ret i32 %2
654 }
656 define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
657 ; CHECKIFD-LABEL: fcmp_uge:
658 ; CHECKIFD: # %bb.0:
659 ; CHECKIFD-NEXT: frflags a0
660 ; CHECKIFD-NEXT: flt.d a1, fa0, fa1
661 ; CHECKIFD-NEXT: fsflags a0
662 ; CHECKIFD-NEXT: xori a0, a1, 1
663 ; CHECKIFD-NEXT: feq.d zero, fa0, fa1
664 ; CHECKIFD-NEXT: ret
665 ;
666 ; RV32IZFINXZDINX-LABEL: fcmp_uge:
667 ; RV32IZFINXZDINX: # %bb.0:
668 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
669 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
670 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
671 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
672 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
673 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
674 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
675 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
676 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
677 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
678 ; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
679 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
680 ; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
681 ; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
682 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
683 ; RV32IZFINXZDINX-NEXT: ret
684 ;
685 ; RV64IZFINXZDINX-LABEL: fcmp_uge:
686 ; RV64IZFINXZDINX: # %bb.0:
687 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
688 ; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
689 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
690 ; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
691 ; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
692 ; RV64IZFINXZDINX-NEXT: mv a0, a2
693 ; RV64IZFINXZDINX-NEXT: ret
694 ;
695 ; RV32I-LABEL: fcmp_uge:
696 ; RV32I: # %bb.0:
697 ; RV32I-NEXT: addi sp, sp, -16
698 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
699 ; RV32I-NEXT: call __ltdf2
700 ; RV32I-NEXT: slti a0, a0, 0
701 ; RV32I-NEXT: xori a0, a0, 1
702 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
703 ; RV32I-NEXT: addi sp, sp, 16
704 ; RV32I-NEXT: ret
705 ;
706 ; RV64I-LABEL: fcmp_uge:
707 ; RV64I: # %bb.0:
708 ; RV64I-NEXT: addi sp, sp, -16
709 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
710 ; RV64I-NEXT: call __ltdf2
711 ; RV64I-NEXT: slti a0, a0, 0
712 ; RV64I-NEXT: xori a0, a0, 1
713 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
714 ; RV64I-NEXT: addi sp, sp, 16
715 ; RV64I-NEXT: ret
716 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
717 %2 = zext i1 %1 to i32
718 ret i32 %2
719 }
721 define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
722 ; CHECKIFD-LABEL: fcmp_ult:
723 ; CHECKIFD: # %bb.0:
724 ; CHECKIFD-NEXT: frflags a0
725 ; CHECKIFD-NEXT: fle.d a1, fa1, fa0
726 ; CHECKIFD-NEXT: fsflags a0
727 ; CHECKIFD-NEXT: xori a0, a1, 1
728 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
729 ; CHECKIFD-NEXT: ret
730 ;
731 ; RV32IZFINXZDINX-LABEL: fcmp_ult:
732 ; RV32IZFINXZDINX: # %bb.0:
733 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
734 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
735 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
736 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
737 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
738 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
739 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
740 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
741 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
742 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
743 ; RV32IZFINXZDINX-NEXT: fle.d a1, a2, a4
744 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
745 ; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
746 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
747 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
748 ; RV32IZFINXZDINX-NEXT: ret
749 ;
750 ; RV64IZFINXZDINX-LABEL: fcmp_ult:
751 ; RV64IZFINXZDINX: # %bb.0:
752 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
753 ; RV64IZFINXZDINX-NEXT: fle.d a3, a1, a0
754 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
755 ; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
756 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
757 ; RV64IZFINXZDINX-NEXT: mv a0, a2
758 ; RV64IZFINXZDINX-NEXT: ret
759 ;
760 ; RV32I-LABEL: fcmp_ult:
761 ; RV32I: # %bb.0:
762 ; RV32I-NEXT: addi sp, sp, -16
763 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
764 ; RV32I-NEXT: call __gedf2
765 ; RV32I-NEXT: slti a0, a0, 0
766 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
767 ; RV32I-NEXT: addi sp, sp, 16
768 ; RV32I-NEXT: ret
769 ;
770 ; RV64I-LABEL: fcmp_ult:
771 ; RV64I: # %bb.0:
772 ; RV64I-NEXT: addi sp, sp, -16
773 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
774 ; RV64I-NEXT: call __gedf2
775 ; RV64I-NEXT: slti a0, a0, 0
776 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
777 ; RV64I-NEXT: addi sp, sp, 16
778 ; RV64I-NEXT: ret
779 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
780 %2 = zext i1 %1 to i32
781 ret i32 %2
782 }
784 define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
785 ; CHECKIFD-LABEL: fcmp_ule:
786 ; CHECKIFD: # %bb.0:
787 ; CHECKIFD-NEXT: frflags a0
788 ; CHECKIFD-NEXT: flt.d a1, fa1, fa0
789 ; CHECKIFD-NEXT: fsflags a0
790 ; CHECKIFD-NEXT: xori a0, a1, 1
791 ; CHECKIFD-NEXT: feq.d zero, fa1, fa0
792 ; CHECKIFD-NEXT: ret
793 ;
794 ; RV32IZFINXZDINX-LABEL: fcmp_ule:
795 ; RV32IZFINXZDINX: # %bb.0:
796 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
797 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
798 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
799 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
800 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
801 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
802 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
803 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
804 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
805 ; RV32IZFINXZDINX-NEXT: csrr a0, fflags
806 ; RV32IZFINXZDINX-NEXT: flt.d a1, a2, a4
807 ; RV32IZFINXZDINX-NEXT: csrw fflags, a0
808 ; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
809 ; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
810 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
811 ; RV32IZFINXZDINX-NEXT: ret
812 ;
813 ; RV64IZFINXZDINX-LABEL: fcmp_ule:
814 ; RV64IZFINXZDINX: # %bb.0:
815 ; RV64IZFINXZDINX-NEXT: csrr a2, fflags
816 ; RV64IZFINXZDINX-NEXT: flt.d a3, a1, a0
817 ; RV64IZFINXZDINX-NEXT: csrw fflags, a2
818 ; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
819 ; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
820 ; RV64IZFINXZDINX-NEXT: mv a0, a2
821 ; RV64IZFINXZDINX-NEXT: ret
822 ;
823 ; RV32I-LABEL: fcmp_ule:
824 ; RV32I: # %bb.0:
825 ; RV32I-NEXT: addi sp, sp, -16
826 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
827 ; RV32I-NEXT: call __gtdf2
828 ; RV32I-NEXT: slti a0, a0, 1
829 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
830 ; RV32I-NEXT: addi sp, sp, 16
831 ; RV32I-NEXT: ret
832 ;
833 ; RV64I-LABEL: fcmp_ule:
834 ; RV64I: # %bb.0:
835 ; RV64I-NEXT: addi sp, sp, -16
836 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
837 ; RV64I-NEXT: call __gtdf2
838 ; RV64I-NEXT: slti a0, a0, 1
839 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
840 ; RV64I-NEXT: addi sp, sp, 16
841 ; RV64I-NEXT: ret
842 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
843 %2 = zext i1 %1 to i32
844 ret i32 %2
845 }
847 define i32 @fcmp_une(double %a, double %b) nounwind strictfp {
848 ; CHECKIFD-LABEL: fcmp_une:
849 ; CHECKIFD: # %bb.0:
850 ; CHECKIFD-NEXT: feq.d a0, fa0, fa1
851 ; CHECKIFD-NEXT: xori a0, a0, 1
852 ; CHECKIFD-NEXT: ret
853 ;
854 ; RV32IZFINXZDINX-LABEL: fcmp_une:
855 ; RV32IZFINXZDINX: # %bb.0:
856 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
857 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
858 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
859 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
860 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
861 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
862 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
863 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
864 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
865 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
866 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
867 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
868 ; RV32IZFINXZDINX-NEXT: ret
869 ;
870 ; RV64IZFINXZDINX-LABEL: fcmp_une:
871 ; RV64IZFINXZDINX: # %bb.0:
872 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a1
873 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
874 ; RV64IZFINXZDINX-NEXT: ret
875 ;
876 ; RV32I-LABEL: fcmp_une:
877 ; RV32I: # %bb.0:
878 ; RV32I-NEXT: addi sp, sp, -16
879 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
880 ; RV32I-NEXT: call __nedf2
881 ; RV32I-NEXT: snez a0, a0
882 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
883 ; RV32I-NEXT: addi sp, sp, 16
884 ; RV32I-NEXT: ret
885 ;
886 ; RV64I-LABEL: fcmp_une:
887 ; RV64I: # %bb.0:
888 ; RV64I-NEXT: addi sp, sp, -16
889 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
890 ; RV64I-NEXT: call __nedf2
891 ; RV64I-NEXT: snez a0, a0
892 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
893 ; RV64I-NEXT: addi sp, sp, 16
894 ; RV64I-NEXT: ret
895 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") strictfp
896 %2 = zext i1 %1 to i32
897 ret i32 %2
898 }
900 define i32 @fcmp_uno(double %a, double %b) nounwind strictfp {
901 ; CHECKIFD-LABEL: fcmp_uno:
902 ; CHECKIFD: # %bb.0:
903 ; CHECKIFD-NEXT: feq.d a0, fa1, fa1
904 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
905 ; CHECKIFD-NEXT: and a0, a1, a0
906 ; CHECKIFD-NEXT: xori a0, a0, 1
907 ; CHECKIFD-NEXT: ret
908 ;
909 ; RV32IZFINXZDINX-LABEL: fcmp_uno:
910 ; RV32IZFINXZDINX: # %bb.0:
911 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
912 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
913 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
914 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
915 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
916 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
917 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
918 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
919 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
920 ; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
921 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
922 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
923 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
924 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
925 ; RV32IZFINXZDINX-NEXT: ret
926 ;
927 ; RV64IZFINXZDINX-LABEL: fcmp_uno:
928 ; RV64IZFINXZDINX: # %bb.0:
929 ; RV64IZFINXZDINX-NEXT: feq.d a1, a1, a1
930 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
931 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
932 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
933 ; RV64IZFINXZDINX-NEXT: ret
934 ;
935 ; RV32I-LABEL: fcmp_uno:
936 ; RV32I: # %bb.0:
937 ; RV32I-NEXT: addi sp, sp, -16
938 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
939 ; RV32I-NEXT: call __unorddf2
940 ; RV32I-NEXT: snez a0, a0
941 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
942 ; RV32I-NEXT: addi sp, sp, 16
943 ; RV32I-NEXT: ret
944 ;
945 ; RV64I-LABEL: fcmp_uno:
946 ; RV64I: # %bb.0:
947 ; RV64I-NEXT: addi sp, sp, -16
948 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
949 ; RV64I-NEXT: call __unorddf2
950 ; RV64I-NEXT: snez a0, a0
951 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
952 ; RV64I-NEXT: addi sp, sp, 16
953 ; RV64I-NEXT: ret
954 %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
955 %2 = zext i1 %1 to i32
956 ret i32 %2
957 }
959 define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp {
960 ; CHECKIFD-LABEL: fcmps_oeq:
961 ; CHECKIFD: # %bb.0:
962 ; CHECKIFD-NEXT: fle.d a0, fa1, fa0
963 ; CHECKIFD-NEXT: fle.d a1, fa0, fa1
964 ; CHECKIFD-NEXT: and a0, a1, a0
965 ; CHECKIFD-NEXT: ret
966 ;
967 ; RV32IZFINXZDINX-LABEL: fcmps_oeq:
968 ; RV32IZFINXZDINX: # %bb.0:
969 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
970 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
971 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
972 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
973 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
974 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
975 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
976 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
977 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
978 ; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
979 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
980 ; RV32IZFINXZDINX-NEXT: and a0, a0, a4
981 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
982 ; RV32IZFINXZDINX-NEXT: ret
983 ;
984 ; RV64IZFINXZDINX-LABEL: fcmps_oeq:
985 ; RV64IZFINXZDINX: # %bb.0:
986 ; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
987 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1
988 ; RV64IZFINXZDINX-NEXT: and a0, a0, a2
989 ; RV64IZFINXZDINX-NEXT: ret
990 ;
991 ; RV32I-LABEL: fcmps_oeq:
992 ; RV32I: # %bb.0:
993 ; RV32I-NEXT: addi sp, sp, -16
994 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
995 ; RV32I-NEXT: call __eqdf2
996 ; RV32I-NEXT: seqz a0, a0
997 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
998 ; RV32I-NEXT: addi sp, sp, 16
999 ; RV32I-NEXT: ret
1000 ;
1001 ; RV64I-LABEL: fcmps_oeq:
1002 ; RV64I: # %bb.0:
1003 ; RV64I-NEXT: addi sp, sp, -16
1004 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1005 ; RV64I-NEXT: call __eqdf2
1006 ; RV64I-NEXT: seqz a0, a0
1007 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1008 ; RV64I-NEXT: addi sp, sp, 16
1009 ; RV64I-NEXT: ret
1010 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
1011 %2 = zext i1 %1 to i32
1012 ret i32 %2
1013 }
1014 declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
1016 define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp {
1017 ; CHECKIFD-LABEL: fcmps_ogt:
1018 ; CHECKIFD: # %bb.0:
1019 ; CHECKIFD-NEXT: flt.d a0, fa1, fa0
1020 ; CHECKIFD-NEXT: ret
1021 ;
1022 ; RV32IZFINXZDINX-LABEL: fcmps_ogt:
1023 ; RV32IZFINXZDINX: # %bb.0:
1024 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1025 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1026 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1027 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1028 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1029 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1030 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1031 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1032 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1033 ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
1034 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1035 ; RV32IZFINXZDINX-NEXT: ret
1036 ;
1037 ; RV64IZFINXZDINX-LABEL: fcmps_ogt:
1038 ; RV64IZFINXZDINX: # %bb.0:
1039 ; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0
1040 ; RV64IZFINXZDINX-NEXT: ret
1041 ;
1042 ; RV32I-LABEL: fcmps_ogt:
1043 ; RV32I: # %bb.0:
1044 ; RV32I-NEXT: addi sp, sp, -16
1045 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1046 ; RV32I-NEXT: call __gtdf2
1047 ; RV32I-NEXT: sgtz a0, a0
1048 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1049 ; RV32I-NEXT: addi sp, sp, 16
1050 ; RV32I-NEXT: ret
1051 ;
1052 ; RV64I-LABEL: fcmps_ogt:
1053 ; RV64I: # %bb.0:
1054 ; RV64I-NEXT: addi sp, sp, -16
1055 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1056 ; RV64I-NEXT: call __gtdf2
1057 ; RV64I-NEXT: sgtz a0, a0
1058 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1059 ; RV64I-NEXT: addi sp, sp, 16
1060 ; RV64I-NEXT: ret
1061 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
1062 %2 = zext i1 %1 to i32
1063 ret i32 %2
1064 }
1066 define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
1067 ; CHECKIFD-LABEL: fcmps_oge:
1068 ; CHECKIFD: # %bb.0:
1069 ; CHECKIFD-NEXT: fle.d a0, fa1, fa0
1070 ; CHECKIFD-NEXT: ret
1071 ;
1072 ; RV32IZFINXZDINX-LABEL: fcmps_oge:
1073 ; RV32IZFINXZDINX: # %bb.0:
1074 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1075 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1076 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1077 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1078 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1079 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1080 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1081 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1082 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1083 ; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
1084 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1085 ; RV32IZFINXZDINX-NEXT: ret
1086 ;
1087 ; RV64IZFINXZDINX-LABEL: fcmps_oge:
1088 ; RV64IZFINXZDINX: # %bb.0:
1089 ; RV64IZFINXZDINX-NEXT: fle.d a0, a1, a0
1090 ; RV64IZFINXZDINX-NEXT: ret
1091 ;
1092 ; RV32I-LABEL: fcmps_oge:
1093 ; RV32I: # %bb.0:
1094 ; RV32I-NEXT: addi sp, sp, -16
1095 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1096 ; RV32I-NEXT: call __gedf2
1097 ; RV32I-NEXT: slti a0, a0, 0
1098 ; RV32I-NEXT: xori a0, a0, 1
1099 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1100 ; RV32I-NEXT: addi sp, sp, 16
1101 ; RV32I-NEXT: ret
1102 ;
1103 ; RV64I-LABEL: fcmps_oge:
1104 ; RV64I: # %bb.0:
1105 ; RV64I-NEXT: addi sp, sp, -16
1106 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1107 ; RV64I-NEXT: call __gedf2
1108 ; RV64I-NEXT: slti a0, a0, 0
1109 ; RV64I-NEXT: xori a0, a0, 1
1110 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1111 ; RV64I-NEXT: addi sp, sp, 16
1112 ; RV64I-NEXT: ret
1113 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
1114 %2 = zext i1 %1 to i32
1115 ret i32 %2
1116 }
1118 define i32 @fcmps_olt(double %a, double %b) nounwind strictfp {
1119 ; CHECKIFD-LABEL: fcmps_olt:
1120 ; CHECKIFD: # %bb.0:
1121 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
1122 ; CHECKIFD-NEXT: ret
1123 ;
1124 ; RV32IZFINXZDINX-LABEL: fcmps_olt:
1125 ; RV32IZFINXZDINX: # %bb.0:
1126 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1127 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1128 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1129 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1130 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1131 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1132 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1133 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1134 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1135 ; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
1136 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1137 ; RV32IZFINXZDINX-NEXT: ret
1138 ;
1139 ; RV64IZFINXZDINX-LABEL: fcmps_olt:
1140 ; RV64IZFINXZDINX: # %bb.0:
1141 ; RV64IZFINXZDINX-NEXT: flt.d a0, a0, a1
1142 ; RV64IZFINXZDINX-NEXT: ret
1143 ;
1144 ; RV32I-LABEL: fcmps_olt:
1145 ; RV32I: # %bb.0:
1146 ; RV32I-NEXT: addi sp, sp, -16
1147 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1148 ; RV32I-NEXT: call __ltdf2
1149 ; RV32I-NEXT: slti a0, a0, 0
1150 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1151 ; RV32I-NEXT: addi sp, sp, 16
1152 ; RV32I-NEXT: ret
1153 ;
1154 ; RV64I-LABEL: fcmps_olt:
1155 ; RV64I: # %bb.0:
1156 ; RV64I-NEXT: addi sp, sp, -16
1157 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1158 ; RV64I-NEXT: call __ltdf2
1159 ; RV64I-NEXT: slti a0, a0, 0
1160 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1161 ; RV64I-NEXT: addi sp, sp, 16
1162 ; RV64I-NEXT: ret
1163 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
1164 %2 = zext i1 %1 to i32
1165 ret i32 %2
1166 }
1168 define i32 @fcmps_ole(double %a, double %b) nounwind strictfp {
1169 ; CHECKIFD-LABEL: fcmps_ole:
1170 ; CHECKIFD: # %bb.0:
1171 ; CHECKIFD-NEXT: fle.d a0, fa0, fa1
1172 ; CHECKIFD-NEXT: ret
1173 ;
1174 ; RV32IZFINXZDINX-LABEL: fcmps_ole:
1175 ; RV32IZFINXZDINX: # %bb.0:
1176 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1177 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1178 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1179 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1180 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1181 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1182 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1183 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1184 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1185 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
1186 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1187 ; RV32IZFINXZDINX-NEXT: ret
1188 ;
1189 ; RV64IZFINXZDINX-LABEL: fcmps_ole:
1190 ; RV64IZFINXZDINX: # %bb.0:
1191 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1
1192 ; RV64IZFINXZDINX-NEXT: ret
1193 ;
1194 ; RV32I-LABEL: fcmps_ole:
1195 ; RV32I: # %bb.0:
1196 ; RV32I-NEXT: addi sp, sp, -16
1197 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1198 ; RV32I-NEXT: call __ledf2
1199 ; RV32I-NEXT: slti a0, a0, 1
1200 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1201 ; RV32I-NEXT: addi sp, sp, 16
1202 ; RV32I-NEXT: ret
1203 ;
1204 ; RV64I-LABEL: fcmps_ole:
1205 ; RV64I: # %bb.0:
1206 ; RV64I-NEXT: addi sp, sp, -16
1207 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1208 ; RV64I-NEXT: call __ledf2
1209 ; RV64I-NEXT: slti a0, a0, 1
1210 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1211 ; RV64I-NEXT: addi sp, sp, 16
1212 ; RV64I-NEXT: ret
1213 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
1214 %2 = zext i1 %1 to i32
1215 ret i32 %2
1216 }
1218 define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
1219 ; CHECKIFD-LABEL: fcmps_one:
1220 ; CHECKIFD: # %bb.0:
1221 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
1222 ; CHECKIFD-NEXT: flt.d a1, fa1, fa0
1223 ; CHECKIFD-NEXT: or a0, a1, a0
1224 ; CHECKIFD-NEXT: ret
1225 ;
1226 ; RV32IZFINXZDINX-LABEL: fcmps_one:
1227 ; RV32IZFINXZDINX: # %bb.0:
1228 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1229 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1230 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1231 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1232 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1233 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1234 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1235 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1236 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1237 ; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
1238 ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
1239 ; RV32IZFINXZDINX-NEXT: or a0, a0, a4
1240 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1241 ; RV32IZFINXZDINX-NEXT: ret
1242 ;
1243 ; RV64IZFINXZDINX-LABEL: fcmps_one:
1244 ; RV64IZFINXZDINX: # %bb.0:
1245 ; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
1246 ; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0
1247 ; RV64IZFINXZDINX-NEXT: or a0, a0, a2
1248 ; RV64IZFINXZDINX-NEXT: ret
1249 ;
1250 ; RV32I-LABEL: fcmps_one:
1251 ; RV32I: # %bb.0:
1252 ; RV32I-NEXT: addi sp, sp, -32
1253 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1254 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1255 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1256 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1257 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1258 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
1259 ; RV32I-NEXT: mv s0, a3
1260 ; RV32I-NEXT: mv s1, a2
1261 ; RV32I-NEXT: mv s2, a1
1262 ; RV32I-NEXT: mv s3, a0
1263 ; RV32I-NEXT: call __eqdf2
1264 ; RV32I-NEXT: snez s4, a0
1265 ; RV32I-NEXT: mv a0, s3
1266 ; RV32I-NEXT: mv a1, s2
1267 ; RV32I-NEXT: mv a2, s1
1268 ; RV32I-NEXT: mv a3, s0
1269 ; RV32I-NEXT: call __unorddf2
1270 ; RV32I-NEXT: seqz a0, a0
1271 ; RV32I-NEXT: and a0, a0, s4
1272 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1273 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1274 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1275 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1276 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1277 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
1278 ; RV32I-NEXT: addi sp, sp, 32
1279 ; RV32I-NEXT: ret
1280 ;
1281 ; RV64I-LABEL: fcmps_one:
1282 ; RV64I: # %bb.0:
1283 ; RV64I-NEXT: addi sp, sp, -32
1284 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1285 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1286 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1287 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1288 ; RV64I-NEXT: mv s0, a1
1289 ; RV64I-NEXT: mv s1, a0
1290 ; RV64I-NEXT: call __eqdf2
1291 ; RV64I-NEXT: snez s2, a0
1292 ; RV64I-NEXT: mv a0, s1
1293 ; RV64I-NEXT: mv a1, s0
1294 ; RV64I-NEXT: call __unorddf2
1295 ; RV64I-NEXT: seqz a0, a0
1296 ; RV64I-NEXT: and a0, a0, s2
1297 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1298 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1299 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1300 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1301 ; RV64I-NEXT: addi sp, sp, 32
1302 ; RV64I-NEXT: ret
1303 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"one", metadata !"fpexcept.strict") strictfp
1304 %2 = zext i1 %1 to i32
1305 ret i32 %2
1306 }
1308 define i32 @fcmps_ord(double %a, double %b) nounwind strictfp {
1309 ; CHECKIFD-LABEL: fcmps_ord:
1310 ; CHECKIFD: # %bb.0:
1311 ; CHECKIFD-NEXT: fle.d a0, fa1, fa1
1312 ; CHECKIFD-NEXT: fle.d a1, fa0, fa0
1313 ; CHECKIFD-NEXT: and a0, a1, a0
1314 ; CHECKIFD-NEXT: ret
1315 ;
1316 ; RV32IZFINXZDINX-LABEL: fcmps_ord:
1317 ; RV32IZFINXZDINX: # %bb.0:
1318 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1319 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1320 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1321 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1322 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1323 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1324 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1325 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1326 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1327 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, a2
1328 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a0
1329 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
1330 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1331 ; RV32IZFINXZDINX-NEXT: ret
1332 ;
1333 ; RV64IZFINXZDINX-LABEL: fcmps_ord:
1334 ; RV64IZFINXZDINX: # %bb.0:
1335 ; RV64IZFINXZDINX-NEXT: fle.d a1, a1, a1
1336 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a0
1337 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1338 ; RV64IZFINXZDINX-NEXT: ret
1339 ;
1340 ; RV32I-LABEL: fcmps_ord:
1341 ; RV32I: # %bb.0:
1342 ; RV32I-NEXT: addi sp, sp, -16
1343 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1344 ; RV32I-NEXT: call __unorddf2
1345 ; RV32I-NEXT: seqz a0, a0
1346 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1347 ; RV32I-NEXT: addi sp, sp, 16
1348 ; RV32I-NEXT: ret
1349 ;
1350 ; RV64I-LABEL: fcmps_ord:
1351 ; RV64I: # %bb.0:
1352 ; RV64I-NEXT: addi sp, sp, -16
1353 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1354 ; RV64I-NEXT: call __unorddf2
1355 ; RV64I-NEXT: seqz a0, a0
1356 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1357 ; RV64I-NEXT: addi sp, sp, 16
1358 ; RV64I-NEXT: ret
1359 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
1360 %2 = zext i1 %1 to i32
1361 ret i32 %2
1362 }
1364 define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
1365 ; CHECKIFD-LABEL: fcmps_ueq:
1366 ; CHECKIFD: # %bb.0:
1367 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
1368 ; CHECKIFD-NEXT: flt.d a1, fa1, fa0
1369 ; CHECKIFD-NEXT: or a0, a1, a0
1370 ; CHECKIFD-NEXT: xori a0, a0, 1
1371 ; CHECKIFD-NEXT: ret
1372 ;
1373 ; RV32IZFINXZDINX-LABEL: fcmps_ueq:
1374 ; RV32IZFINXZDINX: # %bb.0:
1375 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1376 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1377 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1378 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1379 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1380 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1381 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1382 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1383 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1384 ; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
1385 ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
1386 ; RV32IZFINXZDINX-NEXT: or a0, a0, a4
1387 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1388 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1389 ; RV32IZFINXZDINX-NEXT: ret
1390 ;
1391 ; RV64IZFINXZDINX-LABEL: fcmps_ueq:
1392 ; RV64IZFINXZDINX: # %bb.0:
1393 ; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
1394 ; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0
1395 ; RV64IZFINXZDINX-NEXT: or a0, a0, a2
1396 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1397 ; RV64IZFINXZDINX-NEXT: ret
1398 ;
1399 ; RV32I-LABEL: fcmps_ueq:
1400 ; RV32I: # %bb.0:
1401 ; RV32I-NEXT: addi sp, sp, -32
1402 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1403 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1404 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1405 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1406 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1407 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
1408 ; RV32I-NEXT: mv s0, a3
1409 ; RV32I-NEXT: mv s1, a2
1410 ; RV32I-NEXT: mv s2, a1
1411 ; RV32I-NEXT: mv s3, a0
1412 ; RV32I-NEXT: call __eqdf2
1413 ; RV32I-NEXT: seqz s4, a0
1414 ; RV32I-NEXT: mv a0, s3
1415 ; RV32I-NEXT: mv a1, s2
1416 ; RV32I-NEXT: mv a2, s1
1417 ; RV32I-NEXT: mv a3, s0
1418 ; RV32I-NEXT: call __unorddf2
1419 ; RV32I-NEXT: snez a0, a0
1420 ; RV32I-NEXT: or a0, a0, s4
1421 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1422 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1423 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1424 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1425 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1426 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
1427 ; RV32I-NEXT: addi sp, sp, 32
1428 ; RV32I-NEXT: ret
1429 ;
1430 ; RV64I-LABEL: fcmps_ueq:
1431 ; RV64I: # %bb.0:
1432 ; RV64I-NEXT: addi sp, sp, -32
1433 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1434 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1435 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1436 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1437 ; RV64I-NEXT: mv s0, a1
1438 ; RV64I-NEXT: mv s1, a0
1439 ; RV64I-NEXT: call __eqdf2
1440 ; RV64I-NEXT: seqz s2, a0
1441 ; RV64I-NEXT: mv a0, s1
1442 ; RV64I-NEXT: mv a1, s0
1443 ; RV64I-NEXT: call __unorddf2
1444 ; RV64I-NEXT: snez a0, a0
1445 ; RV64I-NEXT: or a0, a0, s2
1446 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1447 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1448 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1449 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1450 ; RV64I-NEXT: addi sp, sp, 32
1451 ; RV64I-NEXT: ret
1452 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
1453 %2 = zext i1 %1 to i32
1454 ret i32 %2
1455 }
1457 define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp {
1458 ; CHECKIFD-LABEL: fcmps_ugt:
1459 ; CHECKIFD: # %bb.0:
1460 ; CHECKIFD-NEXT: fle.d a0, fa0, fa1
1461 ; CHECKIFD-NEXT: xori a0, a0, 1
1462 ; CHECKIFD-NEXT: ret
1463 ;
1464 ; RV32IZFINXZDINX-LABEL: fcmps_ugt:
1465 ; RV32IZFINXZDINX: # %bb.0:
1466 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1467 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1468 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1469 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1470 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1471 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1472 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1473 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1474 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1475 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
1476 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1477 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1478 ; RV32IZFINXZDINX-NEXT: ret
1479 ;
1480 ; RV64IZFINXZDINX-LABEL: fcmps_ugt:
1481 ; RV64IZFINXZDINX: # %bb.0:
1482 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1
1483 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1484 ; RV64IZFINXZDINX-NEXT: ret
1485 ;
1486 ; RV32I-LABEL: fcmps_ugt:
1487 ; RV32I: # %bb.0:
1488 ; RV32I-NEXT: addi sp, sp, -16
1489 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1490 ; RV32I-NEXT: call __ledf2
1491 ; RV32I-NEXT: sgtz a0, a0
1492 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1493 ; RV32I-NEXT: addi sp, sp, 16
1494 ; RV32I-NEXT: ret
1495 ;
1496 ; RV64I-LABEL: fcmps_ugt:
1497 ; RV64I: # %bb.0:
1498 ; RV64I-NEXT: addi sp, sp, -16
1499 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1500 ; RV64I-NEXT: call __ledf2
1501 ; RV64I-NEXT: sgtz a0, a0
1502 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1503 ; RV64I-NEXT: addi sp, sp, 16
1504 ; RV64I-NEXT: ret
1505 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
1506 %2 = zext i1 %1 to i32
1507 ret i32 %2
1508 }
1510 define i32 @fcmps_uge(double %a, double %b) nounwind strictfp {
1511 ; CHECKIFD-LABEL: fcmps_uge:
1512 ; CHECKIFD: # %bb.0:
1513 ; CHECKIFD-NEXT: flt.d a0, fa0, fa1
1514 ; CHECKIFD-NEXT: xori a0, a0, 1
1515 ; CHECKIFD-NEXT: ret
1516 ;
1517 ; RV32IZFINXZDINX-LABEL: fcmps_uge:
1518 ; RV32IZFINXZDINX: # %bb.0:
1519 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1520 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1521 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1522 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1523 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1524 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1525 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1526 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1527 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1528 ; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
1529 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1530 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1531 ; RV32IZFINXZDINX-NEXT: ret
1532 ;
1533 ; RV64IZFINXZDINX-LABEL: fcmps_uge:
1534 ; RV64IZFINXZDINX: # %bb.0:
1535 ; RV64IZFINXZDINX-NEXT: flt.d a0, a0, a1
1536 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1537 ; RV64IZFINXZDINX-NEXT: ret
1538 ;
1539 ; RV32I-LABEL: fcmps_uge:
1540 ; RV32I: # %bb.0:
1541 ; RV32I-NEXT: addi sp, sp, -16
1542 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1543 ; RV32I-NEXT: call __ltdf2
1544 ; RV32I-NEXT: slti a0, a0, 0
1545 ; RV32I-NEXT: xori a0, a0, 1
1546 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1547 ; RV32I-NEXT: addi sp, sp, 16
1548 ; RV32I-NEXT: ret
1549 ;
1550 ; RV64I-LABEL: fcmps_uge:
1551 ; RV64I: # %bb.0:
1552 ; RV64I-NEXT: addi sp, sp, -16
1553 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1554 ; RV64I-NEXT: call __ltdf2
1555 ; RV64I-NEXT: slti a0, a0, 0
1556 ; RV64I-NEXT: xori a0, a0, 1
1557 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1558 ; RV64I-NEXT: addi sp, sp, 16
1559 ; RV64I-NEXT: ret
1560 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
1561 %2 = zext i1 %1 to i32
1562 ret i32 %2
1563 }
1565 define i32 @fcmps_ult(double %a, double %b) nounwind strictfp {
1566 ; CHECKIFD-LABEL: fcmps_ult:
1567 ; CHECKIFD: # %bb.0:
1568 ; CHECKIFD-NEXT: fle.d a0, fa1, fa0
1569 ; CHECKIFD-NEXT: xori a0, a0, 1
1570 ; CHECKIFD-NEXT: ret
1571 ;
1572 ; RV32IZFINXZDINX-LABEL: fcmps_ult:
1573 ; RV32IZFINXZDINX: # %bb.0:
1574 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1575 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1576 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1577 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1578 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1579 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1580 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1581 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1582 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1583 ; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
1584 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1585 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1586 ; RV32IZFINXZDINX-NEXT: ret
1587 ;
1588 ; RV64IZFINXZDINX-LABEL: fcmps_ult:
1589 ; RV64IZFINXZDINX: # %bb.0:
1590 ; RV64IZFINXZDINX-NEXT: fle.d a0, a1, a0
1591 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1592 ; RV64IZFINXZDINX-NEXT: ret
1593 ;
1594 ; RV32I-LABEL: fcmps_ult:
1595 ; RV32I: # %bb.0:
1596 ; RV32I-NEXT: addi sp, sp, -16
1597 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1598 ; RV32I-NEXT: call __gedf2
1599 ; RV32I-NEXT: slti a0, a0, 0
1600 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1601 ; RV32I-NEXT: addi sp, sp, 16
1602 ; RV32I-NEXT: ret
1603 ;
1604 ; RV64I-LABEL: fcmps_ult:
1605 ; RV64I: # %bb.0:
1606 ; RV64I-NEXT: addi sp, sp, -16
1607 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1608 ; RV64I-NEXT: call __gedf2
1609 ; RV64I-NEXT: slti a0, a0, 0
1610 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1611 ; RV64I-NEXT: addi sp, sp, 16
1612 ; RV64I-NEXT: ret
1613 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
1614 %2 = zext i1 %1 to i32
1615 ret i32 %2
1616 }
1618 define i32 @fcmps_ule(double %a, double %b) nounwind strictfp {
1619 ; CHECKIFD-LABEL: fcmps_ule:
1620 ; CHECKIFD: # %bb.0:
1621 ; CHECKIFD-NEXT: flt.d a0, fa1, fa0
1622 ; CHECKIFD-NEXT: xori a0, a0, 1
1623 ; CHECKIFD-NEXT: ret
1624 ;
1625 ; RV32IZFINXZDINX-LABEL: fcmps_ule:
1626 ; RV32IZFINXZDINX: # %bb.0:
1627 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1628 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1629 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1630 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1631 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1632 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1633 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1634 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1635 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1636 ; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
1637 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1638 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1639 ; RV32IZFINXZDINX-NEXT: ret
1640 ;
1641 ; RV64IZFINXZDINX-LABEL: fcmps_ule:
1642 ; RV64IZFINXZDINX: # %bb.0:
1643 ; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0
1644 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1645 ; RV64IZFINXZDINX-NEXT: ret
1646 ;
1647 ; RV32I-LABEL: fcmps_ule:
1648 ; RV32I: # %bb.0:
1649 ; RV32I-NEXT: addi sp, sp, -16
1650 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1651 ; RV32I-NEXT: call __gtdf2
1652 ; RV32I-NEXT: slti a0, a0, 1
1653 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1654 ; RV32I-NEXT: addi sp, sp, 16
1655 ; RV32I-NEXT: ret
1656 ;
1657 ; RV64I-LABEL: fcmps_ule:
1658 ; RV64I: # %bb.0:
1659 ; RV64I-NEXT: addi sp, sp, -16
1660 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1661 ; RV64I-NEXT: call __gtdf2
1662 ; RV64I-NEXT: slti a0, a0, 1
1663 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1664 ; RV64I-NEXT: addi sp, sp, 16
1665 ; RV64I-NEXT: ret
1666 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
1667 %2 = zext i1 %1 to i32
1668 ret i32 %2
1669 }
1671 define i32 @fcmps_une(double %a, double %b) nounwind strictfp {
1672 ; CHECKIFD-LABEL: fcmps_une:
1673 ; CHECKIFD: # %bb.0:
1674 ; CHECKIFD-NEXT: fle.d a0, fa1, fa0
1675 ; CHECKIFD-NEXT: fle.d a1, fa0, fa1
1676 ; CHECKIFD-NEXT: and a0, a1, a0
1677 ; CHECKIFD-NEXT: xori a0, a0, 1
1678 ; CHECKIFD-NEXT: ret
1679 ;
1680 ; RV32IZFINXZDINX-LABEL: fcmps_une:
1681 ; RV32IZFINXZDINX: # %bb.0:
1682 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1683 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1684 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1685 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1686 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1687 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1688 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1689 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1690 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1691 ; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
1692 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
1693 ; RV32IZFINXZDINX-NEXT: and a0, a0, a4
1694 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1695 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1696 ; RV32IZFINXZDINX-NEXT: ret
1697 ;
1698 ; RV64IZFINXZDINX-LABEL: fcmps_une:
1699 ; RV64IZFINXZDINX: # %bb.0:
1700 ; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
1701 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1
1702 ; RV64IZFINXZDINX-NEXT: and a0, a0, a2
1703 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1704 ; RV64IZFINXZDINX-NEXT: ret
1705 ;
1706 ; RV32I-LABEL: fcmps_une:
1707 ; RV32I: # %bb.0:
1708 ; RV32I-NEXT: addi sp, sp, -16
1709 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1710 ; RV32I-NEXT: call __nedf2
1711 ; RV32I-NEXT: snez a0, a0
1712 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1713 ; RV32I-NEXT: addi sp, sp, 16
1714 ; RV32I-NEXT: ret
1715 ;
1716 ; RV64I-LABEL: fcmps_une:
1717 ; RV64I: # %bb.0:
1718 ; RV64I-NEXT: addi sp, sp, -16
1719 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1720 ; RV64I-NEXT: call __nedf2
1721 ; RV64I-NEXT: snez a0, a0
1722 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1723 ; RV64I-NEXT: addi sp, sp, 16
1724 ; RV64I-NEXT: ret
1725 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") strictfp
1726 %2 = zext i1 %1 to i32
1727 ret i32 %2
1728 }
1730 define i32 @fcmps_uno(double %a, double %b) nounwind strictfp {
1731 ; CHECKIFD-LABEL: fcmps_uno:
1732 ; CHECKIFD: # %bb.0:
1733 ; CHECKIFD-NEXT: fle.d a0, fa1, fa1
1734 ; CHECKIFD-NEXT: fle.d a1, fa0, fa0
1735 ; CHECKIFD-NEXT: and a0, a1, a0
1736 ; CHECKIFD-NEXT: xori a0, a0, 1
1737 ; CHECKIFD-NEXT: ret
1738 ;
1739 ; RV32IZFINXZDINX-LABEL: fcmps_uno:
1740 ; RV32IZFINXZDINX: # %bb.0:
1741 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1742 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1743 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1744 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1745 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1746 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
1747 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
1748 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1749 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1750 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, a2
1751 ; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a0
1752 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
1753 ; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
1754 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1755 ; RV32IZFINXZDINX-NEXT: ret
1756 ;
1757 ; RV64IZFINXZDINX-LABEL: fcmps_uno:
1758 ; RV64IZFINXZDINX: # %bb.0:
1759 ; RV64IZFINXZDINX-NEXT: fle.d a1, a1, a1
1760 ; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a0
1761 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1762 ; RV64IZFINXZDINX-NEXT: xori a0, a0, 1
1763 ; RV64IZFINXZDINX-NEXT: ret
1764 ;
1765 ; RV32I-LABEL: fcmps_uno:
1766 ; RV32I: # %bb.0:
1767 ; RV32I-NEXT: addi sp, sp, -16
1768 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1769 ; RV32I-NEXT: call __unorddf2
1770 ; RV32I-NEXT: snez a0, a0
1771 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1772 ; RV32I-NEXT: addi sp, sp, 16
1773 ; RV32I-NEXT: ret
1774 ;
1775 ; RV64I-LABEL: fcmps_uno:
1776 ; RV64I: # %bb.0:
1777 ; RV64I-NEXT: addi sp, sp, -16
1778 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1779 ; RV64I-NEXT: call __unorddf2
1780 ; RV64I-NEXT: snez a0, a0
1781 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1782 ; RV64I-NEXT: addi sp, sp, 16
1783 ; RV64I-NEXT: ret
1784 %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
1785 %2 = zext i1 %1 to i32
1786 ret i32 %2
1787 }