| blob | c574f64150a249690ec1411257f6e3ee746a220a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
3 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32d \
4 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
6 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64d \
7 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
9 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \
10 ; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
12 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \
13 ; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
15 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
16 ; RUN: | FileCheck -check-prefix=RV32I %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
18 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
19 ; RUN: | FileCheck -check-prefix=RV64I %s
21 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
23 define double @sqrt_f64(double %a) nounwind strictfp {
24 ; CHECKIFD-LABEL: sqrt_f64:
25 ; CHECKIFD: # %bb.0:
26 ; CHECKIFD-NEXT: fsqrt.d fa0, fa0
27 ; CHECKIFD-NEXT: ret
28 ;
29 ; RV32IZFINXZDINX-LABEL: sqrt_f64:
30 ; RV32IZFINXZDINX: # %bb.0:
31 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
32 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
33 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
34 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
35 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
36 ; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
37 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
38 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
39 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
40 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
41 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
42 ; RV32IZFINXZDINX-NEXT: ret
43 ;
44 ; RV64IZFINXZDINX-LABEL: sqrt_f64:
45 ; RV64IZFINXZDINX: # %bb.0:
46 ; RV64IZFINXZDINX-NEXT: fsqrt.d a0, a0
47 ; RV64IZFINXZDINX-NEXT: ret
48 ;
49 ; RV32I-LABEL: sqrt_f64:
50 ; RV32I: # %bb.0:
51 ; RV32I-NEXT: addi sp, sp, -16
52 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
53 ; RV32I-NEXT: call sqrt
54 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
55 ; RV32I-NEXT: addi sp, sp, 16
56 ; RV32I-NEXT: ret
57 ;
58 ; RV64I-LABEL: sqrt_f64:
59 ; RV64I: # %bb.0:
60 ; RV64I-NEXT: addi sp, sp, -16
61 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
62 ; RV64I-NEXT: call sqrt
63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
64 ; RV64I-NEXT: addi sp, sp, 16
65 ; RV64I-NEXT: ret
66 %1 = call double @llvm.experimental.constrained.sqrt.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
67 ret double %1
68 }
70 declare double @llvm.experimental.constrained.powi.f64.i32(double, i32, metadata, metadata)
72 define double @powi_f64(double %a, i32 %b) nounwind strictfp {
73 ; RV32IFD-LABEL: powi_f64:
74 ; RV32IFD: # %bb.0:
75 ; RV32IFD-NEXT: addi sp, sp, -16
76 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
77 ; RV32IFD-NEXT: call __powidf2
78 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
79 ; RV32IFD-NEXT: addi sp, sp, 16
80 ; RV32IFD-NEXT: ret
81 ;
82 ; RV64IFD-LABEL: powi_f64:
83 ; RV64IFD: # %bb.0:
84 ; RV64IFD-NEXT: addi sp, sp, -16
85 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
86 ; RV64IFD-NEXT: sext.w a0, a0
87 ; RV64IFD-NEXT: call __powidf2
88 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
89 ; RV64IFD-NEXT: addi sp, sp, 16
90 ; RV64IFD-NEXT: ret
91 ;
92 ; RV32IZFINXZDINX-LABEL: powi_f64:
93 ; RV32IZFINXZDINX: # %bb.0:
94 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
95 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
96 ; RV32IZFINXZDINX-NEXT: call __powidf2
97 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
98 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
99 ; RV32IZFINXZDINX-NEXT: ret
100 ;
101 ; RV64IZFINXZDINX-LABEL: powi_f64:
102 ; RV64IZFINXZDINX: # %bb.0:
103 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
104 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
105 ; RV64IZFINXZDINX-NEXT: sext.w a1, a1
106 ; RV64IZFINXZDINX-NEXT: call __powidf2
107 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
108 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
109 ; RV64IZFINXZDINX-NEXT: ret
110 ;
111 ; RV32I-LABEL: powi_f64:
112 ; RV32I: # %bb.0:
113 ; RV32I-NEXT: addi sp, sp, -16
114 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
115 ; RV32I-NEXT: call __powidf2
116 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
117 ; RV32I-NEXT: addi sp, sp, 16
118 ; RV32I-NEXT: ret
119 ;
120 ; RV64I-LABEL: powi_f64:
121 ; RV64I: # %bb.0:
122 ; RV64I-NEXT: addi sp, sp, -16
123 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
124 ; RV64I-NEXT: sext.w a1, a1
125 ; RV64I-NEXT: call __powidf2
126 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
127 ; RV64I-NEXT: addi sp, sp, 16
128 ; RV64I-NEXT: ret
129 %1 = call double @llvm.experimental.constrained.powi.f64.i32(double %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
130 ret double %1
131 }
133 declare double @llvm.experimental.constrained.sin.f64(double, metadata, metadata)
135 define double @sin_f64(double %a) nounwind strictfp {
136 ; RV32IFD-LABEL: sin_f64:
137 ; RV32IFD: # %bb.0:
138 ; RV32IFD-NEXT: addi sp, sp, -16
139 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
140 ; RV32IFD-NEXT: call sin
141 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
142 ; RV32IFD-NEXT: addi sp, sp, 16
143 ; RV32IFD-NEXT: ret
144 ;
145 ; RV64IFD-LABEL: sin_f64:
146 ; RV64IFD: # %bb.0:
147 ; RV64IFD-NEXT: addi sp, sp, -16
148 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
149 ; RV64IFD-NEXT: call sin
150 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
151 ; RV64IFD-NEXT: addi sp, sp, 16
152 ; RV64IFD-NEXT: ret
153 ;
154 ; RV32IZFINXZDINX-LABEL: sin_f64:
155 ; RV32IZFINXZDINX: # %bb.0:
156 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
157 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
158 ; RV32IZFINXZDINX-NEXT: call sin
159 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
160 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
161 ; RV32IZFINXZDINX-NEXT: ret
162 ;
163 ; RV64IZFINXZDINX-LABEL: sin_f64:
164 ; RV64IZFINXZDINX: # %bb.0:
165 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
166 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
167 ; RV64IZFINXZDINX-NEXT: call sin
168 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
169 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
170 ; RV64IZFINXZDINX-NEXT: ret
171 ;
172 ; RV32I-LABEL: sin_f64:
173 ; RV32I: # %bb.0:
174 ; RV32I-NEXT: addi sp, sp, -16
175 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
176 ; RV32I-NEXT: call sin
177 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
178 ; RV32I-NEXT: addi sp, sp, 16
179 ; RV32I-NEXT: ret
180 ;
181 ; RV64I-LABEL: sin_f64:
182 ; RV64I: # %bb.0:
183 ; RV64I-NEXT: addi sp, sp, -16
184 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
185 ; RV64I-NEXT: call sin
186 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
187 ; RV64I-NEXT: addi sp, sp, 16
188 ; RV64I-NEXT: ret
189 %1 = call double @llvm.experimental.constrained.sin.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
190 ret double %1
191 }
193 declare double @llvm.experimental.constrained.cos.f64(double, metadata, metadata)
195 define double @cos_f64(double %a) nounwind strictfp {
196 ; RV32IFD-LABEL: cos_f64:
197 ; RV32IFD: # %bb.0:
198 ; RV32IFD-NEXT: addi sp, sp, -16
199 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
200 ; RV32IFD-NEXT: call cos
201 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
202 ; RV32IFD-NEXT: addi sp, sp, 16
203 ; RV32IFD-NEXT: ret
204 ;
205 ; RV64IFD-LABEL: cos_f64:
206 ; RV64IFD: # %bb.0:
207 ; RV64IFD-NEXT: addi sp, sp, -16
208 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
209 ; RV64IFD-NEXT: call cos
210 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
211 ; RV64IFD-NEXT: addi sp, sp, 16
212 ; RV64IFD-NEXT: ret
213 ;
214 ; RV32IZFINXZDINX-LABEL: cos_f64:
215 ; RV32IZFINXZDINX: # %bb.0:
216 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
217 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
218 ; RV32IZFINXZDINX-NEXT: call cos
219 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
220 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
221 ; RV32IZFINXZDINX-NEXT: ret
222 ;
223 ; RV64IZFINXZDINX-LABEL: cos_f64:
224 ; RV64IZFINXZDINX: # %bb.0:
225 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
226 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
227 ; RV64IZFINXZDINX-NEXT: call cos
228 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
229 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
230 ; RV64IZFINXZDINX-NEXT: ret
231 ;
232 ; RV32I-LABEL: cos_f64:
233 ; RV32I: # %bb.0:
234 ; RV32I-NEXT: addi sp, sp, -16
235 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
236 ; RV32I-NEXT: call cos
237 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
238 ; RV32I-NEXT: addi sp, sp, 16
239 ; RV32I-NEXT: ret
240 ;
241 ; RV64I-LABEL: cos_f64:
242 ; RV64I: # %bb.0:
243 ; RV64I-NEXT: addi sp, sp, -16
244 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
245 ; RV64I-NEXT: call cos
246 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
247 ; RV64I-NEXT: addi sp, sp, 16
248 ; RV64I-NEXT: ret
249 %1 = call double @llvm.experimental.constrained.cos.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
250 ret double %1
251 }
253 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
254 define double @sincos_f64(double %a) nounwind strictfp {
255 ; RV32IFD-LABEL: sincos_f64:
256 ; RV32IFD: # %bb.0:
257 ; RV32IFD-NEXT: addi sp, sp, -32
258 ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
259 ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
260 ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
261 ; RV32IFD-NEXT: fmv.d fs0, fa0
262 ; RV32IFD-NEXT: call sin
263 ; RV32IFD-NEXT: fmv.d fs1, fa0
264 ; RV32IFD-NEXT: fmv.d fa0, fs0
265 ; RV32IFD-NEXT: call cos
266 ; RV32IFD-NEXT: fadd.d fa0, fs1, fa0
267 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
268 ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
269 ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
270 ; RV32IFD-NEXT: addi sp, sp, 32
271 ; RV32IFD-NEXT: ret
272 ;
273 ; RV64IFD-LABEL: sincos_f64:
274 ; RV64IFD: # %bb.0:
275 ; RV64IFD-NEXT: addi sp, sp, -32
276 ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
277 ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
278 ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
279 ; RV64IFD-NEXT: fmv.d fs0, fa0
280 ; RV64IFD-NEXT: call sin
281 ; RV64IFD-NEXT: fmv.d fs1, fa0
282 ; RV64IFD-NEXT: fmv.d fa0, fs0
283 ; RV64IFD-NEXT: call cos
284 ; RV64IFD-NEXT: fadd.d fa0, fs1, fa0
285 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
286 ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
287 ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
288 ; RV64IFD-NEXT: addi sp, sp, 32
289 ; RV64IFD-NEXT: ret
290 ;
291 ; RV32IZFINXZDINX-LABEL: sincos_f64:
292 ; RV32IZFINXZDINX: # %bb.0:
293 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
294 ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
295 ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
296 ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
297 ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
298 ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
299 ; RV32IZFINXZDINX-NEXT: mv s0, a1
300 ; RV32IZFINXZDINX-NEXT: mv s1, a0
301 ; RV32IZFINXZDINX-NEXT: call sin
302 ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
303 ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
304 ; RV32IZFINXZDINX-NEXT: lw s2, 0(sp)
305 ; RV32IZFINXZDINX-NEXT: lw s3, 4(sp)
306 ; RV32IZFINXZDINX-NEXT: mv a0, s1
307 ; RV32IZFINXZDINX-NEXT: mv a1, s0
308 ; RV32IZFINXZDINX-NEXT: call cos
309 ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
310 ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
311 ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
312 ; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
313 ; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
314 ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
315 ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
316 ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
317 ; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
318 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
319 ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
320 ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
321 ; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
322 ; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
323 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
324 ; RV32IZFINXZDINX-NEXT: ret
325 ;
326 ; RV64IZFINXZDINX-LABEL: sincos_f64:
327 ; RV64IZFINXZDINX: # %bb.0:
328 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -32
329 ; RV64IZFINXZDINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
330 ; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
331 ; RV64IZFINXZDINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
332 ; RV64IZFINXZDINX-NEXT: mv s0, a0
333 ; RV64IZFINXZDINX-NEXT: call sin
334 ; RV64IZFINXZDINX-NEXT: mv s1, a0
335 ; RV64IZFINXZDINX-NEXT: mv a0, s0
336 ; RV64IZFINXZDINX-NEXT: call cos
337 ; RV64IZFINXZDINX-NEXT: fadd.d a0, s1, a0
338 ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
339 ; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
340 ; RV64IZFINXZDINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
341 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 32
342 ; RV64IZFINXZDINX-NEXT: ret
343 ;
344 ; RV32I-LABEL: sincos_f64:
345 ; RV32I: # %bb.0:
346 ; RV32I-NEXT: addi sp, sp, -32
347 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
348 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
349 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
350 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
351 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
352 ; RV32I-NEXT: mv s0, a1
353 ; RV32I-NEXT: mv s1, a0
354 ; RV32I-NEXT: call sin
355 ; RV32I-NEXT: mv s2, a0
356 ; RV32I-NEXT: mv s3, a1
357 ; RV32I-NEXT: mv a0, s1
358 ; RV32I-NEXT: mv a1, s0
359 ; RV32I-NEXT: call cos
360 ; RV32I-NEXT: mv a2, a0
361 ; RV32I-NEXT: mv a3, a1
362 ; RV32I-NEXT: mv a0, s2
363 ; RV32I-NEXT: mv a1, s3
364 ; RV32I-NEXT: call __adddf3
365 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
366 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
367 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
368 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
369 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
370 ; RV32I-NEXT: addi sp, sp, 32
371 ; RV32I-NEXT: ret
372 ;
373 ; RV64I-LABEL: sincos_f64:
374 ; RV64I: # %bb.0:
375 ; RV64I-NEXT: addi sp, sp, -32
376 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
377 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
378 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
379 ; RV64I-NEXT: mv s0, a0
380 ; RV64I-NEXT: call sin
381 ; RV64I-NEXT: mv s1, a0
382 ; RV64I-NEXT: mv a0, s0
383 ; RV64I-NEXT: call cos
384 ; RV64I-NEXT: mv a1, a0
385 ; RV64I-NEXT: mv a0, s1
386 ; RV64I-NEXT: call __adddf3
387 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
388 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
389 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
390 ; RV64I-NEXT: addi sp, sp, 32
391 ; RV64I-NEXT: ret
392 %1 = call double @llvm.experimental.constrained.sin.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
393 %2 = call double @llvm.experimental.constrained.cos.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
394 %3 = fadd double %1, %2
395 ret double %3
396 }
398 declare double @llvm.experimental.constrained.pow.f64(double, double, metadata, metadata)
400 define double @pow_f64(double %a, double %b) nounwind strictfp {
401 ; RV32IFD-LABEL: pow_f64:
402 ; RV32IFD: # %bb.0:
403 ; RV32IFD-NEXT: addi sp, sp, -16
404 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
405 ; RV32IFD-NEXT: call pow
406 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
407 ; RV32IFD-NEXT: addi sp, sp, 16
408 ; RV32IFD-NEXT: ret
409 ;
410 ; RV64IFD-LABEL: pow_f64:
411 ; RV64IFD: # %bb.0:
412 ; RV64IFD-NEXT: addi sp, sp, -16
413 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
414 ; RV64IFD-NEXT: call pow
415 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
416 ; RV64IFD-NEXT: addi sp, sp, 16
417 ; RV64IFD-NEXT: ret
418 ;
419 ; RV32IZFINXZDINX-LABEL: pow_f64:
420 ; RV32IZFINXZDINX: # %bb.0:
421 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
422 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
423 ; RV32IZFINXZDINX-NEXT: call pow
424 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
425 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
426 ; RV32IZFINXZDINX-NEXT: ret
427 ;
428 ; RV64IZFINXZDINX-LABEL: pow_f64:
429 ; RV64IZFINXZDINX: # %bb.0:
430 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
431 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
432 ; RV64IZFINXZDINX-NEXT: call pow
433 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
434 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
435 ; RV64IZFINXZDINX-NEXT: ret
436 ;
437 ; RV32I-LABEL: pow_f64:
438 ; RV32I: # %bb.0:
439 ; RV32I-NEXT: addi sp, sp, -16
440 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
441 ; RV32I-NEXT: call pow
442 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
443 ; RV32I-NEXT: addi sp, sp, 16
444 ; RV32I-NEXT: ret
445 ;
446 ; RV64I-LABEL: pow_f64:
447 ; RV64I: # %bb.0:
448 ; RV64I-NEXT: addi sp, sp, -16
449 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
450 ; RV64I-NEXT: call pow
451 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
452 ; RV64I-NEXT: addi sp, sp, 16
453 ; RV64I-NEXT: ret
454 %1 = call double @llvm.experimental.constrained.pow.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
455 ret double %1
456 }
458 declare double @llvm.experimental.constrained.exp.f64(double, metadata, metadata)
460 define double @exp_f64(double %a) nounwind strictfp {
461 ; RV32IFD-LABEL: exp_f64:
462 ; RV32IFD: # %bb.0:
463 ; RV32IFD-NEXT: addi sp, sp, -16
464 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
465 ; RV32IFD-NEXT: call exp
466 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
467 ; RV32IFD-NEXT: addi sp, sp, 16
468 ; RV32IFD-NEXT: ret
469 ;
470 ; RV64IFD-LABEL: exp_f64:
471 ; RV64IFD: # %bb.0:
472 ; RV64IFD-NEXT: addi sp, sp, -16
473 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
474 ; RV64IFD-NEXT: call exp
475 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
476 ; RV64IFD-NEXT: addi sp, sp, 16
477 ; RV64IFD-NEXT: ret
478 ;
479 ; RV32IZFINXZDINX-LABEL: exp_f64:
480 ; RV32IZFINXZDINX: # %bb.0:
481 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
482 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
483 ; RV32IZFINXZDINX-NEXT: call exp
484 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
485 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
486 ; RV32IZFINXZDINX-NEXT: ret
487 ;
488 ; RV64IZFINXZDINX-LABEL: exp_f64:
489 ; RV64IZFINXZDINX: # %bb.0:
490 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
491 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
492 ; RV64IZFINXZDINX-NEXT: call exp
493 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
494 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
495 ; RV64IZFINXZDINX-NEXT: ret
496 ;
497 ; RV32I-LABEL: exp_f64:
498 ; RV32I: # %bb.0:
499 ; RV32I-NEXT: addi sp, sp, -16
500 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
501 ; RV32I-NEXT: call exp
502 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
503 ; RV32I-NEXT: addi sp, sp, 16
504 ; RV32I-NEXT: ret
505 ;
506 ; RV64I-LABEL: exp_f64:
507 ; RV64I: # %bb.0:
508 ; RV64I-NEXT: addi sp, sp, -16
509 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
510 ; RV64I-NEXT: call exp
511 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
512 ; RV64I-NEXT: addi sp, sp, 16
513 ; RV64I-NEXT: ret
514 %1 = call double @llvm.experimental.constrained.exp.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
515 ret double %1
516 }
518 declare double @llvm.experimental.constrained.exp2.f64(double, metadata, metadata)
520 define double @exp2_f64(double %a) nounwind strictfp {
521 ; RV32IFD-LABEL: exp2_f64:
522 ; RV32IFD: # %bb.0:
523 ; RV32IFD-NEXT: addi sp, sp, -16
524 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
525 ; RV32IFD-NEXT: call exp2
526 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
527 ; RV32IFD-NEXT: addi sp, sp, 16
528 ; RV32IFD-NEXT: ret
529 ;
530 ; RV64IFD-LABEL: exp2_f64:
531 ; RV64IFD: # %bb.0:
532 ; RV64IFD-NEXT: addi sp, sp, -16
533 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
534 ; RV64IFD-NEXT: call exp2
535 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
536 ; RV64IFD-NEXT: addi sp, sp, 16
537 ; RV64IFD-NEXT: ret
538 ;
539 ; RV32IZFINXZDINX-LABEL: exp2_f64:
540 ; RV32IZFINXZDINX: # %bb.0:
541 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
542 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
543 ; RV32IZFINXZDINX-NEXT: call exp2
544 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
545 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
546 ; RV32IZFINXZDINX-NEXT: ret
547 ;
548 ; RV64IZFINXZDINX-LABEL: exp2_f64:
549 ; RV64IZFINXZDINX: # %bb.0:
550 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
551 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
552 ; RV64IZFINXZDINX-NEXT: call exp2
553 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
554 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
555 ; RV64IZFINXZDINX-NEXT: ret
556 ;
557 ; RV32I-LABEL: exp2_f64:
558 ; RV32I: # %bb.0:
559 ; RV32I-NEXT: addi sp, sp, -16
560 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
561 ; RV32I-NEXT: call exp2
562 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
563 ; RV32I-NEXT: addi sp, sp, 16
564 ; RV32I-NEXT: ret
565 ;
566 ; RV64I-LABEL: exp2_f64:
567 ; RV64I: # %bb.0:
568 ; RV64I-NEXT: addi sp, sp, -16
569 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
570 ; RV64I-NEXT: call exp2
571 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
572 ; RV64I-NEXT: addi sp, sp, 16
573 ; RV64I-NEXT: ret
574 %1 = call double @llvm.experimental.constrained.exp2.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
575 ret double %1
576 }
578 declare double @llvm.experimental.constrained.log.f64(double, metadata, metadata)
580 define double @log_f64(double %a) nounwind strictfp {
581 ; RV32IFD-LABEL: log_f64:
582 ; RV32IFD: # %bb.0:
583 ; RV32IFD-NEXT: addi sp, sp, -16
584 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
585 ; RV32IFD-NEXT: call log
586 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
587 ; RV32IFD-NEXT: addi sp, sp, 16
588 ; RV32IFD-NEXT: ret
589 ;
590 ; RV64IFD-LABEL: log_f64:
591 ; RV64IFD: # %bb.0:
592 ; RV64IFD-NEXT: addi sp, sp, -16
593 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
594 ; RV64IFD-NEXT: call log
595 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
596 ; RV64IFD-NEXT: addi sp, sp, 16
597 ; RV64IFD-NEXT: ret
598 ;
599 ; RV32IZFINXZDINX-LABEL: log_f64:
600 ; RV32IZFINXZDINX: # %bb.0:
601 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
602 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
603 ; RV32IZFINXZDINX-NEXT: call log
604 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
605 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
606 ; RV32IZFINXZDINX-NEXT: ret
607 ;
608 ; RV64IZFINXZDINX-LABEL: log_f64:
609 ; RV64IZFINXZDINX: # %bb.0:
610 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
611 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
612 ; RV64IZFINXZDINX-NEXT: call log
613 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
614 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
615 ; RV64IZFINXZDINX-NEXT: ret
616 ;
617 ; RV32I-LABEL: log_f64:
618 ; RV32I: # %bb.0:
619 ; RV32I-NEXT: addi sp, sp, -16
620 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
621 ; RV32I-NEXT: call log
622 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
623 ; RV32I-NEXT: addi sp, sp, 16
624 ; RV32I-NEXT: ret
625 ;
626 ; RV64I-LABEL: log_f64:
627 ; RV64I: # %bb.0:
628 ; RV64I-NEXT: addi sp, sp, -16
629 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
630 ; RV64I-NEXT: call log
631 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
632 ; RV64I-NEXT: addi sp, sp, 16
633 ; RV64I-NEXT: ret
634 %1 = call double @llvm.experimental.constrained.log.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
635 ret double %1
636 }
638 declare double @llvm.experimental.constrained.log10.f64(double, metadata, metadata)
640 define double @log10_f64(double %a) nounwind strictfp {
641 ; RV32IFD-LABEL: log10_f64:
642 ; RV32IFD: # %bb.0:
643 ; RV32IFD-NEXT: addi sp, sp, -16
644 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
645 ; RV32IFD-NEXT: call log10
646 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
647 ; RV32IFD-NEXT: addi sp, sp, 16
648 ; RV32IFD-NEXT: ret
649 ;
650 ; RV64IFD-LABEL: log10_f64:
651 ; RV64IFD: # %bb.0:
652 ; RV64IFD-NEXT: addi sp, sp, -16
653 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
654 ; RV64IFD-NEXT: call log10
655 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
656 ; RV64IFD-NEXT: addi sp, sp, 16
657 ; RV64IFD-NEXT: ret
658 ;
659 ; RV32IZFINXZDINX-LABEL: log10_f64:
660 ; RV32IZFINXZDINX: # %bb.0:
661 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
662 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
663 ; RV32IZFINXZDINX-NEXT: call log10
664 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
665 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
666 ; RV32IZFINXZDINX-NEXT: ret
667 ;
668 ; RV64IZFINXZDINX-LABEL: log10_f64:
669 ; RV64IZFINXZDINX: # %bb.0:
670 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
671 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
672 ; RV64IZFINXZDINX-NEXT: call log10
673 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
674 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
675 ; RV64IZFINXZDINX-NEXT: ret
676 ;
677 ; RV32I-LABEL: log10_f64:
678 ; RV32I: # %bb.0:
679 ; RV32I-NEXT: addi sp, sp, -16
680 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
681 ; RV32I-NEXT: call log10
682 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
683 ; RV32I-NEXT: addi sp, sp, 16
684 ; RV32I-NEXT: ret
685 ;
686 ; RV64I-LABEL: log10_f64:
687 ; RV64I: # %bb.0:
688 ; RV64I-NEXT: addi sp, sp, -16
689 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
690 ; RV64I-NEXT: call log10
691 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
692 ; RV64I-NEXT: addi sp, sp, 16
693 ; RV64I-NEXT: ret
694 %1 = call double @llvm.experimental.constrained.log10.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
695 ret double %1
696 }
698 declare double @llvm.experimental.constrained.log2.f64(double, metadata, metadata)
700 define double @log2_f64(double %a) nounwind strictfp {
701 ; RV32IFD-LABEL: log2_f64:
702 ; RV32IFD: # %bb.0:
703 ; RV32IFD-NEXT: addi sp, sp, -16
704 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
705 ; RV32IFD-NEXT: call log2
706 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
707 ; RV32IFD-NEXT: addi sp, sp, 16
708 ; RV32IFD-NEXT: ret
709 ;
710 ; RV64IFD-LABEL: log2_f64:
711 ; RV64IFD: # %bb.0:
712 ; RV64IFD-NEXT: addi sp, sp, -16
713 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
714 ; RV64IFD-NEXT: call log2
715 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
716 ; RV64IFD-NEXT: addi sp, sp, 16
717 ; RV64IFD-NEXT: ret
718 ;
719 ; RV32IZFINXZDINX-LABEL: log2_f64:
720 ; RV32IZFINXZDINX: # %bb.0:
721 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
722 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
723 ; RV32IZFINXZDINX-NEXT: call log2
724 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
725 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
726 ; RV32IZFINXZDINX-NEXT: ret
727 ;
728 ; RV64IZFINXZDINX-LABEL: log2_f64:
729 ; RV64IZFINXZDINX: # %bb.0:
730 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
731 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
732 ; RV64IZFINXZDINX-NEXT: call log2
733 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
734 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
735 ; RV64IZFINXZDINX-NEXT: ret
736 ;
737 ; RV32I-LABEL: log2_f64:
738 ; RV32I: # %bb.0:
739 ; RV32I-NEXT: addi sp, sp, -16
740 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
741 ; RV32I-NEXT: call log2
742 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
743 ; RV32I-NEXT: addi sp, sp, 16
744 ; RV32I-NEXT: ret
745 ;
746 ; RV64I-LABEL: log2_f64:
747 ; RV64I: # %bb.0:
748 ; RV64I-NEXT: addi sp, sp, -16
749 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
750 ; RV64I-NEXT: call log2
751 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
752 ; RV64I-NEXT: addi sp, sp, 16
753 ; RV64I-NEXT: ret
754 %1 = call double @llvm.experimental.constrained.log2.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
755 ret double %1
756 }
758 declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
760 define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
761 ; CHECKIFD-LABEL: fma_f64:
762 ; CHECKIFD: # %bb.0:
763 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
764 ; CHECKIFD-NEXT: ret
765 ;
766 ; RV32IZFINXZDINX-LABEL: fma_f64:
767 ; RV32IZFINXZDINX: # %bb.0:
768 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
769 ; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
770 ; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
771 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
772 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
773 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
774 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
775 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
776 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
777 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
778 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
779 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
780 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
781 ; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
782 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
783 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
784 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
785 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
786 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
787 ; RV32IZFINXZDINX-NEXT: ret
788 ;
789 ; RV64IZFINXZDINX-LABEL: fma_f64:
790 ; RV64IZFINXZDINX: # %bb.0:
791 ; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
792 ; RV64IZFINXZDINX-NEXT: ret
793 ;
794 ; RV32I-LABEL: fma_f64:
795 ; RV32I: # %bb.0:
796 ; RV32I-NEXT: addi sp, sp, -16
797 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
798 ; RV32I-NEXT: call fma
799 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
800 ; RV32I-NEXT: addi sp, sp, 16
801 ; RV32I-NEXT: ret
802 ;
803 ; RV64I-LABEL: fma_f64:
804 ; RV64I: # %bb.0:
805 ; RV64I-NEXT: addi sp, sp, -16
806 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
807 ; RV64I-NEXT: call fma
808 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
809 ; RV64I-NEXT: addi sp, sp, 16
810 ; RV64I-NEXT: ret
811 %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
812 ret double %1
813 }
815 declare double @llvm.experimental.constrained.fmuladd.f64(double, double, double, metadata, metadata)
817 define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp {
818 ; CHECKIFD-LABEL: fmuladd_f64:
819 ; CHECKIFD: # %bb.0:
820 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
821 ; CHECKIFD-NEXT: ret
822 ;
823 ; RV32IZFINXZDINX-LABEL: fmuladd_f64:
824 ; RV32IZFINXZDINX: # %bb.0:
825 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
826 ; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
827 ; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
828 ; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
829 ; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
830 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
831 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
832 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
833 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
834 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
835 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
836 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
837 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
838 ; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
839 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
840 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
841 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
842 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
843 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
844 ; RV32IZFINXZDINX-NEXT: ret
845 ;
846 ; RV64IZFINXZDINX-LABEL: fmuladd_f64:
847 ; RV64IZFINXZDINX: # %bb.0:
848 ; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
849 ; RV64IZFINXZDINX-NEXT: ret
850 ;
851 ; RV32I-LABEL: fmuladd_f64:
852 ; RV32I: # %bb.0:
853 ; RV32I-NEXT: addi sp, sp, -16
854 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
855 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
856 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
857 ; RV32I-NEXT: mv s0, a5
858 ; RV32I-NEXT: mv s1, a4
859 ; RV32I-NEXT: call __muldf3
860 ; RV32I-NEXT: mv a2, s1
861 ; RV32I-NEXT: mv a3, s0
862 ; RV32I-NEXT: call __adddf3
863 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
864 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
865 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
866 ; RV32I-NEXT: addi sp, sp, 16
867 ; RV32I-NEXT: ret
868 ;
869 ; RV64I-LABEL: fmuladd_f64:
870 ; RV64I: # %bb.0:
871 ; RV64I-NEXT: addi sp, sp, -16
872 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
873 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
874 ; RV64I-NEXT: mv s0, a2
875 ; RV64I-NEXT: call __muldf3
876 ; RV64I-NEXT: mv a1, s0
877 ; RV64I-NEXT: call __adddf3
878 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
879 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
880 ; RV64I-NEXT: addi sp, sp, 16
881 ; RV64I-NEXT: ret
882 %1 = call double @llvm.experimental.constrained.fmuladd.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
883 ret double %1
884 }
886 declare double @llvm.experimental.constrained.minnum.f64(double, double, metadata)
888 define double @minnum_f64(double %a, double %b) nounwind strictfp {
889 ; RV32IFD-LABEL: minnum_f64:
890 ; RV32IFD: # %bb.0:
891 ; RV32IFD-NEXT: addi sp, sp, -16
892 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
893 ; RV32IFD-NEXT: call fmin
894 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
895 ; RV32IFD-NEXT: addi sp, sp, 16
896 ; RV32IFD-NEXT: ret
897 ;
898 ; RV64IFD-LABEL: minnum_f64:
899 ; RV64IFD: # %bb.0:
900 ; RV64IFD-NEXT: addi sp, sp, -16
901 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
902 ; RV64IFD-NEXT: call fmin
903 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
904 ; RV64IFD-NEXT: addi sp, sp, 16
905 ; RV64IFD-NEXT: ret
906 ;
907 ; RV32IZFINXZDINX-LABEL: minnum_f64:
908 ; RV32IZFINXZDINX: # %bb.0:
909 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
910 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
911 ; RV32IZFINXZDINX-NEXT: call fmin
912 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
913 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
914 ; RV32IZFINXZDINX-NEXT: ret
915 ;
916 ; RV64IZFINXZDINX-LABEL: minnum_f64:
917 ; RV64IZFINXZDINX: # %bb.0:
918 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
919 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
920 ; RV64IZFINXZDINX-NEXT: call fmin
921 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
922 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
923 ; RV64IZFINXZDINX-NEXT: ret
924 ;
925 ; RV32I-LABEL: minnum_f64:
926 ; RV32I: # %bb.0:
927 ; RV32I-NEXT: addi sp, sp, -16
928 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
929 ; RV32I-NEXT: call fmin
930 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
931 ; RV32I-NEXT: addi sp, sp, 16
932 ; RV32I-NEXT: ret
933 ;
934 ; RV64I-LABEL: minnum_f64:
935 ; RV64I: # %bb.0:
936 ; RV64I-NEXT: addi sp, sp, -16
937 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
938 ; RV64I-NEXT: call fmin
939 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
940 ; RV64I-NEXT: addi sp, sp, 16
941 ; RV64I-NEXT: ret
942 %1 = call double @llvm.experimental.constrained.minnum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
943 ret double %1
944 }
946 declare double @llvm.experimental.constrained.maxnum.f64(double, double, metadata)
948 define double @maxnum_f64(double %a, double %b) nounwind strictfp {
949 ; RV32IFD-LABEL: maxnum_f64:
950 ; RV32IFD: # %bb.0:
951 ; RV32IFD-NEXT: addi sp, sp, -16
952 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
953 ; RV32IFD-NEXT: call fmax
954 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
955 ; RV32IFD-NEXT: addi sp, sp, 16
956 ; RV32IFD-NEXT: ret
957 ;
958 ; RV64IFD-LABEL: maxnum_f64:
959 ; RV64IFD: # %bb.0:
960 ; RV64IFD-NEXT: addi sp, sp, -16
961 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
962 ; RV64IFD-NEXT: call fmax
963 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
964 ; RV64IFD-NEXT: addi sp, sp, 16
965 ; RV64IFD-NEXT: ret
966 ;
967 ; RV32IZFINXZDINX-LABEL: maxnum_f64:
968 ; RV32IZFINXZDINX: # %bb.0:
969 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
970 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
971 ; RV32IZFINXZDINX-NEXT: call fmax
972 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
973 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
974 ; RV32IZFINXZDINX-NEXT: ret
975 ;
976 ; RV64IZFINXZDINX-LABEL: maxnum_f64:
977 ; RV64IZFINXZDINX: # %bb.0:
978 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
979 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
980 ; RV64IZFINXZDINX-NEXT: call fmax
981 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
982 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
983 ; RV64IZFINXZDINX-NEXT: ret
984 ;
985 ; RV32I-LABEL: maxnum_f64:
986 ; RV32I: # %bb.0:
987 ; RV32I-NEXT: addi sp, sp, -16
988 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
989 ; RV32I-NEXT: call fmax
990 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
991 ; RV32I-NEXT: addi sp, sp, 16
992 ; RV32I-NEXT: ret
993 ;
994 ; RV64I-LABEL: maxnum_f64:
995 ; RV64I: # %bb.0:
996 ; RV64I-NEXT: addi sp, sp, -16
997 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
998 ; RV64I-NEXT: call fmax
999 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1000 ; RV64I-NEXT: addi sp, sp, 16
1001 ; RV64I-NEXT: ret
1002 %1 = call double @llvm.experimental.constrained.maxnum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1003 ret double %1
1004 }
1006 ; TODO: FMINNAN and FMAXNAN aren't handled in
1007 ; SelectionDAGLegalize::ExpandNode.
1009 ; declare double @llvm.experimental.constrained.minimum.f64(double, double, metadata)
1011 ; define double @fminimum_f64(double %a, double %b) nounwind strictfp {
1012 ; %1 = call double @llvm.experimental.constrained.minimum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1013 ; ret double %1
1014 ; }
1016 ; declare double @llvm.experimental.constrained.maximum.f64(double, double, metadata)
1018 ; define double @fmaximum_f64(double %a, double %b) nounwind strictfp {
1019 ; %1 = call double @llvm.experimental.constrained.maximum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
1020 ; ret double %1
1021 ; }
1023 declare double @llvm.experimental.constrained.floor.f64(double, metadata)
1025 define double @floor_f64(double %a) nounwind strictfp {
1026 ; RV32IFD-LABEL: floor_f64:
1027 ; RV32IFD: # %bb.0:
1028 ; RV32IFD-NEXT: addi sp, sp, -16
1029 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1030 ; RV32IFD-NEXT: call floor
1031 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1032 ; RV32IFD-NEXT: addi sp, sp, 16
1033 ; RV32IFD-NEXT: ret
1034 ;
1035 ; RV64IFD-LABEL: floor_f64:
1036 ; RV64IFD: # %bb.0:
1037 ; RV64IFD-NEXT: addi sp, sp, -16
1038 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1039 ; RV64IFD-NEXT: call floor
1040 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1041 ; RV64IFD-NEXT: addi sp, sp, 16
1042 ; RV64IFD-NEXT: ret
1043 ;
1044 ; RV32IZFINXZDINX-LABEL: floor_f64:
1045 ; RV32IZFINXZDINX: # %bb.0:
1046 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1047 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1048 ; RV32IZFINXZDINX-NEXT: call floor
1049 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1050 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1051 ; RV32IZFINXZDINX-NEXT: ret
1052 ;
1053 ; RV64IZFINXZDINX-LABEL: floor_f64:
1054 ; RV64IZFINXZDINX: # %bb.0:
1055 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1056 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1057 ; RV64IZFINXZDINX-NEXT: call floor
1058 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1059 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1060 ; RV64IZFINXZDINX-NEXT: ret
1061 ;
1062 ; RV32I-LABEL: floor_f64:
1063 ; RV32I: # %bb.0:
1064 ; RV32I-NEXT: addi sp, sp, -16
1065 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1066 ; RV32I-NEXT: call floor
1067 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1068 ; RV32I-NEXT: addi sp, sp, 16
1069 ; RV32I-NEXT: ret
1070 ;
1071 ; RV64I-LABEL: floor_f64:
1072 ; RV64I: # %bb.0:
1073 ; RV64I-NEXT: addi sp, sp, -16
1074 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1075 ; RV64I-NEXT: call floor
1076 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1077 ; RV64I-NEXT: addi sp, sp, 16
1078 ; RV64I-NEXT: ret
1079 %1 = call double @llvm.experimental.constrained.floor.f64(double %a, metadata !"fpexcept.strict") strictfp
1080 ret double %1
1081 }
1083 declare double @llvm.experimental.constrained.ceil.f64(double, metadata)
1085 define double @ceil_f64(double %a) nounwind strictfp {
1086 ; RV32IFD-LABEL: ceil_f64:
1087 ; RV32IFD: # %bb.0:
1088 ; RV32IFD-NEXT: addi sp, sp, -16
1089 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1090 ; RV32IFD-NEXT: call ceil
1091 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1092 ; RV32IFD-NEXT: addi sp, sp, 16
1093 ; RV32IFD-NEXT: ret
1094 ;
1095 ; RV64IFD-LABEL: ceil_f64:
1096 ; RV64IFD: # %bb.0:
1097 ; RV64IFD-NEXT: addi sp, sp, -16
1098 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1099 ; RV64IFD-NEXT: call ceil
1100 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1101 ; RV64IFD-NEXT: addi sp, sp, 16
1102 ; RV64IFD-NEXT: ret
1103 ;
1104 ; RV32IZFINXZDINX-LABEL: ceil_f64:
1105 ; RV32IZFINXZDINX: # %bb.0:
1106 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1107 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1108 ; RV32IZFINXZDINX-NEXT: call ceil
1109 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1110 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1111 ; RV32IZFINXZDINX-NEXT: ret
1112 ;
1113 ; RV64IZFINXZDINX-LABEL: ceil_f64:
1114 ; RV64IZFINXZDINX: # %bb.0:
1115 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1116 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1117 ; RV64IZFINXZDINX-NEXT: call ceil
1118 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1119 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1120 ; RV64IZFINXZDINX-NEXT: ret
1121 ;
1122 ; RV32I-LABEL: ceil_f64:
1123 ; RV32I: # %bb.0:
1124 ; RV32I-NEXT: addi sp, sp, -16
1125 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1126 ; RV32I-NEXT: call ceil
1127 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1128 ; RV32I-NEXT: addi sp, sp, 16
1129 ; RV32I-NEXT: ret
1130 ;
1131 ; RV64I-LABEL: ceil_f64:
1132 ; RV64I: # %bb.0:
1133 ; RV64I-NEXT: addi sp, sp, -16
1134 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1135 ; RV64I-NEXT: call ceil
1136 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1137 ; RV64I-NEXT: addi sp, sp, 16
1138 ; RV64I-NEXT: ret
1139 %1 = call double @llvm.experimental.constrained.ceil.f64(double %a, metadata !"fpexcept.strict") strictfp
1140 ret double %1
1141 }
1143 declare double @llvm.experimental.constrained.trunc.f64(double, metadata)
1145 define double @trunc_f64(double %a) nounwind strictfp {
1146 ; RV32IFD-LABEL: trunc_f64:
1147 ; RV32IFD: # %bb.0:
1148 ; RV32IFD-NEXT: addi sp, sp, -16
1149 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1150 ; RV32IFD-NEXT: call trunc
1151 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1152 ; RV32IFD-NEXT: addi sp, sp, 16
1153 ; RV32IFD-NEXT: ret
1154 ;
1155 ; RV64IFD-LABEL: trunc_f64:
1156 ; RV64IFD: # %bb.0:
1157 ; RV64IFD-NEXT: addi sp, sp, -16
1158 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1159 ; RV64IFD-NEXT: call trunc
1160 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1161 ; RV64IFD-NEXT: addi sp, sp, 16
1162 ; RV64IFD-NEXT: ret
1163 ;
1164 ; RV32IZFINXZDINX-LABEL: trunc_f64:
1165 ; RV32IZFINXZDINX: # %bb.0:
1166 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1167 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1168 ; RV32IZFINXZDINX-NEXT: call trunc
1169 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1170 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1171 ; RV32IZFINXZDINX-NEXT: ret
1172 ;
1173 ; RV64IZFINXZDINX-LABEL: trunc_f64:
1174 ; RV64IZFINXZDINX: # %bb.0:
1175 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1176 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1177 ; RV64IZFINXZDINX-NEXT: call trunc
1178 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1179 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1180 ; RV64IZFINXZDINX-NEXT: ret
1181 ;
1182 ; RV32I-LABEL: trunc_f64:
1183 ; RV32I: # %bb.0:
1184 ; RV32I-NEXT: addi sp, sp, -16
1185 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1186 ; RV32I-NEXT: call trunc
1187 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1188 ; RV32I-NEXT: addi sp, sp, 16
1189 ; RV32I-NEXT: ret
1190 ;
1191 ; RV64I-LABEL: trunc_f64:
1192 ; RV64I: # %bb.0:
1193 ; RV64I-NEXT: addi sp, sp, -16
1194 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1195 ; RV64I-NEXT: call trunc
1196 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1197 ; RV64I-NEXT: addi sp, sp, 16
1198 ; RV64I-NEXT: ret
1199 %1 = call double @llvm.experimental.constrained.trunc.f64(double %a, metadata !"fpexcept.strict") strictfp
1200 ret double %1
1201 }
1203 declare double @llvm.experimental.constrained.rint.f64(double, metadata, metadata)
1205 define double @rint_f64(double %a) nounwind strictfp {
1206 ; RV32IFD-LABEL: rint_f64:
1207 ; RV32IFD: # %bb.0:
1208 ; RV32IFD-NEXT: addi sp, sp, -16
1209 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1210 ; RV32IFD-NEXT: call rint
1211 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1212 ; RV32IFD-NEXT: addi sp, sp, 16
1213 ; RV32IFD-NEXT: ret
1214 ;
1215 ; RV64IFD-LABEL: rint_f64:
1216 ; RV64IFD: # %bb.0:
1217 ; RV64IFD-NEXT: addi sp, sp, -16
1218 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1219 ; RV64IFD-NEXT: call rint
1220 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1221 ; RV64IFD-NEXT: addi sp, sp, 16
1222 ; RV64IFD-NEXT: ret
1223 ;
1224 ; RV32IZFINXZDINX-LABEL: rint_f64:
1225 ; RV32IZFINXZDINX: # %bb.0:
1226 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1227 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1228 ; RV32IZFINXZDINX-NEXT: call rint
1229 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1230 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1231 ; RV32IZFINXZDINX-NEXT: ret
1232 ;
1233 ; RV64IZFINXZDINX-LABEL: rint_f64:
1234 ; RV64IZFINXZDINX: # %bb.0:
1235 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1236 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1237 ; RV64IZFINXZDINX-NEXT: call rint
1238 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1239 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1240 ; RV64IZFINXZDINX-NEXT: ret
1241 ;
1242 ; RV32I-LABEL: rint_f64:
1243 ; RV32I: # %bb.0:
1244 ; RV32I-NEXT: addi sp, sp, -16
1245 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1246 ; RV32I-NEXT: call rint
1247 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1248 ; RV32I-NEXT: addi sp, sp, 16
1249 ; RV32I-NEXT: ret
1250 ;
1251 ; RV64I-LABEL: rint_f64:
1252 ; RV64I: # %bb.0:
1253 ; RV64I-NEXT: addi sp, sp, -16
1254 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1255 ; RV64I-NEXT: call rint
1256 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1257 ; RV64I-NEXT: addi sp, sp, 16
1258 ; RV64I-NEXT: ret
1259 %1 = call double @llvm.experimental.constrained.rint.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1260 ret double %1
1261 }
1263 declare double @llvm.experimental.constrained.nearbyint.f64(double, metadata, metadata)
1265 define double @nearbyint_f64(double %a) nounwind strictfp {
1266 ; RV32IFD-LABEL: nearbyint_f64:
1267 ; RV32IFD: # %bb.0:
1268 ; RV32IFD-NEXT: addi sp, sp, -16
1269 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1270 ; RV32IFD-NEXT: call nearbyint
1271 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1272 ; RV32IFD-NEXT: addi sp, sp, 16
1273 ; RV32IFD-NEXT: ret
1274 ;
1275 ; RV64IFD-LABEL: nearbyint_f64:
1276 ; RV64IFD: # %bb.0:
1277 ; RV64IFD-NEXT: addi sp, sp, -16
1278 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1279 ; RV64IFD-NEXT: call nearbyint
1280 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1281 ; RV64IFD-NEXT: addi sp, sp, 16
1282 ; RV64IFD-NEXT: ret
1283 ;
1284 ; RV32IZFINXZDINX-LABEL: nearbyint_f64:
1285 ; RV32IZFINXZDINX: # %bb.0:
1286 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1287 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1288 ; RV32IZFINXZDINX-NEXT: call nearbyint
1289 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1290 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1291 ; RV32IZFINXZDINX-NEXT: ret
1292 ;
1293 ; RV64IZFINXZDINX-LABEL: nearbyint_f64:
1294 ; RV64IZFINXZDINX: # %bb.0:
1295 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1296 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1297 ; RV64IZFINXZDINX-NEXT: call nearbyint
1298 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1299 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1300 ; RV64IZFINXZDINX-NEXT: ret
1301 ;
1302 ; RV32I-LABEL: nearbyint_f64:
1303 ; RV32I: # %bb.0:
1304 ; RV32I-NEXT: addi sp, sp, -16
1305 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1306 ; RV32I-NEXT: call nearbyint
1307 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1308 ; RV32I-NEXT: addi sp, sp, 16
1309 ; RV32I-NEXT: ret
1310 ;
1311 ; RV64I-LABEL: nearbyint_f64:
1312 ; RV64I: # %bb.0:
1313 ; RV64I-NEXT: addi sp, sp, -16
1314 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1315 ; RV64I-NEXT: call nearbyint
1316 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1317 ; RV64I-NEXT: addi sp, sp, 16
1318 ; RV64I-NEXT: ret
1319 %1 = call double @llvm.experimental.constrained.nearbyint.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1320 ret double %1
1321 }
1323 declare double @llvm.experimental.constrained.round.f64(double, metadata)
1325 define double @round_f64(double %a) nounwind strictfp {
1326 ; RV32IFD-LABEL: round_f64:
1327 ; RV32IFD: # %bb.0:
1328 ; RV32IFD-NEXT: addi sp, sp, -16
1329 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1330 ; RV32IFD-NEXT: call round
1331 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1332 ; RV32IFD-NEXT: addi sp, sp, 16
1333 ; RV32IFD-NEXT: ret
1334 ;
1335 ; RV64IFD-LABEL: round_f64:
1336 ; RV64IFD: # %bb.0:
1337 ; RV64IFD-NEXT: addi sp, sp, -16
1338 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1339 ; RV64IFD-NEXT: call round
1340 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1341 ; RV64IFD-NEXT: addi sp, sp, 16
1342 ; RV64IFD-NEXT: ret
1343 ;
1344 ; RV32IZFINXZDINX-LABEL: round_f64:
1345 ; RV32IZFINXZDINX: # %bb.0:
1346 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1347 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1348 ; RV32IZFINXZDINX-NEXT: call round
1349 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1350 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1351 ; RV32IZFINXZDINX-NEXT: ret
1352 ;
1353 ; RV64IZFINXZDINX-LABEL: round_f64:
1354 ; RV64IZFINXZDINX: # %bb.0:
1355 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1356 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1357 ; RV64IZFINXZDINX-NEXT: call round
1358 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1359 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1360 ; RV64IZFINXZDINX-NEXT: ret
1361 ;
1362 ; RV32I-LABEL: round_f64:
1363 ; RV32I: # %bb.0:
1364 ; RV32I-NEXT: addi sp, sp, -16
1365 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1366 ; RV32I-NEXT: call round
1367 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1368 ; RV32I-NEXT: addi sp, sp, 16
1369 ; RV32I-NEXT: ret
1370 ;
1371 ; RV64I-LABEL: round_f64:
1372 ; RV64I: # %bb.0:
1373 ; RV64I-NEXT: addi sp, sp, -16
1374 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1375 ; RV64I-NEXT: call round
1376 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1377 ; RV64I-NEXT: addi sp, sp, 16
1378 ; RV64I-NEXT: ret
1379 %1 = call double @llvm.experimental.constrained.round.f64(double %a, metadata !"fpexcept.strict") strictfp
1380 ret double %1
1381 }
1383 declare double @llvm.experimental.constrained.roundeven.f64(double, metadata)
1385 define double @roundeven_f64(double %a) nounwind strictfp {
1386 ; RV32IFD-LABEL: roundeven_f64:
1387 ; RV32IFD: # %bb.0:
1388 ; RV32IFD-NEXT: addi sp, sp, -16
1389 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1390 ; RV32IFD-NEXT: call roundeven
1391 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1392 ; RV32IFD-NEXT: addi sp, sp, 16
1393 ; RV32IFD-NEXT: ret
1394 ;
1395 ; RV64IFD-LABEL: roundeven_f64:
1396 ; RV64IFD: # %bb.0:
1397 ; RV64IFD-NEXT: addi sp, sp, -16
1398 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1399 ; RV64IFD-NEXT: call roundeven
1400 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1401 ; RV64IFD-NEXT: addi sp, sp, 16
1402 ; RV64IFD-NEXT: ret
1403 ;
1404 ; RV32IZFINXZDINX-LABEL: roundeven_f64:
1405 ; RV32IZFINXZDINX: # %bb.0:
1406 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1407 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1408 ; RV32IZFINXZDINX-NEXT: call roundeven
1409 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1410 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1411 ; RV32IZFINXZDINX-NEXT: ret
1412 ;
1413 ; RV64IZFINXZDINX-LABEL: roundeven_f64:
1414 ; RV64IZFINXZDINX: # %bb.0:
1415 ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1416 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1417 ; RV64IZFINXZDINX-NEXT: call roundeven
1418 ; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1419 ; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1420 ; RV64IZFINXZDINX-NEXT: ret
1421 ;
1422 ; RV32I-LABEL: roundeven_f64:
1423 ; RV32I: # %bb.0:
1424 ; RV32I-NEXT: addi sp, sp, -16
1425 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1426 ; RV32I-NEXT: call roundeven
1427 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1428 ; RV32I-NEXT: addi sp, sp, 16
1429 ; RV32I-NEXT: ret
1430 ;
1431 ; RV64I-LABEL: roundeven_f64:
1432 ; RV64I: # %bb.0:
1433 ; RV64I-NEXT: addi sp, sp, -16
1434 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1435 ; RV64I-NEXT: call roundeven
1436 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1437 ; RV64I-NEXT: addi sp, sp, 16
1438 ; RV64I-NEXT: ret
1439 %1 = call double @llvm.experimental.constrained.roundeven.f64(double %a, metadata !"fpexcept.strict") strictfp
1440 ret double %1
1441 }
1443 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f64(double, metadata, metadata)
1445 define iXLen @lrint_f64(double %a) nounwind strictfp {
1446 ; RV32IFD-LABEL: lrint_f64:
1447 ; RV32IFD: # %bb.0:
1448 ; RV32IFD-NEXT: fcvt.w.d a0, fa0
1449 ; RV32IFD-NEXT: ret
1450 ;
1451 ; RV64IFD-LABEL: lrint_f64:
1452 ; RV64IFD: # %bb.0:
1453 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
1454 ; RV64IFD-NEXT: ret
1455 ;
1456 ; RV32IZFINXZDINX-LABEL: lrint_f64:
1457 ; RV32IZFINXZDINX: # %bb.0:
1458 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1459 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1460 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1461 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1462 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1463 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0
1464 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1465 ; RV32IZFINXZDINX-NEXT: ret
1466 ;
1467 ; RV64IZFINXZDINX-LABEL: lrint_f64:
1468 ; RV64IZFINXZDINX: # %bb.0:
1469 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0
1470 ; RV64IZFINXZDINX-NEXT: ret
1471 ;
1472 ; RV32I-LABEL: lrint_f64:
1473 ; RV32I: # %bb.0:
1474 ; RV32I-NEXT: addi sp, sp, -16
1475 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1476 ; RV32I-NEXT: call lrint
1477 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1478 ; RV32I-NEXT: addi sp, sp, 16
1479 ; RV32I-NEXT: ret
1480 ;
1481 ; RV64I-LABEL: lrint_f64:
1482 ; RV64I: # %bb.0:
1483 ; RV64I-NEXT: addi sp, sp, -16
1484 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1485 ; RV64I-NEXT: call lrint
1486 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1487 ; RV64I-NEXT: addi sp, sp, 16
1488 ; RV64I-NEXT: ret
1489 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1490 ret iXLen %1
1491 }
1493 declare iXLen @llvm.experimental.constrained.lround.iXLen.f64(double, metadata)
1495 define iXLen @lround_f64(double %a) nounwind strictfp {
1496 ; RV32IFD-LABEL: lround_f64:
1497 ; RV32IFD: # %bb.0:
1498 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
1499 ; RV32IFD-NEXT: ret
1500 ;
1501 ; RV64IFD-LABEL: lround_f64:
1502 ; RV64IFD: # %bb.0:
1503 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
1504 ; RV64IFD-NEXT: ret
1505 ;
1506 ; RV32IZFINXZDINX-LABEL: lround_f64:
1507 ; RV32IZFINXZDINX: # %bb.0:
1508 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1509 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1510 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1511 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1512 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1513 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
1514 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1515 ; RV32IZFINXZDINX-NEXT: ret
1516 ;
1517 ; RV64IZFINXZDINX-LABEL: lround_f64:
1518 ; RV64IZFINXZDINX: # %bb.0:
1519 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm
1520 ; RV64IZFINXZDINX-NEXT: ret
1521 ;
1522 ; RV32I-LABEL: lround_f64:
1523 ; RV32I: # %bb.0:
1524 ; RV32I-NEXT: addi sp, sp, -16
1525 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1526 ; RV32I-NEXT: call lround
1527 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1528 ; RV32I-NEXT: addi sp, sp, 16
1529 ; RV32I-NEXT: ret
1530 ;
1531 ; RV64I-LABEL: lround_f64:
1532 ; RV64I: # %bb.0:
1533 ; RV64I-NEXT: addi sp, sp, -16
1534 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1535 ; RV64I-NEXT: call lround
1536 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1537 ; RV64I-NEXT: addi sp, sp, 16
1538 ; RV64I-NEXT: ret
1539 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f64(double %a, metadata !"fpexcept.strict") strictfp
1540 ret iXLen %1
1541 }
1543 declare i64 @llvm.experimental.constrained.llrint.i64.f64(double, metadata, metadata)
1545 define i64 @llrint_f64(double %a) nounwind strictfp {
1546 ; RV32IFD-LABEL: llrint_f64:
1547 ; RV32IFD: # %bb.0:
1548 ; RV32IFD-NEXT: addi sp, sp, -16
1549 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1550 ; RV32IFD-NEXT: call llrint
1551 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1552 ; RV32IFD-NEXT: addi sp, sp, 16
1553 ; RV32IFD-NEXT: ret
1554 ;
1555 ; RV64IFD-LABEL: llrint_f64:
1556 ; RV64IFD: # %bb.0:
1557 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
1558 ; RV64IFD-NEXT: ret
1559 ;
1560 ; RV32IZFINXZDINX-LABEL: llrint_f64:
1561 ; RV32IZFINXZDINX: # %bb.0:
1562 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1563 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1564 ; RV32IZFINXZDINX-NEXT: call llrint
1565 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1566 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1567 ; RV32IZFINXZDINX-NEXT: ret
1568 ;
1569 ; RV64IZFINXZDINX-LABEL: llrint_f64:
1570 ; RV64IZFINXZDINX: # %bb.0:
1571 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0
1572 ; RV64IZFINXZDINX-NEXT: ret
1573 ;
1574 ; RV32I-LABEL: llrint_f64:
1575 ; RV32I: # %bb.0:
1576 ; RV32I-NEXT: addi sp, sp, -16
1577 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1578 ; RV32I-NEXT: call llrint
1579 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1580 ; RV32I-NEXT: addi sp, sp, 16
1581 ; RV32I-NEXT: ret
1582 ;
1583 ; RV64I-LABEL: llrint_f64:
1584 ; RV64I: # %bb.0:
1585 ; RV64I-NEXT: addi sp, sp, -16
1586 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1587 ; RV64I-NEXT: call llrint
1588 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1589 ; RV64I-NEXT: addi sp, sp, 16
1590 ; RV64I-NEXT: ret
1591 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1592 ret i64 %1
1593 }
1595 declare i64 @llvm.experimental.constrained.llround.i64.f64(double, metadata)
1597 define i64 @llround_f64(double %a) nounwind strictfp {
1598 ; RV32IFD-LABEL: llround_f64:
1599 ; RV32IFD: # %bb.0:
1600 ; RV32IFD-NEXT: addi sp, sp, -16
1601 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1602 ; RV32IFD-NEXT: call llround
1603 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1604 ; RV32IFD-NEXT: addi sp, sp, 16
1605 ; RV32IFD-NEXT: ret
1606 ;
1607 ; RV64IFD-LABEL: llround_f64:
1608 ; RV64IFD: # %bb.0:
1609 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
1610 ; RV64IFD-NEXT: ret
1611 ;
1612 ; RV32IZFINXZDINX-LABEL: llround_f64:
1613 ; RV32IZFINXZDINX: # %bb.0:
1614 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1615 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1616 ; RV32IZFINXZDINX-NEXT: call llround
1617 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1618 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1619 ; RV32IZFINXZDINX-NEXT: ret
1620 ;
1621 ; RV64IZFINXZDINX-LABEL: llround_f64:
1622 ; RV64IZFINXZDINX: # %bb.0:
1623 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm
1624 ; RV64IZFINXZDINX-NEXT: ret
1625 ;
1626 ; RV32I-LABEL: llround_f64:
1627 ; RV32I: # %bb.0:
1628 ; RV32I-NEXT: addi sp, sp, -16
1629 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1630 ; RV32I-NEXT: call llround
1631 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1632 ; RV32I-NEXT: addi sp, sp, 16
1633 ; RV32I-NEXT: ret
1634 ;
1635 ; RV64I-LABEL: llround_f64:
1636 ; RV64I: # %bb.0:
1637 ; RV64I-NEXT: addi sp, sp, -16
1638 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1639 ; RV64I-NEXT: call llround
1640 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1641 ; RV64I-NEXT: addi sp, sp, 16
1642 ; RV64I-NEXT: ret
1643 %1 = call i64 @llvm.experimental.constrained.llround.i64.f64(double %a, metadata !"fpexcept.strict") strictfp
1644 ret i64 %1
1645 }