| blob | 626db1985bfc7ec5bff33ef63c6513041cdde975 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
3 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
4 ; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
6 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
7 ; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \
9 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \
10 ; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \
12 ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \
13 ; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
15 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
16 ; RUN: | FileCheck -check-prefix=RV32I %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
18 ; RUN: -verify-machineinstrs -disable-strictnode-mutation \
19 ; RUN: | FileCheck -check-prefix=RV64I %s
21 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
23 define float @sqrt_f32(float %a) nounwind strictfp {
24 ; CHECKIF-LABEL: sqrt_f32:
25 ; CHECKIF: # %bb.0:
26 ; CHECKIF-NEXT: fsqrt.s fa0, fa0
27 ; CHECKIF-NEXT: ret
28 ;
29 ; CHECKIZFINX-LABEL: sqrt_f32:
30 ; CHECKIZFINX: # %bb.0:
31 ; CHECKIZFINX-NEXT: fsqrt.s a0, a0
32 ; CHECKIZFINX-NEXT: ret
33 ;
34 ; RV32I-LABEL: sqrt_f32:
35 ; RV32I: # %bb.0:
36 ; RV32I-NEXT: addi sp, sp, -16
37 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
38 ; RV32I-NEXT: call sqrtf
39 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
40 ; RV32I-NEXT: addi sp, sp, 16
41 ; RV32I-NEXT: ret
42 ;
43 ; RV64I-LABEL: sqrt_f32:
44 ; RV64I: # %bb.0:
45 ; RV64I-NEXT: addi sp, sp, -16
46 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
47 ; RV64I-NEXT: call sqrtf
48 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
49 ; RV64I-NEXT: addi sp, sp, 16
50 ; RV64I-NEXT: ret
51 %1 = call float @llvm.experimental.constrained.sqrt.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
52 ret float %1
53 }
55 declare float @llvm.experimental.constrained.powi.f32.i32(float, i32, metadata, metadata)
57 define float @powi_f32(float %a, i32 %b) nounwind strictfp {
58 ; RV32IF-LABEL: powi_f32:
59 ; RV32IF: # %bb.0:
60 ; RV32IF-NEXT: addi sp, sp, -16
61 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
62 ; RV32IF-NEXT: call __powisf2
63 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
64 ; RV32IF-NEXT: addi sp, sp, 16
65 ; RV32IF-NEXT: ret
66 ;
67 ; RV64IF-LABEL: powi_f32:
68 ; RV64IF: # %bb.0:
69 ; RV64IF-NEXT: addi sp, sp, -16
70 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
71 ; RV64IF-NEXT: sext.w a0, a0
72 ; RV64IF-NEXT: call __powisf2
73 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
74 ; RV64IF-NEXT: addi sp, sp, 16
75 ; RV64IF-NEXT: ret
76 ;
77 ; RV32IZFINX-LABEL: powi_f32:
78 ; RV32IZFINX: # %bb.0:
79 ; RV32IZFINX-NEXT: addi sp, sp, -16
80 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
81 ; RV32IZFINX-NEXT: call __powisf2
82 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
83 ; RV32IZFINX-NEXT: addi sp, sp, 16
84 ; RV32IZFINX-NEXT: ret
85 ;
86 ; RV64IZFINX-LABEL: powi_f32:
87 ; RV64IZFINX: # %bb.0:
88 ; RV64IZFINX-NEXT: addi sp, sp, -16
89 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
90 ; RV64IZFINX-NEXT: sext.w a1, a1
91 ; RV64IZFINX-NEXT: call __powisf2
92 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
93 ; RV64IZFINX-NEXT: addi sp, sp, 16
94 ; RV64IZFINX-NEXT: ret
95 ;
96 ; RV32I-LABEL: powi_f32:
97 ; RV32I: # %bb.0:
98 ; RV32I-NEXT: addi sp, sp, -16
99 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
100 ; RV32I-NEXT: call __powisf2
101 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
102 ; RV32I-NEXT: addi sp, sp, 16
103 ; RV32I-NEXT: ret
104 ;
105 ; RV64I-LABEL: powi_f32:
106 ; RV64I: # %bb.0:
107 ; RV64I-NEXT: addi sp, sp, -16
108 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
109 ; RV64I-NEXT: sext.w a1, a1
110 ; RV64I-NEXT: call __powisf2
111 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
112 ; RV64I-NEXT: addi sp, sp, 16
113 ; RV64I-NEXT: ret
114 %1 = call float @llvm.experimental.constrained.powi.f32.i32(float %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
115 ret float %1
116 }
118 declare float @llvm.experimental.constrained.sin.f32(float, metadata, metadata)
120 define float @sin_f32(float %a) nounwind strictfp {
121 ; RV32IF-LABEL: sin_f32:
122 ; RV32IF: # %bb.0:
123 ; RV32IF-NEXT: addi sp, sp, -16
124 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
125 ; RV32IF-NEXT: call sinf
126 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
127 ; RV32IF-NEXT: addi sp, sp, 16
128 ; RV32IF-NEXT: ret
129 ;
130 ; RV64IF-LABEL: sin_f32:
131 ; RV64IF: # %bb.0:
132 ; RV64IF-NEXT: addi sp, sp, -16
133 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
134 ; RV64IF-NEXT: call sinf
135 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
136 ; RV64IF-NEXT: addi sp, sp, 16
137 ; RV64IF-NEXT: ret
138 ;
139 ; RV32IZFINX-LABEL: sin_f32:
140 ; RV32IZFINX: # %bb.0:
141 ; RV32IZFINX-NEXT: addi sp, sp, -16
142 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
143 ; RV32IZFINX-NEXT: call sinf
144 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
145 ; RV32IZFINX-NEXT: addi sp, sp, 16
146 ; RV32IZFINX-NEXT: ret
147 ;
148 ; RV64IZFINX-LABEL: sin_f32:
149 ; RV64IZFINX: # %bb.0:
150 ; RV64IZFINX-NEXT: addi sp, sp, -16
151 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
152 ; RV64IZFINX-NEXT: call sinf
153 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
154 ; RV64IZFINX-NEXT: addi sp, sp, 16
155 ; RV64IZFINX-NEXT: ret
156 ;
157 ; RV32I-LABEL: sin_f32:
158 ; RV32I: # %bb.0:
159 ; RV32I-NEXT: addi sp, sp, -16
160 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
161 ; RV32I-NEXT: call sinf
162 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
163 ; RV32I-NEXT: addi sp, sp, 16
164 ; RV32I-NEXT: ret
165 ;
166 ; RV64I-LABEL: sin_f32:
167 ; RV64I: # %bb.0:
168 ; RV64I-NEXT: addi sp, sp, -16
169 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
170 ; RV64I-NEXT: call sinf
171 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
172 ; RV64I-NEXT: addi sp, sp, 16
173 ; RV64I-NEXT: ret
174 %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
175 ret float %1
176 }
178 declare float @llvm.experimental.constrained.cos.f32(float, metadata, metadata)
180 define float @cos_f32(float %a) nounwind strictfp {
181 ; RV32IF-LABEL: cos_f32:
182 ; RV32IF: # %bb.0:
183 ; RV32IF-NEXT: addi sp, sp, -16
184 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
185 ; RV32IF-NEXT: call cosf
186 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
187 ; RV32IF-NEXT: addi sp, sp, 16
188 ; RV32IF-NEXT: ret
189 ;
190 ; RV64IF-LABEL: cos_f32:
191 ; RV64IF: # %bb.0:
192 ; RV64IF-NEXT: addi sp, sp, -16
193 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
194 ; RV64IF-NEXT: call cosf
195 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
196 ; RV64IF-NEXT: addi sp, sp, 16
197 ; RV64IF-NEXT: ret
198 ;
199 ; RV32IZFINX-LABEL: cos_f32:
200 ; RV32IZFINX: # %bb.0:
201 ; RV32IZFINX-NEXT: addi sp, sp, -16
202 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
203 ; RV32IZFINX-NEXT: call cosf
204 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
205 ; RV32IZFINX-NEXT: addi sp, sp, 16
206 ; RV32IZFINX-NEXT: ret
207 ;
208 ; RV64IZFINX-LABEL: cos_f32:
209 ; RV64IZFINX: # %bb.0:
210 ; RV64IZFINX-NEXT: addi sp, sp, -16
211 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
212 ; RV64IZFINX-NEXT: call cosf
213 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
214 ; RV64IZFINX-NEXT: addi sp, sp, 16
215 ; RV64IZFINX-NEXT: ret
216 ;
217 ; RV32I-LABEL: cos_f32:
218 ; RV32I: # %bb.0:
219 ; RV32I-NEXT: addi sp, sp, -16
220 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
221 ; RV32I-NEXT: call cosf
222 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
223 ; RV32I-NEXT: addi sp, sp, 16
224 ; RV32I-NEXT: ret
225 ;
226 ; RV64I-LABEL: cos_f32:
227 ; RV64I: # %bb.0:
228 ; RV64I-NEXT: addi sp, sp, -16
229 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
230 ; RV64I-NEXT: call cosf
231 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
232 ; RV64I-NEXT: addi sp, sp, 16
233 ; RV64I-NEXT: ret
234 %1 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
235 ret float %1
236 }
238 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
239 define float @sincos_f32(float %a) nounwind strictfp {
240 ; RV32IF-LABEL: sincos_f32:
241 ; RV32IF: # %bb.0:
242 ; RV32IF-NEXT: addi sp, sp, -16
243 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
244 ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
245 ; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
246 ; RV32IF-NEXT: fmv.s fs0, fa0
247 ; RV32IF-NEXT: call sinf
248 ; RV32IF-NEXT: fmv.s fs1, fa0
249 ; RV32IF-NEXT: fmv.s fa0, fs0
250 ; RV32IF-NEXT: call cosf
251 ; RV32IF-NEXT: fadd.s fa0, fs1, fa0
252 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
253 ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
254 ; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
255 ; RV32IF-NEXT: addi sp, sp, 16
256 ; RV32IF-NEXT: ret
257 ;
258 ; RV64IF-LABEL: sincos_f32:
259 ; RV64IF: # %bb.0:
260 ; RV64IF-NEXT: addi sp, sp, -16
261 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
262 ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
263 ; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
264 ; RV64IF-NEXT: fmv.s fs0, fa0
265 ; RV64IF-NEXT: call sinf
266 ; RV64IF-NEXT: fmv.s fs1, fa0
267 ; RV64IF-NEXT: fmv.s fa0, fs0
268 ; RV64IF-NEXT: call cosf
269 ; RV64IF-NEXT: fadd.s fa0, fs1, fa0
270 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
271 ; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
272 ; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
273 ; RV64IF-NEXT: addi sp, sp, 16
274 ; RV64IF-NEXT: ret
275 ;
276 ; RV32IZFINX-LABEL: sincos_f32:
277 ; RV32IZFINX: # %bb.0:
278 ; RV32IZFINX-NEXT: addi sp, sp, -16
279 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
280 ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
281 ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
282 ; RV32IZFINX-NEXT: mv s0, a0
283 ; RV32IZFINX-NEXT: call sinf
284 ; RV32IZFINX-NEXT: mv s1, a0
285 ; RV32IZFINX-NEXT: mv a0, s0
286 ; RV32IZFINX-NEXT: call cosf
287 ; RV32IZFINX-NEXT: fadd.s a0, s1, a0
288 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
289 ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
290 ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
291 ; RV32IZFINX-NEXT: addi sp, sp, 16
292 ; RV32IZFINX-NEXT: ret
293 ;
294 ; RV64IZFINX-LABEL: sincos_f32:
295 ; RV64IZFINX: # %bb.0:
296 ; RV64IZFINX-NEXT: addi sp, sp, -32
297 ; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
298 ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
299 ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
300 ; RV64IZFINX-NEXT: mv s0, a0
301 ; RV64IZFINX-NEXT: call sinf
302 ; RV64IZFINX-NEXT: mv s1, a0
303 ; RV64IZFINX-NEXT: mv a0, s0
304 ; RV64IZFINX-NEXT: call cosf
305 ; RV64IZFINX-NEXT: fadd.s a0, s1, a0
306 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
307 ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
308 ; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
309 ; RV64IZFINX-NEXT: addi sp, sp, 32
310 ; RV64IZFINX-NEXT: ret
311 ;
312 ; RV32I-LABEL: sincos_f32:
313 ; RV32I: # %bb.0:
314 ; RV32I-NEXT: addi sp, sp, -16
315 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
316 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
317 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
318 ; RV32I-NEXT: mv s0, a0
319 ; RV32I-NEXT: call sinf
320 ; RV32I-NEXT: mv s1, a0
321 ; RV32I-NEXT: mv a0, s0
322 ; RV32I-NEXT: call cosf
323 ; RV32I-NEXT: mv a1, a0
324 ; RV32I-NEXT: mv a0, s1
325 ; RV32I-NEXT: call __addsf3
326 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
327 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
328 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
329 ; RV32I-NEXT: addi sp, sp, 16
330 ; RV32I-NEXT: ret
331 ;
332 ; RV64I-LABEL: sincos_f32:
333 ; RV64I: # %bb.0:
334 ; RV64I-NEXT: addi sp, sp, -32
335 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
336 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
337 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
338 ; RV64I-NEXT: mv s0, a0
339 ; RV64I-NEXT: call sinf
340 ; RV64I-NEXT: mv s1, a0
341 ; RV64I-NEXT: mv a0, s0
342 ; RV64I-NEXT: call cosf
343 ; RV64I-NEXT: mv a1, a0
344 ; RV64I-NEXT: mv a0, s1
345 ; RV64I-NEXT: call __addsf3
346 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
347 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
348 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
349 ; RV64I-NEXT: addi sp, sp, 32
350 ; RV64I-NEXT: ret
351 %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
352 %2 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
353 %3 = fadd float %1, %2
354 ret float %3
355 }
357 declare float @llvm.experimental.constrained.pow.f32(float, float, metadata, metadata)
359 define float @pow_f32(float %a, float %b) nounwind strictfp {
360 ; RV32IF-LABEL: pow_f32:
361 ; RV32IF: # %bb.0:
362 ; RV32IF-NEXT: addi sp, sp, -16
363 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
364 ; RV32IF-NEXT: call powf
365 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
366 ; RV32IF-NEXT: addi sp, sp, 16
367 ; RV32IF-NEXT: ret
368 ;
369 ; RV64IF-LABEL: pow_f32:
370 ; RV64IF: # %bb.0:
371 ; RV64IF-NEXT: addi sp, sp, -16
372 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
373 ; RV64IF-NEXT: call powf
374 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
375 ; RV64IF-NEXT: addi sp, sp, 16
376 ; RV64IF-NEXT: ret
377 ;
378 ; RV32IZFINX-LABEL: pow_f32:
379 ; RV32IZFINX: # %bb.0:
380 ; RV32IZFINX-NEXT: addi sp, sp, -16
381 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
382 ; RV32IZFINX-NEXT: call powf
383 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
384 ; RV32IZFINX-NEXT: addi sp, sp, 16
385 ; RV32IZFINX-NEXT: ret
386 ;
387 ; RV64IZFINX-LABEL: pow_f32:
388 ; RV64IZFINX: # %bb.0:
389 ; RV64IZFINX-NEXT: addi sp, sp, -16
390 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
391 ; RV64IZFINX-NEXT: call powf
392 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
393 ; RV64IZFINX-NEXT: addi sp, sp, 16
394 ; RV64IZFINX-NEXT: ret
395 ;
396 ; RV32I-LABEL: pow_f32:
397 ; RV32I: # %bb.0:
398 ; RV32I-NEXT: addi sp, sp, -16
399 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
400 ; RV32I-NEXT: call powf
401 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
402 ; RV32I-NEXT: addi sp, sp, 16
403 ; RV32I-NEXT: ret
404 ;
405 ; RV64I-LABEL: pow_f32:
406 ; RV64I: # %bb.0:
407 ; RV64I-NEXT: addi sp, sp, -16
408 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
409 ; RV64I-NEXT: call powf
410 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
411 ; RV64I-NEXT: addi sp, sp, 16
412 ; RV64I-NEXT: ret
413 %1 = call float @llvm.experimental.constrained.pow.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
414 ret float %1
415 }
417 declare float @llvm.experimental.constrained.exp.f32(float, metadata, metadata)
419 define float @exp_f32(float %a) nounwind strictfp {
420 ; RV32IF-LABEL: exp_f32:
421 ; RV32IF: # %bb.0:
422 ; RV32IF-NEXT: addi sp, sp, -16
423 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
424 ; RV32IF-NEXT: call expf
425 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
426 ; RV32IF-NEXT: addi sp, sp, 16
427 ; RV32IF-NEXT: ret
428 ;
429 ; RV64IF-LABEL: exp_f32:
430 ; RV64IF: # %bb.0:
431 ; RV64IF-NEXT: addi sp, sp, -16
432 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
433 ; RV64IF-NEXT: call expf
434 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
435 ; RV64IF-NEXT: addi sp, sp, 16
436 ; RV64IF-NEXT: ret
437 ;
438 ; RV32IZFINX-LABEL: exp_f32:
439 ; RV32IZFINX: # %bb.0:
440 ; RV32IZFINX-NEXT: addi sp, sp, -16
441 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
442 ; RV32IZFINX-NEXT: call expf
443 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
444 ; RV32IZFINX-NEXT: addi sp, sp, 16
445 ; RV32IZFINX-NEXT: ret
446 ;
447 ; RV64IZFINX-LABEL: exp_f32:
448 ; RV64IZFINX: # %bb.0:
449 ; RV64IZFINX-NEXT: addi sp, sp, -16
450 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
451 ; RV64IZFINX-NEXT: call expf
452 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
453 ; RV64IZFINX-NEXT: addi sp, sp, 16
454 ; RV64IZFINX-NEXT: ret
455 ;
456 ; RV32I-LABEL: exp_f32:
457 ; RV32I: # %bb.0:
458 ; RV32I-NEXT: addi sp, sp, -16
459 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
460 ; RV32I-NEXT: call expf
461 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
462 ; RV32I-NEXT: addi sp, sp, 16
463 ; RV32I-NEXT: ret
464 ;
465 ; RV64I-LABEL: exp_f32:
466 ; RV64I: # %bb.0:
467 ; RV64I-NEXT: addi sp, sp, -16
468 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
469 ; RV64I-NEXT: call expf
470 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
471 ; RV64I-NEXT: addi sp, sp, 16
472 ; RV64I-NEXT: ret
473 %1 = call float @llvm.experimental.constrained.exp.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
474 ret float %1
475 }
477 declare float @llvm.experimental.constrained.exp2.f32(float, metadata, metadata)
479 define float @exp2_f32(float %a) nounwind strictfp {
480 ; RV32IF-LABEL: exp2_f32:
481 ; RV32IF: # %bb.0:
482 ; RV32IF-NEXT: addi sp, sp, -16
483 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
484 ; RV32IF-NEXT: call exp2f
485 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
486 ; RV32IF-NEXT: addi sp, sp, 16
487 ; RV32IF-NEXT: ret
488 ;
489 ; RV64IF-LABEL: exp2_f32:
490 ; RV64IF: # %bb.0:
491 ; RV64IF-NEXT: addi sp, sp, -16
492 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
493 ; RV64IF-NEXT: call exp2f
494 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
495 ; RV64IF-NEXT: addi sp, sp, 16
496 ; RV64IF-NEXT: ret
497 ;
498 ; RV32IZFINX-LABEL: exp2_f32:
499 ; RV32IZFINX: # %bb.0:
500 ; RV32IZFINX-NEXT: addi sp, sp, -16
501 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
502 ; RV32IZFINX-NEXT: call exp2f
503 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
504 ; RV32IZFINX-NEXT: addi sp, sp, 16
505 ; RV32IZFINX-NEXT: ret
506 ;
507 ; RV64IZFINX-LABEL: exp2_f32:
508 ; RV64IZFINX: # %bb.0:
509 ; RV64IZFINX-NEXT: addi sp, sp, -16
510 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
511 ; RV64IZFINX-NEXT: call exp2f
512 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
513 ; RV64IZFINX-NEXT: addi sp, sp, 16
514 ; RV64IZFINX-NEXT: ret
515 ;
516 ; RV32I-LABEL: exp2_f32:
517 ; RV32I: # %bb.0:
518 ; RV32I-NEXT: addi sp, sp, -16
519 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
520 ; RV32I-NEXT: call exp2f
521 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
522 ; RV32I-NEXT: addi sp, sp, 16
523 ; RV32I-NEXT: ret
524 ;
525 ; RV64I-LABEL: exp2_f32:
526 ; RV64I: # %bb.0:
527 ; RV64I-NEXT: addi sp, sp, -16
528 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
529 ; RV64I-NEXT: call exp2f
530 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
531 ; RV64I-NEXT: addi sp, sp, 16
532 ; RV64I-NEXT: ret
533 %1 = call float @llvm.experimental.constrained.exp2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
534 ret float %1
535 }
537 declare float @llvm.experimental.constrained.log.f32(float, metadata, metadata)
539 define float @log_f32(float %a) nounwind strictfp {
540 ; RV32IF-LABEL: log_f32:
541 ; RV32IF: # %bb.0:
542 ; RV32IF-NEXT: addi sp, sp, -16
543 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
544 ; RV32IF-NEXT: call logf
545 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
546 ; RV32IF-NEXT: addi sp, sp, 16
547 ; RV32IF-NEXT: ret
548 ;
549 ; RV64IF-LABEL: log_f32:
550 ; RV64IF: # %bb.0:
551 ; RV64IF-NEXT: addi sp, sp, -16
552 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
553 ; RV64IF-NEXT: call logf
554 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
555 ; RV64IF-NEXT: addi sp, sp, 16
556 ; RV64IF-NEXT: ret
557 ;
558 ; RV32IZFINX-LABEL: log_f32:
559 ; RV32IZFINX: # %bb.0:
560 ; RV32IZFINX-NEXT: addi sp, sp, -16
561 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
562 ; RV32IZFINX-NEXT: call logf
563 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
564 ; RV32IZFINX-NEXT: addi sp, sp, 16
565 ; RV32IZFINX-NEXT: ret
566 ;
567 ; RV64IZFINX-LABEL: log_f32:
568 ; RV64IZFINX: # %bb.0:
569 ; RV64IZFINX-NEXT: addi sp, sp, -16
570 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
571 ; RV64IZFINX-NEXT: call logf
572 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
573 ; RV64IZFINX-NEXT: addi sp, sp, 16
574 ; RV64IZFINX-NEXT: ret
575 ;
576 ; RV32I-LABEL: log_f32:
577 ; RV32I: # %bb.0:
578 ; RV32I-NEXT: addi sp, sp, -16
579 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
580 ; RV32I-NEXT: call logf
581 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
582 ; RV32I-NEXT: addi sp, sp, 16
583 ; RV32I-NEXT: ret
584 ;
585 ; RV64I-LABEL: log_f32:
586 ; RV64I: # %bb.0:
587 ; RV64I-NEXT: addi sp, sp, -16
588 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
589 ; RV64I-NEXT: call logf
590 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
591 ; RV64I-NEXT: addi sp, sp, 16
592 ; RV64I-NEXT: ret
593 %1 = call float @llvm.experimental.constrained.log.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
594 ret float %1
595 }
597 declare float @llvm.experimental.constrained.log10.f32(float, metadata, metadata)
599 define float @log10_f32(float %a) nounwind strictfp {
600 ; RV32IF-LABEL: log10_f32:
601 ; RV32IF: # %bb.0:
602 ; RV32IF-NEXT: addi sp, sp, -16
603 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
604 ; RV32IF-NEXT: call log10f
605 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
606 ; RV32IF-NEXT: addi sp, sp, 16
607 ; RV32IF-NEXT: ret
608 ;
609 ; RV64IF-LABEL: log10_f32:
610 ; RV64IF: # %bb.0:
611 ; RV64IF-NEXT: addi sp, sp, -16
612 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
613 ; RV64IF-NEXT: call log10f
614 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
615 ; RV64IF-NEXT: addi sp, sp, 16
616 ; RV64IF-NEXT: ret
617 ;
618 ; RV32IZFINX-LABEL: log10_f32:
619 ; RV32IZFINX: # %bb.0:
620 ; RV32IZFINX-NEXT: addi sp, sp, -16
621 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
622 ; RV32IZFINX-NEXT: call log10f
623 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
624 ; RV32IZFINX-NEXT: addi sp, sp, 16
625 ; RV32IZFINX-NEXT: ret
626 ;
627 ; RV64IZFINX-LABEL: log10_f32:
628 ; RV64IZFINX: # %bb.0:
629 ; RV64IZFINX-NEXT: addi sp, sp, -16
630 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
631 ; RV64IZFINX-NEXT: call log10f
632 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
633 ; RV64IZFINX-NEXT: addi sp, sp, 16
634 ; RV64IZFINX-NEXT: ret
635 ;
636 ; RV32I-LABEL: log10_f32:
637 ; RV32I: # %bb.0:
638 ; RV32I-NEXT: addi sp, sp, -16
639 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
640 ; RV32I-NEXT: call log10f
641 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
642 ; RV32I-NEXT: addi sp, sp, 16
643 ; RV32I-NEXT: ret
644 ;
645 ; RV64I-LABEL: log10_f32:
646 ; RV64I: # %bb.0:
647 ; RV64I-NEXT: addi sp, sp, -16
648 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
649 ; RV64I-NEXT: call log10f
650 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
651 ; RV64I-NEXT: addi sp, sp, 16
652 ; RV64I-NEXT: ret
653 %1 = call float @llvm.experimental.constrained.log10.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
654 ret float %1
655 }
657 declare float @llvm.experimental.constrained.log2.f32(float, metadata, metadata)
659 define float @log2_f32(float %a) nounwind strictfp {
660 ; RV32IF-LABEL: log2_f32:
661 ; RV32IF: # %bb.0:
662 ; RV32IF-NEXT: addi sp, sp, -16
663 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
664 ; RV32IF-NEXT: call log2f
665 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
666 ; RV32IF-NEXT: addi sp, sp, 16
667 ; RV32IF-NEXT: ret
668 ;
669 ; RV64IF-LABEL: log2_f32:
670 ; RV64IF: # %bb.0:
671 ; RV64IF-NEXT: addi sp, sp, -16
672 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
673 ; RV64IF-NEXT: call log2f
674 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
675 ; RV64IF-NEXT: addi sp, sp, 16
676 ; RV64IF-NEXT: ret
677 ;
678 ; RV32IZFINX-LABEL: log2_f32:
679 ; RV32IZFINX: # %bb.0:
680 ; RV32IZFINX-NEXT: addi sp, sp, -16
681 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
682 ; RV32IZFINX-NEXT: call log2f
683 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
684 ; RV32IZFINX-NEXT: addi sp, sp, 16
685 ; RV32IZFINX-NEXT: ret
686 ;
687 ; RV64IZFINX-LABEL: log2_f32:
688 ; RV64IZFINX: # %bb.0:
689 ; RV64IZFINX-NEXT: addi sp, sp, -16
690 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
691 ; RV64IZFINX-NEXT: call log2f
692 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
693 ; RV64IZFINX-NEXT: addi sp, sp, 16
694 ; RV64IZFINX-NEXT: ret
695 ;
696 ; RV32I-LABEL: log2_f32:
697 ; RV32I: # %bb.0:
698 ; RV32I-NEXT: addi sp, sp, -16
699 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
700 ; RV32I-NEXT: call log2f
701 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
702 ; RV32I-NEXT: addi sp, sp, 16
703 ; RV32I-NEXT: ret
704 ;
705 ; RV64I-LABEL: log2_f32:
706 ; RV64I: # %bb.0:
707 ; RV64I-NEXT: addi sp, sp, -16
708 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
709 ; RV64I-NEXT: call log2f
710 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
711 ; RV64I-NEXT: addi sp, sp, 16
712 ; RV64I-NEXT: ret
713 %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
714 ret float %1
715 }
717 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
719 define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
720 ; CHECKIF-LABEL: fma_f32:
721 ; CHECKIF: # %bb.0:
722 ; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
723 ; CHECKIF-NEXT: ret
724 ;
725 ; CHECKIZFINX-LABEL: fma_f32:
726 ; CHECKIZFINX: # %bb.0:
727 ; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2
728 ; CHECKIZFINX-NEXT: ret
729 ;
730 ; RV32I-LABEL: fma_f32:
731 ; RV32I: # %bb.0:
732 ; RV32I-NEXT: addi sp, sp, -16
733 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
734 ; RV32I-NEXT: call fmaf
735 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
736 ; RV32I-NEXT: addi sp, sp, 16
737 ; RV32I-NEXT: ret
738 ;
739 ; RV64I-LABEL: fma_f32:
740 ; RV64I: # %bb.0:
741 ; RV64I-NEXT: addi sp, sp, -16
742 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
743 ; RV64I-NEXT: call fmaf
744 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
745 ; RV64I-NEXT: addi sp, sp, 16
746 ; RV64I-NEXT: ret
747 %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
748 ret float %1
749 }
751 declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)
753 define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
754 ; CHECKIF-LABEL: fmuladd_f32:
755 ; CHECKIF: # %bb.0:
756 ; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
757 ; CHECKIF-NEXT: ret
758 ;
759 ; CHECKIZFINX-LABEL: fmuladd_f32:
760 ; CHECKIZFINX: # %bb.0:
761 ; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2
762 ; CHECKIZFINX-NEXT: ret
763 ;
764 ; RV32I-LABEL: fmuladd_f32:
765 ; RV32I: # %bb.0:
766 ; RV32I-NEXT: addi sp, sp, -16
767 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
768 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
769 ; RV32I-NEXT: mv s0, a2
770 ; RV32I-NEXT: call __mulsf3
771 ; RV32I-NEXT: mv a1, s0
772 ; RV32I-NEXT: call __addsf3
773 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
774 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
775 ; RV32I-NEXT: addi sp, sp, 16
776 ; RV32I-NEXT: ret
777 ;
778 ; RV64I-LABEL: fmuladd_f32:
779 ; RV64I: # %bb.0:
780 ; RV64I-NEXT: addi sp, sp, -16
781 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
782 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
783 ; RV64I-NEXT: mv s0, a2
784 ; RV64I-NEXT: call __mulsf3
785 ; RV64I-NEXT: mv a1, s0
786 ; RV64I-NEXT: call __addsf3
787 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
788 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
789 ; RV64I-NEXT: addi sp, sp, 16
790 ; RV64I-NEXT: ret
791 %1 = call float @llvm.experimental.constrained.fmuladd.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
792 ret float %1
793 }
795 declare float @llvm.experimental.constrained.minnum.f32(float, float, metadata)
797 define float @minnum_f32(float %a, float %b) nounwind strictfp {
798 ; RV32IF-LABEL: minnum_f32:
799 ; RV32IF: # %bb.0:
800 ; RV32IF-NEXT: addi sp, sp, -16
801 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
802 ; RV32IF-NEXT: call fminf
803 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
804 ; RV32IF-NEXT: addi sp, sp, 16
805 ; RV32IF-NEXT: ret
806 ;
807 ; RV64IF-LABEL: minnum_f32:
808 ; RV64IF: # %bb.0:
809 ; RV64IF-NEXT: addi sp, sp, -16
810 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
811 ; RV64IF-NEXT: call fminf
812 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
813 ; RV64IF-NEXT: addi sp, sp, 16
814 ; RV64IF-NEXT: ret
815 ;
816 ; RV32IZFINX-LABEL: minnum_f32:
817 ; RV32IZFINX: # %bb.0:
818 ; RV32IZFINX-NEXT: addi sp, sp, -16
819 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
820 ; RV32IZFINX-NEXT: call fminf
821 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
822 ; RV32IZFINX-NEXT: addi sp, sp, 16
823 ; RV32IZFINX-NEXT: ret
824 ;
825 ; RV64IZFINX-LABEL: minnum_f32:
826 ; RV64IZFINX: # %bb.0:
827 ; RV64IZFINX-NEXT: addi sp, sp, -16
828 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
829 ; RV64IZFINX-NEXT: call fminf
830 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
831 ; RV64IZFINX-NEXT: addi sp, sp, 16
832 ; RV64IZFINX-NEXT: ret
833 ;
834 ; RV32I-LABEL: minnum_f32:
835 ; RV32I: # %bb.0:
836 ; RV32I-NEXT: addi sp, sp, -16
837 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
838 ; RV32I-NEXT: call fminf
839 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
840 ; RV32I-NEXT: addi sp, sp, 16
841 ; RV32I-NEXT: ret
842 ;
843 ; RV64I-LABEL: minnum_f32:
844 ; RV64I: # %bb.0:
845 ; RV64I-NEXT: addi sp, sp, -16
846 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
847 ; RV64I-NEXT: call fminf
848 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
849 ; RV64I-NEXT: addi sp, sp, 16
850 ; RV64I-NEXT: ret
851 %1 = call float @llvm.experimental.constrained.minnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
852 ret float %1
853 }
855 declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata)
857 define float @maxnum_f32(float %a, float %b) nounwind strictfp {
858 ; RV32IF-LABEL: maxnum_f32:
859 ; RV32IF: # %bb.0:
860 ; RV32IF-NEXT: addi sp, sp, -16
861 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
862 ; RV32IF-NEXT: call fmaxf
863 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
864 ; RV32IF-NEXT: addi sp, sp, 16
865 ; RV32IF-NEXT: ret
866 ;
867 ; RV64IF-LABEL: maxnum_f32:
868 ; RV64IF: # %bb.0:
869 ; RV64IF-NEXT: addi sp, sp, -16
870 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
871 ; RV64IF-NEXT: call fmaxf
872 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
873 ; RV64IF-NEXT: addi sp, sp, 16
874 ; RV64IF-NEXT: ret
875 ;
876 ; RV32IZFINX-LABEL: maxnum_f32:
877 ; RV32IZFINX: # %bb.0:
878 ; RV32IZFINX-NEXT: addi sp, sp, -16
879 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
880 ; RV32IZFINX-NEXT: call fmaxf
881 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
882 ; RV32IZFINX-NEXT: addi sp, sp, 16
883 ; RV32IZFINX-NEXT: ret
884 ;
885 ; RV64IZFINX-LABEL: maxnum_f32:
886 ; RV64IZFINX: # %bb.0:
887 ; RV64IZFINX-NEXT: addi sp, sp, -16
888 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
889 ; RV64IZFINX-NEXT: call fmaxf
890 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
891 ; RV64IZFINX-NEXT: addi sp, sp, 16
892 ; RV64IZFINX-NEXT: ret
893 ;
894 ; RV32I-LABEL: maxnum_f32:
895 ; RV32I: # %bb.0:
896 ; RV32I-NEXT: addi sp, sp, -16
897 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
898 ; RV32I-NEXT: call fmaxf
899 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
900 ; RV32I-NEXT: addi sp, sp, 16
901 ; RV32I-NEXT: ret
902 ;
903 ; RV64I-LABEL: maxnum_f32:
904 ; RV64I: # %bb.0:
905 ; RV64I-NEXT: addi sp, sp, -16
906 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
907 ; RV64I-NEXT: call fmaxf
908 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
909 ; RV64I-NEXT: addi sp, sp, 16
910 ; RV64I-NEXT: ret
911 %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
912 ret float %1
913 }
915 ; TODO: FMINNAN and FMAXNAN aren't handled in
916 ; SelectionDAGLegalize::ExpandNode.
918 ; declare float @llvm.experimental.constrained.minimum.f32(float, float, metadata)
920 ; define float @fminimum_f32(float %a, float %b) nounwind strictfp {
921 ; %1 = call float @llvm.experimental.constrained.minimum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
922 ; ret float %1
923 ; }
925 ; declare float @llvm.experimental.constrained.maximum.f32(float, float, metadata)
927 ; define float @fmaximum_f32(float %a, float %b) nounwind strictfp {
928 ; %1 = call float @llvm.experimental.constrained.maximum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
929 ; ret float %1
930 ; }
932 declare float @llvm.experimental.constrained.floor.f32(float, metadata)
934 define float @floor_f32(float %a) nounwind strictfp {
935 ; RV32IF-LABEL: floor_f32:
936 ; RV32IF: # %bb.0:
937 ; RV32IF-NEXT: addi sp, sp, -16
938 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
939 ; RV32IF-NEXT: call floorf
940 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
941 ; RV32IF-NEXT: addi sp, sp, 16
942 ; RV32IF-NEXT: ret
943 ;
944 ; RV64IF-LABEL: floor_f32:
945 ; RV64IF: # %bb.0:
946 ; RV64IF-NEXT: addi sp, sp, -16
947 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
948 ; RV64IF-NEXT: call floorf
949 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
950 ; RV64IF-NEXT: addi sp, sp, 16
951 ; RV64IF-NEXT: ret
952 ;
953 ; RV32IZFINX-LABEL: floor_f32:
954 ; RV32IZFINX: # %bb.0:
955 ; RV32IZFINX-NEXT: addi sp, sp, -16
956 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
957 ; RV32IZFINX-NEXT: call floorf
958 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
959 ; RV32IZFINX-NEXT: addi sp, sp, 16
960 ; RV32IZFINX-NEXT: ret
961 ;
962 ; RV64IZFINX-LABEL: floor_f32:
963 ; RV64IZFINX: # %bb.0:
964 ; RV64IZFINX-NEXT: addi sp, sp, -16
965 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
966 ; RV64IZFINX-NEXT: call floorf
967 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
968 ; RV64IZFINX-NEXT: addi sp, sp, 16
969 ; RV64IZFINX-NEXT: ret
970 ;
971 ; RV32I-LABEL: floor_f32:
972 ; RV32I: # %bb.0:
973 ; RV32I-NEXT: addi sp, sp, -16
974 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
975 ; RV32I-NEXT: call floorf
976 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
977 ; RV32I-NEXT: addi sp, sp, 16
978 ; RV32I-NEXT: ret
979 ;
980 ; RV64I-LABEL: floor_f32:
981 ; RV64I: # %bb.0:
982 ; RV64I-NEXT: addi sp, sp, -16
983 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
984 ; RV64I-NEXT: call floorf
985 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
986 ; RV64I-NEXT: addi sp, sp, 16
987 ; RV64I-NEXT: ret
988 %1 = call float @llvm.experimental.constrained.floor.f32(float %a, metadata !"fpexcept.strict") strictfp
989 ret float %1
990 }
992 declare float @llvm.experimental.constrained.ceil.f32(float, metadata)
994 define float @ceil_f32(float %a) nounwind strictfp {
995 ; RV32IF-LABEL: ceil_f32:
996 ; RV32IF: # %bb.0:
997 ; RV32IF-NEXT: addi sp, sp, -16
998 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
999 ; RV32IF-NEXT: call ceilf
1000 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1001 ; RV32IF-NEXT: addi sp, sp, 16
1002 ; RV32IF-NEXT: ret
1003 ;
1004 ; RV64IF-LABEL: ceil_f32:
1005 ; RV64IF: # %bb.0:
1006 ; RV64IF-NEXT: addi sp, sp, -16
1007 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1008 ; RV64IF-NEXT: call ceilf
1009 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1010 ; RV64IF-NEXT: addi sp, sp, 16
1011 ; RV64IF-NEXT: ret
1012 ;
1013 ; RV32IZFINX-LABEL: ceil_f32:
1014 ; RV32IZFINX: # %bb.0:
1015 ; RV32IZFINX-NEXT: addi sp, sp, -16
1016 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1017 ; RV32IZFINX-NEXT: call ceilf
1018 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1019 ; RV32IZFINX-NEXT: addi sp, sp, 16
1020 ; RV32IZFINX-NEXT: ret
1021 ;
1022 ; RV64IZFINX-LABEL: ceil_f32:
1023 ; RV64IZFINX: # %bb.0:
1024 ; RV64IZFINX-NEXT: addi sp, sp, -16
1025 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1026 ; RV64IZFINX-NEXT: call ceilf
1027 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1028 ; RV64IZFINX-NEXT: addi sp, sp, 16
1029 ; RV64IZFINX-NEXT: ret
1030 ;
1031 ; RV32I-LABEL: ceil_f32:
1032 ; RV32I: # %bb.0:
1033 ; RV32I-NEXT: addi sp, sp, -16
1034 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1035 ; RV32I-NEXT: call ceilf
1036 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1037 ; RV32I-NEXT: addi sp, sp, 16
1038 ; RV32I-NEXT: ret
1039 ;
1040 ; RV64I-LABEL: ceil_f32:
1041 ; RV64I: # %bb.0:
1042 ; RV64I-NEXT: addi sp, sp, -16
1043 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1044 ; RV64I-NEXT: call ceilf
1045 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1046 ; RV64I-NEXT: addi sp, sp, 16
1047 ; RV64I-NEXT: ret
1048 %1 = call float @llvm.experimental.constrained.ceil.f32(float %a, metadata !"fpexcept.strict") strictfp
1049 ret float %1
1050 }
1052 declare float @llvm.experimental.constrained.trunc.f32(float, metadata)
1054 define float @trunc_f32(float %a) nounwind strictfp {
1055 ; RV32IF-LABEL: trunc_f32:
1056 ; RV32IF: # %bb.0:
1057 ; RV32IF-NEXT: addi sp, sp, -16
1058 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1059 ; RV32IF-NEXT: call truncf
1060 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1061 ; RV32IF-NEXT: addi sp, sp, 16
1062 ; RV32IF-NEXT: ret
1063 ;
1064 ; RV64IF-LABEL: trunc_f32:
1065 ; RV64IF: # %bb.0:
1066 ; RV64IF-NEXT: addi sp, sp, -16
1067 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1068 ; RV64IF-NEXT: call truncf
1069 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1070 ; RV64IF-NEXT: addi sp, sp, 16
1071 ; RV64IF-NEXT: ret
1072 ;
1073 ; RV32IZFINX-LABEL: trunc_f32:
1074 ; RV32IZFINX: # %bb.0:
1075 ; RV32IZFINX-NEXT: addi sp, sp, -16
1076 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1077 ; RV32IZFINX-NEXT: call truncf
1078 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1079 ; RV32IZFINX-NEXT: addi sp, sp, 16
1080 ; RV32IZFINX-NEXT: ret
1081 ;
1082 ; RV64IZFINX-LABEL: trunc_f32:
1083 ; RV64IZFINX: # %bb.0:
1084 ; RV64IZFINX-NEXT: addi sp, sp, -16
1085 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1086 ; RV64IZFINX-NEXT: call truncf
1087 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1088 ; RV64IZFINX-NEXT: addi sp, sp, 16
1089 ; RV64IZFINX-NEXT: ret
1090 ;
1091 ; RV32I-LABEL: trunc_f32:
1092 ; RV32I: # %bb.0:
1093 ; RV32I-NEXT: addi sp, sp, -16
1094 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1095 ; RV32I-NEXT: call truncf
1096 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1097 ; RV32I-NEXT: addi sp, sp, 16
1098 ; RV32I-NEXT: ret
1099 ;
1100 ; RV64I-LABEL: trunc_f32:
1101 ; RV64I: # %bb.0:
1102 ; RV64I-NEXT: addi sp, sp, -16
1103 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1104 ; RV64I-NEXT: call truncf
1105 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1106 ; RV64I-NEXT: addi sp, sp, 16
1107 ; RV64I-NEXT: ret
1108 %1 = call float @llvm.experimental.constrained.trunc.f32(float %a, metadata !"fpexcept.strict") strictfp
1109 ret float %1
1110 }
1112 declare float @llvm.experimental.constrained.rint.f32(float, metadata, metadata)
1114 define float @rint_f32(float %a) nounwind strictfp {
1115 ; RV32IF-LABEL: rint_f32:
1116 ; RV32IF: # %bb.0:
1117 ; RV32IF-NEXT: addi sp, sp, -16
1118 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1119 ; RV32IF-NEXT: call rintf
1120 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1121 ; RV32IF-NEXT: addi sp, sp, 16
1122 ; RV32IF-NEXT: ret
1123 ;
1124 ; RV64IF-LABEL: rint_f32:
1125 ; RV64IF: # %bb.0:
1126 ; RV64IF-NEXT: addi sp, sp, -16
1127 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1128 ; RV64IF-NEXT: call rintf
1129 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1130 ; RV64IF-NEXT: addi sp, sp, 16
1131 ; RV64IF-NEXT: ret
1132 ;
1133 ; RV32IZFINX-LABEL: rint_f32:
1134 ; RV32IZFINX: # %bb.0:
1135 ; RV32IZFINX-NEXT: addi sp, sp, -16
1136 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1137 ; RV32IZFINX-NEXT: call rintf
1138 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1139 ; RV32IZFINX-NEXT: addi sp, sp, 16
1140 ; RV32IZFINX-NEXT: ret
1141 ;
1142 ; RV64IZFINX-LABEL: rint_f32:
1143 ; RV64IZFINX: # %bb.0:
1144 ; RV64IZFINX-NEXT: addi sp, sp, -16
1145 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1146 ; RV64IZFINX-NEXT: call rintf
1147 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1148 ; RV64IZFINX-NEXT: addi sp, sp, 16
1149 ; RV64IZFINX-NEXT: ret
1150 ;
1151 ; RV32I-LABEL: rint_f32:
1152 ; RV32I: # %bb.0:
1153 ; RV32I-NEXT: addi sp, sp, -16
1154 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1155 ; RV32I-NEXT: call rintf
1156 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1157 ; RV32I-NEXT: addi sp, sp, 16
1158 ; RV32I-NEXT: ret
1159 ;
1160 ; RV64I-LABEL: rint_f32:
1161 ; RV64I: # %bb.0:
1162 ; RV64I-NEXT: addi sp, sp, -16
1163 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1164 ; RV64I-NEXT: call rintf
1165 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1166 ; RV64I-NEXT: addi sp, sp, 16
1167 ; RV64I-NEXT: ret
1168 %1 = call float @llvm.experimental.constrained.rint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1169 ret float %1
1170 }
1172 declare float @llvm.experimental.constrained.nearbyint.f32(float, metadata, metadata)
1174 define float @nearbyint_f32(float %a) nounwind strictfp {
1175 ; RV32IF-LABEL: nearbyint_f32:
1176 ; RV32IF: # %bb.0:
1177 ; RV32IF-NEXT: addi sp, sp, -16
1178 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1179 ; RV32IF-NEXT: call nearbyintf
1180 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1181 ; RV32IF-NEXT: addi sp, sp, 16
1182 ; RV32IF-NEXT: ret
1183 ;
1184 ; RV64IF-LABEL: nearbyint_f32:
1185 ; RV64IF: # %bb.0:
1186 ; RV64IF-NEXT: addi sp, sp, -16
1187 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1188 ; RV64IF-NEXT: call nearbyintf
1189 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1190 ; RV64IF-NEXT: addi sp, sp, 16
1191 ; RV64IF-NEXT: ret
1192 ;
1193 ; RV32IZFINX-LABEL: nearbyint_f32:
1194 ; RV32IZFINX: # %bb.0:
1195 ; RV32IZFINX-NEXT: addi sp, sp, -16
1196 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1197 ; RV32IZFINX-NEXT: call nearbyintf
1198 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1199 ; RV32IZFINX-NEXT: addi sp, sp, 16
1200 ; RV32IZFINX-NEXT: ret
1201 ;
1202 ; RV64IZFINX-LABEL: nearbyint_f32:
1203 ; RV64IZFINX: # %bb.0:
1204 ; RV64IZFINX-NEXT: addi sp, sp, -16
1205 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1206 ; RV64IZFINX-NEXT: call nearbyintf
1207 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1208 ; RV64IZFINX-NEXT: addi sp, sp, 16
1209 ; RV64IZFINX-NEXT: ret
1210 ;
1211 ; RV32I-LABEL: nearbyint_f32:
1212 ; RV32I: # %bb.0:
1213 ; RV32I-NEXT: addi sp, sp, -16
1214 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1215 ; RV32I-NEXT: call nearbyintf
1216 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1217 ; RV32I-NEXT: addi sp, sp, 16
1218 ; RV32I-NEXT: ret
1219 ;
1220 ; RV64I-LABEL: nearbyint_f32:
1221 ; RV64I: # %bb.0:
1222 ; RV64I-NEXT: addi sp, sp, -16
1223 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1224 ; RV64I-NEXT: call nearbyintf
1225 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1226 ; RV64I-NEXT: addi sp, sp, 16
1227 ; RV64I-NEXT: ret
1228 %1 = call float @llvm.experimental.constrained.nearbyint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1229 ret float %1
1230 }
1232 declare float @llvm.experimental.constrained.round.f32(float, metadata)
1234 define float @round_f32(float %a) nounwind strictfp {
1235 ; RV32IF-LABEL: round_f32:
1236 ; RV32IF: # %bb.0:
1237 ; RV32IF-NEXT: addi sp, sp, -16
1238 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1239 ; RV32IF-NEXT: call roundf
1240 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1241 ; RV32IF-NEXT: addi sp, sp, 16
1242 ; RV32IF-NEXT: ret
1243 ;
1244 ; RV64IF-LABEL: round_f32:
1245 ; RV64IF: # %bb.0:
1246 ; RV64IF-NEXT: addi sp, sp, -16
1247 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1248 ; RV64IF-NEXT: call roundf
1249 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1250 ; RV64IF-NEXT: addi sp, sp, 16
1251 ; RV64IF-NEXT: ret
1252 ;
1253 ; RV32IZFINX-LABEL: round_f32:
1254 ; RV32IZFINX: # %bb.0:
1255 ; RV32IZFINX-NEXT: addi sp, sp, -16
1256 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1257 ; RV32IZFINX-NEXT: call roundf
1258 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1259 ; RV32IZFINX-NEXT: addi sp, sp, 16
1260 ; RV32IZFINX-NEXT: ret
1261 ;
1262 ; RV64IZFINX-LABEL: round_f32:
1263 ; RV64IZFINX: # %bb.0:
1264 ; RV64IZFINX-NEXT: addi sp, sp, -16
1265 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1266 ; RV64IZFINX-NEXT: call roundf
1267 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1268 ; RV64IZFINX-NEXT: addi sp, sp, 16
1269 ; RV64IZFINX-NEXT: ret
1270 ;
1271 ; RV32I-LABEL: round_f32:
1272 ; RV32I: # %bb.0:
1273 ; RV32I-NEXT: addi sp, sp, -16
1274 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1275 ; RV32I-NEXT: call roundf
1276 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1277 ; RV32I-NEXT: addi sp, sp, 16
1278 ; RV32I-NEXT: ret
1279 ;
1280 ; RV64I-LABEL: round_f32:
1281 ; RV64I: # %bb.0:
1282 ; RV64I-NEXT: addi sp, sp, -16
1283 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1284 ; RV64I-NEXT: call roundf
1285 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1286 ; RV64I-NEXT: addi sp, sp, 16
1287 ; RV64I-NEXT: ret
1288 %1 = call float @llvm.experimental.constrained.round.f32(float %a, metadata !"fpexcept.strict") strictfp
1289 ret float %1
1290 }
1292 declare float @llvm.experimental.constrained.roundeven.f32(float, metadata)
1294 define float @roundeven_f32(float %a) nounwind strictfp {
1295 ; RV32IF-LABEL: roundeven_f32:
1296 ; RV32IF: # %bb.0:
1297 ; RV32IF-NEXT: addi sp, sp, -16
1298 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1299 ; RV32IF-NEXT: call roundevenf
1300 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1301 ; RV32IF-NEXT: addi sp, sp, 16
1302 ; RV32IF-NEXT: ret
1303 ;
1304 ; RV64IF-LABEL: roundeven_f32:
1305 ; RV64IF: # %bb.0:
1306 ; RV64IF-NEXT: addi sp, sp, -16
1307 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1308 ; RV64IF-NEXT: call roundevenf
1309 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1310 ; RV64IF-NEXT: addi sp, sp, 16
1311 ; RV64IF-NEXT: ret
1312 ;
1313 ; RV32IZFINX-LABEL: roundeven_f32:
1314 ; RV32IZFINX: # %bb.0:
1315 ; RV32IZFINX-NEXT: addi sp, sp, -16
1316 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1317 ; RV32IZFINX-NEXT: call roundevenf
1318 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1319 ; RV32IZFINX-NEXT: addi sp, sp, 16
1320 ; RV32IZFINX-NEXT: ret
1321 ;
1322 ; RV64IZFINX-LABEL: roundeven_f32:
1323 ; RV64IZFINX: # %bb.0:
1324 ; RV64IZFINX-NEXT: addi sp, sp, -16
1325 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1326 ; RV64IZFINX-NEXT: call roundevenf
1327 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1328 ; RV64IZFINX-NEXT: addi sp, sp, 16
1329 ; RV64IZFINX-NEXT: ret
1330 ;
1331 ; RV32I-LABEL: roundeven_f32:
1332 ; RV32I: # %bb.0:
1333 ; RV32I-NEXT: addi sp, sp, -16
1334 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1335 ; RV32I-NEXT: call roundevenf
1336 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1337 ; RV32I-NEXT: addi sp, sp, 16
1338 ; RV32I-NEXT: ret
1339 ;
1340 ; RV64I-LABEL: roundeven_f32:
1341 ; RV64I: # %bb.0:
1342 ; RV64I-NEXT: addi sp, sp, -16
1343 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1344 ; RV64I-NEXT: call roundevenf
1345 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1346 ; RV64I-NEXT: addi sp, sp, 16
1347 ; RV64I-NEXT: ret
1348 %1 = call float @llvm.experimental.constrained.roundeven.f32(float %a, metadata !"fpexcept.strict") strictfp
1349 ret float %1
1350 }
1352 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f32(float, metadata, metadata)
1354 define iXLen @lrint_f32(float %a) nounwind strictfp {
1355 ; RV32IF-LABEL: lrint_f32:
1356 ; RV32IF: # %bb.0:
1357 ; RV32IF-NEXT: fcvt.w.s a0, fa0
1358 ; RV32IF-NEXT: ret
1359 ;
1360 ; RV64IF-LABEL: lrint_f32:
1361 ; RV64IF: # %bb.0:
1362 ; RV64IF-NEXT: fcvt.l.s a0, fa0
1363 ; RV64IF-NEXT: ret
1364 ;
1365 ; RV32IZFINX-LABEL: lrint_f32:
1366 ; RV32IZFINX: # %bb.0:
1367 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0
1368 ; RV32IZFINX-NEXT: ret
1369 ;
1370 ; RV64IZFINX-LABEL: lrint_f32:
1371 ; RV64IZFINX: # %bb.0:
1372 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1373 ; RV64IZFINX-NEXT: ret
1374 ;
1375 ; RV32I-LABEL: lrint_f32:
1376 ; RV32I: # %bb.0:
1377 ; RV32I-NEXT: addi sp, sp, -16
1378 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1379 ; RV32I-NEXT: call lrintf
1380 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1381 ; RV32I-NEXT: addi sp, sp, 16
1382 ; RV32I-NEXT: ret
1383 ;
1384 ; RV64I-LABEL: lrint_f32:
1385 ; RV64I: # %bb.0:
1386 ; RV64I-NEXT: addi sp, sp, -16
1387 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1388 ; RV64I-NEXT: call lrintf
1389 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1390 ; RV64I-NEXT: addi sp, sp, 16
1391 ; RV64I-NEXT: ret
1392 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1393 ret iXLen %1
1394 }
1396 declare iXLen @llvm.experimental.constrained.lround.iXLen.f32(float, metadata)
1398 define iXLen @lround_f32(float %a) nounwind strictfp {
1399 ; RV32IF-LABEL: lround_f32:
1400 ; RV32IF: # %bb.0:
1401 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
1402 ; RV32IF-NEXT: ret
1403 ;
1404 ; RV64IF-LABEL: lround_f32:
1405 ; RV64IF: # %bb.0:
1406 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
1407 ; RV64IF-NEXT: ret
1408 ;
1409 ; RV32IZFINX-LABEL: lround_f32:
1410 ; RV32IZFINX: # %bb.0:
1411 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm
1412 ; RV32IZFINX-NEXT: ret
1413 ;
1414 ; RV64IZFINX-LABEL: lround_f32:
1415 ; RV64IZFINX: # %bb.0:
1416 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1417 ; RV64IZFINX-NEXT: ret
1418 ;
1419 ; RV32I-LABEL: lround_f32:
1420 ; RV32I: # %bb.0:
1421 ; RV32I-NEXT: addi sp, sp, -16
1422 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1423 ; RV32I-NEXT: call lroundf
1424 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1425 ; RV32I-NEXT: addi sp, sp, 16
1426 ; RV32I-NEXT: ret
1427 ;
1428 ; RV64I-LABEL: lround_f32:
1429 ; RV64I: # %bb.0:
1430 ; RV64I-NEXT: addi sp, sp, -16
1431 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1432 ; RV64I-NEXT: call lroundf
1433 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1434 ; RV64I-NEXT: addi sp, sp, 16
1435 ; RV64I-NEXT: ret
1436 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f32(float %a, metadata !"fpexcept.strict") strictfp
1437 ret iXLen %1
1438 }
1440 declare i64 @llvm.experimental.constrained.llrint.i64.f32(float, metadata, metadata)
1442 define i64 @llrint_f32(float %a) nounwind strictfp {
1443 ; RV32IF-LABEL: llrint_f32:
1444 ; RV32IF: # %bb.0:
1445 ; RV32IF-NEXT: addi sp, sp, -16
1446 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1447 ; RV32IF-NEXT: call llrintf
1448 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1449 ; RV32IF-NEXT: addi sp, sp, 16
1450 ; RV32IF-NEXT: ret
1451 ;
1452 ; RV64IF-LABEL: llrint_f32:
1453 ; RV64IF: # %bb.0:
1454 ; RV64IF-NEXT: fcvt.l.s a0, fa0
1455 ; RV64IF-NEXT: ret
1456 ;
1457 ; RV32IZFINX-LABEL: llrint_f32:
1458 ; RV32IZFINX: # %bb.0:
1459 ; RV32IZFINX-NEXT: addi sp, sp, -16
1460 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1461 ; RV32IZFINX-NEXT: call llrintf
1462 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1463 ; RV32IZFINX-NEXT: addi sp, sp, 16
1464 ; RV32IZFINX-NEXT: ret
1465 ;
1466 ; RV64IZFINX-LABEL: llrint_f32:
1467 ; RV64IZFINX: # %bb.0:
1468 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1469 ; RV64IZFINX-NEXT: ret
1470 ;
1471 ; RV32I-LABEL: llrint_f32:
1472 ; RV32I: # %bb.0:
1473 ; RV32I-NEXT: addi sp, sp, -16
1474 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1475 ; RV32I-NEXT: call llrintf
1476 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1477 ; RV32I-NEXT: addi sp, sp, 16
1478 ; RV32I-NEXT: ret
1479 ;
1480 ; RV64I-LABEL: llrint_f32:
1481 ; RV64I: # %bb.0:
1482 ; RV64I-NEXT: addi sp, sp, -16
1483 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1484 ; RV64I-NEXT: call llrintf
1485 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1486 ; RV64I-NEXT: addi sp, sp, 16
1487 ; RV64I-NEXT: ret
1488 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
1489 ret i64 %1
1490 }
1492 declare i64 @llvm.experimental.constrained.llround.i64.f32(float, metadata)
1494 define i64 @llround_f32(float %a) nounwind strictfp {
1495 ; RV32IF-LABEL: llround_f32:
1496 ; RV32IF: # %bb.0:
1497 ; RV32IF-NEXT: addi sp, sp, -16
1498 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1499 ; RV32IF-NEXT: call llroundf
1500 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1501 ; RV32IF-NEXT: addi sp, sp, 16
1502 ; RV32IF-NEXT: ret
1503 ;
1504 ; RV64IF-LABEL: llround_f32:
1505 ; RV64IF: # %bb.0:
1506 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
1507 ; RV64IF-NEXT: ret
1508 ;
1509 ; RV32IZFINX-LABEL: llround_f32:
1510 ; RV32IZFINX: # %bb.0:
1511 ; RV32IZFINX-NEXT: addi sp, sp, -16
1512 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1513 ; RV32IZFINX-NEXT: call llroundf
1514 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1515 ; RV32IZFINX-NEXT: addi sp, sp, 16
1516 ; RV32IZFINX-NEXT: ret
1517 ;
1518 ; RV64IZFINX-LABEL: llround_f32:
1519 ; RV64IZFINX: # %bb.0:
1520 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1521 ; RV64IZFINX-NEXT: ret
1522 ;
1523 ; RV32I-LABEL: llround_f32:
1524 ; RV32I: # %bb.0:
1525 ; RV32I-NEXT: addi sp, sp, -16
1526 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1527 ; RV32I-NEXT: call llroundf
1528 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1529 ; RV32I-NEXT: addi sp, sp, 16
1530 ; RV32I-NEXT: ret
1531 ;
1532 ; RV64I-LABEL: llround_f32:
1533 ; RV64I: # %bb.0:
1534 ; RV64I-NEXT: addi sp, sp, -16
1535 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1536 ; RV64I-NEXT: call llroundf
1537 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1538 ; RV64I-NEXT: addi sp, sp, 16
1539 ; RV64I-NEXT: ret
1540 %1 = call i64 @llvm.experimental.constrained.llround.i64.f32(float %a, metadata !"fpexcept.strict") strictfp
1541 ret i64 %1
1542 }