| blob | a00d82942cabe889325d442f891a497d78d426ce |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
3 ; RUN: -verify-machineinstrs -target-abi=ilp32f \
4 ; RUN: | FileCheck -check-prefix=RV32IF %s
5 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \
6 ; RUN: -verify-machineinstrs -target-abi=ilp32 \
7 ; RUN: | FileCheck -check-prefix=RV32IZFINX %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
9 ; RUN: -verify-machineinstrs -target-abi=ilp32f \
10 ; RUN: | FileCheck -check-prefix=RV32IF %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
12 ; RUN: -verify-machineinstrs -target-abi=lp64f \
13 ; RUN: | FileCheck -check-prefix=RV64IF %s
14 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \
15 ; RUN: -verify-machineinstrs -target-abi=lp64 \
16 ; RUN: | FileCheck -check-prefix=RV64IZFINX %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
18 ; RUN: -verify-machineinstrs -target-abi=lp64d \
19 ; RUN: | FileCheck -check-prefix=RV64IF %s
20 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
21 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
22 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
23 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
25 declare float @llvm.sqrt.f32(float)
27 define float @sqrt_f32(float %a) nounwind {
28 ; RV32IF-LABEL: sqrt_f32:
29 ; RV32IF: # %bb.0:
30 ; RV32IF-NEXT: fsqrt.s fa0, fa0
31 ; RV32IF-NEXT: ret
32 ;
33 ; RV32IZFINX-LABEL: sqrt_f32:
34 ; RV32IZFINX: # %bb.0:
35 ; RV32IZFINX-NEXT: fsqrt.s a0, a0
36 ; RV32IZFINX-NEXT: ret
37 ;
38 ; RV64IF-LABEL: sqrt_f32:
39 ; RV64IF: # %bb.0:
40 ; RV64IF-NEXT: fsqrt.s fa0, fa0
41 ; RV64IF-NEXT: ret
42 ;
43 ; RV64IZFINX-LABEL: sqrt_f32:
44 ; RV64IZFINX: # %bb.0:
45 ; RV64IZFINX-NEXT: fsqrt.s a0, a0
46 ; RV64IZFINX-NEXT: ret
47 ;
48 ; RV32I-LABEL: sqrt_f32:
49 ; RV32I: # %bb.0:
50 ; RV32I-NEXT: addi sp, sp, -16
51 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
52 ; RV32I-NEXT: call sqrtf
53 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
54 ; RV32I-NEXT: addi sp, sp, 16
55 ; RV32I-NEXT: ret
56 ;
57 ; RV64I-LABEL: sqrt_f32:
58 ; RV64I: # %bb.0:
59 ; RV64I-NEXT: addi sp, sp, -16
60 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
61 ; RV64I-NEXT: call sqrtf
62 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
63 ; RV64I-NEXT: addi sp, sp, 16
64 ; RV64I-NEXT: ret
65 %1 = call float @llvm.sqrt.f32(float %a)
66 ret float %1
67 }
69 declare float @llvm.powi.f32.i32(float, i32)
71 define float @powi_f32(float %a, i32 %b) nounwind {
72 ; RV32IF-LABEL: powi_f32:
73 ; RV32IF: # %bb.0:
74 ; RV32IF-NEXT: tail __powisf2
75 ;
76 ; RV32IZFINX-LABEL: powi_f32:
77 ; RV32IZFINX: # %bb.0:
78 ; RV32IZFINX-NEXT: tail __powisf2
79 ;
80 ; RV64IF-LABEL: powi_f32:
81 ; RV64IF: # %bb.0:
82 ; RV64IF-NEXT: addi sp, sp, -16
83 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
84 ; RV64IF-NEXT: sext.w a0, a0
85 ; RV64IF-NEXT: call __powisf2
86 ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
87 ; RV64IF-NEXT: addi sp, sp, 16
88 ; RV64IF-NEXT: ret
89 ;
90 ; RV64IZFINX-LABEL: powi_f32:
91 ; RV64IZFINX: # %bb.0:
92 ; RV64IZFINX-NEXT: addi sp, sp, -16
93 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
94 ; RV64IZFINX-NEXT: sext.w a1, a1
95 ; RV64IZFINX-NEXT: call __powisf2
96 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
97 ; RV64IZFINX-NEXT: addi sp, sp, 16
98 ; RV64IZFINX-NEXT: ret
99 ;
100 ; RV32I-LABEL: powi_f32:
101 ; RV32I: # %bb.0:
102 ; RV32I-NEXT: addi sp, sp, -16
103 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
104 ; RV32I-NEXT: call __powisf2
105 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
106 ; RV32I-NEXT: addi sp, sp, 16
107 ; RV32I-NEXT: ret
108 ;
109 ; RV64I-LABEL: powi_f32:
110 ; RV64I: # %bb.0:
111 ; RV64I-NEXT: addi sp, sp, -16
112 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
113 ; RV64I-NEXT: sext.w a1, a1
114 ; RV64I-NEXT: call __powisf2
115 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
116 ; RV64I-NEXT: addi sp, sp, 16
117 ; RV64I-NEXT: ret
118 %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
119 ret float %1
120 }
122 declare float @llvm.sin.f32(float)
124 define float @sin_f32(float %a) nounwind {
125 ; RV32IF-LABEL: sin_f32:
126 ; RV32IF: # %bb.0:
127 ; RV32IF-NEXT: tail sinf
128 ;
129 ; RV32IZFINX-LABEL: sin_f32:
130 ; RV32IZFINX: # %bb.0:
131 ; RV32IZFINX-NEXT: tail sinf
132 ;
133 ; RV64IF-LABEL: sin_f32:
134 ; RV64IF: # %bb.0:
135 ; RV64IF-NEXT: tail sinf
136 ;
137 ; RV64IZFINX-LABEL: sin_f32:
138 ; RV64IZFINX: # %bb.0:
139 ; RV64IZFINX-NEXT: addi sp, sp, -16
140 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
141 ; RV64IZFINX-NEXT: call sinf
142 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
143 ; RV64IZFINX-NEXT: addi sp, sp, 16
144 ; RV64IZFINX-NEXT: ret
145 ;
146 ; RV32I-LABEL: sin_f32:
147 ; RV32I: # %bb.0:
148 ; RV32I-NEXT: addi sp, sp, -16
149 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
150 ; RV32I-NEXT: call sinf
151 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
152 ; RV32I-NEXT: addi sp, sp, 16
153 ; RV32I-NEXT: ret
154 ;
155 ; RV64I-LABEL: sin_f32:
156 ; RV64I: # %bb.0:
157 ; RV64I-NEXT: addi sp, sp, -16
158 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
159 ; RV64I-NEXT: call sinf
160 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
161 ; RV64I-NEXT: addi sp, sp, 16
162 ; RV64I-NEXT: ret
163 %1 = call float @llvm.sin.f32(float %a)
164 ret float %1
165 }
167 declare float @llvm.cos.f32(float)
169 define float @cos_f32(float %a) nounwind {
170 ; RV32IF-LABEL: cos_f32:
171 ; RV32IF: # %bb.0:
172 ; RV32IF-NEXT: tail cosf
173 ;
174 ; RV32IZFINX-LABEL: cos_f32:
175 ; RV32IZFINX: # %bb.0:
176 ; RV32IZFINX-NEXT: tail cosf
177 ;
178 ; RV64IF-LABEL: cos_f32:
179 ; RV64IF: # %bb.0:
180 ; RV64IF-NEXT: tail cosf
181 ;
182 ; RV64IZFINX-LABEL: cos_f32:
183 ; RV64IZFINX: # %bb.0:
184 ; RV64IZFINX-NEXT: addi sp, sp, -16
185 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
186 ; RV64IZFINX-NEXT: call cosf
187 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
188 ; RV64IZFINX-NEXT: addi sp, sp, 16
189 ; RV64IZFINX-NEXT: ret
190 ;
191 ; RV32I-LABEL: cos_f32:
192 ; RV32I: # %bb.0:
193 ; RV32I-NEXT: addi sp, sp, -16
194 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
195 ; RV32I-NEXT: call cosf
196 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
197 ; RV32I-NEXT: addi sp, sp, 16
198 ; RV32I-NEXT: ret
199 ;
200 ; RV64I-LABEL: cos_f32:
201 ; RV64I: # %bb.0:
202 ; RV64I-NEXT: addi sp, sp, -16
203 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
204 ; RV64I-NEXT: call cosf
205 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
206 ; RV64I-NEXT: addi sp, sp, 16
207 ; RV64I-NEXT: ret
208 %1 = call float @llvm.cos.f32(float %a)
209 ret float %1
210 }
212 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
213 define float @sincos_f32(float %a) nounwind {
214 ; RV32IF-LABEL: sincos_f32:
215 ; RV32IF: # %bb.0:
216 ; RV32IF-NEXT: addi sp, sp, -16
217 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
218 ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
219 ; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
220 ; RV32IF-NEXT: fmv.s fs0, fa0
221 ; RV32IF-NEXT: call sinf
222 ; RV32IF-NEXT: fmv.s fs1, fa0
223 ; RV32IF-NEXT: fmv.s fa0, fs0
224 ; RV32IF-NEXT: call cosf
225 ; RV32IF-NEXT: fadd.s fa0, fs1, fa0
226 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
227 ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
228 ; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
229 ; RV32IF-NEXT: addi sp, sp, 16
230 ; RV32IF-NEXT: ret
231 ;
232 ; RV32IZFINX-LABEL: sincos_f32:
233 ; RV32IZFINX: # %bb.0:
234 ; RV32IZFINX-NEXT: addi sp, sp, -16
235 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
236 ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
237 ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
238 ; RV32IZFINX-NEXT: mv s0, a0
239 ; RV32IZFINX-NEXT: call sinf
240 ; RV32IZFINX-NEXT: mv s1, a0
241 ; RV32IZFINX-NEXT: mv a0, s0
242 ; RV32IZFINX-NEXT: call cosf
243 ; RV32IZFINX-NEXT: fadd.s a0, s1, a0
244 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
245 ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
246 ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
247 ; RV32IZFINX-NEXT: addi sp, sp, 16
248 ; RV32IZFINX-NEXT: ret
249 ;
250 ; RV64IZFINX-LABEL: sincos_f32:
251 ; RV64IZFINX: # %bb.0:
252 ; RV64IZFINX-NEXT: addi sp, sp, -32
253 ; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
254 ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
255 ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
256 ; RV64IZFINX-NEXT: mv s0, a0
257 ; RV64IZFINX-NEXT: call sinf
258 ; RV64IZFINX-NEXT: mv s1, a0
259 ; RV64IZFINX-NEXT: mv a0, s0
260 ; RV64IZFINX-NEXT: call cosf
261 ; RV64IZFINX-NEXT: fadd.s a0, s1, a0
262 ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
263 ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
264 ; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
265 ; RV64IZFINX-NEXT: addi sp, sp, 32
266 ; RV64IZFINX-NEXT: ret
267 ;
268 ; RV32I-LABEL: sincos_f32:
269 ; RV32I: # %bb.0:
270 ; RV32I-NEXT: addi sp, sp, -16
271 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
272 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
273 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
274 ; RV32I-NEXT: mv s0, a0
275 ; RV32I-NEXT: call sinf
276 ; RV32I-NEXT: mv s1, a0
277 ; RV32I-NEXT: mv a0, s0
278 ; RV32I-NEXT: call cosf
279 ; RV32I-NEXT: mv a1, a0
280 ; RV32I-NEXT: mv a0, s1
281 ; RV32I-NEXT: call __addsf3
282 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
283 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
284 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
285 ; RV32I-NEXT: addi sp, sp, 16
286 ; RV32I-NEXT: ret
287 ;
288 ; RV64I-LABEL: sincos_f32:
289 ; RV64I: # %bb.0:
290 ; RV64I-NEXT: addi sp, sp, -32
291 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
292 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
293 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
294 ; RV64I-NEXT: mv s0, a0
295 ; RV64I-NEXT: call sinf
296 ; RV64I-NEXT: mv s1, a0
297 ; RV64I-NEXT: mv a0, s0
298 ; RV64I-NEXT: call cosf
299 ; RV64I-NEXT: mv a1, a0
300 ; RV64I-NEXT: mv a0, s1
301 ; RV64I-NEXT: call __addsf3
302 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
303 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
304 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
305 ; RV64I-NEXT: addi sp, sp, 32
306 ; RV64I-NEXT: ret
307 %1 = call float @llvm.sin.f32(float %a)
308 %2 = call float @llvm.cos.f32(float %a)
309 %3 = fadd float %1, %2
310 ret float %3
311 }
313 declare float @llvm.pow.f32(float, float)
315 define float @pow_f32(float %a, float %b) nounwind {
316 ; RV32IF-LABEL: pow_f32:
317 ; RV32IF: # %bb.0:
318 ; RV32IF-NEXT: tail powf
319 ;
320 ; RV32IZFINX-LABEL: pow_f32:
321 ; RV32IZFINX: # %bb.0:
322 ; RV32IZFINX-NEXT: tail powf
323 ;
324 ; RV64IF-LABEL: pow_f32:
325 ; RV64IF: # %bb.0:
326 ; RV64IF-NEXT: tail powf
327 ;
328 ; RV64IZFINX-LABEL: pow_f32:
329 ; RV64IZFINX: # %bb.0:
330 ; RV64IZFINX-NEXT: addi sp, sp, -16
331 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
332 ; RV64IZFINX-NEXT: call powf
333 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
334 ; RV64IZFINX-NEXT: addi sp, sp, 16
335 ; RV64IZFINX-NEXT: ret
336 ;
337 ; RV32I-LABEL: pow_f32:
338 ; RV32I: # %bb.0:
339 ; RV32I-NEXT: addi sp, sp, -16
340 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
341 ; RV32I-NEXT: call powf
342 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
343 ; RV32I-NEXT: addi sp, sp, 16
344 ; RV32I-NEXT: ret
345 ;
346 ; RV64I-LABEL: pow_f32:
347 ; RV64I: # %bb.0:
348 ; RV64I-NEXT: addi sp, sp, -16
349 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
350 ; RV64I-NEXT: call powf
351 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
352 ; RV64I-NEXT: addi sp, sp, 16
353 ; RV64I-NEXT: ret
354 %1 = call float @llvm.pow.f32(float %a, float %b)
355 ret float %1
356 }
358 declare float @llvm.exp.f32(float)
360 define float @exp_f32(float %a) nounwind {
361 ; RV32IF-LABEL: exp_f32:
362 ; RV32IF: # %bb.0:
363 ; RV32IF-NEXT: tail expf
364 ;
365 ; RV32IZFINX-LABEL: exp_f32:
366 ; RV32IZFINX: # %bb.0:
367 ; RV32IZFINX-NEXT: tail expf
368 ;
369 ; RV64IF-LABEL: exp_f32:
370 ; RV64IF: # %bb.0:
371 ; RV64IF-NEXT: tail expf
372 ;
373 ; RV64IZFINX-LABEL: exp_f32:
374 ; RV64IZFINX: # %bb.0:
375 ; RV64IZFINX-NEXT: addi sp, sp, -16
376 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
377 ; RV64IZFINX-NEXT: call expf
378 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
379 ; RV64IZFINX-NEXT: addi sp, sp, 16
380 ; RV64IZFINX-NEXT: ret
381 ;
382 ; RV32I-LABEL: exp_f32:
383 ; RV32I: # %bb.0:
384 ; RV32I-NEXT: addi sp, sp, -16
385 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
386 ; RV32I-NEXT: call expf
387 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
388 ; RV32I-NEXT: addi sp, sp, 16
389 ; RV32I-NEXT: ret
390 ;
391 ; RV64I-LABEL: exp_f32:
392 ; RV64I: # %bb.0:
393 ; RV64I-NEXT: addi sp, sp, -16
394 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
395 ; RV64I-NEXT: call expf
396 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
397 ; RV64I-NEXT: addi sp, sp, 16
398 ; RV64I-NEXT: ret
399 %1 = call float @llvm.exp.f32(float %a)
400 ret float %1
401 }
403 declare float @llvm.exp2.f32(float)
405 define float @exp2_f32(float %a) nounwind {
406 ; RV32IF-LABEL: exp2_f32:
407 ; RV32IF: # %bb.0:
408 ; RV32IF-NEXT: tail exp2f
409 ;
410 ; RV32IZFINX-LABEL: exp2_f32:
411 ; RV32IZFINX: # %bb.0:
412 ; RV32IZFINX-NEXT: tail exp2f
413 ;
414 ; RV64IF-LABEL: exp2_f32:
415 ; RV64IF: # %bb.0:
416 ; RV64IF-NEXT: tail exp2f
417 ;
418 ; RV64IZFINX-LABEL: exp2_f32:
419 ; RV64IZFINX: # %bb.0:
420 ; RV64IZFINX-NEXT: addi sp, sp, -16
421 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
422 ; RV64IZFINX-NEXT: call exp2f
423 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
424 ; RV64IZFINX-NEXT: addi sp, sp, 16
425 ; RV64IZFINX-NEXT: ret
426 ;
427 ; RV32I-LABEL: exp2_f32:
428 ; RV32I: # %bb.0:
429 ; RV32I-NEXT: addi sp, sp, -16
430 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
431 ; RV32I-NEXT: call exp2f
432 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
433 ; RV32I-NEXT: addi sp, sp, 16
434 ; RV32I-NEXT: ret
435 ;
436 ; RV64I-LABEL: exp2_f32:
437 ; RV64I: # %bb.0:
438 ; RV64I-NEXT: addi sp, sp, -16
439 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
440 ; RV64I-NEXT: call exp2f
441 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
442 ; RV64I-NEXT: addi sp, sp, 16
443 ; RV64I-NEXT: ret
444 %1 = call float @llvm.exp2.f32(float %a)
445 ret float %1
446 }
448 declare float @llvm.log.f32(float)
450 define float @log_f32(float %a) nounwind {
451 ; RV32IF-LABEL: log_f32:
452 ; RV32IF: # %bb.0:
453 ; RV32IF-NEXT: tail logf
454 ;
455 ; RV32IZFINX-LABEL: log_f32:
456 ; RV32IZFINX: # %bb.0:
457 ; RV32IZFINX-NEXT: tail logf
458 ;
459 ; RV64IF-LABEL: log_f32:
460 ; RV64IF: # %bb.0:
461 ; RV64IF-NEXT: tail logf
462 ;
463 ; RV64IZFINX-LABEL: log_f32:
464 ; RV64IZFINX: # %bb.0:
465 ; RV64IZFINX-NEXT: addi sp, sp, -16
466 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
467 ; RV64IZFINX-NEXT: call logf
468 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
469 ; RV64IZFINX-NEXT: addi sp, sp, 16
470 ; RV64IZFINX-NEXT: ret
471 ;
472 ; RV32I-LABEL: log_f32:
473 ; RV32I: # %bb.0:
474 ; RV32I-NEXT: addi sp, sp, -16
475 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
476 ; RV32I-NEXT: call logf
477 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
478 ; RV32I-NEXT: addi sp, sp, 16
479 ; RV32I-NEXT: ret
480 ;
481 ; RV64I-LABEL: log_f32:
482 ; RV64I: # %bb.0:
483 ; RV64I-NEXT: addi sp, sp, -16
484 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
485 ; RV64I-NEXT: call logf
486 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
487 ; RV64I-NEXT: addi sp, sp, 16
488 ; RV64I-NEXT: ret
489 %1 = call float @llvm.log.f32(float %a)
490 ret float %1
491 }
493 declare float @llvm.log10.f32(float)
495 define float @log10_f32(float %a) nounwind {
496 ; RV32IF-LABEL: log10_f32:
497 ; RV32IF: # %bb.0:
498 ; RV32IF-NEXT: tail log10f
499 ;
500 ; RV32IZFINX-LABEL: log10_f32:
501 ; RV32IZFINX: # %bb.0:
502 ; RV32IZFINX-NEXT: tail log10f
503 ;
504 ; RV64IF-LABEL: log10_f32:
505 ; RV64IF: # %bb.0:
506 ; RV64IF-NEXT: tail log10f
507 ;
508 ; RV64IZFINX-LABEL: log10_f32:
509 ; RV64IZFINX: # %bb.0:
510 ; RV64IZFINX-NEXT: addi sp, sp, -16
511 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
512 ; RV64IZFINX-NEXT: call log10f
513 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
514 ; RV64IZFINX-NEXT: addi sp, sp, 16
515 ; RV64IZFINX-NEXT: ret
516 ;
517 ; RV32I-LABEL: log10_f32:
518 ; RV32I: # %bb.0:
519 ; RV32I-NEXT: addi sp, sp, -16
520 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
521 ; RV32I-NEXT: call log10f
522 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
523 ; RV32I-NEXT: addi sp, sp, 16
524 ; RV32I-NEXT: ret
525 ;
526 ; RV64I-LABEL: log10_f32:
527 ; RV64I: # %bb.0:
528 ; RV64I-NEXT: addi sp, sp, -16
529 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
530 ; RV64I-NEXT: call log10f
531 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
532 ; RV64I-NEXT: addi sp, sp, 16
533 ; RV64I-NEXT: ret
534 %1 = call float @llvm.log10.f32(float %a)
535 ret float %1
536 }
538 declare float @llvm.log2.f32(float)
540 define float @log2_f32(float %a) nounwind {
541 ; RV32IF-LABEL: log2_f32:
542 ; RV32IF: # %bb.0:
543 ; RV32IF-NEXT: tail log2f
544 ;
545 ; RV32IZFINX-LABEL: log2_f32:
546 ; RV32IZFINX: # %bb.0:
547 ; RV32IZFINX-NEXT: tail log2f
548 ;
549 ; RV64IF-LABEL: log2_f32:
550 ; RV64IF: # %bb.0:
551 ; RV64IF-NEXT: tail log2f
552 ;
553 ; RV64IZFINX-LABEL: log2_f32:
554 ; RV64IZFINX: # %bb.0:
555 ; RV64IZFINX-NEXT: addi sp, sp, -16
556 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
557 ; RV64IZFINX-NEXT: call log2f
558 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
559 ; RV64IZFINX-NEXT: addi sp, sp, 16
560 ; RV64IZFINX-NEXT: ret
561 ;
562 ; RV32I-LABEL: log2_f32:
563 ; RV32I: # %bb.0:
564 ; RV32I-NEXT: addi sp, sp, -16
565 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
566 ; RV32I-NEXT: call log2f
567 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
568 ; RV32I-NEXT: addi sp, sp, 16
569 ; RV32I-NEXT: ret
570 ;
571 ; RV64I-LABEL: log2_f32:
572 ; RV64I: # %bb.0:
573 ; RV64I-NEXT: addi sp, sp, -16
574 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
575 ; RV64I-NEXT: call log2f
576 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
577 ; RV64I-NEXT: addi sp, sp, 16
578 ; RV64I-NEXT: ret
579 %1 = call float @llvm.log2.f32(float %a)
580 ret float %1
581 }
583 declare float @llvm.fma.f32(float, float, float)
585 define float @fma_f32(float %a, float %b, float %c) nounwind {
586 ; RV32IF-LABEL: fma_f32:
587 ; RV32IF: # %bb.0:
588 ; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
589 ; RV32IF-NEXT: ret
590 ;
591 ; RV32IZFINX-LABEL: fma_f32:
592 ; RV32IZFINX: # %bb.0:
593 ; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2
594 ; RV32IZFINX-NEXT: ret
595 ;
596 ; RV64IF-LABEL: fma_f32:
597 ; RV64IF: # %bb.0:
598 ; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
599 ; RV64IF-NEXT: ret
600 ;
601 ; RV64IZFINX-LABEL: fma_f32:
602 ; RV64IZFINX: # %bb.0:
603 ; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2
604 ; RV64IZFINX-NEXT: ret
605 ;
606 ; RV32I-LABEL: fma_f32:
607 ; RV32I: # %bb.0:
608 ; RV32I-NEXT: addi sp, sp, -16
609 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
610 ; RV32I-NEXT: call fmaf
611 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
612 ; RV32I-NEXT: addi sp, sp, 16
613 ; RV32I-NEXT: ret
614 ;
615 ; RV64I-LABEL: fma_f32:
616 ; RV64I: # %bb.0:
617 ; RV64I-NEXT: addi sp, sp, -16
618 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
619 ; RV64I-NEXT: call fmaf
620 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
621 ; RV64I-NEXT: addi sp, sp, 16
622 ; RV64I-NEXT: ret
623 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
624 ret float %1
625 }
627 declare float @llvm.fmuladd.f32(float, float, float)
629 define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
630 ; RV32IF-LABEL: fmuladd_f32:
631 ; RV32IF: # %bb.0:
632 ; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
633 ; RV32IF-NEXT: ret
634 ;
635 ; RV32IZFINX-LABEL: fmuladd_f32:
636 ; RV32IZFINX: # %bb.0:
637 ; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2
638 ; RV32IZFINX-NEXT: ret
639 ;
640 ; RV64IF-LABEL: fmuladd_f32:
641 ; RV64IF: # %bb.0:
642 ; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
643 ; RV64IF-NEXT: ret
644 ;
645 ; RV64IZFINX-LABEL: fmuladd_f32:
646 ; RV64IZFINX: # %bb.0:
647 ; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2
648 ; RV64IZFINX-NEXT: ret
649 ;
650 ; RV32I-LABEL: fmuladd_f32:
651 ; RV32I: # %bb.0:
652 ; RV32I-NEXT: addi sp, sp, -16
653 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
654 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
655 ; RV32I-NEXT: mv s0, a2
656 ; RV32I-NEXT: call __mulsf3
657 ; RV32I-NEXT: mv a1, s0
658 ; RV32I-NEXT: call __addsf3
659 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
660 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
661 ; RV32I-NEXT: addi sp, sp, 16
662 ; RV32I-NEXT: ret
663 ;
664 ; RV64I-LABEL: fmuladd_f32:
665 ; RV64I: # %bb.0:
666 ; RV64I-NEXT: addi sp, sp, -16
667 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
668 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
669 ; RV64I-NEXT: mv s0, a2
670 ; RV64I-NEXT: call __mulsf3
671 ; RV64I-NEXT: mv a1, s0
672 ; RV64I-NEXT: call __addsf3
673 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
674 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
675 ; RV64I-NEXT: addi sp, sp, 16
676 ; RV64I-NEXT: ret
677 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
678 ret float %1
679 }
681 declare float @llvm.fabs.f32(float)
683 define float @fabs_f32(float %a) nounwind {
684 ; RV32IF-LABEL: fabs_f32:
685 ; RV32IF: # %bb.0:
686 ; RV32IF-NEXT: fabs.s fa0, fa0
687 ; RV32IF-NEXT: ret
688 ;
689 ; RV32IZFINX-LABEL: fabs_f32:
690 ; RV32IZFINX: # %bb.0:
691 ; RV32IZFINX-NEXT: slli a0, a0, 1
692 ; RV32IZFINX-NEXT: srli a0, a0, 1
693 ; RV32IZFINX-NEXT: ret
694 ;
695 ; RV64IF-LABEL: fabs_f32:
696 ; RV64IF: # %bb.0:
697 ; RV64IF-NEXT: fabs.s fa0, fa0
698 ; RV64IF-NEXT: ret
699 ;
700 ; RV64IZFINX-LABEL: fabs_f32:
701 ; RV64IZFINX: # %bb.0:
702 ; RV64IZFINX-NEXT: slli a0, a0, 33
703 ; RV64IZFINX-NEXT: srli a0, a0, 33
704 ; RV64IZFINX-NEXT: ret
705 ;
706 ; RV32I-LABEL: fabs_f32:
707 ; RV32I: # %bb.0:
708 ; RV32I-NEXT: slli a0, a0, 1
709 ; RV32I-NEXT: srli a0, a0, 1
710 ; RV32I-NEXT: ret
711 ;
712 ; RV64I-LABEL: fabs_f32:
713 ; RV64I: # %bb.0:
714 ; RV64I-NEXT: slli a0, a0, 33
715 ; RV64I-NEXT: srli a0, a0, 33
716 ; RV64I-NEXT: ret
717 %1 = call float @llvm.fabs.f32(float %a)
718 ret float %1
719 }
721 declare float @llvm.minnum.f32(float, float)
723 define float @minnum_f32(float %a, float %b) nounwind {
724 ; RV32IF-LABEL: minnum_f32:
725 ; RV32IF: # %bb.0:
726 ; RV32IF-NEXT: fmin.s fa0, fa0, fa1
727 ; RV32IF-NEXT: ret
728 ;
729 ; RV32IZFINX-LABEL: minnum_f32:
730 ; RV32IZFINX: # %bb.0:
731 ; RV32IZFINX-NEXT: fmin.s a0, a0, a1
732 ; RV32IZFINX-NEXT: ret
733 ;
734 ; RV64IF-LABEL: minnum_f32:
735 ; RV64IF: # %bb.0:
736 ; RV64IF-NEXT: fmin.s fa0, fa0, fa1
737 ; RV64IF-NEXT: ret
738 ;
739 ; RV64IZFINX-LABEL: minnum_f32:
740 ; RV64IZFINX: # %bb.0:
741 ; RV64IZFINX-NEXT: fmin.s a0, a0, a1
742 ; RV64IZFINX-NEXT: ret
743 ;
744 ; RV32I-LABEL: minnum_f32:
745 ; RV32I: # %bb.0:
746 ; RV32I-NEXT: addi sp, sp, -16
747 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
748 ; RV32I-NEXT: call fminf
749 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
750 ; RV32I-NEXT: addi sp, sp, 16
751 ; RV32I-NEXT: ret
752 ;
753 ; RV64I-LABEL: minnum_f32:
754 ; RV64I: # %bb.0:
755 ; RV64I-NEXT: addi sp, sp, -16
756 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
757 ; RV64I-NEXT: call fminf
758 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
759 ; RV64I-NEXT: addi sp, sp, 16
760 ; RV64I-NEXT: ret
761 %1 = call float @llvm.minnum.f32(float %a, float %b)
762 ret float %1
763 }
765 declare float @llvm.maxnum.f32(float, float)
767 define float @maxnum_f32(float %a, float %b) nounwind {
768 ; RV32IF-LABEL: maxnum_f32:
769 ; RV32IF: # %bb.0:
770 ; RV32IF-NEXT: fmax.s fa0, fa0, fa1
771 ; RV32IF-NEXT: ret
772 ;
773 ; RV32IZFINX-LABEL: maxnum_f32:
774 ; RV32IZFINX: # %bb.0:
775 ; RV32IZFINX-NEXT: fmax.s a0, a0, a1
776 ; RV32IZFINX-NEXT: ret
777 ;
778 ; RV64IF-LABEL: maxnum_f32:
779 ; RV64IF: # %bb.0:
780 ; RV64IF-NEXT: fmax.s fa0, fa0, fa1
781 ; RV64IF-NEXT: ret
782 ;
783 ; RV64IZFINX-LABEL: maxnum_f32:
784 ; RV64IZFINX: # %bb.0:
785 ; RV64IZFINX-NEXT: fmax.s a0, a0, a1
786 ; RV64IZFINX-NEXT: ret
787 ;
788 ; RV32I-LABEL: maxnum_f32:
789 ; RV32I: # %bb.0:
790 ; RV32I-NEXT: addi sp, sp, -16
791 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
792 ; RV32I-NEXT: call fmaxf
793 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
794 ; RV32I-NEXT: addi sp, sp, 16
795 ; RV32I-NEXT: ret
796 ;
797 ; RV64I-LABEL: maxnum_f32:
798 ; RV64I: # %bb.0:
799 ; RV64I-NEXT: addi sp, sp, -16
800 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
801 ; RV64I-NEXT: call fmaxf
802 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
803 ; RV64I-NEXT: addi sp, sp, 16
804 ; RV64I-NEXT: ret
805 %1 = call float @llvm.maxnum.f32(float %a, float %b)
806 ret float %1
807 }
809 ; TODO: FMINNAN and FMAXNAN aren't handled in
810 ; SelectionDAGLegalize::ExpandNode.
812 ; declare float @llvm.minimum.f32(float, float)
814 ; define float @fminimum_f32(float %a, float %b) nounwind {
815 ; %1 = call float @llvm.minimum.f32(float %a, float %b)
816 ; ret float %1
817 ; }
819 ; declare float @llvm.maximum.f32(float, float)
821 ; define float @fmaximum_f32(float %a, float %b) nounwind {
822 ; %1 = call float @llvm.maximum.f32(float %a, float %b)
823 ; ret float %1
824 ; }
826 declare float @llvm.copysign.f32(float, float)
828 define float @copysign_f32(float %a, float %b) nounwind {
829 ; RV32IF-LABEL: copysign_f32:
830 ; RV32IF: # %bb.0:
831 ; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1
832 ; RV32IF-NEXT: ret
833 ;
834 ; RV32IZFINX-LABEL: copysign_f32:
835 ; RV32IZFINX: # %bb.0:
836 ; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1
837 ; RV32IZFINX-NEXT: ret
838 ;
839 ; RV64IF-LABEL: copysign_f32:
840 ; RV64IF: # %bb.0:
841 ; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1
842 ; RV64IF-NEXT: ret
843 ;
844 ; RV64IZFINX-LABEL: copysign_f32:
845 ; RV64IZFINX: # %bb.0:
846 ; RV64IZFINX-NEXT: fsgnj.s a0, a0, a1
847 ; RV64IZFINX-NEXT: ret
848 ;
849 ; RV32I-LABEL: copysign_f32:
850 ; RV32I: # %bb.0:
851 ; RV32I-NEXT: lui a2, 524288
852 ; RV32I-NEXT: and a1, a1, a2
853 ; RV32I-NEXT: slli a0, a0, 1
854 ; RV32I-NEXT: srli a0, a0, 1
855 ; RV32I-NEXT: or a0, a0, a1
856 ; RV32I-NEXT: ret
857 ;
858 ; RV64I-LABEL: copysign_f32:
859 ; RV64I: # %bb.0:
860 ; RV64I-NEXT: lui a2, 524288
861 ; RV64I-NEXT: and a1, a1, a2
862 ; RV64I-NEXT: slli a0, a0, 33
863 ; RV64I-NEXT: srli a0, a0, 33
864 ; RV64I-NEXT: or a0, a0, a1
865 ; RV64I-NEXT: ret
866 %1 = call float @llvm.copysign.f32(float %a, float %b)
867 ret float %1
868 }
870 declare float @llvm.floor.f32(float)
872 define float @floor_f32(float %a) nounwind {
873 ; RV32IF-LABEL: floor_f32:
874 ; RV32IF: # %bb.0:
875 ; RV32IF-NEXT: lui a0, 307200
876 ; RV32IF-NEXT: fmv.w.x fa5, a0
877 ; RV32IF-NEXT: fabs.s fa4, fa0
878 ; RV32IF-NEXT: flt.s a0, fa4, fa5
879 ; RV32IF-NEXT: beqz a0, .LBB17_2
880 ; RV32IF-NEXT: # %bb.1:
881 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
882 ; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn
883 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
884 ; RV32IF-NEXT: .LBB17_2:
885 ; RV32IF-NEXT: ret
886 ;
887 ; RV32IZFINX-LABEL: floor_f32:
888 ; RV32IZFINX: # %bb.0:
889 ; RV32IZFINX-NEXT: lui a1, 307200
890 ; RV32IZFINX-NEXT: fabs.s a2, a0
891 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
892 ; RV32IZFINX-NEXT: beqz a1, .LBB17_2
893 ; RV32IZFINX-NEXT: # %bb.1:
894 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn
895 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn
896 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
897 ; RV32IZFINX-NEXT: .LBB17_2:
898 ; RV32IZFINX-NEXT: ret
899 ;
900 ; RV64IF-LABEL: floor_f32:
901 ; RV64IF: # %bb.0:
902 ; RV64IF-NEXT: lui a0, 307200
903 ; RV64IF-NEXT: fmv.w.x fa5, a0
904 ; RV64IF-NEXT: fabs.s fa4, fa0
905 ; RV64IF-NEXT: flt.s a0, fa4, fa5
906 ; RV64IF-NEXT: beqz a0, .LBB17_2
907 ; RV64IF-NEXT: # %bb.1:
908 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
909 ; RV64IF-NEXT: fcvt.s.w fa5, a0, rdn
910 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
911 ; RV64IF-NEXT: .LBB17_2:
912 ; RV64IF-NEXT: ret
913 ;
914 ; RV64IZFINX-LABEL: floor_f32:
915 ; RV64IZFINX: # %bb.0:
916 ; RV64IZFINX-NEXT: lui a1, 307200
917 ; RV64IZFINX-NEXT: fabs.s a2, a0
918 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
919 ; RV64IZFINX-NEXT: beqz a1, .LBB17_2
920 ; RV64IZFINX-NEXT: # %bb.1:
921 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rdn
922 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rdn
923 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
924 ; RV64IZFINX-NEXT: .LBB17_2:
925 ; RV64IZFINX-NEXT: ret
926 ;
927 ; RV32I-LABEL: floor_f32:
928 ; RV32I: # %bb.0:
929 ; RV32I-NEXT: addi sp, sp, -16
930 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
931 ; RV32I-NEXT: call floorf
932 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
933 ; RV32I-NEXT: addi sp, sp, 16
934 ; RV32I-NEXT: ret
935 ;
936 ; RV64I-LABEL: floor_f32:
937 ; RV64I: # %bb.0:
938 ; RV64I-NEXT: addi sp, sp, -16
939 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
940 ; RV64I-NEXT: call floorf
941 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
942 ; RV64I-NEXT: addi sp, sp, 16
943 ; RV64I-NEXT: ret
944 %1 = call float @llvm.floor.f32(float %a)
945 ret float %1
946 }
948 declare float @llvm.ceil.f32(float)
950 define float @ceil_f32(float %a) nounwind {
951 ; RV32IF-LABEL: ceil_f32:
952 ; RV32IF: # %bb.0:
953 ; RV32IF-NEXT: lui a0, 307200
954 ; RV32IF-NEXT: fmv.w.x fa5, a0
955 ; RV32IF-NEXT: fabs.s fa4, fa0
956 ; RV32IF-NEXT: flt.s a0, fa4, fa5
957 ; RV32IF-NEXT: beqz a0, .LBB18_2
958 ; RV32IF-NEXT: # %bb.1:
959 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
960 ; RV32IF-NEXT: fcvt.s.w fa5, a0, rup
961 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
962 ; RV32IF-NEXT: .LBB18_2:
963 ; RV32IF-NEXT: ret
964 ;
965 ; RV32IZFINX-LABEL: ceil_f32:
966 ; RV32IZFINX: # %bb.0:
967 ; RV32IZFINX-NEXT: lui a1, 307200
968 ; RV32IZFINX-NEXT: fabs.s a2, a0
969 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
970 ; RV32IZFINX-NEXT: beqz a1, .LBB18_2
971 ; RV32IZFINX-NEXT: # %bb.1:
972 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup
973 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup
974 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
975 ; RV32IZFINX-NEXT: .LBB18_2:
976 ; RV32IZFINX-NEXT: ret
977 ;
978 ; RV64IF-LABEL: ceil_f32:
979 ; RV64IF: # %bb.0:
980 ; RV64IF-NEXT: lui a0, 307200
981 ; RV64IF-NEXT: fmv.w.x fa5, a0
982 ; RV64IF-NEXT: fabs.s fa4, fa0
983 ; RV64IF-NEXT: flt.s a0, fa4, fa5
984 ; RV64IF-NEXT: beqz a0, .LBB18_2
985 ; RV64IF-NEXT: # %bb.1:
986 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
987 ; RV64IF-NEXT: fcvt.s.w fa5, a0, rup
988 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
989 ; RV64IF-NEXT: .LBB18_2:
990 ; RV64IF-NEXT: ret
991 ;
992 ; RV64IZFINX-LABEL: ceil_f32:
993 ; RV64IZFINX: # %bb.0:
994 ; RV64IZFINX-NEXT: lui a1, 307200
995 ; RV64IZFINX-NEXT: fabs.s a2, a0
996 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
997 ; RV64IZFINX-NEXT: beqz a1, .LBB18_2
998 ; RV64IZFINX-NEXT: # %bb.1:
999 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rup
1000 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rup
1001 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
1002 ; RV64IZFINX-NEXT: .LBB18_2:
1003 ; RV64IZFINX-NEXT: ret
1004 ;
1005 ; RV32I-LABEL: ceil_f32:
1006 ; RV32I: # %bb.0:
1007 ; RV32I-NEXT: addi sp, sp, -16
1008 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1009 ; RV32I-NEXT: call ceilf
1010 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1011 ; RV32I-NEXT: addi sp, sp, 16
1012 ; RV32I-NEXT: ret
1013 ;
1014 ; RV64I-LABEL: ceil_f32:
1015 ; RV64I: # %bb.0:
1016 ; RV64I-NEXT: addi sp, sp, -16
1017 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1018 ; RV64I-NEXT: call ceilf
1019 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1020 ; RV64I-NEXT: addi sp, sp, 16
1021 ; RV64I-NEXT: ret
1022 %1 = call float @llvm.ceil.f32(float %a)
1023 ret float %1
1024 }
1026 declare float @llvm.trunc.f32(float)
1028 define float @trunc_f32(float %a) nounwind {
1029 ; RV32IF-LABEL: trunc_f32:
1030 ; RV32IF: # %bb.0:
1031 ; RV32IF-NEXT: lui a0, 307200
1032 ; RV32IF-NEXT: fmv.w.x fa5, a0
1033 ; RV32IF-NEXT: fabs.s fa4, fa0
1034 ; RV32IF-NEXT: flt.s a0, fa4, fa5
1035 ; RV32IF-NEXT: beqz a0, .LBB19_2
1036 ; RV32IF-NEXT: # %bb.1:
1037 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
1038 ; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz
1039 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
1040 ; RV32IF-NEXT: .LBB19_2:
1041 ; RV32IF-NEXT: ret
1042 ;
1043 ; RV32IZFINX-LABEL: trunc_f32:
1044 ; RV32IZFINX: # %bb.0:
1045 ; RV32IZFINX-NEXT: lui a1, 307200
1046 ; RV32IZFINX-NEXT: fabs.s a2, a0
1047 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
1048 ; RV32IZFINX-NEXT: beqz a1, .LBB19_2
1049 ; RV32IZFINX-NEXT: # %bb.1:
1050 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz
1051 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz
1052 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
1053 ; RV32IZFINX-NEXT: .LBB19_2:
1054 ; RV32IZFINX-NEXT: ret
1055 ;
1056 ; RV64IF-LABEL: trunc_f32:
1057 ; RV64IF: # %bb.0:
1058 ; RV64IF-NEXT: lui a0, 307200
1059 ; RV64IF-NEXT: fmv.w.x fa5, a0
1060 ; RV64IF-NEXT: fabs.s fa4, fa0
1061 ; RV64IF-NEXT: flt.s a0, fa4, fa5
1062 ; RV64IF-NEXT: beqz a0, .LBB19_2
1063 ; RV64IF-NEXT: # %bb.1:
1064 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
1065 ; RV64IF-NEXT: fcvt.s.w fa5, a0, rtz
1066 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
1067 ; RV64IF-NEXT: .LBB19_2:
1068 ; RV64IF-NEXT: ret
1069 ;
1070 ; RV64IZFINX-LABEL: trunc_f32:
1071 ; RV64IZFINX: # %bb.0:
1072 ; RV64IZFINX-NEXT: lui a1, 307200
1073 ; RV64IZFINX-NEXT: fabs.s a2, a0
1074 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
1075 ; RV64IZFINX-NEXT: beqz a1, .LBB19_2
1076 ; RV64IZFINX-NEXT: # %bb.1:
1077 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rtz
1078 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rtz
1079 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
1080 ; RV64IZFINX-NEXT: .LBB19_2:
1081 ; RV64IZFINX-NEXT: ret
1082 ;
1083 ; RV32I-LABEL: trunc_f32:
1084 ; RV32I: # %bb.0:
1085 ; RV32I-NEXT: addi sp, sp, -16
1086 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1087 ; RV32I-NEXT: call truncf
1088 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1089 ; RV32I-NEXT: addi sp, sp, 16
1090 ; RV32I-NEXT: ret
1091 ;
1092 ; RV64I-LABEL: trunc_f32:
1093 ; RV64I: # %bb.0:
1094 ; RV64I-NEXT: addi sp, sp, -16
1095 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1096 ; RV64I-NEXT: call truncf
1097 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1098 ; RV64I-NEXT: addi sp, sp, 16
1099 ; RV64I-NEXT: ret
1100 %1 = call float @llvm.trunc.f32(float %a)
1101 ret float %1
1102 }
1104 declare float @llvm.rint.f32(float)
1106 define float @rint_f32(float %a) nounwind {
1107 ; RV32IF-LABEL: rint_f32:
1108 ; RV32IF: # %bb.0:
1109 ; RV32IF-NEXT: lui a0, 307200
1110 ; RV32IF-NEXT: fmv.w.x fa5, a0
1111 ; RV32IF-NEXT: fabs.s fa4, fa0
1112 ; RV32IF-NEXT: flt.s a0, fa4, fa5
1113 ; RV32IF-NEXT: beqz a0, .LBB20_2
1114 ; RV32IF-NEXT: # %bb.1:
1115 ; RV32IF-NEXT: fcvt.w.s a0, fa0
1116 ; RV32IF-NEXT: fcvt.s.w fa5, a0
1117 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
1118 ; RV32IF-NEXT: .LBB20_2:
1119 ; RV32IF-NEXT: ret
1120 ;
1121 ; RV32IZFINX-LABEL: rint_f32:
1122 ; RV32IZFINX: # %bb.0:
1123 ; RV32IZFINX-NEXT: lui a1, 307200
1124 ; RV32IZFINX-NEXT: fabs.s a2, a0
1125 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
1126 ; RV32IZFINX-NEXT: beqz a1, .LBB20_2
1127 ; RV32IZFINX-NEXT: # %bb.1:
1128 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0
1129 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1
1130 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
1131 ; RV32IZFINX-NEXT: .LBB20_2:
1132 ; RV32IZFINX-NEXT: ret
1133 ;
1134 ; RV64IF-LABEL: rint_f32:
1135 ; RV64IF: # %bb.0:
1136 ; RV64IF-NEXT: lui a0, 307200
1137 ; RV64IF-NEXT: fmv.w.x fa5, a0
1138 ; RV64IF-NEXT: fabs.s fa4, fa0
1139 ; RV64IF-NEXT: flt.s a0, fa4, fa5
1140 ; RV64IF-NEXT: beqz a0, .LBB20_2
1141 ; RV64IF-NEXT: # %bb.1:
1142 ; RV64IF-NEXT: fcvt.w.s a0, fa0
1143 ; RV64IF-NEXT: fcvt.s.w fa5, a0
1144 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
1145 ; RV64IF-NEXT: .LBB20_2:
1146 ; RV64IF-NEXT: ret
1147 ;
1148 ; RV64IZFINX-LABEL: rint_f32:
1149 ; RV64IZFINX: # %bb.0:
1150 ; RV64IZFINX-NEXT: lui a1, 307200
1151 ; RV64IZFINX-NEXT: fabs.s a2, a0
1152 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
1153 ; RV64IZFINX-NEXT: beqz a1, .LBB20_2
1154 ; RV64IZFINX-NEXT: # %bb.1:
1155 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0
1156 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1
1157 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
1158 ; RV64IZFINX-NEXT: .LBB20_2:
1159 ; RV64IZFINX-NEXT: ret
1160 ;
1161 ; RV32I-LABEL: rint_f32:
1162 ; RV32I: # %bb.0:
1163 ; RV32I-NEXT: addi sp, sp, -16
1164 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1165 ; RV32I-NEXT: call rintf
1166 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1167 ; RV32I-NEXT: addi sp, sp, 16
1168 ; RV32I-NEXT: ret
1169 ;
1170 ; RV64I-LABEL: rint_f32:
1171 ; RV64I: # %bb.0:
1172 ; RV64I-NEXT: addi sp, sp, -16
1173 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1174 ; RV64I-NEXT: call rintf
1175 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1176 ; RV64I-NEXT: addi sp, sp, 16
1177 ; RV64I-NEXT: ret
1178 %1 = call float @llvm.rint.f32(float %a)
1179 ret float %1
1180 }
1182 declare float @llvm.nearbyint.f32(float)
1184 define float @nearbyint_f32(float %a) nounwind {
1185 ; RV32IF-LABEL: nearbyint_f32:
1186 ; RV32IF: # %bb.0:
1187 ; RV32IF-NEXT: tail nearbyintf
1188 ;
1189 ; RV32IZFINX-LABEL: nearbyint_f32:
1190 ; RV32IZFINX: # %bb.0:
1191 ; RV32IZFINX-NEXT: tail nearbyintf
1192 ;
1193 ; RV64IF-LABEL: nearbyint_f32:
1194 ; RV64IF: # %bb.0:
1195 ; RV64IF-NEXT: tail nearbyintf
1196 ;
1197 ; RV64IZFINX-LABEL: nearbyint_f32:
1198 ; RV64IZFINX: # %bb.0:
1199 ; RV64IZFINX-NEXT: addi sp, sp, -16
1200 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1201 ; RV64IZFINX-NEXT: call nearbyintf
1202 ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1203 ; RV64IZFINX-NEXT: addi sp, sp, 16
1204 ; RV64IZFINX-NEXT: ret
1205 ;
1206 ; RV32I-LABEL: nearbyint_f32:
1207 ; RV32I: # %bb.0:
1208 ; RV32I-NEXT: addi sp, sp, -16
1209 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1210 ; RV32I-NEXT: call nearbyintf
1211 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1212 ; RV32I-NEXT: addi sp, sp, 16
1213 ; RV32I-NEXT: ret
1214 ;
1215 ; RV64I-LABEL: nearbyint_f32:
1216 ; RV64I: # %bb.0:
1217 ; RV64I-NEXT: addi sp, sp, -16
1218 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1219 ; RV64I-NEXT: call nearbyintf
1220 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1221 ; RV64I-NEXT: addi sp, sp, 16
1222 ; RV64I-NEXT: ret
1223 %1 = call float @llvm.nearbyint.f32(float %a)
1224 ret float %1
1225 }
1227 declare float @llvm.round.f32(float)
1229 define float @round_f32(float %a) nounwind {
1230 ; RV32IF-LABEL: round_f32:
1231 ; RV32IF: # %bb.0:
1232 ; RV32IF-NEXT: lui a0, 307200
1233 ; RV32IF-NEXT: fmv.w.x fa5, a0
1234 ; RV32IF-NEXT: fabs.s fa4, fa0
1235 ; RV32IF-NEXT: flt.s a0, fa4, fa5
1236 ; RV32IF-NEXT: beqz a0, .LBB22_2
1237 ; RV32IF-NEXT: # %bb.1:
1238 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
1239 ; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm
1240 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
1241 ; RV32IF-NEXT: .LBB22_2:
1242 ; RV32IF-NEXT: ret
1243 ;
1244 ; RV32IZFINX-LABEL: round_f32:
1245 ; RV32IZFINX: # %bb.0:
1246 ; RV32IZFINX-NEXT: lui a1, 307200
1247 ; RV32IZFINX-NEXT: fabs.s a2, a0
1248 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
1249 ; RV32IZFINX-NEXT: beqz a1, .LBB22_2
1250 ; RV32IZFINX-NEXT: # %bb.1:
1251 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm
1252 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm
1253 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
1254 ; RV32IZFINX-NEXT: .LBB22_2:
1255 ; RV32IZFINX-NEXT: ret
1256 ;
1257 ; RV64IF-LABEL: round_f32:
1258 ; RV64IF: # %bb.0:
1259 ; RV64IF-NEXT: lui a0, 307200
1260 ; RV64IF-NEXT: fmv.w.x fa5, a0
1261 ; RV64IF-NEXT: fabs.s fa4, fa0
1262 ; RV64IF-NEXT: flt.s a0, fa4, fa5
1263 ; RV64IF-NEXT: beqz a0, .LBB22_2
1264 ; RV64IF-NEXT: # %bb.1:
1265 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
1266 ; RV64IF-NEXT: fcvt.s.w fa5, a0, rmm
1267 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
1268 ; RV64IF-NEXT: .LBB22_2:
1269 ; RV64IF-NEXT: ret
1270 ;
1271 ; RV64IZFINX-LABEL: round_f32:
1272 ; RV64IZFINX: # %bb.0:
1273 ; RV64IZFINX-NEXT: lui a1, 307200
1274 ; RV64IZFINX-NEXT: fabs.s a2, a0
1275 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
1276 ; RV64IZFINX-NEXT: beqz a1, .LBB22_2
1277 ; RV64IZFINX-NEXT: # %bb.1:
1278 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rmm
1279 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rmm
1280 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
1281 ; RV64IZFINX-NEXT: .LBB22_2:
1282 ; RV64IZFINX-NEXT: ret
1283 ;
1284 ; RV32I-LABEL: round_f32:
1285 ; RV32I: # %bb.0:
1286 ; RV32I-NEXT: addi sp, sp, -16
1287 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1288 ; RV32I-NEXT: call roundf
1289 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1290 ; RV32I-NEXT: addi sp, sp, 16
1291 ; RV32I-NEXT: ret
1292 ;
1293 ; RV64I-LABEL: round_f32:
1294 ; RV64I: # %bb.0:
1295 ; RV64I-NEXT: addi sp, sp, -16
1296 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1297 ; RV64I-NEXT: call roundf
1298 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1299 ; RV64I-NEXT: addi sp, sp, 16
1300 ; RV64I-NEXT: ret
1301 %1 = call float @llvm.round.f32(float %a)
1302 ret float %1
1303 }
1305 declare float @llvm.roundeven.f32(float)
1307 define float @roundeven_f32(float %a) nounwind {
1308 ; RV32IF-LABEL: roundeven_f32:
1309 ; RV32IF: # %bb.0:
1310 ; RV32IF-NEXT: lui a0, 307200
1311 ; RV32IF-NEXT: fmv.w.x fa5, a0
1312 ; RV32IF-NEXT: fabs.s fa4, fa0
1313 ; RV32IF-NEXT: flt.s a0, fa4, fa5
1314 ; RV32IF-NEXT: beqz a0, .LBB23_2
1315 ; RV32IF-NEXT: # %bb.1:
1316 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
1317 ; RV32IF-NEXT: fcvt.s.w fa5, a0, rne
1318 ; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0
1319 ; RV32IF-NEXT: .LBB23_2:
1320 ; RV32IF-NEXT: ret
1321 ;
1322 ; RV32IZFINX-LABEL: roundeven_f32:
1323 ; RV32IZFINX: # %bb.0:
1324 ; RV32IZFINX-NEXT: lui a1, 307200
1325 ; RV32IZFINX-NEXT: fabs.s a2, a0
1326 ; RV32IZFINX-NEXT: flt.s a1, a2, a1
1327 ; RV32IZFINX-NEXT: beqz a1, .LBB23_2
1328 ; RV32IZFINX-NEXT: # %bb.1:
1329 ; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne
1330 ; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne
1331 ; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0
1332 ; RV32IZFINX-NEXT: .LBB23_2:
1333 ; RV32IZFINX-NEXT: ret
1334 ;
1335 ; RV64IF-LABEL: roundeven_f32:
1336 ; RV64IF: # %bb.0:
1337 ; RV64IF-NEXT: lui a0, 307200
1338 ; RV64IF-NEXT: fmv.w.x fa5, a0
1339 ; RV64IF-NEXT: fabs.s fa4, fa0
1340 ; RV64IF-NEXT: flt.s a0, fa4, fa5
1341 ; RV64IF-NEXT: beqz a0, .LBB23_2
1342 ; RV64IF-NEXT: # %bb.1:
1343 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
1344 ; RV64IF-NEXT: fcvt.s.w fa5, a0, rne
1345 ; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0
1346 ; RV64IF-NEXT: .LBB23_2:
1347 ; RV64IF-NEXT: ret
1348 ;
1349 ; RV64IZFINX-LABEL: roundeven_f32:
1350 ; RV64IZFINX: # %bb.0:
1351 ; RV64IZFINX-NEXT: lui a1, 307200
1352 ; RV64IZFINX-NEXT: fabs.s a2, a0
1353 ; RV64IZFINX-NEXT: flt.s a1, a2, a1
1354 ; RV64IZFINX-NEXT: beqz a1, .LBB23_2
1355 ; RV64IZFINX-NEXT: # %bb.1:
1356 ; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rne
1357 ; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rne
1358 ; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0
1359 ; RV64IZFINX-NEXT: .LBB23_2:
1360 ; RV64IZFINX-NEXT: ret
1361 ;
1362 ; RV32I-LABEL: roundeven_f32:
1363 ; RV32I: # %bb.0:
1364 ; RV32I-NEXT: addi sp, sp, -16
1365 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1366 ; RV32I-NEXT: call roundevenf
1367 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1368 ; RV32I-NEXT: addi sp, sp, 16
1369 ; RV32I-NEXT: ret
1370 ;
1371 ; RV64I-LABEL: roundeven_f32:
1372 ; RV64I: # %bb.0:
1373 ; RV64I-NEXT: addi sp, sp, -16
1374 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1375 ; RV64I-NEXT: call roundevenf
1376 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1377 ; RV64I-NEXT: addi sp, sp, 16
1378 ; RV64I-NEXT: ret
1379 %1 = call float @llvm.roundeven.f32(float %a)
1380 ret float %1
1381 }
1383 declare iXLen @llvm.lrint.iXLen.f32(float)
1385 define iXLen @lrint_f32(float %a) nounwind {
1386 ; RV32IF-LABEL: lrint_f32:
1387 ; RV32IF: # %bb.0:
1388 ; RV32IF-NEXT: fcvt.w.s a0, fa0
1389 ; RV32IF-NEXT: ret
1390 ;
1391 ; RV32IZFINX-LABEL: lrint_f32:
1392 ; RV32IZFINX: # %bb.0:
1393 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0
1394 ; RV32IZFINX-NEXT: ret
1395 ;
1396 ; RV64IF-LABEL: lrint_f32:
1397 ; RV64IF: # %bb.0:
1398 ; RV64IF-NEXT: fcvt.l.s a0, fa0
1399 ; RV64IF-NEXT: ret
1400 ;
1401 ; RV64IZFINX-LABEL: lrint_f32:
1402 ; RV64IZFINX: # %bb.0:
1403 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1404 ; RV64IZFINX-NEXT: ret
1405 ;
1406 ; RV32I-LABEL: lrint_f32:
1407 ; RV32I: # %bb.0:
1408 ; RV32I-NEXT: addi sp, sp, -16
1409 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1410 ; RV32I-NEXT: call lrintf
1411 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1412 ; RV32I-NEXT: addi sp, sp, 16
1413 ; RV32I-NEXT: ret
1414 ;
1415 ; RV64I-LABEL: lrint_f32:
1416 ; RV64I: # %bb.0:
1417 ; RV64I-NEXT: addi sp, sp, -16
1418 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1419 ; RV64I-NEXT: call lrintf
1420 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1421 ; RV64I-NEXT: addi sp, sp, 16
1422 ; RV64I-NEXT: ret
1423 %1 = call iXLen @llvm.lrint.iXLen.f32(float %a)
1424 ret iXLen %1
1425 }
1427 declare i32 @llvm.lround.i32.f32(float)
1428 declare i64 @llvm.lround.i64.f32(float)
1430 define iXLen @lround_f32(float %a) nounwind {
1431 ; RV32IF-LABEL: lround_f32:
1432 ; RV32IF: # %bb.0:
1433 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
1434 ; RV32IF-NEXT: ret
1435 ;
1436 ; RV32IZFINX-LABEL: lround_f32:
1437 ; RV32IZFINX: # %bb.0:
1438 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm
1439 ; RV32IZFINX-NEXT: ret
1440 ;
1441 ; RV64IF-LABEL: lround_f32:
1442 ; RV64IF: # %bb.0:
1443 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
1444 ; RV64IF-NEXT: ret
1445 ;
1446 ; RV64IZFINX-LABEL: lround_f32:
1447 ; RV64IZFINX: # %bb.0:
1448 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1449 ; RV64IZFINX-NEXT: ret
1450 ;
1451 ; RV32I-LABEL: lround_f32:
1452 ; RV32I: # %bb.0:
1453 ; RV32I-NEXT: addi sp, sp, -16
1454 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1455 ; RV32I-NEXT: call lroundf
1456 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1457 ; RV32I-NEXT: addi sp, sp, 16
1458 ; RV32I-NEXT: ret
1459 ;
1460 ; RV64I-LABEL: lround_f32:
1461 ; RV64I: # %bb.0:
1462 ; RV64I-NEXT: addi sp, sp, -16
1463 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1464 ; RV64I-NEXT: call lroundf
1465 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1466 ; RV64I-NEXT: addi sp, sp, 16
1467 ; RV64I-NEXT: ret
1468 %1 = call iXLen @llvm.lround.iXLen.f32(float %a)
1469 ret iXLen %1
1470 }
1472 ; We support i32 lround on RV64 even though long isn't 32 bits. This is needed
1473 ; by flang.
1474 define i32 @lround_i32_f32(float %a) nounwind {
1475 ; RV32IF-LABEL: lround_i32_f32:
1476 ; RV32IF: # %bb.0:
1477 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
1478 ; RV32IF-NEXT: ret
1479 ;
1480 ; RV32IZFINX-LABEL: lround_i32_f32:
1481 ; RV32IZFINX: # %bb.0:
1482 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm
1483 ; RV32IZFINX-NEXT: ret
1484 ;
1485 ; RV64IF-LABEL: lround_i32_f32:
1486 ; RV64IF: # %bb.0:
1487 ; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
1488 ; RV64IF-NEXT: ret
1489 ;
1490 ; RV64IZFINX-LABEL: lround_i32_f32:
1491 ; RV64IZFINX: # %bb.0:
1492 ; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rmm
1493 ; RV64IZFINX-NEXT: ret
1494 ;
1495 ; RV32I-LABEL: lround_i32_f32:
1496 ; RV32I: # %bb.0:
1497 ; RV32I-NEXT: addi sp, sp, -16
1498 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1499 ; RV32I-NEXT: call lroundf
1500 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1501 ; RV32I-NEXT: addi sp, sp, 16
1502 ; RV32I-NEXT: ret
1503 ;
1504 ; RV64I-LABEL: lround_i32_f32:
1505 ; RV64I: # %bb.0:
1506 ; RV64I-NEXT: addi sp, sp, -16
1507 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1508 ; RV64I-NEXT: call lroundf
1509 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1510 ; RV64I-NEXT: addi sp, sp, 16
1511 ; RV64I-NEXT: ret
1512 %1 = call i32 @llvm.lround.i32.f32(float %a)
1513 ret i32 %1
1514 }
1516 declare i64 @llvm.llrint.i64.f32(float)
1518 define i64 @llrint_f32(float %a) nounwind {
1519 ; RV32IF-LABEL: llrint_f32:
1520 ; RV32IF: # %bb.0:
1521 ; RV32IF-NEXT: addi sp, sp, -16
1522 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1523 ; RV32IF-NEXT: call llrintf
1524 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1525 ; RV32IF-NEXT: addi sp, sp, 16
1526 ; RV32IF-NEXT: ret
1527 ;
1528 ; RV32IZFINX-LABEL: llrint_f32:
1529 ; RV32IZFINX: # %bb.0:
1530 ; RV32IZFINX-NEXT: addi sp, sp, -16
1531 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1532 ; RV32IZFINX-NEXT: call llrintf
1533 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1534 ; RV32IZFINX-NEXT: addi sp, sp, 16
1535 ; RV32IZFINX-NEXT: ret
1536 ;
1537 ; RV64IF-LABEL: llrint_f32:
1538 ; RV64IF: # %bb.0:
1539 ; RV64IF-NEXT: fcvt.l.s a0, fa0
1540 ; RV64IF-NEXT: ret
1541 ;
1542 ; RV64IZFINX-LABEL: llrint_f32:
1543 ; RV64IZFINX: # %bb.0:
1544 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1545 ; RV64IZFINX-NEXT: ret
1546 ;
1547 ; RV32I-LABEL: llrint_f32:
1548 ; RV32I: # %bb.0:
1549 ; RV32I-NEXT: addi sp, sp, -16
1550 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1551 ; RV32I-NEXT: call llrintf
1552 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1553 ; RV32I-NEXT: addi sp, sp, 16
1554 ; RV32I-NEXT: ret
1555 ;
1556 ; RV64I-LABEL: llrint_f32:
1557 ; RV64I: # %bb.0:
1558 ; RV64I-NEXT: addi sp, sp, -16
1559 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1560 ; RV64I-NEXT: call llrintf
1561 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1562 ; RV64I-NEXT: addi sp, sp, 16
1563 ; RV64I-NEXT: ret
1564 %1 = call i64 @llvm.llrint.i64.f32(float %a)
1565 ret i64 %1
1566 }
1568 declare i64 @llvm.llround.i64.f32(float)
1570 define i64 @llround_f32(float %a) nounwind {
1571 ; RV32IF-LABEL: llround_f32:
1572 ; RV32IF: # %bb.0:
1573 ; RV32IF-NEXT: addi sp, sp, -16
1574 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1575 ; RV32IF-NEXT: call llroundf
1576 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1577 ; RV32IF-NEXT: addi sp, sp, 16
1578 ; RV32IF-NEXT: ret
1579 ;
1580 ; RV32IZFINX-LABEL: llround_f32:
1581 ; RV32IZFINX: # %bb.0:
1582 ; RV32IZFINX-NEXT: addi sp, sp, -16
1583 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1584 ; RV32IZFINX-NEXT: call llroundf
1585 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1586 ; RV32IZFINX-NEXT: addi sp, sp, 16
1587 ; RV32IZFINX-NEXT: ret
1588 ;
1589 ; RV64IF-LABEL: llround_f32:
1590 ; RV64IF: # %bb.0:
1591 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
1592 ; RV64IF-NEXT: ret
1593 ;
1594 ; RV64IZFINX-LABEL: llround_f32:
1595 ; RV64IZFINX: # %bb.0:
1596 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0
1597 ; RV64IZFINX-NEXT: ret
1598 ;
1599 ; RV32I-LABEL: llround_f32:
1600 ; RV32I: # %bb.0:
1601 ; RV32I-NEXT: addi sp, sp, -16
1602 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1603 ; RV32I-NEXT: call llroundf
1604 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1605 ; RV32I-NEXT: addi sp, sp, 16
1606 ; RV32I-NEXT: ret
1607 ;
1608 ; RV64I-LABEL: llround_f32:
1609 ; RV64I: # %bb.0:
1610 ; RV64I-NEXT: addi sp, sp, -16
1611 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1612 ; RV64I-NEXT: call llroundf
1613 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1614 ; RV64I-NEXT: addi sp, sp, 16
1615 ; RV64I-NEXT: ret
1616 %1 = call i64 @llvm.llround.i64.f32(float %a)
1617 ret i64 %1
1618 }
1620 declare i1 @llvm.is.fpclass.f32(float, i32)
1621 define i1 @fpclass(float %x) {
1622 ; RV32IF-LABEL: fpclass:
1623 ; RV32IF: # %bb.0:
1624 ; RV32IF-NEXT: fclass.s a0, fa0
1625 ; RV32IF-NEXT: andi a0, a0, 927
1626 ; RV32IF-NEXT: snez a0, a0
1627 ; RV32IF-NEXT: ret
1628 ;
1629 ; RV32IZFINX-LABEL: fpclass:
1630 ; RV32IZFINX: # %bb.0:
1631 ; RV32IZFINX-NEXT: fclass.s a0, a0
1632 ; RV32IZFINX-NEXT: andi a0, a0, 927
1633 ; RV32IZFINX-NEXT: snez a0, a0
1634 ; RV32IZFINX-NEXT: ret
1635 ;
1636 ; RV64IF-LABEL: fpclass:
1637 ; RV64IF: # %bb.0:
1638 ; RV64IF-NEXT: fclass.s a0, fa0
1639 ; RV64IF-NEXT: andi a0, a0, 927
1640 ; RV64IF-NEXT: snez a0, a0
1641 ; RV64IF-NEXT: ret
1642 ;
1643 ; RV64IZFINX-LABEL: fpclass:
1644 ; RV64IZFINX: # %bb.0:
1645 ; RV64IZFINX-NEXT: fclass.s a0, a0
1646 ; RV64IZFINX-NEXT: andi a0, a0, 927
1647 ; RV64IZFINX-NEXT: snez a0, a0
1648 ; RV64IZFINX-NEXT: ret
1649 ;
1650 ; RV32I-LABEL: fpclass:
1651 ; RV32I: # %bb.0:
1652 ; RV32I-NEXT: slli a1, a0, 1
1653 ; RV32I-NEXT: srli a1, a1, 1
1654 ; RV32I-NEXT: addi a2, a1, -1
1655 ; RV32I-NEXT: lui a3, 2048
1656 ; RV32I-NEXT: addi a3, a3, -1
1657 ; RV32I-NEXT: sltu a2, a2, a3
1658 ; RV32I-NEXT: slti a0, a0, 0
1659 ; RV32I-NEXT: and a2, a2, a0
1660 ; RV32I-NEXT: seqz a3, a1
1661 ; RV32I-NEXT: lui a4, 522240
1662 ; RV32I-NEXT: xor a5, a1, a4
1663 ; RV32I-NEXT: seqz a5, a5
1664 ; RV32I-NEXT: or a3, a3, a5
1665 ; RV32I-NEXT: or a2, a3, a2
1666 ; RV32I-NEXT: slt a3, a4, a1
1667 ; RV32I-NEXT: or a2, a2, a3
1668 ; RV32I-NEXT: lui a3, 1046528
1669 ; RV32I-NEXT: add a1, a1, a3
1670 ; RV32I-NEXT: srli a1, a1, 24
1671 ; RV32I-NEXT: sltiu a1, a1, 127
1672 ; RV32I-NEXT: and a0, a1, a0
1673 ; RV32I-NEXT: or a0, a2, a0
1674 ; RV32I-NEXT: ret
1675 ;
1676 ; RV64I-LABEL: fpclass:
1677 ; RV64I: # %bb.0:
1678 ; RV64I-NEXT: sext.w a1, a0
1679 ; RV64I-NEXT: slli a0, a0, 33
1680 ; RV64I-NEXT: srli a0, a0, 33
1681 ; RV64I-NEXT: addi a2, a0, -1
1682 ; RV64I-NEXT: lui a3, 2048
1683 ; RV64I-NEXT: addiw a3, a3, -1
1684 ; RV64I-NEXT: sltu a2, a2, a3
1685 ; RV64I-NEXT: slti a1, a1, 0
1686 ; RV64I-NEXT: and a2, a2, a1
1687 ; RV64I-NEXT: seqz a3, a0
1688 ; RV64I-NEXT: lui a4, 522240
1689 ; RV64I-NEXT: xor a5, a0, a4
1690 ; RV64I-NEXT: seqz a5, a5
1691 ; RV64I-NEXT: or a3, a3, a5
1692 ; RV64I-NEXT: or a2, a3, a2
1693 ; RV64I-NEXT: slt a3, a4, a0
1694 ; RV64I-NEXT: or a2, a2, a3
1695 ; RV64I-NEXT: lui a3, 1046528
1696 ; RV64I-NEXT: add a0, a0, a3
1697 ; RV64I-NEXT: srliw a0, a0, 24
1698 ; RV64I-NEXT: sltiu a0, a0, 127
1699 ; RV64I-NEXT: and a0, a0, a1
1700 ; RV64I-NEXT: or a0, a2, a0
1701 ; RV64I-NEXT: ret
1702 %cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)
1703 ret i1 %cmp
1704 }
1706 define i1 @isnan_fpclass(float %x) {
1707 ; RV32IF-LABEL: isnan_fpclass:
1708 ; RV32IF: # %bb.0:
1709 ; RV32IF-NEXT: fclass.s a0, fa0
1710 ; RV32IF-NEXT: andi a0, a0, 768
1711 ; RV32IF-NEXT: snez a0, a0
1712 ; RV32IF-NEXT: ret
1713 ;
1714 ; RV32IZFINX-LABEL: isnan_fpclass:
1715 ; RV32IZFINX: # %bb.0:
1716 ; RV32IZFINX-NEXT: fclass.s a0, a0
1717 ; RV32IZFINX-NEXT: andi a0, a0, 768
1718 ; RV32IZFINX-NEXT: snez a0, a0
1719 ; RV32IZFINX-NEXT: ret
1720 ;
1721 ; RV64IF-LABEL: isnan_fpclass:
1722 ; RV64IF: # %bb.0:
1723 ; RV64IF-NEXT: fclass.s a0, fa0
1724 ; RV64IF-NEXT: andi a0, a0, 768
1725 ; RV64IF-NEXT: snez a0, a0
1726 ; RV64IF-NEXT: ret
1727 ;
1728 ; RV64IZFINX-LABEL: isnan_fpclass:
1729 ; RV64IZFINX: # %bb.0:
1730 ; RV64IZFINX-NEXT: fclass.s a0, a0
1731 ; RV64IZFINX-NEXT: andi a0, a0, 768
1732 ; RV64IZFINX-NEXT: snez a0, a0
1733 ; RV64IZFINX-NEXT: ret
1734 ;
1735 ; RV32I-LABEL: isnan_fpclass:
1736 ; RV32I: # %bb.0:
1737 ; RV32I-NEXT: slli a0, a0, 1
1738 ; RV32I-NEXT: srli a0, a0, 1
1739 ; RV32I-NEXT: lui a1, 522240
1740 ; RV32I-NEXT: slt a0, a1, a0
1741 ; RV32I-NEXT: ret
1742 ;
1743 ; RV64I-LABEL: isnan_fpclass:
1744 ; RV64I: # %bb.0:
1745 ; RV64I-NEXT: slli a0, a0, 33
1746 ; RV64I-NEXT: srli a0, a0, 33
1747 ; RV64I-NEXT: lui a1, 522240
1748 ; RV64I-NEXT: slt a0, a1, a0
1749 ; RV64I-NEXT: ret
1750 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
1751 ret i1 %1
1752 }
1754 define i1 @isqnan_fpclass(float %x) {
1755 ; RV32IF-LABEL: isqnan_fpclass:
1756 ; RV32IF: # %bb.0:
1757 ; RV32IF-NEXT: fclass.s a0, fa0
1758 ; RV32IF-NEXT: srli a0, a0, 9
1759 ; RV32IF-NEXT: ret
1760 ;
1761 ; RV32IZFINX-LABEL: isqnan_fpclass:
1762 ; RV32IZFINX: # %bb.0:
1763 ; RV32IZFINX-NEXT: fclass.s a0, a0
1764 ; RV32IZFINX-NEXT: srli a0, a0, 9
1765 ; RV32IZFINX-NEXT: ret
1766 ;
1767 ; RV64IF-LABEL: isqnan_fpclass:
1768 ; RV64IF: # %bb.0:
1769 ; RV64IF-NEXT: fclass.s a0, fa0
1770 ; RV64IF-NEXT: srli a0, a0, 9
1771 ; RV64IF-NEXT: ret
1772 ;
1773 ; RV64IZFINX-LABEL: isqnan_fpclass:
1774 ; RV64IZFINX: # %bb.0:
1775 ; RV64IZFINX-NEXT: fclass.s a0, a0
1776 ; RV64IZFINX-NEXT: srli a0, a0, 9
1777 ; RV64IZFINX-NEXT: ret
1778 ;
1779 ; RV32I-LABEL: isqnan_fpclass:
1780 ; RV32I: # %bb.0:
1781 ; RV32I-NEXT: slli a0, a0, 1
1782 ; RV32I-NEXT: srli a0, a0, 1
1783 ; RV32I-NEXT: lui a1, 523264
1784 ; RV32I-NEXT: addi a1, a1, -1
1785 ; RV32I-NEXT: slt a0, a1, a0
1786 ; RV32I-NEXT: ret
1787 ;
1788 ; RV64I-LABEL: isqnan_fpclass:
1789 ; RV64I: # %bb.0:
1790 ; RV64I-NEXT: slli a0, a0, 33
1791 ; RV64I-NEXT: srli a0, a0, 33
1792 ; RV64I-NEXT: lui a1, 523264
1793 ; RV64I-NEXT: addiw a1, a1, -1
1794 ; RV64I-NEXT: slt a0, a1, a0
1795 ; RV64I-NEXT: ret
1796 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; qnan
1797 ret i1 %1
1798 }
1800 define i1 @issnan_fpclass(float %x) {
1801 ; RV32IF-LABEL: issnan_fpclass:
1802 ; RV32IF: # %bb.0:
1803 ; RV32IF-NEXT: fclass.s a0, fa0
1804 ; RV32IF-NEXT: slli a0, a0, 23
1805 ; RV32IF-NEXT: srli a0, a0, 31
1806 ; RV32IF-NEXT: ret
1807 ;
1808 ; RV32IZFINX-LABEL: issnan_fpclass:
1809 ; RV32IZFINX: # %bb.0:
1810 ; RV32IZFINX-NEXT: fclass.s a0, a0
1811 ; RV32IZFINX-NEXT: slli a0, a0, 23
1812 ; RV32IZFINX-NEXT: srli a0, a0, 31
1813 ; RV32IZFINX-NEXT: ret
1814 ;
1815 ; RV64IF-LABEL: issnan_fpclass:
1816 ; RV64IF: # %bb.0:
1817 ; RV64IF-NEXT: fclass.s a0, fa0
1818 ; RV64IF-NEXT: slli a0, a0, 55
1819 ; RV64IF-NEXT: srli a0, a0, 63
1820 ; RV64IF-NEXT: ret
1821 ;
1822 ; RV64IZFINX-LABEL: issnan_fpclass:
1823 ; RV64IZFINX: # %bb.0:
1824 ; RV64IZFINX-NEXT: fclass.s a0, a0
1825 ; RV64IZFINX-NEXT: slli a0, a0, 55
1826 ; RV64IZFINX-NEXT: srli a0, a0, 63
1827 ; RV64IZFINX-NEXT: ret
1828 ;
1829 ; RV32I-LABEL: issnan_fpclass:
1830 ; RV32I: # %bb.0:
1831 ; RV32I-NEXT: slli a0, a0, 1
1832 ; RV32I-NEXT: srli a0, a0, 1
1833 ; RV32I-NEXT: lui a1, 523264
1834 ; RV32I-NEXT: slt a1, a0, a1
1835 ; RV32I-NEXT: lui a2, 522240
1836 ; RV32I-NEXT: slt a0, a2, a0
1837 ; RV32I-NEXT: and a0, a0, a1
1838 ; RV32I-NEXT: ret
1839 ;
1840 ; RV64I-LABEL: issnan_fpclass:
1841 ; RV64I: # %bb.0:
1842 ; RV64I-NEXT: slli a0, a0, 33
1843 ; RV64I-NEXT: srli a0, a0, 33
1844 ; RV64I-NEXT: lui a1, 523264
1845 ; RV64I-NEXT: slt a1, a0, a1
1846 ; RV64I-NEXT: lui a2, 522240
1847 ; RV64I-NEXT: slt a0, a2, a0
1848 ; RV64I-NEXT: and a0, a0, a1
1849 ; RV64I-NEXT: ret
1850 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; snan
1851 ret i1 %1
1852 }
1854 define i1 @isinf_fpclass(float %x) {
1855 ; RV32IF-LABEL: isinf_fpclass:
1856 ; RV32IF: # %bb.0:
1857 ; RV32IF-NEXT: fclass.s a0, fa0
1858 ; RV32IF-NEXT: andi a0, a0, 129
1859 ; RV32IF-NEXT: snez a0, a0
1860 ; RV32IF-NEXT: ret
1861 ;
1862 ; RV32IZFINX-LABEL: isinf_fpclass:
1863 ; RV32IZFINX: # %bb.0:
1864 ; RV32IZFINX-NEXT: fclass.s a0, a0
1865 ; RV32IZFINX-NEXT: andi a0, a0, 129
1866 ; RV32IZFINX-NEXT: snez a0, a0
1867 ; RV32IZFINX-NEXT: ret
1868 ;
1869 ; RV64IF-LABEL: isinf_fpclass:
1870 ; RV64IF: # %bb.0:
1871 ; RV64IF-NEXT: fclass.s a0, fa0
1872 ; RV64IF-NEXT: andi a0, a0, 129
1873 ; RV64IF-NEXT: snez a0, a0
1874 ; RV64IF-NEXT: ret
1875 ;
1876 ; RV64IZFINX-LABEL: isinf_fpclass:
1877 ; RV64IZFINX: # %bb.0:
1878 ; RV64IZFINX-NEXT: fclass.s a0, a0
1879 ; RV64IZFINX-NEXT: andi a0, a0, 129
1880 ; RV64IZFINX-NEXT: snez a0, a0
1881 ; RV64IZFINX-NEXT: ret
1882 ;
1883 ; RV32I-LABEL: isinf_fpclass:
1884 ; RV32I: # %bb.0:
1885 ; RV32I-NEXT: slli a0, a0, 1
1886 ; RV32I-NEXT: srli a0, a0, 1
1887 ; RV32I-NEXT: lui a1, 522240
1888 ; RV32I-NEXT: xor a0, a0, a1
1889 ; RV32I-NEXT: seqz a0, a0
1890 ; RV32I-NEXT: ret
1891 ;
1892 ; RV64I-LABEL: isinf_fpclass:
1893 ; RV64I: # %bb.0:
1894 ; RV64I-NEXT: slli a0, a0, 33
1895 ; RV64I-NEXT: srli a0, a0, 33
1896 ; RV64I-NEXT: lui a1, 522240
1897 ; RV64I-NEXT: xor a0, a0, a1
1898 ; RV64I-NEXT: seqz a0, a0
1899 ; RV64I-NEXT: ret
1900 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
1901 ret i1 %1
1902 }
1904 define i1 @isposinf_fpclass(float %x) {
1905 ; RV32IF-LABEL: isposinf_fpclass:
1906 ; RV32IF: # %bb.0:
1907 ; RV32IF-NEXT: fclass.s a0, fa0
1908 ; RV32IF-NEXT: slli a0, a0, 24
1909 ; RV32IF-NEXT: srli a0, a0, 31
1910 ; RV32IF-NEXT: ret
1911 ;
1912 ; RV32IZFINX-LABEL: isposinf_fpclass:
1913 ; RV32IZFINX: # %bb.0:
1914 ; RV32IZFINX-NEXT: fclass.s a0, a0
1915 ; RV32IZFINX-NEXT: slli a0, a0, 24
1916 ; RV32IZFINX-NEXT: srli a0, a0, 31
1917 ; RV32IZFINX-NEXT: ret
1918 ;
1919 ; RV64IF-LABEL: isposinf_fpclass:
1920 ; RV64IF: # %bb.0:
1921 ; RV64IF-NEXT: fclass.s a0, fa0
1922 ; RV64IF-NEXT: slli a0, a0, 56
1923 ; RV64IF-NEXT: srli a0, a0, 63
1924 ; RV64IF-NEXT: ret
1925 ;
1926 ; RV64IZFINX-LABEL: isposinf_fpclass:
1927 ; RV64IZFINX: # %bb.0:
1928 ; RV64IZFINX-NEXT: fclass.s a0, a0
1929 ; RV64IZFINX-NEXT: slli a0, a0, 56
1930 ; RV64IZFINX-NEXT: srli a0, a0, 63
1931 ; RV64IZFINX-NEXT: ret
1932 ;
1933 ; RV32I-LABEL: isposinf_fpclass:
1934 ; RV32I: # %bb.0:
1935 ; RV32I-NEXT: lui a1, 522240
1936 ; RV32I-NEXT: xor a0, a0, a1
1937 ; RV32I-NEXT: seqz a0, a0
1938 ; RV32I-NEXT: ret
1939 ;
1940 ; RV64I-LABEL: isposinf_fpclass:
1941 ; RV64I: # %bb.0:
1942 ; RV64I-NEXT: sext.w a0, a0
1943 ; RV64I-NEXT: lui a1, 522240
1944 ; RV64I-NEXT: xor a0, a0, a1
1945 ; RV64I-NEXT: seqz a0, a0
1946 ; RV64I-NEXT: ret
1947 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
1948 ret i1 %1
1949 }
1951 define i1 @isneginf_fpclass(float %x) {
1952 ; RV32IF-LABEL: isneginf_fpclass:
1953 ; RV32IF: # %bb.0:
1954 ; RV32IF-NEXT: fclass.s a0, fa0
1955 ; RV32IF-NEXT: andi a0, a0, 1
1956 ; RV32IF-NEXT: ret
1957 ;
1958 ; RV32IZFINX-LABEL: isneginf_fpclass:
1959 ; RV32IZFINX: # %bb.0:
1960 ; RV32IZFINX-NEXT: fclass.s a0, a0
1961 ; RV32IZFINX-NEXT: andi a0, a0, 1
1962 ; RV32IZFINX-NEXT: ret
1963 ;
1964 ; RV64IF-LABEL: isneginf_fpclass:
1965 ; RV64IF: # %bb.0:
1966 ; RV64IF-NEXT: fclass.s a0, fa0
1967 ; RV64IF-NEXT: andi a0, a0, 1
1968 ; RV64IF-NEXT: ret
1969 ;
1970 ; RV64IZFINX-LABEL: isneginf_fpclass:
1971 ; RV64IZFINX: # %bb.0:
1972 ; RV64IZFINX-NEXT: fclass.s a0, a0
1973 ; RV64IZFINX-NEXT: andi a0, a0, 1
1974 ; RV64IZFINX-NEXT: ret
1975 ;
1976 ; RV32I-LABEL: isneginf_fpclass:
1977 ; RV32I: # %bb.0:
1978 ; RV32I-NEXT: lui a1, 1046528
1979 ; RV32I-NEXT: xor a0, a0, a1
1980 ; RV32I-NEXT: seqz a0, a0
1981 ; RV32I-NEXT: ret
1982 ;
1983 ; RV64I-LABEL: isneginf_fpclass:
1984 ; RV64I: # %bb.0:
1985 ; RV64I-NEXT: sext.w a0, a0
1986 ; RV64I-NEXT: lui a1, 1046528
1987 ; RV64I-NEXT: xor a0, a0, a1
1988 ; RV64I-NEXT: seqz a0, a0
1989 ; RV64I-NEXT: ret
1990 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
1991 ret i1 %1
1992 }
1994 define i1 @isfinite_fpclass(float %x) {
1995 ; RV32IF-LABEL: isfinite_fpclass:
1996 ; RV32IF: # %bb.0:
1997 ; RV32IF-NEXT: fclass.s a0, fa0
1998 ; RV32IF-NEXT: andi a0, a0, 126
1999 ; RV32IF-NEXT: snez a0, a0
2000 ; RV32IF-NEXT: ret
2001 ;
2002 ; RV32IZFINX-LABEL: isfinite_fpclass:
2003 ; RV32IZFINX: # %bb.0:
2004 ; RV32IZFINX-NEXT: fclass.s a0, a0
2005 ; RV32IZFINX-NEXT: andi a0, a0, 126
2006 ; RV32IZFINX-NEXT: snez a0, a0
2007 ; RV32IZFINX-NEXT: ret
2008 ;
2009 ; RV64IF-LABEL: isfinite_fpclass:
2010 ; RV64IF: # %bb.0:
2011 ; RV64IF-NEXT: fclass.s a0, fa0
2012 ; RV64IF-NEXT: andi a0, a0, 126
2013 ; RV64IF-NEXT: snez a0, a0
2014 ; RV64IF-NEXT: ret
2015 ;
2016 ; RV64IZFINX-LABEL: isfinite_fpclass:
2017 ; RV64IZFINX: # %bb.0:
2018 ; RV64IZFINX-NEXT: fclass.s a0, a0
2019 ; RV64IZFINX-NEXT: andi a0, a0, 126
2020 ; RV64IZFINX-NEXT: snez a0, a0
2021 ; RV64IZFINX-NEXT: ret
2022 ;
2023 ; RV32I-LABEL: isfinite_fpclass:
2024 ; RV32I: # %bb.0:
2025 ; RV32I-NEXT: slli a0, a0, 1
2026 ; RV32I-NEXT: srli a0, a0, 1
2027 ; RV32I-NEXT: lui a1, 522240
2028 ; RV32I-NEXT: slt a0, a0, a1
2029 ; RV32I-NEXT: ret
2030 ;
2031 ; RV64I-LABEL: isfinite_fpclass:
2032 ; RV64I: # %bb.0:
2033 ; RV64I-NEXT: slli a0, a0, 33
2034 ; RV64I-NEXT: srli a0, a0, 33
2035 ; RV64I-NEXT: lui a1, 522240
2036 ; RV64I-NEXT: slt a0, a0, a1
2037 ; RV64I-NEXT: ret
2038 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
2039 ret i1 %1
2040 }
2042 define i1 @isposfinite_fpclass(float %x) {
2043 ; RV32IF-LABEL: isposfinite_fpclass:
2044 ; RV32IF: # %bb.0:
2045 ; RV32IF-NEXT: fclass.s a0, fa0
2046 ; RV32IF-NEXT: andi a0, a0, 112
2047 ; RV32IF-NEXT: snez a0, a0
2048 ; RV32IF-NEXT: ret
2049 ;
2050 ; RV32IZFINX-LABEL: isposfinite_fpclass:
2051 ; RV32IZFINX: # %bb.0:
2052 ; RV32IZFINX-NEXT: fclass.s a0, a0
2053 ; RV32IZFINX-NEXT: andi a0, a0, 112
2054 ; RV32IZFINX-NEXT: snez a0, a0
2055 ; RV32IZFINX-NEXT: ret
2056 ;
2057 ; RV64IF-LABEL: isposfinite_fpclass:
2058 ; RV64IF: # %bb.0:
2059 ; RV64IF-NEXT: fclass.s a0, fa0
2060 ; RV64IF-NEXT: andi a0, a0, 112
2061 ; RV64IF-NEXT: snez a0, a0
2062 ; RV64IF-NEXT: ret
2063 ;
2064 ; RV64IZFINX-LABEL: isposfinite_fpclass:
2065 ; RV64IZFINX: # %bb.0:
2066 ; RV64IZFINX-NEXT: fclass.s a0, a0
2067 ; RV64IZFINX-NEXT: andi a0, a0, 112
2068 ; RV64IZFINX-NEXT: snez a0, a0
2069 ; RV64IZFINX-NEXT: ret
2070 ;
2071 ; RV32I-LABEL: isposfinite_fpclass:
2072 ; RV32I: # %bb.0:
2073 ; RV32I-NEXT: srli a0, a0, 23
2074 ; RV32I-NEXT: sltiu a0, a0, 255
2075 ; RV32I-NEXT: ret
2076 ;
2077 ; RV64I-LABEL: isposfinite_fpclass:
2078 ; RV64I: # %bb.0:
2079 ; RV64I-NEXT: srliw a0, a0, 23
2080 ; RV64I-NEXT: sltiu a0, a0, 255
2081 ; RV64I-NEXT: ret
2082 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
2083 ret i1 %1
2084 }
2086 define i1 @isnegfinite_fpclass(float %x) {
2087 ; RV32IF-LABEL: isnegfinite_fpclass:
2088 ; RV32IF: # %bb.0:
2089 ; RV32IF-NEXT: fclass.s a0, fa0
2090 ; RV32IF-NEXT: andi a0, a0, 14
2091 ; RV32IF-NEXT: snez a0, a0
2092 ; RV32IF-NEXT: ret
2093 ;
2094 ; RV32IZFINX-LABEL: isnegfinite_fpclass:
2095 ; RV32IZFINX: # %bb.0:
2096 ; RV32IZFINX-NEXT: fclass.s a0, a0
2097 ; RV32IZFINX-NEXT: andi a0, a0, 14
2098 ; RV32IZFINX-NEXT: snez a0, a0
2099 ; RV32IZFINX-NEXT: ret
2100 ;
2101 ; RV64IF-LABEL: isnegfinite_fpclass:
2102 ; RV64IF: # %bb.0:
2103 ; RV64IF-NEXT: fclass.s a0, fa0
2104 ; RV64IF-NEXT: andi a0, a0, 14
2105 ; RV64IF-NEXT: snez a0, a0
2106 ; RV64IF-NEXT: ret
2107 ;
2108 ; RV64IZFINX-LABEL: isnegfinite_fpclass:
2109 ; RV64IZFINX: # %bb.0:
2110 ; RV64IZFINX-NEXT: fclass.s a0, a0
2111 ; RV64IZFINX-NEXT: andi a0, a0, 14
2112 ; RV64IZFINX-NEXT: snez a0, a0
2113 ; RV64IZFINX-NEXT: ret
2114 ;
2115 ; RV32I-LABEL: isnegfinite_fpclass:
2116 ; RV32I: # %bb.0:
2117 ; RV32I-NEXT: slli a1, a0, 1
2118 ; RV32I-NEXT: srli a1, a1, 1
2119 ; RV32I-NEXT: lui a2, 522240
2120 ; RV32I-NEXT: slt a1, a1, a2
2121 ; RV32I-NEXT: slti a0, a0, 0
2122 ; RV32I-NEXT: and a0, a1, a0
2123 ; RV32I-NEXT: ret
2124 ;
2125 ; RV64I-LABEL: isnegfinite_fpclass:
2126 ; RV64I: # %bb.0:
2127 ; RV64I-NEXT: sext.w a1, a0
2128 ; RV64I-NEXT: slli a0, a0, 33
2129 ; RV64I-NEXT: srli a0, a0, 33
2130 ; RV64I-NEXT: lui a2, 522240
2131 ; RV64I-NEXT: slt a0, a0, a2
2132 ; RV64I-NEXT: slti a1, a1, 0
2133 ; RV64I-NEXT: and a0, a0, a1
2134 ; RV64I-NEXT: ret
2135 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"
2136 ret i1 %1
2137 }
2139 define i1 @isnotfinite_fpclass(float %x) {
2140 ; RV32IF-LABEL: isnotfinite_fpclass:
2141 ; RV32IF: # %bb.0:
2142 ; RV32IF-NEXT: fclass.s a0, fa0
2143 ; RV32IF-NEXT: andi a0, a0, 897
2144 ; RV32IF-NEXT: snez a0, a0
2145 ; RV32IF-NEXT: ret
2146 ;
2147 ; RV32IZFINX-LABEL: isnotfinite_fpclass:
2148 ; RV32IZFINX: # %bb.0:
2149 ; RV32IZFINX-NEXT: fclass.s a0, a0
2150 ; RV32IZFINX-NEXT: andi a0, a0, 897
2151 ; RV32IZFINX-NEXT: snez a0, a0
2152 ; RV32IZFINX-NEXT: ret
2153 ;
2154 ; RV64IF-LABEL: isnotfinite_fpclass:
2155 ; RV64IF: # %bb.0:
2156 ; RV64IF-NEXT: fclass.s a0, fa0
2157 ; RV64IF-NEXT: andi a0, a0, 897
2158 ; RV64IF-NEXT: snez a0, a0
2159 ; RV64IF-NEXT: ret
2160 ;
2161 ; RV64IZFINX-LABEL: isnotfinite_fpclass:
2162 ; RV64IZFINX: # %bb.0:
2163 ; RV64IZFINX-NEXT: fclass.s a0, a0
2164 ; RV64IZFINX-NEXT: andi a0, a0, 897
2165 ; RV64IZFINX-NEXT: snez a0, a0
2166 ; RV64IZFINX-NEXT: ret
2167 ;
2168 ; RV32I-LABEL: isnotfinite_fpclass:
2169 ; RV32I: # %bb.0:
2170 ; RV32I-NEXT: slli a0, a0, 1
2171 ; RV32I-NEXT: srli a0, a0, 1
2172 ; RV32I-NEXT: lui a1, 522240
2173 ; RV32I-NEXT: addi a1, a1, -1
2174 ; RV32I-NEXT: slt a0, a1, a0
2175 ; RV32I-NEXT: ret
2176 ;
2177 ; RV64I-LABEL: isnotfinite_fpclass:
2178 ; RV64I: # %bb.0:
2179 ; RV64I-NEXT: slli a0, a0, 33
2180 ; RV64I-NEXT: srli a0, a0, 33
2181 ; RV64I-NEXT: lui a1, 522240
2182 ; RV64I-NEXT: addiw a1, a1, -1
2183 ; RV64I-NEXT: slt a0, a1, a0
2184 ; RV64I-NEXT: ret
2185 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"
2186 ret i1 %1
2187 }