| blob | f03a020762bb3c4742b5807873f2625b0f3394a0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \
4 ; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
5 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
6 ; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \
7 ; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
8 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
9 ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \
10 ; RUN: | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
11 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
12 ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \
13 ; RUN: | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
14 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
15 ; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \
16 ; RUN: | FileCheck -check-prefix=RV32IDZFH %s
17 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
18 ; RUN: -target-abi lp64d -disable-strictnode-mutation < %s \
19 ; RUN: | FileCheck -check-prefix=RV64IDZFH %s
20 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs \
21 ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \
22 ; RUN: | FileCheck -check-prefix=RV32IZDINXZHINX %s
23 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs \
24 ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \
25 ; RUN: | FileCheck -check-prefix=RV64IZDINXZHINX %s
26 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
27 ; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \
28 ; RUN: | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s
29 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
30 ; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \
31 ; RUN: | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s
32 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
33 ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \
34 ; RUN: | FileCheck -check-prefixes=CHECK32-IZHINXMIN %s
35 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
36 ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \
37 ; RUN: | FileCheck -check-prefixes=CHECK64-IZHINXMIN %s
38 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \
39 ; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \
40 ; RUN: | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s
41 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \
42 ; RUN: -target-abi lp64d -disable-strictnode-mutation < %s \
43 ; RUN: | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s
44 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
45 ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \
46 ; RUN: | FileCheck -check-prefixes=CHECK32-IZDINXZHINXMIN %s
47 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
48 ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \
49 ; RUN: | FileCheck -check-prefixes=CHECK64-IZDINXZHINXMIN %s
51 ; NOTE: The rounding mode metadata does not effect which instruction is
52 ; selected. Dynamic rounding mode is always used for operations that
53 ; support rounding mode.
55 define i16 @fcvt_si_h(half %a) nounwind strictfp {
56 ; RV32IZFH-LABEL: fcvt_si_h:
57 ; RV32IZFH: # %bb.0:
58 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
59 ; RV32IZFH-NEXT: ret
60 ;
61 ; RV64IZFH-LABEL: fcvt_si_h:
62 ; RV64IZFH: # %bb.0:
63 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
64 ; RV64IZFH-NEXT: ret
65 ;
66 ; RV32IZHINX-LABEL: fcvt_si_h:
67 ; RV32IZHINX: # %bb.0:
68 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
69 ; RV32IZHINX-NEXT: ret
70 ;
71 ; RV64IZHINX-LABEL: fcvt_si_h:
72 ; RV64IZHINX: # %bb.0:
73 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
74 ; RV64IZHINX-NEXT: ret
75 ;
76 ; RV32IDZFH-LABEL: fcvt_si_h:
77 ; RV32IDZFH: # %bb.0:
78 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
79 ; RV32IDZFH-NEXT: ret
80 ;
81 ; RV64IDZFH-LABEL: fcvt_si_h:
82 ; RV64IDZFH: # %bb.0:
83 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
84 ; RV64IDZFH-NEXT: ret
85 ;
86 ; RV32IZDINXZHINX-LABEL: fcvt_si_h:
87 ; RV32IZDINXZHINX: # %bb.0:
88 ; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
89 ; RV32IZDINXZHINX-NEXT: ret
90 ;
91 ; RV64IZDINXZHINX-LABEL: fcvt_si_h:
92 ; RV64IZDINXZHINX: # %bb.0:
93 ; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
94 ; RV64IZDINXZHINX-NEXT: ret
95 ;
96 ; CHECK32-IZFHMIN-LABEL: fcvt_si_h:
97 ; CHECK32-IZFHMIN: # %bb.0:
98 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
99 ; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
100 ; CHECK32-IZFHMIN-NEXT: ret
101 ;
102 ; CHECK64-IZFHMIN-LABEL: fcvt_si_h:
103 ; CHECK64-IZFHMIN: # %bb.0:
104 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
105 ; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
106 ; CHECK64-IZFHMIN-NEXT: ret
107 ;
108 ; CHECK32-IZHINXMIN-LABEL: fcvt_si_h:
109 ; CHECK32-IZHINXMIN: # %bb.0:
110 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
111 ; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
112 ; CHECK32-IZHINXMIN-NEXT: ret
113 ;
114 ; CHECK64-IZHINXMIN-LABEL: fcvt_si_h:
115 ; CHECK64-IZHINXMIN: # %bb.0:
116 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
117 ; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
118 ; CHECK64-IZHINXMIN-NEXT: ret
119 ;
120 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h:
121 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
122 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
123 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
124 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
125 ;
126 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h:
127 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
128 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
129 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
130 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
131 %1 = call i16 @llvm.experimental.constrained.fptosi.i16.f16(half %a, metadata !"fpexcept.strict")
132 ret i16 %1
133 }
134 declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
136 define i16 @fcvt_ui_h(half %a) nounwind strictfp {
137 ; RV32IZFH-LABEL: fcvt_ui_h:
138 ; RV32IZFH: # %bb.0:
139 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
140 ; RV32IZFH-NEXT: ret
141 ;
142 ; RV64IZFH-LABEL: fcvt_ui_h:
143 ; RV64IZFH: # %bb.0:
144 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
145 ; RV64IZFH-NEXT: ret
146 ;
147 ; RV32IZHINX-LABEL: fcvt_ui_h:
148 ; RV32IZHINX: # %bb.0:
149 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
150 ; RV32IZHINX-NEXT: ret
151 ;
152 ; RV64IZHINX-LABEL: fcvt_ui_h:
153 ; RV64IZHINX: # %bb.0:
154 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
155 ; RV64IZHINX-NEXT: ret
156 ;
157 ; RV32IDZFH-LABEL: fcvt_ui_h:
158 ; RV32IDZFH: # %bb.0:
159 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
160 ; RV32IDZFH-NEXT: ret
161 ;
162 ; RV64IDZFH-LABEL: fcvt_ui_h:
163 ; RV64IDZFH: # %bb.0:
164 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
165 ; RV64IDZFH-NEXT: ret
166 ;
167 ; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
168 ; RV32IZDINXZHINX: # %bb.0:
169 ; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
170 ; RV32IZDINXZHINX-NEXT: ret
171 ;
172 ; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
173 ; RV64IZDINXZHINX: # %bb.0:
174 ; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
175 ; RV64IZDINXZHINX-NEXT: ret
176 ;
177 ; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
178 ; CHECK32-IZFHMIN: # %bb.0:
179 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
180 ; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
181 ; CHECK32-IZFHMIN-NEXT: ret
182 ;
183 ; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
184 ; CHECK64-IZFHMIN: # %bb.0:
185 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
186 ; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
187 ; CHECK64-IZFHMIN-NEXT: ret
188 ;
189 ; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
190 ; CHECK32-IZHINXMIN: # %bb.0:
191 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
192 ; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
193 ; CHECK32-IZHINXMIN-NEXT: ret
194 ;
195 ; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
196 ; CHECK64-IZHINXMIN: # %bb.0:
197 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
198 ; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
199 ; CHECK64-IZHINXMIN-NEXT: ret
200 ;
201 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
202 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
203 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
204 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
205 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
206 ;
207 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
208 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
209 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
210 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
211 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
212 %1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict")
213 ret i16 %1
214 }
215 declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)
217 define i32 @fcvt_w_h(half %a) nounwind strictfp {
218 ; CHECKIZFH-LABEL: fcvt_w_h:
219 ; CHECKIZFH: # %bb.0:
220 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
221 ; CHECKIZFH-NEXT: ret
222 ;
223 ; CHECKIZHINX-LABEL: fcvt_w_h:
224 ; CHECKIZHINX: # %bb.0:
225 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
226 ; CHECKIZHINX-NEXT: ret
227 ;
228 ; RV32IDZFH-LABEL: fcvt_w_h:
229 ; RV32IDZFH: # %bb.0:
230 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
231 ; RV32IDZFH-NEXT: ret
232 ;
233 ; RV64IDZFH-LABEL: fcvt_w_h:
234 ; RV64IDZFH: # %bb.0:
235 ; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
236 ; RV64IDZFH-NEXT: ret
237 ;
238 ; RV32IZDINXZHINX-LABEL: fcvt_w_h:
239 ; RV32IZDINXZHINX: # %bb.0:
240 ; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
241 ; RV32IZDINXZHINX-NEXT: ret
242 ;
243 ; RV64IZDINXZHINX-LABEL: fcvt_w_h:
244 ; RV64IZDINXZHINX: # %bb.0:
245 ; RV64IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
246 ; RV64IZDINXZHINX-NEXT: ret
247 ;
248 ; CHECK32-IZFHMIN-LABEL: fcvt_w_h:
249 ; CHECK32-IZFHMIN: # %bb.0:
250 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
251 ; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
252 ; CHECK32-IZFHMIN-NEXT: ret
253 ;
254 ; CHECK64-IZFHMIN-LABEL: fcvt_w_h:
255 ; CHECK64-IZFHMIN: # %bb.0:
256 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
257 ; CHECK64-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
258 ; CHECK64-IZFHMIN-NEXT: ret
259 ;
260 ; CHECK32-IZHINXMIN-LABEL: fcvt_w_h:
261 ; CHECK32-IZHINXMIN: # %bb.0:
262 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
263 ; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
264 ; CHECK32-IZHINXMIN-NEXT: ret
265 ;
266 ; CHECK64-IZHINXMIN-LABEL: fcvt_w_h:
267 ; CHECK64-IZHINXMIN: # %bb.0:
268 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
269 ; CHECK64-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
270 ; CHECK64-IZHINXMIN-NEXT: ret
271 ;
272 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h:
273 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
274 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
275 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
276 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
277 ;
278 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h:
279 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
280 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
281 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
282 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
283 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")
284 ret i32 %1
285 }
286 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
288 define i32 @fcvt_wu_h(half %a) nounwind strictfp {
289 ; CHECKIZFH-LABEL: fcvt_wu_h:
290 ; CHECKIZFH: # %bb.0:
291 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
292 ; CHECKIZFH-NEXT: ret
293 ;
294 ; CHECKIZHINX-LABEL: fcvt_wu_h:
295 ; CHECKIZHINX: # %bb.0:
296 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
297 ; CHECKIZHINX-NEXT: ret
298 ;
299 ; RV32IDZFH-LABEL: fcvt_wu_h:
300 ; RV32IDZFH: # %bb.0:
301 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
302 ; RV32IDZFH-NEXT: ret
303 ;
304 ; RV64IDZFH-LABEL: fcvt_wu_h:
305 ; RV64IDZFH: # %bb.0:
306 ; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
307 ; RV64IDZFH-NEXT: ret
308 ;
309 ; RV32IZDINXZHINX-LABEL: fcvt_wu_h:
310 ; RV32IZDINXZHINX: # %bb.0:
311 ; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
312 ; RV32IZDINXZHINX-NEXT: ret
313 ;
314 ; RV64IZDINXZHINX-LABEL: fcvt_wu_h:
315 ; RV64IZDINXZHINX: # %bb.0:
316 ; RV64IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
317 ; RV64IZDINXZHINX-NEXT: ret
318 ;
319 ; CHECK32-IZFHMIN-LABEL: fcvt_wu_h:
320 ; CHECK32-IZFHMIN: # %bb.0:
321 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
322 ; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
323 ; CHECK32-IZFHMIN-NEXT: ret
324 ;
325 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h:
326 ; CHECK64-IZFHMIN: # %bb.0:
327 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
328 ; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
329 ; CHECK64-IZFHMIN-NEXT: ret
330 ;
331 ; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h:
332 ; CHECK32-IZHINXMIN: # %bb.0:
333 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
334 ; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
335 ; CHECK32-IZHINXMIN-NEXT: ret
336 ;
337 ; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h:
338 ; CHECK64-IZHINXMIN: # %bb.0:
339 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
340 ; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
341 ; CHECK64-IZHINXMIN-NEXT: ret
342 ;
343 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
344 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
345 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
346 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
347 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
348 ;
349 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
350 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
351 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
352 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
353 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
354 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")
355 ret i32 %1
356 }
357 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
359 ; Test where the fptoui has multiple uses, one of which causes a sext to be
360 ; inserted on RV64.
361 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
362 define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp {
363 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
364 ; CHECKIZFH: # %bb.0:
365 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
366 ; CHECKIZFH-NEXT: seqz a1, a0
367 ; CHECKIZFH-NEXT: add a0, a0, a1
368 ; CHECKIZFH-NEXT: ret
369 ;
370 ; CHECKIZHINX-LABEL: fcvt_wu_h_multiple_use:
371 ; CHECKIZHINX: # %bb.0:
372 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
373 ; CHECKIZHINX-NEXT: seqz a1, a0
374 ; CHECKIZHINX-NEXT: add a0, a0, a1
375 ; CHECKIZHINX-NEXT: ret
376 ;
377 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
378 ; RV32IDZFH: # %bb.0:
379 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
380 ; RV32IDZFH-NEXT: seqz a1, a0
381 ; RV32IDZFH-NEXT: add a0, a0, a1
382 ; RV32IDZFH-NEXT: ret
383 ;
384 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
385 ; RV64IDZFH: # %bb.0:
386 ; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
387 ; RV64IDZFH-NEXT: seqz a1, a0
388 ; RV64IDZFH-NEXT: add a0, a0, a1
389 ; RV64IDZFH-NEXT: ret
390 ;
391 ; RV32IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use:
392 ; RV32IZDINXZHINX: # %bb.0:
393 ; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
394 ; RV32IZDINXZHINX-NEXT: seqz a1, a0
395 ; RV32IZDINXZHINX-NEXT: add a0, a0, a1
396 ; RV32IZDINXZHINX-NEXT: ret
397 ;
398 ; RV64IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use:
399 ; RV64IZDINXZHINX: # %bb.0:
400 ; RV64IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
401 ; RV64IZDINXZHINX-NEXT: seqz a1, a0
402 ; RV64IZDINXZHINX-NEXT: add a0, a0, a1
403 ; RV64IZDINXZHINX-NEXT: ret
404 ;
405 ; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
406 ; CHECK32-IZFHMIN: # %bb.0:
407 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
408 ; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
409 ; CHECK32-IZFHMIN-NEXT: seqz a1, a0
410 ; CHECK32-IZFHMIN-NEXT: add a0, a0, a1
411 ; CHECK32-IZFHMIN-NEXT: ret
412 ;
413 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
414 ; CHECK64-IZFHMIN: # %bb.0:
415 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
416 ; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
417 ; CHECK64-IZFHMIN-NEXT: seqz a1, a0
418 ; CHECK64-IZFHMIN-NEXT: add a0, a0, a1
419 ; CHECK64-IZFHMIN-NEXT: ret
420 ;
421 ; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
422 ; CHECK32-IZHINXMIN: # %bb.0:
423 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
424 ; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
425 ; CHECK32-IZHINXMIN-NEXT: seqz a1, a0
426 ; CHECK32-IZHINXMIN-NEXT: add a0, a0, a1
427 ; CHECK32-IZHINXMIN-NEXT: ret
428 ;
429 ; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
430 ; CHECK64-IZHINXMIN: # %bb.0:
431 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
432 ; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
433 ; CHECK64-IZHINXMIN-NEXT: seqz a1, a0
434 ; CHECK64-IZHINXMIN-NEXT: add a0, a0, a1
435 ; CHECK64-IZHINXMIN-NEXT: ret
436 ;
437 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
438 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
439 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
440 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
441 ; CHECK32-IZDINXZHINXMIN-NEXT: seqz a1, a0
442 ; CHECK32-IZDINXZHINXMIN-NEXT: add a0, a0, a1
443 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
444 ;
445 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
446 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
447 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
448 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
449 ; CHECK64-IZDINXZHINXMIN-NEXT: seqz a1, a0
450 ; CHECK64-IZDINXZHINXMIN-NEXT: add a0, a0, a1
451 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
452 %a = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
453 %b = icmp eq i32 %a, 0
454 %c = select i1 %b, i32 1, i32 %a
455 ret i32 %c
456 }
458 define i64 @fcvt_l_h(half %a) nounwind strictfp {
459 ; RV32IZFH-LABEL: fcvt_l_h:
460 ; RV32IZFH: # %bb.0:
461 ; RV32IZFH-NEXT: addi sp, sp, -16
462 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
463 ; RV32IZFH-NEXT: call __fixhfdi
464 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
465 ; RV32IZFH-NEXT: addi sp, sp, 16
466 ; RV32IZFH-NEXT: ret
467 ;
468 ; RV64IZFH-LABEL: fcvt_l_h:
469 ; RV64IZFH: # %bb.0:
470 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
471 ; RV64IZFH-NEXT: ret
472 ;
473 ; RV32IZHINX-LABEL: fcvt_l_h:
474 ; RV32IZHINX: # %bb.0:
475 ; RV32IZHINX-NEXT: addi sp, sp, -16
476 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
477 ; RV32IZHINX-NEXT: call __fixhfdi
478 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
479 ; RV32IZHINX-NEXT: addi sp, sp, 16
480 ; RV32IZHINX-NEXT: ret
481 ;
482 ; RV64IZHINX-LABEL: fcvt_l_h:
483 ; RV64IZHINX: # %bb.0:
484 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
485 ; RV64IZHINX-NEXT: ret
486 ;
487 ; RV32IDZFH-LABEL: fcvt_l_h:
488 ; RV32IDZFH: # %bb.0:
489 ; RV32IDZFH-NEXT: addi sp, sp, -16
490 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
491 ; RV32IDZFH-NEXT: call __fixhfdi
492 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
493 ; RV32IDZFH-NEXT: addi sp, sp, 16
494 ; RV32IDZFH-NEXT: ret
495 ;
496 ; RV64IDZFH-LABEL: fcvt_l_h:
497 ; RV64IDZFH: # %bb.0:
498 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
499 ; RV64IDZFH-NEXT: ret
500 ;
501 ; RV32IZDINXZHINX-LABEL: fcvt_l_h:
502 ; RV32IZDINXZHINX: # %bb.0:
503 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
504 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
505 ; RV32IZDINXZHINX-NEXT: call __fixhfdi
506 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
507 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
508 ; RV32IZDINXZHINX-NEXT: ret
509 ;
510 ; RV64IZDINXZHINX-LABEL: fcvt_l_h:
511 ; RV64IZDINXZHINX: # %bb.0:
512 ; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
513 ; RV64IZDINXZHINX-NEXT: ret
514 ;
515 ; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
516 ; CHECK32-IZFHMIN: # %bb.0:
517 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
518 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
519 ; CHECK32-IZFHMIN-NEXT: call __fixhfdi
520 ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
521 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
522 ; CHECK32-IZFHMIN-NEXT: ret
523 ;
524 ; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
525 ; CHECK64-IZFHMIN: # %bb.0:
526 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
527 ; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
528 ; CHECK64-IZFHMIN-NEXT: ret
529 ;
530 ; CHECK32-IZHINXMIN-LABEL: fcvt_l_h:
531 ; CHECK32-IZHINXMIN: # %bb.0:
532 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
533 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
534 ; CHECK32-IZHINXMIN-NEXT: call __fixhfdi
535 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
536 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
537 ; CHECK32-IZHINXMIN-NEXT: ret
538 ;
539 ; CHECK64-IZHINXMIN-LABEL: fcvt_l_h:
540 ; CHECK64-IZHINXMIN: # %bb.0:
541 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
542 ; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
543 ; CHECK64-IZHINXMIN-NEXT: ret
544 ;
545 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h:
546 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
547 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
548 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
549 ; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi
550 ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
551 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
552 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
553 ;
554 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h:
555 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
556 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
557 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
558 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
559 %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %a, metadata !"fpexcept.strict")
560 ret i64 %1
561 }
562 declare i64 @llvm.experimental.constrained.fptosi.i64.f16(half, metadata)
564 define i64 @fcvt_lu_h(half %a) nounwind strictfp {
565 ; RV32IZFH-LABEL: fcvt_lu_h:
566 ; RV32IZFH: # %bb.0:
567 ; RV32IZFH-NEXT: addi sp, sp, -16
568 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
569 ; RV32IZFH-NEXT: call __fixunshfdi
570 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
571 ; RV32IZFH-NEXT: addi sp, sp, 16
572 ; RV32IZFH-NEXT: ret
573 ;
574 ; RV64IZFH-LABEL: fcvt_lu_h:
575 ; RV64IZFH: # %bb.0:
576 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
577 ; RV64IZFH-NEXT: ret
578 ;
579 ; RV32IZHINX-LABEL: fcvt_lu_h:
580 ; RV32IZHINX: # %bb.0:
581 ; RV32IZHINX-NEXT: addi sp, sp, -16
582 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
583 ; RV32IZHINX-NEXT: call __fixunshfdi
584 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
585 ; RV32IZHINX-NEXT: addi sp, sp, 16
586 ; RV32IZHINX-NEXT: ret
587 ;
588 ; RV64IZHINX-LABEL: fcvt_lu_h:
589 ; RV64IZHINX: # %bb.0:
590 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
591 ; RV64IZHINX-NEXT: ret
592 ;
593 ; RV32IDZFH-LABEL: fcvt_lu_h:
594 ; RV32IDZFH: # %bb.0:
595 ; RV32IDZFH-NEXT: addi sp, sp, -16
596 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
597 ; RV32IDZFH-NEXT: call __fixunshfdi
598 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
599 ; RV32IDZFH-NEXT: addi sp, sp, 16
600 ; RV32IDZFH-NEXT: ret
601 ;
602 ; RV64IDZFH-LABEL: fcvt_lu_h:
603 ; RV64IDZFH: # %bb.0:
604 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
605 ; RV64IDZFH-NEXT: ret
606 ;
607 ; RV32IZDINXZHINX-LABEL: fcvt_lu_h:
608 ; RV32IZDINXZHINX: # %bb.0:
609 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
610 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
611 ; RV32IZDINXZHINX-NEXT: call __fixunshfdi
612 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
613 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
614 ; RV32IZDINXZHINX-NEXT: ret
615 ;
616 ; RV64IZDINXZHINX-LABEL: fcvt_lu_h:
617 ; RV64IZDINXZHINX: # %bb.0:
618 ; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
619 ; RV64IZDINXZHINX-NEXT: ret
620 ;
621 ; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
622 ; CHECK32-IZFHMIN: # %bb.0:
623 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
624 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
625 ; CHECK32-IZFHMIN-NEXT: call __fixunshfdi
626 ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
627 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
628 ; CHECK32-IZFHMIN-NEXT: ret
629 ;
630 ; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
631 ; CHECK64-IZFHMIN: # %bb.0:
632 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
633 ; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
634 ; CHECK64-IZFHMIN-NEXT: ret
635 ;
636 ; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h:
637 ; CHECK32-IZHINXMIN: # %bb.0:
638 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
639 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
640 ; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi
641 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
642 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
643 ; CHECK32-IZHINXMIN-NEXT: ret
644 ;
645 ; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h:
646 ; CHECK64-IZHINXMIN: # %bb.0:
647 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
648 ; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
649 ; CHECK64-IZHINXMIN-NEXT: ret
650 ;
651 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
652 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
653 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
654 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
655 ; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi
656 ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
657 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
658 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
659 ;
660 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
661 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
662 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
663 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
664 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
665 %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %a, metadata !"fpexcept.strict")
666 ret i64 %1
667 }
668 declare i64 @llvm.experimental.constrained.fptoui.i64.f16(half, metadata)
670 define half @fcvt_h_si(i16 %a) nounwind strictfp {
671 ; RV32IZFH-LABEL: fcvt_h_si:
672 ; RV32IZFH: # %bb.0:
673 ; RV32IZFH-NEXT: slli a0, a0, 16
674 ; RV32IZFH-NEXT: srai a0, a0, 16
675 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
676 ; RV32IZFH-NEXT: ret
677 ;
678 ; RV64IZFH-LABEL: fcvt_h_si:
679 ; RV64IZFH: # %bb.0:
680 ; RV64IZFH-NEXT: slli a0, a0, 48
681 ; RV64IZFH-NEXT: srai a0, a0, 48
682 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
683 ; RV64IZFH-NEXT: ret
684 ;
685 ; RV32IZHINX-LABEL: fcvt_h_si:
686 ; RV32IZHINX: # %bb.0:
687 ; RV32IZHINX-NEXT: slli a0, a0, 16
688 ; RV32IZHINX-NEXT: srai a0, a0, 16
689 ; RV32IZHINX-NEXT: fcvt.h.w a0, a0
690 ; RV32IZHINX-NEXT: ret
691 ;
692 ; RV64IZHINX-LABEL: fcvt_h_si:
693 ; RV64IZHINX: # %bb.0:
694 ; RV64IZHINX-NEXT: slli a0, a0, 48
695 ; RV64IZHINX-NEXT: srai a0, a0, 48
696 ; RV64IZHINX-NEXT: fcvt.h.w a0, a0
697 ; RV64IZHINX-NEXT: ret
698 ;
699 ; RV32IDZFH-LABEL: fcvt_h_si:
700 ; RV32IDZFH: # %bb.0:
701 ; RV32IDZFH-NEXT: slli a0, a0, 16
702 ; RV32IDZFH-NEXT: srai a0, a0, 16
703 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
704 ; RV32IDZFH-NEXT: ret
705 ;
706 ; RV64IDZFH-LABEL: fcvt_h_si:
707 ; RV64IDZFH: # %bb.0:
708 ; RV64IDZFH-NEXT: slli a0, a0, 48
709 ; RV64IDZFH-NEXT: srai a0, a0, 48
710 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
711 ; RV64IDZFH-NEXT: ret
712 ;
713 ; RV32IZDINXZHINX-LABEL: fcvt_h_si:
714 ; RV32IZDINXZHINX: # %bb.0:
715 ; RV32IZDINXZHINX-NEXT: slli a0, a0, 16
716 ; RV32IZDINXZHINX-NEXT: srai a0, a0, 16
717 ; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0
718 ; RV32IZDINXZHINX-NEXT: ret
719 ;
720 ; RV64IZDINXZHINX-LABEL: fcvt_h_si:
721 ; RV64IZDINXZHINX: # %bb.0:
722 ; RV64IZDINXZHINX-NEXT: slli a0, a0, 48
723 ; RV64IZDINXZHINX-NEXT: srai a0, a0, 48
724 ; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
725 ; RV64IZDINXZHINX-NEXT: ret
726 ;
727 ; CHECK32-IZFHMIN-LABEL: fcvt_h_si:
728 ; CHECK32-IZFHMIN: # %bb.0:
729 ; CHECK32-IZFHMIN-NEXT: slli a0, a0, 16
730 ; CHECK32-IZFHMIN-NEXT: srai a0, a0, 16
731 ; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
732 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
733 ; CHECK32-IZFHMIN-NEXT: ret
734 ;
735 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si:
736 ; CHECK64-IZFHMIN: # %bb.0:
737 ; CHECK64-IZFHMIN-NEXT: slli a0, a0, 48
738 ; CHECK64-IZFHMIN-NEXT: srai a0, a0, 48
739 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
740 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
741 ; CHECK64-IZFHMIN-NEXT: ret
742 ;
743 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_si:
744 ; CHECK32-IZHINXMIN: # %bb.0:
745 ; CHECK32-IZHINXMIN-NEXT: slli a0, a0, 16
746 ; CHECK32-IZHINXMIN-NEXT: srai a0, a0, 16
747 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0
748 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
749 ; CHECK32-IZHINXMIN-NEXT: ret
750 ;
751 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_si:
752 ; CHECK64-IZHINXMIN: # %bb.0:
753 ; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 48
754 ; CHECK64-IZHINXMIN-NEXT: srai a0, a0, 48
755 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
756 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
757 ; CHECK64-IZHINXMIN-NEXT: ret
758 ;
759 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si:
760 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
761 ; CHECK32-IZDINXZHINXMIN-NEXT: slli a0, a0, 16
762 ; CHECK32-IZDINXZHINXMIN-NEXT: srai a0, a0, 16
763 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
764 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
765 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
766 ;
767 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si:
768 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
769 ; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48
770 ; CHECK64-IZDINXZHINXMIN-NEXT: srai a0, a0, 48
771 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
772 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
773 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
774 %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
775 ret half %1
776 }
777 declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)
779 define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
780 ; CHECKIZFH-LABEL: fcvt_h_si_signext:
781 ; CHECKIZFH: # %bb.0:
782 ; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
783 ; CHECKIZFH-NEXT: ret
784 ;
785 ; CHECKIZHINX-LABEL: fcvt_h_si_signext:
786 ; CHECKIZHINX: # %bb.0:
787 ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
788 ; CHECKIZHINX-NEXT: ret
789 ;
790 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
791 ; RV32IDZFH: # %bb.0:
792 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
793 ; RV32IDZFH-NEXT: ret
794 ;
795 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
796 ; RV64IDZFH: # %bb.0:
797 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
798 ; RV64IDZFH-NEXT: ret
799 ;
800 ; RV32IZDINXZHINX-LABEL: fcvt_h_si_signext:
801 ; RV32IZDINXZHINX: # %bb.0:
802 ; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0
803 ; RV32IZDINXZHINX-NEXT: ret
804 ;
805 ; RV64IZDINXZHINX-LABEL: fcvt_h_si_signext:
806 ; RV64IZDINXZHINX: # %bb.0:
807 ; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
808 ; RV64IZDINXZHINX-NEXT: ret
809 ;
810 ; CHECK32-IZFHMIN-LABEL: fcvt_h_si_signext:
811 ; CHECK32-IZFHMIN: # %bb.0:
812 ; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
813 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
814 ; CHECK32-IZFHMIN-NEXT: ret
815 ;
816 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
817 ; CHECK64-IZFHMIN: # %bb.0:
818 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
819 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
820 ; CHECK64-IZFHMIN-NEXT: ret
821 ;
822 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_si_signext:
823 ; CHECK32-IZHINXMIN: # %bb.0:
824 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0
825 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
826 ; CHECK32-IZHINXMIN-NEXT: ret
827 ;
828 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_si_signext:
829 ; CHECK64-IZHINXMIN: # %bb.0:
830 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
831 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
832 ; CHECK64-IZHINXMIN-NEXT: ret
833 ;
834 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
835 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
836 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
837 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
838 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
839 ;
840 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
841 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
842 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
843 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
844 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
845 %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
846 ret half %1
847 }
849 define half @fcvt_h_ui(i16 %a) nounwind strictfp {
850 ; RV32IZFH-LABEL: fcvt_h_ui:
851 ; RV32IZFH: # %bb.0:
852 ; RV32IZFH-NEXT: slli a0, a0, 16
853 ; RV32IZFH-NEXT: srli a0, a0, 16
854 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
855 ; RV32IZFH-NEXT: ret
856 ;
857 ; RV64IZFH-LABEL: fcvt_h_ui:
858 ; RV64IZFH: # %bb.0:
859 ; RV64IZFH-NEXT: slli a0, a0, 48
860 ; RV64IZFH-NEXT: srli a0, a0, 48
861 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
862 ; RV64IZFH-NEXT: ret
863 ;
864 ; RV32IZHINX-LABEL: fcvt_h_ui:
865 ; RV32IZHINX: # %bb.0:
866 ; RV32IZHINX-NEXT: slli a0, a0, 16
867 ; RV32IZHINX-NEXT: srli a0, a0, 16
868 ; RV32IZHINX-NEXT: fcvt.h.wu a0, a0
869 ; RV32IZHINX-NEXT: ret
870 ;
871 ; RV64IZHINX-LABEL: fcvt_h_ui:
872 ; RV64IZHINX: # %bb.0:
873 ; RV64IZHINX-NEXT: slli a0, a0, 48
874 ; RV64IZHINX-NEXT: srli a0, a0, 48
875 ; RV64IZHINX-NEXT: fcvt.h.wu a0, a0
876 ; RV64IZHINX-NEXT: ret
877 ;
878 ; RV32IDZFH-LABEL: fcvt_h_ui:
879 ; RV32IDZFH: # %bb.0:
880 ; RV32IDZFH-NEXT: slli a0, a0, 16
881 ; RV32IDZFH-NEXT: srli a0, a0, 16
882 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
883 ; RV32IDZFH-NEXT: ret
884 ;
885 ; RV64IDZFH-LABEL: fcvt_h_ui:
886 ; RV64IDZFH: # %bb.0:
887 ; RV64IDZFH-NEXT: slli a0, a0, 48
888 ; RV64IDZFH-NEXT: srli a0, a0, 48
889 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
890 ; RV64IDZFH-NEXT: ret
891 ;
892 ; RV32IZDINXZHINX-LABEL: fcvt_h_ui:
893 ; RV32IZDINXZHINX: # %bb.0:
894 ; RV32IZDINXZHINX-NEXT: slli a0, a0, 16
895 ; RV32IZDINXZHINX-NEXT: srli a0, a0, 16
896 ; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
897 ; RV32IZDINXZHINX-NEXT: ret
898 ;
899 ; RV64IZDINXZHINX-LABEL: fcvt_h_ui:
900 ; RV64IZDINXZHINX: # %bb.0:
901 ; RV64IZDINXZHINX-NEXT: slli a0, a0, 48
902 ; RV64IZDINXZHINX-NEXT: srli a0, a0, 48
903 ; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
904 ; RV64IZDINXZHINX-NEXT: ret
905 ;
906 ; CHECK32-IZFHMIN-LABEL: fcvt_h_ui:
907 ; CHECK32-IZFHMIN: # %bb.0:
908 ; CHECK32-IZFHMIN-NEXT: slli a0, a0, 16
909 ; CHECK32-IZFHMIN-NEXT: srli a0, a0, 16
910 ; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
911 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
912 ; CHECK32-IZFHMIN-NEXT: ret
913 ;
914 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui:
915 ; CHECK64-IZFHMIN: # %bb.0:
916 ; CHECK64-IZFHMIN-NEXT: slli a0, a0, 48
917 ; CHECK64-IZFHMIN-NEXT: srli a0, a0, 48
918 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
919 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
920 ; CHECK64-IZFHMIN-NEXT: ret
921 ;
922 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui:
923 ; CHECK32-IZHINXMIN: # %bb.0:
924 ; CHECK32-IZHINXMIN-NEXT: slli a0, a0, 16
925 ; CHECK32-IZHINXMIN-NEXT: srli a0, a0, 16
926 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
927 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
928 ; CHECK32-IZHINXMIN-NEXT: ret
929 ;
930 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui:
931 ; CHECK64-IZHINXMIN: # %bb.0:
932 ; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 48
933 ; CHECK64-IZHINXMIN-NEXT: srli a0, a0, 48
934 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
935 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
936 ; CHECK64-IZHINXMIN-NEXT: ret
937 ;
938 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
939 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
940 ; CHECK32-IZDINXZHINXMIN-NEXT: slli a0, a0, 16
941 ; CHECK32-IZDINXZHINXMIN-NEXT: srli a0, a0, 16
942 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
943 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
944 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
945 ;
946 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
947 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
948 ; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48
949 ; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 48
950 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
951 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
952 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
953 %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
954 ret half %1
955 }
956 declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)
958 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
959 ; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
960 ; CHECKIZFH: # %bb.0:
961 ; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
962 ; CHECKIZFH-NEXT: ret
963 ;
964 ; CHECKIZHINX-LABEL: fcvt_h_ui_zeroext:
965 ; CHECKIZHINX: # %bb.0:
966 ; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0
967 ; CHECKIZHINX-NEXT: ret
968 ;
969 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
970 ; RV32IDZFH: # %bb.0:
971 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
972 ; RV32IDZFH-NEXT: ret
973 ;
974 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
975 ; RV64IDZFH: # %bb.0:
976 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
977 ; RV64IDZFH-NEXT: ret
978 ;
979 ; RV32IZDINXZHINX-LABEL: fcvt_h_ui_zeroext:
980 ; RV32IZDINXZHINX: # %bb.0:
981 ; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
982 ; RV32IZDINXZHINX-NEXT: ret
983 ;
984 ; RV64IZDINXZHINX-LABEL: fcvt_h_ui_zeroext:
985 ; RV64IZDINXZHINX: # %bb.0:
986 ; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
987 ; RV64IZDINXZHINX-NEXT: ret
988 ;
989 ; CHECK32-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
990 ; CHECK32-IZFHMIN: # %bb.0:
991 ; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
992 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
993 ; CHECK32-IZFHMIN-NEXT: ret
994 ;
995 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
996 ; CHECK64-IZFHMIN: # %bb.0:
997 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
998 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
999 ; CHECK64-IZFHMIN-NEXT: ret
1000 ;
1001 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
1002 ; CHECK32-IZHINXMIN: # %bb.0:
1003 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
1004 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1005 ; CHECK32-IZHINXMIN-NEXT: ret
1006 ;
1007 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
1008 ; CHECK64-IZHINXMIN: # %bb.0:
1009 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
1010 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1011 ; CHECK64-IZHINXMIN-NEXT: ret
1012 ;
1013 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
1014 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1015 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
1016 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1017 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1018 ;
1019 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
1020 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1021 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
1022 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1023 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1024 %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1025 ret half %1
1026 }
1028 define half @fcvt_h_w(i32 %a) nounwind strictfp {
1029 ; CHECKIZFH-LABEL: fcvt_h_w:
1030 ; CHECKIZFH: # %bb.0:
1031 ; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
1032 ; CHECKIZFH-NEXT: ret
1033 ;
1034 ; CHECKIZHINX-LABEL: fcvt_h_w:
1035 ; CHECKIZHINX: # %bb.0:
1036 ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
1037 ; CHECKIZHINX-NEXT: ret
1038 ;
1039 ; RV32IDZFH-LABEL: fcvt_h_w:
1040 ; RV32IDZFH: # %bb.0:
1041 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
1042 ; RV32IDZFH-NEXT: ret
1043 ;
1044 ; RV64IDZFH-LABEL: fcvt_h_w:
1045 ; RV64IDZFH: # %bb.0:
1046 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
1047 ; RV64IDZFH-NEXT: ret
1048 ;
1049 ; RV32IZDINXZHINX-LABEL: fcvt_h_w:
1050 ; RV32IZDINXZHINX: # %bb.0:
1051 ; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0
1052 ; RV32IZDINXZHINX-NEXT: ret
1053 ;
1054 ; RV64IZDINXZHINX-LABEL: fcvt_h_w:
1055 ; RV64IZDINXZHINX: # %bb.0:
1056 ; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
1057 ; RV64IZDINXZHINX-NEXT: ret
1058 ;
1059 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w:
1060 ; CHECK32-IZFHMIN: # %bb.0:
1061 ; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
1062 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1063 ; CHECK32-IZFHMIN-NEXT: ret
1064 ;
1065 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
1066 ; CHECK64-IZFHMIN: # %bb.0:
1067 ; CHECK64-IZFHMIN-NEXT: sext.w a0, a0
1068 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
1069 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1070 ; CHECK64-IZFHMIN-NEXT: ret
1071 ;
1072 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_w:
1073 ; CHECK32-IZHINXMIN: # %bb.0:
1074 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0
1075 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1076 ; CHECK32-IZHINXMIN-NEXT: ret
1077 ;
1078 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_w:
1079 ; CHECK64-IZHINXMIN: # %bb.0:
1080 ; CHECK64-IZHINXMIN-NEXT: sext.w a0, a0
1081 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
1082 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1083 ; CHECK64-IZHINXMIN-NEXT: ret
1084 ;
1085 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w:
1086 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1087 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
1088 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1089 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1090 ;
1091 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w:
1092 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1093 ; CHECK64-IZDINXZHINXMIN-NEXT: sext.w a0, a0
1094 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
1095 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1096 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1097 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1098 ret half %1
1099 }
1100 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)
1102 define half @fcvt_h_w_load(ptr %p) nounwind strictfp {
1103 ; CHECKIZFH-LABEL: fcvt_h_w_load:
1104 ; CHECKIZFH: # %bb.0:
1105 ; CHECKIZFH-NEXT: lw a0, 0(a0)
1106 ; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
1107 ; CHECKIZFH-NEXT: ret
1108 ;
1109 ; CHECKIZHINX-LABEL: fcvt_h_w_load:
1110 ; CHECKIZHINX: # %bb.0:
1111 ; CHECKIZHINX-NEXT: lw a0, 0(a0)
1112 ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
1113 ; CHECKIZHINX-NEXT: ret
1114 ;
1115 ; RV32IDZFH-LABEL: fcvt_h_w_load:
1116 ; RV32IDZFH: # %bb.0:
1117 ; RV32IDZFH-NEXT: lw a0, 0(a0)
1118 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
1119 ; RV32IDZFH-NEXT: ret
1120 ;
1121 ; RV64IDZFH-LABEL: fcvt_h_w_load:
1122 ; RV64IDZFH: # %bb.0:
1123 ; RV64IDZFH-NEXT: lw a0, 0(a0)
1124 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
1125 ; RV64IDZFH-NEXT: ret
1126 ;
1127 ; RV32IZDINXZHINX-LABEL: fcvt_h_w_load:
1128 ; RV32IZDINXZHINX: # %bb.0:
1129 ; RV32IZDINXZHINX-NEXT: lw a0, 0(a0)
1130 ; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0
1131 ; RV32IZDINXZHINX-NEXT: ret
1132 ;
1133 ; RV64IZDINXZHINX-LABEL: fcvt_h_w_load:
1134 ; RV64IZDINXZHINX: # %bb.0:
1135 ; RV64IZDINXZHINX-NEXT: lw a0, 0(a0)
1136 ; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
1137 ; RV64IZDINXZHINX-NEXT: ret
1138 ;
1139 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w_load:
1140 ; CHECK32-IZFHMIN: # %bb.0:
1141 ; CHECK32-IZFHMIN-NEXT: lw a0, 0(a0)
1142 ; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
1143 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1144 ; CHECK32-IZFHMIN-NEXT: ret
1145 ;
1146 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
1147 ; CHECK64-IZFHMIN: # %bb.0:
1148 ; CHECK64-IZFHMIN-NEXT: lw a0, 0(a0)
1149 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
1150 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1151 ; CHECK64-IZFHMIN-NEXT: ret
1152 ;
1153 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_load:
1154 ; CHECK32-IZHINXMIN: # %bb.0:
1155 ; CHECK32-IZHINXMIN-NEXT: lw a0, 0(a0)
1156 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0
1157 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1158 ; CHECK32-IZHINXMIN-NEXT: ret
1159 ;
1160 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_load:
1161 ; CHECK64-IZHINXMIN: # %bb.0:
1162 ; CHECK64-IZHINXMIN-NEXT: lw a0, 0(a0)
1163 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
1164 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1165 ; CHECK64-IZHINXMIN-NEXT: ret
1166 ;
1167 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
1168 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1169 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 0(a0)
1170 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
1171 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1172 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1173 ;
1174 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
1175 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1176 ; CHECK64-IZDINXZHINXMIN-NEXT: lw a0, 0(a0)
1177 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
1178 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1179 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1180 %a = load i32, ptr %p
1181 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1182 ret half %1
1183 }
1185 define half @fcvt_h_wu(i32 %a) nounwind strictfp {
1186 ; CHECKIZFH-LABEL: fcvt_h_wu:
1187 ; CHECKIZFH: # %bb.0:
1188 ; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
1189 ; CHECKIZFH-NEXT: ret
1190 ;
1191 ; CHECKIZHINX-LABEL: fcvt_h_wu:
1192 ; CHECKIZHINX: # %bb.0:
1193 ; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0
1194 ; CHECKIZHINX-NEXT: ret
1195 ;
1196 ; RV32IDZFH-LABEL: fcvt_h_wu:
1197 ; RV32IDZFH: # %bb.0:
1198 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
1199 ; RV32IDZFH-NEXT: ret
1200 ;
1201 ; RV64IDZFH-LABEL: fcvt_h_wu:
1202 ; RV64IDZFH: # %bb.0:
1203 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
1204 ; RV64IDZFH-NEXT: ret
1205 ;
1206 ; RV32IZDINXZHINX-LABEL: fcvt_h_wu:
1207 ; RV32IZDINXZHINX: # %bb.0:
1208 ; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
1209 ; RV32IZDINXZHINX-NEXT: ret
1210 ;
1211 ; RV64IZDINXZHINX-LABEL: fcvt_h_wu:
1212 ; RV64IZDINXZHINX: # %bb.0:
1213 ; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
1214 ; RV64IZDINXZHINX-NEXT: ret
1215 ;
1216 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu:
1217 ; CHECK32-IZFHMIN: # %bb.0:
1218 ; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
1219 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1220 ; CHECK32-IZFHMIN-NEXT: ret
1221 ;
1222 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
1223 ; CHECK64-IZFHMIN: # %bb.0:
1224 ; CHECK64-IZFHMIN-NEXT: slli a0, a0, 32
1225 ; CHECK64-IZFHMIN-NEXT: srli a0, a0, 32
1226 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
1227 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1228 ; CHECK64-IZFHMIN-NEXT: ret
1229 ;
1230 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu:
1231 ; CHECK32-IZHINXMIN: # %bb.0:
1232 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
1233 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1234 ; CHECK32-IZHINXMIN-NEXT: ret
1235 ;
1236 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu:
1237 ; CHECK64-IZHINXMIN: # %bb.0:
1238 ; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 32
1239 ; CHECK64-IZHINXMIN-NEXT: srli a0, a0, 32
1240 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
1241 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1242 ; CHECK64-IZHINXMIN-NEXT: ret
1243 ;
1244 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
1245 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1246 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
1247 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1248 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1249 ;
1250 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
1251 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1252 ; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 32
1253 ; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 32
1254 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
1255 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1256 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1257 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1258 ret half %1
1259 }
1260 declare half @llvm.experimental.constrained.uitofp.f16.i32(i32, metadata, metadata)
1262 define half @fcvt_h_wu_load(ptr %p) nounwind strictfp {
1263 ; RV32IZFH-LABEL: fcvt_h_wu_load:
1264 ; RV32IZFH: # %bb.0:
1265 ; RV32IZFH-NEXT: lw a0, 0(a0)
1266 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
1267 ; RV32IZFH-NEXT: ret
1268 ;
1269 ; RV64IZFH-LABEL: fcvt_h_wu_load:
1270 ; RV64IZFH: # %bb.0:
1271 ; RV64IZFH-NEXT: lwu a0, 0(a0)
1272 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
1273 ; RV64IZFH-NEXT: ret
1274 ;
1275 ; RV32IZHINX-LABEL: fcvt_h_wu_load:
1276 ; RV32IZHINX: # %bb.0:
1277 ; RV32IZHINX-NEXT: lw a0, 0(a0)
1278 ; RV32IZHINX-NEXT: fcvt.h.wu a0, a0
1279 ; RV32IZHINX-NEXT: ret
1280 ;
1281 ; RV64IZHINX-LABEL: fcvt_h_wu_load:
1282 ; RV64IZHINX: # %bb.0:
1283 ; RV64IZHINX-NEXT: lwu a0, 0(a0)
1284 ; RV64IZHINX-NEXT: fcvt.h.wu a0, a0
1285 ; RV64IZHINX-NEXT: ret
1286 ;
1287 ; RV32IDZFH-LABEL: fcvt_h_wu_load:
1288 ; RV32IDZFH: # %bb.0:
1289 ; RV32IDZFH-NEXT: lw a0, 0(a0)
1290 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
1291 ; RV32IDZFH-NEXT: ret
1292 ;
1293 ; RV64IDZFH-LABEL: fcvt_h_wu_load:
1294 ; RV64IDZFH: # %bb.0:
1295 ; RV64IDZFH-NEXT: lwu a0, 0(a0)
1296 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
1297 ; RV64IDZFH-NEXT: ret
1298 ;
1299 ; RV32IZDINXZHINX-LABEL: fcvt_h_wu_load:
1300 ; RV32IZDINXZHINX: # %bb.0:
1301 ; RV32IZDINXZHINX-NEXT: lw a0, 0(a0)
1302 ; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
1303 ; RV32IZDINXZHINX-NEXT: ret
1304 ;
1305 ; RV64IZDINXZHINX-LABEL: fcvt_h_wu_load:
1306 ; RV64IZDINXZHINX: # %bb.0:
1307 ; RV64IZDINXZHINX-NEXT: lwu a0, 0(a0)
1308 ; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0
1309 ; RV64IZDINXZHINX-NEXT: ret
1310 ;
1311 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_load:
1312 ; CHECK32-IZFHMIN: # %bb.0:
1313 ; CHECK32-IZFHMIN-NEXT: lw a0, 0(a0)
1314 ; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
1315 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1316 ; CHECK32-IZFHMIN-NEXT: ret
1317 ;
1318 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load:
1319 ; CHECK64-IZFHMIN: # %bb.0:
1320 ; CHECK64-IZFHMIN-NEXT: lwu a0, 0(a0)
1321 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
1322 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1323 ; CHECK64-IZFHMIN-NEXT: ret
1324 ;
1325 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_load:
1326 ; CHECK32-IZHINXMIN: # %bb.0:
1327 ; CHECK32-IZHINXMIN-NEXT: lw a0, 0(a0)
1328 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0
1329 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1330 ; CHECK32-IZHINXMIN-NEXT: ret
1331 ;
1332 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_load:
1333 ; CHECK64-IZHINXMIN: # %bb.0:
1334 ; CHECK64-IZHINXMIN-NEXT: lwu a0, 0(a0)
1335 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
1336 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1337 ; CHECK64-IZHINXMIN-NEXT: ret
1338 ;
1339 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
1340 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1341 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 0(a0)
1342 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0
1343 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1344 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1345 ;
1346 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
1347 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1348 ; CHECK64-IZDINXZHINXMIN-NEXT: lwu a0, 0(a0)
1349 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
1350 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1351 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1352 %a = load i32, ptr %p
1353 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1354 ret half %1
1355 }
1357 define half @fcvt_h_l(i64 %a) nounwind strictfp {
1358 ; RV32IZFH-LABEL: fcvt_h_l:
1359 ; RV32IZFH: # %bb.0:
1360 ; RV32IZFH-NEXT: addi sp, sp, -16
1361 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1362 ; RV32IZFH-NEXT: call __floatdihf
1363 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1364 ; RV32IZFH-NEXT: addi sp, sp, 16
1365 ; RV32IZFH-NEXT: ret
1366 ;
1367 ; RV64IZFH-LABEL: fcvt_h_l:
1368 ; RV64IZFH: # %bb.0:
1369 ; RV64IZFH-NEXT: fcvt.h.l fa0, a0
1370 ; RV64IZFH-NEXT: ret
1371 ;
1372 ; RV32IZHINX-LABEL: fcvt_h_l:
1373 ; RV32IZHINX: # %bb.0:
1374 ; RV32IZHINX-NEXT: addi sp, sp, -16
1375 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1376 ; RV32IZHINX-NEXT: call __floatdihf
1377 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1378 ; RV32IZHINX-NEXT: addi sp, sp, 16
1379 ; RV32IZHINX-NEXT: ret
1380 ;
1381 ; RV64IZHINX-LABEL: fcvt_h_l:
1382 ; RV64IZHINX: # %bb.0:
1383 ; RV64IZHINX-NEXT: fcvt.h.l a0, a0
1384 ; RV64IZHINX-NEXT: ret
1385 ;
1386 ; RV32IDZFH-LABEL: fcvt_h_l:
1387 ; RV32IDZFH: # %bb.0:
1388 ; RV32IDZFH-NEXT: addi sp, sp, -16
1389 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1390 ; RV32IDZFH-NEXT: call __floatdihf
1391 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1392 ; RV32IDZFH-NEXT: addi sp, sp, 16
1393 ; RV32IDZFH-NEXT: ret
1394 ;
1395 ; RV64IDZFH-LABEL: fcvt_h_l:
1396 ; RV64IDZFH: # %bb.0:
1397 ; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
1398 ; RV64IDZFH-NEXT: ret
1399 ;
1400 ; RV32IZDINXZHINX-LABEL: fcvt_h_l:
1401 ; RV32IZDINXZHINX: # %bb.0:
1402 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
1403 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1404 ; RV32IZDINXZHINX-NEXT: call __floatdihf
1405 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1406 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
1407 ; RV32IZDINXZHINX-NEXT: ret
1408 ;
1409 ; RV64IZDINXZHINX-LABEL: fcvt_h_l:
1410 ; RV64IZDINXZHINX: # %bb.0:
1411 ; RV64IZDINXZHINX-NEXT: fcvt.h.l a0, a0
1412 ; RV64IZDINXZHINX-NEXT: ret
1413 ;
1414 ; CHECK32-IZFHMIN-LABEL: fcvt_h_l:
1415 ; CHECK32-IZFHMIN: # %bb.0:
1416 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
1417 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1418 ; CHECK32-IZFHMIN-NEXT: call __floatdihf
1419 ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1420 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
1421 ; CHECK32-IZFHMIN-NEXT: ret
1422 ;
1423 ; CHECK64-IZFHMIN-LABEL: fcvt_h_l:
1424 ; CHECK64-IZFHMIN: # %bb.0:
1425 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
1426 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1427 ; CHECK64-IZFHMIN-NEXT: ret
1428 ;
1429 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_l:
1430 ; CHECK32-IZHINXMIN: # %bb.0:
1431 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
1432 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1433 ; CHECK32-IZHINXMIN-NEXT: call __floatdihf
1434 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1435 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
1436 ; CHECK32-IZHINXMIN-NEXT: ret
1437 ;
1438 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_l:
1439 ; CHECK64-IZHINXMIN: # %bb.0:
1440 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a0
1441 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1442 ; CHECK64-IZHINXMIN-NEXT: ret
1443 ;
1444 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_l:
1445 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1446 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
1447 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1448 ; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf
1449 ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1450 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
1451 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1452 ;
1453 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_l:
1454 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1455 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0
1456 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1457 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1458 %1 = call half @llvm.experimental.constrained.sitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1459 ret half %1
1460 }
1461 declare half @llvm.experimental.constrained.sitofp.f16.i64(i64, metadata, metadata)
1463 define half @fcvt_h_lu(i64 %a) nounwind strictfp {
1464 ; RV32IZFH-LABEL: fcvt_h_lu:
1465 ; RV32IZFH: # %bb.0:
1466 ; RV32IZFH-NEXT: addi sp, sp, -16
1467 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1468 ; RV32IZFH-NEXT: call __floatundihf
1469 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1470 ; RV32IZFH-NEXT: addi sp, sp, 16
1471 ; RV32IZFH-NEXT: ret
1472 ;
1473 ; RV64IZFH-LABEL: fcvt_h_lu:
1474 ; RV64IZFH: # %bb.0:
1475 ; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
1476 ; RV64IZFH-NEXT: ret
1477 ;
1478 ; RV32IZHINX-LABEL: fcvt_h_lu:
1479 ; RV32IZHINX: # %bb.0:
1480 ; RV32IZHINX-NEXT: addi sp, sp, -16
1481 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1482 ; RV32IZHINX-NEXT: call __floatundihf
1483 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1484 ; RV32IZHINX-NEXT: addi sp, sp, 16
1485 ; RV32IZHINX-NEXT: ret
1486 ;
1487 ; RV64IZHINX-LABEL: fcvt_h_lu:
1488 ; RV64IZHINX: # %bb.0:
1489 ; RV64IZHINX-NEXT: fcvt.h.lu a0, a0
1490 ; RV64IZHINX-NEXT: ret
1491 ;
1492 ; RV32IDZFH-LABEL: fcvt_h_lu:
1493 ; RV32IDZFH: # %bb.0:
1494 ; RV32IDZFH-NEXT: addi sp, sp, -16
1495 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1496 ; RV32IDZFH-NEXT: call __floatundihf
1497 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1498 ; RV32IDZFH-NEXT: addi sp, sp, 16
1499 ; RV32IDZFH-NEXT: ret
1500 ;
1501 ; RV64IDZFH-LABEL: fcvt_h_lu:
1502 ; RV64IDZFH: # %bb.0:
1503 ; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
1504 ; RV64IDZFH-NEXT: ret
1505 ;
1506 ; RV32IZDINXZHINX-LABEL: fcvt_h_lu:
1507 ; RV32IZDINXZHINX: # %bb.0:
1508 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
1509 ; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1510 ; RV32IZDINXZHINX-NEXT: call __floatundihf
1511 ; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1512 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
1513 ; RV32IZDINXZHINX-NEXT: ret
1514 ;
1515 ; RV64IZDINXZHINX-LABEL: fcvt_h_lu:
1516 ; RV64IZDINXZHINX: # %bb.0:
1517 ; RV64IZDINXZHINX-NEXT: fcvt.h.lu a0, a0
1518 ; RV64IZDINXZHINX-NEXT: ret
1519 ;
1520 ; CHECK32-IZFHMIN-LABEL: fcvt_h_lu:
1521 ; CHECK32-IZFHMIN: # %bb.0:
1522 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
1523 ; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1524 ; CHECK32-IZFHMIN-NEXT: call __floatundihf
1525 ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1526 ; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
1527 ; CHECK32-IZFHMIN-NEXT: ret
1528 ;
1529 ; CHECK64-IZFHMIN-LABEL: fcvt_h_lu:
1530 ; CHECK64-IZFHMIN: # %bb.0:
1531 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a0
1532 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1533 ; CHECK64-IZFHMIN-NEXT: ret
1534 ;
1535 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_lu:
1536 ; CHECK32-IZHINXMIN: # %bb.0:
1537 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
1538 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1539 ; CHECK32-IZHINXMIN-NEXT: call __floatundihf
1540 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1541 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
1542 ; CHECK32-IZHINXMIN-NEXT: ret
1543 ;
1544 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_lu:
1545 ; CHECK64-IZHINXMIN: # %bb.0:
1546 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a0
1547 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1548 ; CHECK64-IZHINXMIN-NEXT: ret
1549 ;
1550 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
1551 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1552 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
1553 ; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1554 ; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf
1555 ; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1556 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
1557 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1558 ;
1559 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
1560 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1561 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0
1562 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1563 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1564 %1 = call half @llvm.experimental.constrained.uitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1565 ret half %1
1566 }
1567 declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)
1569 define half @fcvt_h_s(float %a) nounwind strictfp {
1570 ; CHECKIZFH-LABEL: fcvt_h_s:
1571 ; CHECKIZFH: # %bb.0:
1572 ; CHECKIZFH-NEXT: fcvt.h.s fa0, fa0
1573 ; CHECKIZFH-NEXT: ret
1574 ;
1575 ; CHECKIZHINX-LABEL: fcvt_h_s:
1576 ; CHECKIZHINX: # %bb.0:
1577 ; CHECKIZHINX-NEXT: fcvt.h.s a0, a0
1578 ; CHECKIZHINX-NEXT: ret
1579 ;
1580 ; RV32IDZFH-LABEL: fcvt_h_s:
1581 ; RV32IDZFH: # %bb.0:
1582 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1583 ; RV32IDZFH-NEXT: ret
1584 ;
1585 ; RV64IDZFH-LABEL: fcvt_h_s:
1586 ; RV64IDZFH: # %bb.0:
1587 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1588 ; RV64IDZFH-NEXT: ret
1589 ;
1590 ; RV32IZDINXZHINX-LABEL: fcvt_h_s:
1591 ; RV32IZDINXZHINX: # %bb.0:
1592 ; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0
1593 ; RV32IZDINXZHINX-NEXT: ret
1594 ;
1595 ; RV64IZDINXZHINX-LABEL: fcvt_h_s:
1596 ; RV64IZDINXZHINX: # %bb.0:
1597 ; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0
1598 ; RV64IZDINXZHINX-NEXT: ret
1599 ;
1600 ; CHECK32-IZFHMIN-LABEL: fcvt_h_s:
1601 ; CHECK32-IZFHMIN: # %bb.0:
1602 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1603 ; CHECK32-IZFHMIN-NEXT: ret
1604 ;
1605 ; CHECK64-IZFHMIN-LABEL: fcvt_h_s:
1606 ; CHECK64-IZFHMIN: # %bb.0:
1607 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1608 ; CHECK64-IZFHMIN-NEXT: ret
1609 ;
1610 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_s:
1611 ; CHECK32-IZHINXMIN: # %bb.0:
1612 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1613 ; CHECK32-IZHINXMIN-NEXT: ret
1614 ;
1615 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_s:
1616 ; CHECK64-IZHINXMIN: # %bb.0:
1617 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
1618 ; CHECK64-IZHINXMIN-NEXT: ret
1619 ;
1620 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_s:
1621 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1622 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1623 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1624 ;
1625 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_s:
1626 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1627 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
1628 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1629 %1 = call half @llvm.experimental.constrained.fptrunc.f16.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1630 ret half %1
1631 }
1632 declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)
1634 define float @fcvt_s_h(half %a) nounwind strictfp {
1635 ; CHECKIZFH-LABEL: fcvt_s_h:
1636 ; CHECKIZFH: # %bb.0:
1637 ; CHECKIZFH-NEXT: fcvt.s.h fa0, fa0
1638 ; CHECKIZFH-NEXT: ret
1639 ;
1640 ; CHECKIZHINX-LABEL: fcvt_s_h:
1641 ; CHECKIZHINX: # %bb.0:
1642 ; CHECKIZHINX-NEXT: fcvt.s.h a0, a0
1643 ; CHECKIZHINX-NEXT: ret
1644 ;
1645 ; RV32IDZFH-LABEL: fcvt_s_h:
1646 ; RV32IDZFH: # %bb.0:
1647 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1648 ; RV32IDZFH-NEXT: ret
1649 ;
1650 ; RV64IDZFH-LABEL: fcvt_s_h:
1651 ; RV64IDZFH: # %bb.0:
1652 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1653 ; RV64IDZFH-NEXT: ret
1654 ;
1655 ; RV32IZDINXZHINX-LABEL: fcvt_s_h:
1656 ; RV32IZDINXZHINX: # %bb.0:
1657 ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
1658 ; RV32IZDINXZHINX-NEXT: ret
1659 ;
1660 ; RV64IZDINXZHINX-LABEL: fcvt_s_h:
1661 ; RV64IZDINXZHINX: # %bb.0:
1662 ; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
1663 ; RV64IZDINXZHINX-NEXT: ret
1664 ;
1665 ; CHECK32-IZFHMIN-LABEL: fcvt_s_h:
1666 ; CHECK32-IZFHMIN: # %bb.0:
1667 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1668 ; CHECK32-IZFHMIN-NEXT: ret
1669 ;
1670 ; CHECK64-IZFHMIN-LABEL: fcvt_s_h:
1671 ; CHECK64-IZFHMIN: # %bb.0:
1672 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1673 ; CHECK64-IZFHMIN-NEXT: ret
1674 ;
1675 ; CHECK32-IZHINXMIN-LABEL: fcvt_s_h:
1676 ; CHECK32-IZHINXMIN: # %bb.0:
1677 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
1678 ; CHECK32-IZHINXMIN-NEXT: ret
1679 ;
1680 ; CHECK64-IZHINXMIN-LABEL: fcvt_s_h:
1681 ; CHECK64-IZHINXMIN: # %bb.0:
1682 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
1683 ; CHECK64-IZHINXMIN-NEXT: ret
1684 ;
1685 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_s_h:
1686 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1687 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
1688 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1689 ;
1690 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_s_h:
1691 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1692 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
1693 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1694 %1 = call float @llvm.experimental.constrained.fpext.f32.f16(half %a, metadata !"fpexcept.strict")
1695 ret float %1
1696 }
1697 declare float @llvm.experimental.constrained.fpext.f32.f16(half, metadata)
1699 define half @fcvt_h_d(double %a) nounwind strictfp {
1700 ; RV32IZFH-LABEL: fcvt_h_d:
1701 ; RV32IZFH: # %bb.0:
1702 ; RV32IZFH-NEXT: addi sp, sp, -16
1703 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1704 ; RV32IZFH-NEXT: call __truncdfhf2
1705 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1706 ; RV32IZFH-NEXT: addi sp, sp, 16
1707 ; RV32IZFH-NEXT: ret
1708 ;
1709 ; RV64IZFH-LABEL: fcvt_h_d:
1710 ; RV64IZFH: # %bb.0:
1711 ; RV64IZFH-NEXT: addi sp, sp, -16
1712 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1713 ; RV64IZFH-NEXT: call __truncdfhf2
1714 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1715 ; RV64IZFH-NEXT: addi sp, sp, 16
1716 ; RV64IZFH-NEXT: ret
1717 ;
1718 ; RV32IZHINX-LABEL: fcvt_h_d:
1719 ; RV32IZHINX: # %bb.0:
1720 ; RV32IZHINX-NEXT: addi sp, sp, -16
1721 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1722 ; RV32IZHINX-NEXT: call __truncdfhf2
1723 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1724 ; RV32IZHINX-NEXT: addi sp, sp, 16
1725 ; RV32IZHINX-NEXT: ret
1726 ;
1727 ; RV64IZHINX-LABEL: fcvt_h_d:
1728 ; RV64IZHINX: # %bb.0:
1729 ; RV64IZHINX-NEXT: addi sp, sp, -16
1730 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1731 ; RV64IZHINX-NEXT: call __truncdfhf2
1732 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1733 ; RV64IZHINX-NEXT: addi sp, sp, 16
1734 ; RV64IZHINX-NEXT: ret
1735 ;
1736 ; RV32IDZFH-LABEL: fcvt_h_d:
1737 ; RV32IDZFH: # %bb.0:
1738 ; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0
1739 ; RV32IDZFH-NEXT: ret
1740 ;
1741 ; RV64IDZFH-LABEL: fcvt_h_d:
1742 ; RV64IDZFH: # %bb.0:
1743 ; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0
1744 ; RV64IDZFH-NEXT: ret
1745 ;
1746 ; RV32IZDINXZHINX-LABEL: fcvt_h_d:
1747 ; RV32IZDINXZHINX: # %bb.0:
1748 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
1749 ; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
1750 ; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
1751 ; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
1752 ; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
1753 ; RV32IZDINXZHINX-NEXT: fcvt.h.d a0, a0
1754 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
1755 ; RV32IZDINXZHINX-NEXT: ret
1756 ;
1757 ; RV64IZDINXZHINX-LABEL: fcvt_h_d:
1758 ; RV64IZDINXZHINX: # %bb.0:
1759 ; RV64IZDINXZHINX-NEXT: fcvt.h.d a0, a0
1760 ; RV64IZDINXZHINX-NEXT: ret
1761 ;
1762 ; RV32IFZFHMIN-LABEL: fcvt_h_d:
1763 ; RV32IFZFHMIN: # %bb.0:
1764 ; RV32IFZFHMIN-NEXT: addi sp, sp, -16
1765 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1766 ; RV32IFZFHMIN-NEXT: call __truncdfhf2
1767 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1768 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
1769 ; RV32IFZFHMIN-NEXT: ret
1770 ;
1771 ; RV64IFZFHMIN-LABEL: fcvt_h_d:
1772 ; RV64IFZFHMIN: # %bb.0:
1773 ; RV64IFZFHMIN-NEXT: addi sp, sp, -16
1774 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1775 ; RV64IFZFHMIN-NEXT: call __truncdfhf2
1776 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1777 ; RV64IFZFHMIN-NEXT: addi sp, sp, 16
1778 ; RV64IFZFHMIN-NEXT: ret
1779 ;
1780 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_d:
1781 ; CHECK32-IZHINXMIN: # %bb.0:
1782 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
1783 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1784 ; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2
1785 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1786 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
1787 ; CHECK32-IZHINXMIN-NEXT: ret
1788 ;
1789 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_d:
1790 ; CHECK64-IZHINXMIN: # %bb.0:
1791 ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16
1792 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1793 ; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2
1794 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1795 ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16
1796 ; CHECK64-IZHINXMIN-NEXT: ret
1797 ;
1798 ; RV32IDZFHMIN-LABEL: fcvt_h_d:
1799 ; RV32IDZFHMIN: # %bb.0:
1800 ; RV32IDZFHMIN-NEXT: fcvt.h.d fa0, fa0
1801 ; RV32IDZFHMIN-NEXT: ret
1802 ;
1803 ; RV64IDZFHMIN-LABEL: fcvt_h_d:
1804 ; RV64IDZFHMIN: # %bb.0:
1805 ; RV64IDZFHMIN-NEXT: fcvt.h.d fa0, fa0
1806 ; RV64IDZFHMIN-NEXT: ret
1807 ;
1808 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d:
1809 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1810 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
1811 ; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
1812 ; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
1813 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
1814 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
1815 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0
1816 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
1817 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1818 ;
1819 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d:
1820 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1821 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0
1822 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1823 %1 = call half @llvm.experimental.constrained.fptrunc.f16.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
1824 ret half %1
1825 }
1826 declare half @llvm.experimental.constrained.fptrunc.f16.f64(double, metadata, metadata)
1828 define double @fcvt_d_h(half %a) nounwind strictfp {
1829 ; RV32IZFH-LABEL: fcvt_d_h:
1830 ; RV32IZFH: # %bb.0:
1831 ; RV32IZFH-NEXT: addi sp, sp, -16
1832 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1833 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1834 ; RV32IZFH-NEXT: call __extendsfdf2
1835 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1836 ; RV32IZFH-NEXT: addi sp, sp, 16
1837 ; RV32IZFH-NEXT: ret
1838 ;
1839 ; RV64IZFH-LABEL: fcvt_d_h:
1840 ; RV64IZFH: # %bb.0:
1841 ; RV64IZFH-NEXT: addi sp, sp, -16
1842 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1843 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1844 ; RV64IZFH-NEXT: call __extendsfdf2
1845 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1846 ; RV64IZFH-NEXT: addi sp, sp, 16
1847 ; RV64IZFH-NEXT: ret
1848 ;
1849 ; RV32IZHINX-LABEL: fcvt_d_h:
1850 ; RV32IZHINX: # %bb.0:
1851 ; RV32IZHINX-NEXT: addi sp, sp, -16
1852 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1853 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1854 ; RV32IZHINX-NEXT: call __extendsfdf2
1855 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1856 ; RV32IZHINX-NEXT: addi sp, sp, 16
1857 ; RV32IZHINX-NEXT: ret
1858 ;
1859 ; RV64IZHINX-LABEL: fcvt_d_h:
1860 ; RV64IZHINX: # %bb.0:
1861 ; RV64IZHINX-NEXT: addi sp, sp, -16
1862 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1863 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1864 ; RV64IZHINX-NEXT: call __extendsfdf2
1865 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1866 ; RV64IZHINX-NEXT: addi sp, sp, 16
1867 ; RV64IZHINX-NEXT: ret
1868 ;
1869 ; RV32IDZFH-LABEL: fcvt_d_h:
1870 ; RV32IDZFH: # %bb.0:
1871 ; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0
1872 ; RV32IDZFH-NEXT: ret
1873 ;
1874 ; RV64IDZFH-LABEL: fcvt_d_h:
1875 ; RV64IDZFH: # %bb.0:
1876 ; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0
1877 ; RV64IDZFH-NEXT: ret
1878 ;
1879 ; RV32IZDINXZHINX-LABEL: fcvt_d_h:
1880 ; RV32IZDINXZHINX: # %bb.0:
1881 ; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
1882 ; RV32IZDINXZHINX-NEXT: fcvt.d.h a0, a0
1883 ; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
1884 ; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
1885 ; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
1886 ; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
1887 ; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
1888 ; RV32IZDINXZHINX-NEXT: ret
1889 ;
1890 ; RV64IZDINXZHINX-LABEL: fcvt_d_h:
1891 ; RV64IZDINXZHINX: # %bb.0:
1892 ; RV64IZDINXZHINX-NEXT: fcvt.d.h a0, a0
1893 ; RV64IZDINXZHINX-NEXT: ret
1894 ;
1895 ; RV32IFZFHMIN-LABEL: fcvt_d_h:
1896 ; RV32IFZFHMIN: # %bb.0:
1897 ; RV32IFZFHMIN-NEXT: addi sp, sp, -16
1898 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1899 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa0, fa0
1900 ; RV32IFZFHMIN-NEXT: call __extendsfdf2
1901 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1902 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
1903 ; RV32IFZFHMIN-NEXT: ret
1904 ;
1905 ; RV64IFZFHMIN-LABEL: fcvt_d_h:
1906 ; RV64IFZFHMIN: # %bb.0:
1907 ; RV64IFZFHMIN-NEXT: addi sp, sp, -16
1908 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1909 ; RV64IFZFHMIN-NEXT: fcvt.s.h fa0, fa0
1910 ; RV64IFZFHMIN-NEXT: call __extendsfdf2
1911 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1912 ; RV64IFZFHMIN-NEXT: addi sp, sp, 16
1913 ; RV64IFZFHMIN-NEXT: ret
1914 ;
1915 ; CHECK32-IZHINXMIN-LABEL: fcvt_d_h:
1916 ; CHECK32-IZHINXMIN: # %bb.0:
1917 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
1918 ; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1919 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
1920 ; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2
1921 ; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1922 ; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
1923 ; CHECK32-IZHINXMIN-NEXT: ret
1924 ;
1925 ; CHECK64-IZHINXMIN-LABEL: fcvt_d_h:
1926 ; CHECK64-IZHINXMIN: # %bb.0:
1927 ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16
1928 ; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1929 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
1930 ; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2
1931 ; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1932 ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16
1933 ; CHECK64-IZHINXMIN-NEXT: ret
1934 ;
1935 ; RV32IDZFHMIN-LABEL: fcvt_d_h:
1936 ; RV32IDZFHMIN: # %bb.0:
1937 ; RV32IDZFHMIN-NEXT: fcvt.d.h fa0, fa0
1938 ; RV32IDZFHMIN-NEXT: ret
1939 ;
1940 ; RV64IDZFHMIN-LABEL: fcvt_d_h:
1941 ; RV64IDZFHMIN: # %bb.0:
1942 ; RV64IDZFHMIN-NEXT: fcvt.d.h fa0, fa0
1943 ; RV64IDZFHMIN-NEXT: ret
1944 ;
1945 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h:
1946 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
1947 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
1948 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0
1949 ; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
1950 ; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
1951 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
1952 ; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
1953 ; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
1954 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
1955 ;
1956 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h:
1957 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
1958 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0
1959 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
1960 %1 = call double @llvm.experimental.constrained.fpext.f64.f16(half %a, metadata !"fpexcept.strict")
1961 ret double %1
1962 }
1963 declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata)
1965 ; Make sure we select W version of addi on RV64.
1966 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
1967 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
1968 ; RV32IZFH: # %bb.0:
1969 ; RV32IZFH-NEXT: addi a0, a0, 1
1970 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0
1971 ; RV32IZFH-NEXT: fsh fa5, 0(a1)
1972 ; RV32IZFH-NEXT: ret
1973 ;
1974 ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
1975 ; RV64IZFH: # %bb.0:
1976 ; RV64IZFH-NEXT: addiw a0, a0, 1
1977 ; RV64IZFH-NEXT: fcvt.h.w fa5, a0
1978 ; RV64IZFH-NEXT: fsh fa5, 0(a1)
1979 ; RV64IZFH-NEXT: ret
1980 ;
1981 ; RV32IZHINX-LABEL: fcvt_h_w_demanded_bits:
1982 ; RV32IZHINX: # %bb.0:
1983 ; RV32IZHINX-NEXT: addi a0, a0, 1
1984 ; RV32IZHINX-NEXT: fcvt.h.w a2, a0
1985 ; RV32IZHINX-NEXT: sh a2, 0(a1)
1986 ; RV32IZHINX-NEXT: ret
1987 ;
1988 ; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
1989 ; RV64IZHINX: # %bb.0:
1990 ; RV64IZHINX-NEXT: addiw a2, a0, 1
1991 ; RV64IZHINX-NEXT: addi a0, a0, 1
1992 ; RV64IZHINX-NEXT: fcvt.h.w a0, a0
1993 ; RV64IZHINX-NEXT: sh a0, 0(a1)
1994 ; RV64IZHINX-NEXT: mv a0, a2
1995 ; RV64IZHINX-NEXT: ret
1996 ;
1997 ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
1998 ; RV32IDZFH: # %bb.0:
1999 ; RV32IDZFH-NEXT: addi a0, a0, 1
2000 ; RV32IDZFH-NEXT: fcvt.h.w fa5, a0
2001 ; RV32IDZFH-NEXT: fsh fa5, 0(a1)
2002 ; RV32IDZFH-NEXT: ret
2003 ;
2004 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
2005 ; RV64IDZFH: # %bb.0:
2006 ; RV64IDZFH-NEXT: addiw a0, a0, 1
2007 ; RV64IDZFH-NEXT: fcvt.h.w fa5, a0
2008 ; RV64IDZFH-NEXT: fsh fa5, 0(a1)
2009 ; RV64IDZFH-NEXT: ret
2010 ;
2011 ; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
2012 ; RV32IZDINXZHINX: # %bb.0:
2013 ; RV32IZDINXZHINX-NEXT: addi a0, a0, 1
2014 ; RV32IZDINXZHINX-NEXT: fcvt.h.w a2, a0
2015 ; RV32IZDINXZHINX-NEXT: sh a2, 0(a1)
2016 ; RV32IZDINXZHINX-NEXT: ret
2017 ;
2018 ; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
2019 ; RV64IZDINXZHINX: # %bb.0:
2020 ; RV64IZDINXZHINX-NEXT: addiw a2, a0, 1
2021 ; RV64IZDINXZHINX-NEXT: addi a0, a0, 1
2022 ; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
2023 ; RV64IZDINXZHINX-NEXT: sh a0, 0(a1)
2024 ; RV64IZDINXZHINX-NEXT: mv a0, a2
2025 ; RV64IZDINXZHINX-NEXT: ret
2026 ;
2027 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
2028 ; CHECK32-IZFHMIN: # %bb.0:
2029 ; CHECK32-IZFHMIN-NEXT: addi a0, a0, 1
2030 ; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
2031 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2032 ; CHECK32-IZFHMIN-NEXT: fsh fa5, 0(a1)
2033 ; CHECK32-IZFHMIN-NEXT: ret
2034 ;
2035 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
2036 ; CHECK64-IZFHMIN: # %bb.0:
2037 ; CHECK64-IZFHMIN-NEXT: addiw a0, a0, 1
2038 ; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a0
2039 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2040 ; CHECK64-IZFHMIN-NEXT: fsh fa5, 0(a1)
2041 ; CHECK64-IZFHMIN-NEXT: ret
2042 ;
2043 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
2044 ; CHECK32-IZHINXMIN: # %bb.0:
2045 ; CHECK32-IZHINXMIN-NEXT: addi a0, a0, 1
2046 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a2, a0
2047 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a2, a2
2048 ; CHECK32-IZHINXMIN-NEXT: sh a2, 0(a1)
2049 ; CHECK32-IZHINXMIN-NEXT: ret
2050 ;
2051 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
2052 ; CHECK64-IZHINXMIN: # %bb.0:
2053 ; CHECK64-IZHINXMIN-NEXT: addiw a0, a0, 1
2054 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a2, a0
2055 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a2, a2
2056 ; CHECK64-IZHINXMIN-NEXT: sh a2, 0(a1)
2057 ; CHECK64-IZHINXMIN-NEXT: ret
2058 ;
2059 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
2060 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
2061 ; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, a0, 1
2062 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a2, a0
2063 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2
2064 ; CHECK32-IZDINXZHINXMIN-NEXT: sh a2, 0(a1)
2065 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
2066 ;
2067 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
2068 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
2069 ; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, 1
2070 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a2, a0
2071 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2
2072 ; CHECK64-IZDINXZHINXMIN-NEXT: sh a2, 0(a1)
2073 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
2074 %3 = add i32 %0, 1
2075 %4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")
2076 store half %4, ptr %1, align 2
2077 ret i32 %3
2078 }
2080 ; Make sure we select W version of addi on RV64.
2081 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp {
2082 ; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
2083 ; RV32IZFH: # %bb.0:
2084 ; RV32IZFH-NEXT: addi a0, a0, 1
2085 ; RV32IZFH-NEXT: fcvt.h.wu fa5, a0
2086 ; RV32IZFH-NEXT: fsh fa5, 0(a1)
2087 ; RV32IZFH-NEXT: ret
2088 ;
2089 ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
2090 ; RV64IZFH: # %bb.0:
2091 ; RV64IZFH-NEXT: addiw a0, a0, 1
2092 ; RV64IZFH-NEXT: fcvt.h.wu fa5, a0
2093 ; RV64IZFH-NEXT: fsh fa5, 0(a1)
2094 ; RV64IZFH-NEXT: ret
2095 ;
2096 ; RV32IZHINX-LABEL: fcvt_h_wu_demanded_bits:
2097 ; RV32IZHINX: # %bb.0:
2098 ; RV32IZHINX-NEXT: addi a0, a0, 1
2099 ; RV32IZHINX-NEXT: fcvt.h.wu a2, a0
2100 ; RV32IZHINX-NEXT: sh a2, 0(a1)
2101 ; RV32IZHINX-NEXT: ret
2102 ;
2103 ; RV64IZHINX-LABEL: fcvt_h_wu_demanded_bits:
2104 ; RV64IZHINX: # %bb.0:
2105 ; RV64IZHINX-NEXT: addiw a0, a0, 1
2106 ; RV64IZHINX-NEXT: fcvt.h.wu a2, a0
2107 ; RV64IZHINX-NEXT: sh a2, 0(a1)
2108 ; RV64IZHINX-NEXT: ret
2109 ;
2110 ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
2111 ; RV32IDZFH: # %bb.0:
2112 ; RV32IDZFH-NEXT: addi a0, a0, 1
2113 ; RV32IDZFH-NEXT: fcvt.h.wu fa5, a0
2114 ; RV32IDZFH-NEXT: fsh fa5, 0(a1)
2115 ; RV32IDZFH-NEXT: ret
2116 ;
2117 ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
2118 ; RV64IDZFH: # %bb.0:
2119 ; RV64IDZFH-NEXT: addiw a0, a0, 1
2120 ; RV64IDZFH-NEXT: fcvt.h.wu fa5, a0
2121 ; RV64IDZFH-NEXT: fsh fa5, 0(a1)
2122 ; RV64IDZFH-NEXT: ret
2123 ;
2124 ; RV32IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
2125 ; RV32IZDINXZHINX: # %bb.0:
2126 ; RV32IZDINXZHINX-NEXT: addi a0, a0, 1
2127 ; RV32IZDINXZHINX-NEXT: fcvt.h.wu a2, a0
2128 ; RV32IZDINXZHINX-NEXT: sh a2, 0(a1)
2129 ; RV32IZDINXZHINX-NEXT: ret
2130 ;
2131 ; RV64IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
2132 ; RV64IZDINXZHINX: # %bb.0:
2133 ; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1
2134 ; RV64IZDINXZHINX-NEXT: fcvt.h.wu a2, a0
2135 ; RV64IZDINXZHINX-NEXT: sh a2, 0(a1)
2136 ; RV64IZDINXZHINX-NEXT: ret
2137 ;
2138 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
2139 ; CHECK32-IZFHMIN: # %bb.0:
2140 ; CHECK32-IZFHMIN-NEXT: addi a0, a0, 1
2141 ; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0
2142 ; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2143 ; CHECK32-IZFHMIN-NEXT: fsh fa5, 0(a1)
2144 ; CHECK32-IZFHMIN-NEXT: ret
2145 ;
2146 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
2147 ; CHECK64-IZFHMIN: # %bb.0:
2148 ; CHECK64-IZFHMIN-NEXT: addiw a0, a0, 1
2149 ; CHECK64-IZFHMIN-NEXT: slli a2, a0, 32
2150 ; CHECK64-IZFHMIN-NEXT: srli a2, a2, 32
2151 ; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a2
2152 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2153 ; CHECK64-IZFHMIN-NEXT: fsh fa5, 0(a1)
2154 ; CHECK64-IZFHMIN-NEXT: ret
2155 ;
2156 ; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
2157 ; CHECK32-IZHINXMIN: # %bb.0:
2158 ; CHECK32-IZHINXMIN-NEXT: addi a0, a0, 1
2159 ; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a2, a0
2160 ; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a2, a2
2161 ; CHECK32-IZHINXMIN-NEXT: sh a2, 0(a1)
2162 ; CHECK32-IZHINXMIN-NEXT: ret
2163 ;
2164 ; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
2165 ; CHECK64-IZHINXMIN: # %bb.0:
2166 ; CHECK64-IZHINXMIN-NEXT: addiw a0, a0, 1
2167 ; CHECK64-IZHINXMIN-NEXT: slli a2, a0, 32
2168 ; CHECK64-IZHINXMIN-NEXT: srli a2, a2, 32
2169 ; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a2, a2
2170 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a2, a2
2171 ; CHECK64-IZHINXMIN-NEXT: sh a2, 0(a1)
2172 ; CHECK64-IZHINXMIN-NEXT: ret
2173 ;
2174 ; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
2175 ; CHECK32-IZDINXZHINXMIN: # %bb.0:
2176 ; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, a0, 1
2177 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a2, a0
2178 ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2
2179 ; CHECK32-IZDINXZHINXMIN-NEXT: sh a2, 0(a1)
2180 ; CHECK32-IZDINXZHINXMIN-NEXT: ret
2181 ;
2182 ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
2183 ; CHECK64-IZDINXZHINXMIN: # %bb.0:
2184 ; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, 1
2185 ; CHECK64-IZDINXZHINXMIN-NEXT: slli a2, a0, 32
2186 ; CHECK64-IZDINXZHINXMIN-NEXT: srli a2, a2, 32
2187 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a2, a2
2188 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2
2189 ; CHECK64-IZDINXZHINXMIN-NEXT: sh a2, 0(a1)
2190 ; CHECK64-IZDINXZHINXMIN-NEXT: ret
2191 %3 = add i32 %0, 1
2192 %4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")
2193 store half %4, ptr %1, align 2
2194 ret i32 %3
2195 }