| blob | c493a9b2cb1dfbcba064f4418b10625097657b18 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
3 ; RUN: -verify-machineinstrs -target-abi ilp32f | \
4 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IFZFH %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
6 ; RUN: -verify-machineinstrs -target-abi lp64f | \
7 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IFZFH %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinx \
9 ; RUN: -verify-machineinstrs -target-abi ilp32 | \
10 ; RUN: FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinx \
12 ; RUN: -verify-machineinstrs -target-abi lp64 | \
13 ; RUN: FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
15 ; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
16 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IDZFH %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
18 ; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
19 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IDZFH %s
20 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
21 ; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \
22 ; RUN: FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
23 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
24 ; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
25 ; RUN: FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
26 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
27 ; RUN: -verify-machineinstrs | \
28 ; RUN: FileCheck -check-prefix=RV32I %s
29 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
30 ; RUN: -verify-machineinstrs | \
31 ; RUN: FileCheck -check-prefix=RV64I %s
33 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
34 ; RUN: -verify-machineinstrs -target-abi ilp32f | \
35 ; RUN: FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IFZFHMIN %s
36 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
37 ; RUN: -verify-machineinstrs -target-abi lp64f | \
38 ; RUN: FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IFZFHMIN %s
39 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
40 ; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
41 ; RUN: FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IDZFHMIN %s
42 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
43 ; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
44 ; RUN: FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IDZFHMIN %s
46 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
47 ; RUN: -verify-machineinstrs -target-abi ilp32 | \
48 ; RUN: FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
49 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
50 ; RUN: -verify-machineinstrs -target-abi lp64 | \
51 ; RUN: FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
52 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
53 ; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
54 ; RUN: FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
55 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
56 ; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
57 ; RUN: FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
59 declare half @llvm.sqrt.f16(half)
61 define half @sqrt_f16(half %a) nounwind {
62 ; CHECKIZFH-LABEL: sqrt_f16:
63 ; CHECKIZFH: # %bb.0:
64 ; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
65 ; CHECKIZFH-NEXT: ret
66 ;
67 ; CHECKIZHINX-LABEL: sqrt_f16:
68 ; CHECKIZHINX: # %bb.0:
69 ; CHECKIZHINX-NEXT: fsqrt.h a0, a0
70 ; CHECKIZHINX-NEXT: ret
71 ;
72 ; RV32I-LABEL: sqrt_f16:
73 ; RV32I: # %bb.0:
74 ; RV32I-NEXT: addi sp, sp, -16
75 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
76 ; RV32I-NEXT: slli a0, a0, 16
77 ; RV32I-NEXT: srli a0, a0, 16
78 ; RV32I-NEXT: call __extendhfsf2
79 ; RV32I-NEXT: call sqrtf
80 ; RV32I-NEXT: call __truncsfhf2
81 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
82 ; RV32I-NEXT: addi sp, sp, 16
83 ; RV32I-NEXT: ret
84 ;
85 ; RV64I-LABEL: sqrt_f16:
86 ; RV64I: # %bb.0:
87 ; RV64I-NEXT: addi sp, sp, -16
88 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
89 ; RV64I-NEXT: slli a0, a0, 48
90 ; RV64I-NEXT: srli a0, a0, 48
91 ; RV64I-NEXT: call __extendhfsf2
92 ; RV64I-NEXT: call sqrtf
93 ; RV64I-NEXT: call __truncsfhf2
94 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
95 ; RV64I-NEXT: addi sp, sp, 16
96 ; RV64I-NEXT: ret
97 ;
98 ; CHECKIZFHMIN-LABEL: sqrt_f16:
99 ; CHECKIZFHMIN: # %bb.0:
100 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
101 ; CHECKIZFHMIN-NEXT: fsqrt.s fa5, fa5
102 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
103 ; CHECKIZFHMIN-NEXT: ret
104 ;
105 ; CHECKIZHINXMIN-LABEL: sqrt_f16:
106 ; CHECKIZHINXMIN: # %bb.0:
107 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
108 ; CHECKIZHINXMIN-NEXT: fsqrt.s a0, a0
109 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
110 ; CHECKIZHINXMIN-NEXT: ret
111 %1 = call half @llvm.sqrt.f16(half %a)
112 ret half %1
113 }
115 declare half @llvm.powi.f16.i32(half, i32)
117 define half @powi_f16(half %a, i32 %b) nounwind {
118 ; RV32IZFH-LABEL: powi_f16:
119 ; RV32IZFH: # %bb.0:
120 ; RV32IZFH-NEXT: addi sp, sp, -16
121 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
122 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
123 ; RV32IZFH-NEXT: call __powisf2
124 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
125 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
126 ; RV32IZFH-NEXT: addi sp, sp, 16
127 ; RV32IZFH-NEXT: ret
128 ;
129 ; RV64IZFH-LABEL: powi_f16:
130 ; RV64IZFH: # %bb.0:
131 ; RV64IZFH-NEXT: addi sp, sp, -16
132 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
133 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
134 ; RV64IZFH-NEXT: sext.w a0, a0
135 ; RV64IZFH-NEXT: call __powisf2
136 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
137 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
138 ; RV64IZFH-NEXT: addi sp, sp, 16
139 ; RV64IZFH-NEXT: ret
140 ;
141 ; RV32IZHINX-LABEL: powi_f16:
142 ; RV32IZHINX: # %bb.0:
143 ; RV32IZHINX-NEXT: addi sp, sp, -16
144 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
145 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
146 ; RV32IZHINX-NEXT: call __powisf2
147 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
148 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
149 ; RV32IZHINX-NEXT: addi sp, sp, 16
150 ; RV32IZHINX-NEXT: ret
151 ;
152 ; RV64IZHINX-LABEL: powi_f16:
153 ; RV64IZHINX: # %bb.0:
154 ; RV64IZHINX-NEXT: addi sp, sp, -16
155 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
156 ; RV64IZHINX-NEXT: sext.w a1, a1
157 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
158 ; RV64IZHINX-NEXT: call __powisf2
159 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
160 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
161 ; RV64IZHINX-NEXT: addi sp, sp, 16
162 ; RV64IZHINX-NEXT: ret
163 ;
164 ; RV32I-LABEL: powi_f16:
165 ; RV32I: # %bb.0:
166 ; RV32I-NEXT: addi sp, sp, -16
167 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
168 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
169 ; RV32I-NEXT: mv s0, a1
170 ; RV32I-NEXT: slli a0, a0, 16
171 ; RV32I-NEXT: srli a0, a0, 16
172 ; RV32I-NEXT: call __extendhfsf2
173 ; RV32I-NEXT: mv a1, s0
174 ; RV32I-NEXT: call __powisf2
175 ; RV32I-NEXT: call __truncsfhf2
176 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
177 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
178 ; RV32I-NEXT: addi sp, sp, 16
179 ; RV32I-NEXT: ret
180 ;
181 ; RV64I-LABEL: powi_f16:
182 ; RV64I: # %bb.0:
183 ; RV64I-NEXT: addi sp, sp, -16
184 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
185 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
186 ; RV64I-NEXT: mv s0, a1
187 ; RV64I-NEXT: slli a0, a0, 48
188 ; RV64I-NEXT: srli a0, a0, 48
189 ; RV64I-NEXT: call __extendhfsf2
190 ; RV64I-NEXT: sext.w a1, s0
191 ; RV64I-NEXT: call __powisf2
192 ; RV64I-NEXT: call __truncsfhf2
193 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
194 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
195 ; RV64I-NEXT: addi sp, sp, 16
196 ; RV64I-NEXT: ret
197 ;
198 ; RV32IZFHMIN-LABEL: powi_f16:
199 ; RV32IZFHMIN: # %bb.0:
200 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
201 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
202 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
203 ; RV32IZFHMIN-NEXT: call __powisf2
204 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
205 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
206 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
207 ; RV32IZFHMIN-NEXT: ret
208 ;
209 ; RV64IZFHMIN-LABEL: powi_f16:
210 ; RV64IZFHMIN: # %bb.0:
211 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
212 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
213 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
214 ; RV64IZFHMIN-NEXT: sext.w a0, a0
215 ; RV64IZFHMIN-NEXT: call __powisf2
216 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
217 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
218 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
219 ; RV64IZFHMIN-NEXT: ret
220 ;
221 ; RV32IZHINXMIN-LABEL: powi_f16:
222 ; RV32IZHINXMIN: # %bb.0:
223 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
224 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
225 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
226 ; RV32IZHINXMIN-NEXT: call __powisf2
227 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
228 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
229 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
230 ; RV32IZHINXMIN-NEXT: ret
231 ;
232 ; RV64IZHINXMIN-LABEL: powi_f16:
233 ; RV64IZHINXMIN: # %bb.0:
234 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
235 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
236 ; RV64IZHINXMIN-NEXT: sext.w a1, a1
237 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
238 ; RV64IZHINXMIN-NEXT: call __powisf2
239 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
240 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
241 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
242 ; RV64IZHINXMIN-NEXT: ret
243 %1 = call half @llvm.powi.f16.i32(half %a, i32 %b)
244 ret half %1
245 }
247 declare half @llvm.sin.f16(half)
249 define half @sin_f16(half %a) nounwind {
250 ; RV32IZFH-LABEL: sin_f16:
251 ; RV32IZFH: # %bb.0:
252 ; RV32IZFH-NEXT: addi sp, sp, -16
253 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
254 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
255 ; RV32IZFH-NEXT: call sinf
256 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
257 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
258 ; RV32IZFH-NEXT: addi sp, sp, 16
259 ; RV32IZFH-NEXT: ret
260 ;
261 ; RV64IZFH-LABEL: sin_f16:
262 ; RV64IZFH: # %bb.0:
263 ; RV64IZFH-NEXT: addi sp, sp, -16
264 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
265 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
266 ; RV64IZFH-NEXT: call sinf
267 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
268 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
269 ; RV64IZFH-NEXT: addi sp, sp, 16
270 ; RV64IZFH-NEXT: ret
271 ;
272 ; RV32IZHINX-LABEL: sin_f16:
273 ; RV32IZHINX: # %bb.0:
274 ; RV32IZHINX-NEXT: addi sp, sp, -16
275 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
276 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
277 ; RV32IZHINX-NEXT: call sinf
278 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
279 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
280 ; RV32IZHINX-NEXT: addi sp, sp, 16
281 ; RV32IZHINX-NEXT: ret
282 ;
283 ; RV64IZHINX-LABEL: sin_f16:
284 ; RV64IZHINX: # %bb.0:
285 ; RV64IZHINX-NEXT: addi sp, sp, -16
286 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
287 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
288 ; RV64IZHINX-NEXT: call sinf
289 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
290 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
291 ; RV64IZHINX-NEXT: addi sp, sp, 16
292 ; RV64IZHINX-NEXT: ret
293 ;
294 ; RV32I-LABEL: sin_f16:
295 ; RV32I: # %bb.0:
296 ; RV32I-NEXT: addi sp, sp, -16
297 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
298 ; RV32I-NEXT: slli a0, a0, 16
299 ; RV32I-NEXT: srli a0, a0, 16
300 ; RV32I-NEXT: call __extendhfsf2
301 ; RV32I-NEXT: call sinf
302 ; RV32I-NEXT: call __truncsfhf2
303 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
304 ; RV32I-NEXT: addi sp, sp, 16
305 ; RV32I-NEXT: ret
306 ;
307 ; RV64I-LABEL: sin_f16:
308 ; RV64I: # %bb.0:
309 ; RV64I-NEXT: addi sp, sp, -16
310 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
311 ; RV64I-NEXT: slli a0, a0, 48
312 ; RV64I-NEXT: srli a0, a0, 48
313 ; RV64I-NEXT: call __extendhfsf2
314 ; RV64I-NEXT: call sinf
315 ; RV64I-NEXT: call __truncsfhf2
316 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
317 ; RV64I-NEXT: addi sp, sp, 16
318 ; RV64I-NEXT: ret
319 ;
320 ; RV32IZFHMIN-LABEL: sin_f16:
321 ; RV32IZFHMIN: # %bb.0:
322 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
323 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
324 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
325 ; RV32IZFHMIN-NEXT: call sinf
326 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
327 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
328 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
329 ; RV32IZFHMIN-NEXT: ret
330 ;
331 ; RV64IZFHMIN-LABEL: sin_f16:
332 ; RV64IZFHMIN: # %bb.0:
333 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
334 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
335 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
336 ; RV64IZFHMIN-NEXT: call sinf
337 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
338 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
339 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
340 ; RV64IZFHMIN-NEXT: ret
341 ;
342 ; RV32IZHINXMIN-LABEL: sin_f16:
343 ; RV32IZHINXMIN: # %bb.0:
344 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
345 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
346 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
347 ; RV32IZHINXMIN-NEXT: call sinf
348 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
349 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
350 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
351 ; RV32IZHINXMIN-NEXT: ret
352 ;
353 ; RV64IZHINXMIN-LABEL: sin_f16:
354 ; RV64IZHINXMIN: # %bb.0:
355 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
356 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
357 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
358 ; RV64IZHINXMIN-NEXT: call sinf
359 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
360 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
361 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
362 ; RV64IZHINXMIN-NEXT: ret
363 %1 = call half @llvm.sin.f16(half %a)
364 ret half %1
365 }
367 declare half @llvm.cos.f16(half)
369 define half @cos_f16(half %a) nounwind {
370 ; RV32IZFH-LABEL: cos_f16:
371 ; RV32IZFH: # %bb.0:
372 ; RV32IZFH-NEXT: addi sp, sp, -16
373 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
374 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
375 ; RV32IZFH-NEXT: call cosf
376 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
377 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
378 ; RV32IZFH-NEXT: addi sp, sp, 16
379 ; RV32IZFH-NEXT: ret
380 ;
381 ; RV64IZFH-LABEL: cos_f16:
382 ; RV64IZFH: # %bb.0:
383 ; RV64IZFH-NEXT: addi sp, sp, -16
384 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
385 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
386 ; RV64IZFH-NEXT: call cosf
387 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
388 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
389 ; RV64IZFH-NEXT: addi sp, sp, 16
390 ; RV64IZFH-NEXT: ret
391 ;
392 ; RV32IZHINX-LABEL: cos_f16:
393 ; RV32IZHINX: # %bb.0:
394 ; RV32IZHINX-NEXT: addi sp, sp, -16
395 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
396 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
397 ; RV32IZHINX-NEXT: call cosf
398 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
399 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
400 ; RV32IZHINX-NEXT: addi sp, sp, 16
401 ; RV32IZHINX-NEXT: ret
402 ;
403 ; RV64IZHINX-LABEL: cos_f16:
404 ; RV64IZHINX: # %bb.0:
405 ; RV64IZHINX-NEXT: addi sp, sp, -16
406 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
407 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
408 ; RV64IZHINX-NEXT: call cosf
409 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
410 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
411 ; RV64IZHINX-NEXT: addi sp, sp, 16
412 ; RV64IZHINX-NEXT: ret
413 ;
414 ; RV32I-LABEL: cos_f16:
415 ; RV32I: # %bb.0:
416 ; RV32I-NEXT: addi sp, sp, -16
417 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
418 ; RV32I-NEXT: slli a0, a0, 16
419 ; RV32I-NEXT: srli a0, a0, 16
420 ; RV32I-NEXT: call __extendhfsf2
421 ; RV32I-NEXT: call cosf
422 ; RV32I-NEXT: call __truncsfhf2
423 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
424 ; RV32I-NEXT: addi sp, sp, 16
425 ; RV32I-NEXT: ret
426 ;
427 ; RV64I-LABEL: cos_f16:
428 ; RV64I: # %bb.0:
429 ; RV64I-NEXT: addi sp, sp, -16
430 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
431 ; RV64I-NEXT: slli a0, a0, 48
432 ; RV64I-NEXT: srli a0, a0, 48
433 ; RV64I-NEXT: call __extendhfsf2
434 ; RV64I-NEXT: call cosf
435 ; RV64I-NEXT: call __truncsfhf2
436 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
437 ; RV64I-NEXT: addi sp, sp, 16
438 ; RV64I-NEXT: ret
439 ;
440 ; RV32IZFHMIN-LABEL: cos_f16:
441 ; RV32IZFHMIN: # %bb.0:
442 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
443 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
444 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
445 ; RV32IZFHMIN-NEXT: call cosf
446 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
447 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
448 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
449 ; RV32IZFHMIN-NEXT: ret
450 ;
451 ; RV64IZFHMIN-LABEL: cos_f16:
452 ; RV64IZFHMIN: # %bb.0:
453 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
454 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
455 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
456 ; RV64IZFHMIN-NEXT: call cosf
457 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
458 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
459 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
460 ; RV64IZFHMIN-NEXT: ret
461 ;
462 ; RV32IZHINXMIN-LABEL: cos_f16:
463 ; RV32IZHINXMIN: # %bb.0:
464 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
465 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
466 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
467 ; RV32IZHINXMIN-NEXT: call cosf
468 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
469 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
470 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
471 ; RV32IZHINXMIN-NEXT: ret
472 ;
473 ; RV64IZHINXMIN-LABEL: cos_f16:
474 ; RV64IZHINXMIN: # %bb.0:
475 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
476 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
477 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
478 ; RV64IZHINXMIN-NEXT: call cosf
479 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
480 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
481 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
482 ; RV64IZHINXMIN-NEXT: ret
483 %1 = call half @llvm.cos.f16(half %a)
484 ret half %1
485 }
487 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
488 define half @sincos_f16(half %a) nounwind {
489 ; RV32IFZFH-LABEL: sincos_f16:
490 ; RV32IFZFH: # %bb.0:
491 ; RV32IFZFH-NEXT: addi sp, sp, -16
492 ; RV32IFZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
493 ; RV32IFZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
494 ; RV32IFZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
495 ; RV32IFZFH-NEXT: fcvt.s.h fs0, fa0
496 ; RV32IFZFH-NEXT: fmv.s fa0, fs0
497 ; RV32IFZFH-NEXT: call sinf
498 ; RV32IFZFH-NEXT: fcvt.h.s fs1, fa0
499 ; RV32IFZFH-NEXT: fmv.s fa0, fs0
500 ; RV32IFZFH-NEXT: call cosf
501 ; RV32IFZFH-NEXT: fcvt.h.s fa5, fa0
502 ; RV32IFZFH-NEXT: fadd.h fa0, fs1, fa5
503 ; RV32IFZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
504 ; RV32IFZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
505 ; RV32IFZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
506 ; RV32IFZFH-NEXT: addi sp, sp, 16
507 ; RV32IFZFH-NEXT: ret
508 ;
509 ; RV64IFZFH-LABEL: sincos_f16:
510 ; RV64IFZFH: # %bb.0:
511 ; RV64IFZFH-NEXT: addi sp, sp, -16
512 ; RV64IFZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
513 ; RV64IFZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
514 ; RV64IFZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
515 ; RV64IFZFH-NEXT: fcvt.s.h fs0, fa0
516 ; RV64IFZFH-NEXT: fmv.s fa0, fs0
517 ; RV64IFZFH-NEXT: call sinf
518 ; RV64IFZFH-NEXT: fcvt.h.s fs1, fa0
519 ; RV64IFZFH-NEXT: fmv.s fa0, fs0
520 ; RV64IFZFH-NEXT: call cosf
521 ; RV64IFZFH-NEXT: fcvt.h.s fa5, fa0
522 ; RV64IFZFH-NEXT: fadd.h fa0, fs1, fa5
523 ; RV64IFZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
524 ; RV64IFZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
525 ; RV64IFZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
526 ; RV64IFZFH-NEXT: addi sp, sp, 16
527 ; RV64IFZFH-NEXT: ret
528 ;
529 ; RV32IZHINX-LABEL: sincos_f16:
530 ; RV32IZHINX: # %bb.0:
531 ; RV32IZHINX-NEXT: addi sp, sp, -16
532 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
533 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
534 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
535 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
536 ; RV32IZHINX-NEXT: mv a0, s0
537 ; RV32IZHINX-NEXT: call sinf
538 ; RV32IZHINX-NEXT: fcvt.h.s s1, a0
539 ; RV32IZHINX-NEXT: mv a0, s0
540 ; RV32IZHINX-NEXT: call cosf
541 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
542 ; RV32IZHINX-NEXT: fadd.h a0, s1, a0
543 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
544 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
545 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
546 ; RV32IZHINX-NEXT: addi sp, sp, 16
547 ; RV32IZHINX-NEXT: ret
548 ;
549 ; RV64IZHINX-LABEL: sincos_f16:
550 ; RV64IZHINX: # %bb.0:
551 ; RV64IZHINX-NEXT: addi sp, sp, -32
552 ; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
553 ; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
554 ; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
555 ; RV64IZHINX-NEXT: fcvt.s.h s0, a0
556 ; RV64IZHINX-NEXT: mv a0, s0
557 ; RV64IZHINX-NEXT: call sinf
558 ; RV64IZHINX-NEXT: fcvt.h.s s1, a0
559 ; RV64IZHINX-NEXT: mv a0, s0
560 ; RV64IZHINX-NEXT: call cosf
561 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
562 ; RV64IZHINX-NEXT: fadd.h a0, s1, a0
563 ; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
564 ; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
565 ; RV64IZHINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
566 ; RV64IZHINX-NEXT: addi sp, sp, 32
567 ; RV64IZHINX-NEXT: ret
568 ;
569 ; RV32IDZFH-LABEL: sincos_f16:
570 ; RV32IDZFH: # %bb.0:
571 ; RV32IDZFH-NEXT: addi sp, sp, -32
572 ; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
573 ; RV32IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
574 ; RV32IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
575 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
576 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
577 ; RV32IDZFH-NEXT: call sinf
578 ; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0
579 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
580 ; RV32IDZFH-NEXT: call cosf
581 ; RV32IDZFH-NEXT: fcvt.h.s fa5, fa0
582 ; RV32IDZFH-NEXT: fadd.h fa0, fs1, fa5
583 ; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
584 ; RV32IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
585 ; RV32IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
586 ; RV32IDZFH-NEXT: addi sp, sp, 32
587 ; RV32IDZFH-NEXT: ret
588 ;
589 ; RV64IDZFH-LABEL: sincos_f16:
590 ; RV64IDZFH: # %bb.0:
591 ; RV64IDZFH-NEXT: addi sp, sp, -32
592 ; RV64IDZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
593 ; RV64IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
594 ; RV64IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
595 ; RV64IDZFH-NEXT: fcvt.s.h fs0, fa0
596 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
597 ; RV64IDZFH-NEXT: call sinf
598 ; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0
599 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
600 ; RV64IDZFH-NEXT: call cosf
601 ; RV64IDZFH-NEXT: fcvt.h.s fa5, fa0
602 ; RV64IDZFH-NEXT: fadd.h fa0, fs1, fa5
603 ; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
604 ; RV64IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
605 ; RV64IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
606 ; RV64IDZFH-NEXT: addi sp, sp, 32
607 ; RV64IDZFH-NEXT: ret
608 ;
609 ; RV32I-LABEL: sincos_f16:
610 ; RV32I: # %bb.0:
611 ; RV32I-NEXT: addi sp, sp, -16
612 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
613 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
614 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
615 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
616 ; RV32I-NEXT: lui a1, 16
617 ; RV32I-NEXT: addi s2, a1, -1
618 ; RV32I-NEXT: and a0, a0, s2
619 ; RV32I-NEXT: call __extendhfsf2
620 ; RV32I-NEXT: mv s0, a0
621 ; RV32I-NEXT: call sinf
622 ; RV32I-NEXT: call __truncsfhf2
623 ; RV32I-NEXT: mv s1, a0
624 ; RV32I-NEXT: mv a0, s0
625 ; RV32I-NEXT: call cosf
626 ; RV32I-NEXT: call __truncsfhf2
627 ; RV32I-NEXT: mv s0, a0
628 ; RV32I-NEXT: and a0, s1, s2
629 ; RV32I-NEXT: call __extendhfsf2
630 ; RV32I-NEXT: mv s1, a0
631 ; RV32I-NEXT: and a0, s0, s2
632 ; RV32I-NEXT: call __extendhfsf2
633 ; RV32I-NEXT: mv a1, a0
634 ; RV32I-NEXT: mv a0, s1
635 ; RV32I-NEXT: call __addsf3
636 ; RV32I-NEXT: call __truncsfhf2
637 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
638 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
639 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
640 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
641 ; RV32I-NEXT: addi sp, sp, 16
642 ; RV32I-NEXT: ret
643 ;
644 ; RV64I-LABEL: sincos_f16:
645 ; RV64I: # %bb.0:
646 ; RV64I-NEXT: addi sp, sp, -32
647 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
648 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
649 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
650 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
651 ; RV64I-NEXT: lui a1, 16
652 ; RV64I-NEXT: addiw s2, a1, -1
653 ; RV64I-NEXT: and a0, a0, s2
654 ; RV64I-NEXT: call __extendhfsf2
655 ; RV64I-NEXT: mv s0, a0
656 ; RV64I-NEXT: call sinf
657 ; RV64I-NEXT: call __truncsfhf2
658 ; RV64I-NEXT: mv s1, a0
659 ; RV64I-NEXT: mv a0, s0
660 ; RV64I-NEXT: call cosf
661 ; RV64I-NEXT: call __truncsfhf2
662 ; RV64I-NEXT: mv s0, a0
663 ; RV64I-NEXT: and a0, s1, s2
664 ; RV64I-NEXT: call __extendhfsf2
665 ; RV64I-NEXT: mv s1, a0
666 ; RV64I-NEXT: and a0, s0, s2
667 ; RV64I-NEXT: call __extendhfsf2
668 ; RV64I-NEXT: mv a1, a0
669 ; RV64I-NEXT: mv a0, s1
670 ; RV64I-NEXT: call __addsf3
671 ; RV64I-NEXT: call __truncsfhf2
672 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
673 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
674 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
675 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
676 ; RV64I-NEXT: addi sp, sp, 32
677 ; RV64I-NEXT: ret
678 ;
679 ; RV32IFZFHMIN-LABEL: sincos_f16:
680 ; RV32IFZFHMIN: # %bb.0:
681 ; RV32IFZFHMIN-NEXT: addi sp, sp, -16
682 ; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
683 ; RV32IFZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
684 ; RV32IFZFHMIN-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
685 ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0
686 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0
687 ; RV32IFZFHMIN-NEXT: call sinf
688 ; RV32IFZFHMIN-NEXT: fcvt.h.s fs1, fa0
689 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0
690 ; RV32IFZFHMIN-NEXT: call cosf
691 ; RV32IFZFHMIN-NEXT: fcvt.h.s fa5, fa0
692 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa5, fa5
693 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa4, fs1
694 ; RV32IFZFHMIN-NEXT: fadd.s fa5, fa4, fa5
695 ; RV32IFZFHMIN-NEXT: fcvt.h.s fa0, fa5
696 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
697 ; RV32IFZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
698 ; RV32IFZFHMIN-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
699 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
700 ; RV32IFZFHMIN-NEXT: ret
701 ;
702 ; RV64IFZFHMIN-LABEL: sincos_f16:
703 ; RV64IFZFHMIN: # %bb.0:
704 ; RV64IFZFHMIN-NEXT: addi sp, sp, -16
705 ; RV64IFZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
706 ; RV64IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
707 ; RV64IFZFHMIN-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
708 ; RV64IFZFHMIN-NEXT: fcvt.s.h fs0, fa0
709 ; RV64IFZFHMIN-NEXT: fmv.s fa0, fs0
710 ; RV64IFZFHMIN-NEXT: call sinf
711 ; RV64IFZFHMIN-NEXT: fcvt.h.s fs1, fa0
712 ; RV64IFZFHMIN-NEXT: fmv.s fa0, fs0
713 ; RV64IFZFHMIN-NEXT: call cosf
714 ; RV64IFZFHMIN-NEXT: fcvt.h.s fa5, fa0
715 ; RV64IFZFHMIN-NEXT: fcvt.s.h fa5, fa5
716 ; RV64IFZFHMIN-NEXT: fcvt.s.h fa4, fs1
717 ; RV64IFZFHMIN-NEXT: fadd.s fa5, fa4, fa5
718 ; RV64IFZFHMIN-NEXT: fcvt.h.s fa0, fa5
719 ; RV64IFZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
720 ; RV64IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
721 ; RV64IFZFHMIN-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
722 ; RV64IFZFHMIN-NEXT: addi sp, sp, 16
723 ; RV64IFZFHMIN-NEXT: ret
724 ;
725 ; RV32IDZFHMIN-LABEL: sincos_f16:
726 ; RV32IDZFHMIN: # %bb.0:
727 ; RV32IDZFHMIN-NEXT: addi sp, sp, -32
728 ; RV32IDZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
729 ; RV32IDZFHMIN-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
730 ; RV32IDZFHMIN-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
731 ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0
732 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0
733 ; RV32IDZFHMIN-NEXT: call sinf
734 ; RV32IDZFHMIN-NEXT: fcvt.h.s fs1, fa0
735 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0
736 ; RV32IDZFHMIN-NEXT: call cosf
737 ; RV32IDZFHMIN-NEXT: fcvt.h.s fa5, fa0
738 ; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa5
739 ; RV32IDZFHMIN-NEXT: fcvt.s.h fa4, fs1
740 ; RV32IDZFHMIN-NEXT: fadd.s fa5, fa4, fa5
741 ; RV32IDZFHMIN-NEXT: fcvt.h.s fa0, fa5
742 ; RV32IDZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
743 ; RV32IDZFHMIN-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
744 ; RV32IDZFHMIN-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
745 ; RV32IDZFHMIN-NEXT: addi sp, sp, 32
746 ; RV32IDZFHMIN-NEXT: ret
747 ;
748 ; RV64IDZFHMIN-LABEL: sincos_f16:
749 ; RV64IDZFHMIN: # %bb.0:
750 ; RV64IDZFHMIN-NEXT: addi sp, sp, -32
751 ; RV64IDZFHMIN-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
752 ; RV64IDZFHMIN-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
753 ; RV64IDZFHMIN-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
754 ; RV64IDZFHMIN-NEXT: fcvt.s.h fs0, fa0
755 ; RV64IDZFHMIN-NEXT: fmv.s fa0, fs0
756 ; RV64IDZFHMIN-NEXT: call sinf
757 ; RV64IDZFHMIN-NEXT: fcvt.h.s fs1, fa0
758 ; RV64IDZFHMIN-NEXT: fmv.s fa0, fs0
759 ; RV64IDZFHMIN-NEXT: call cosf
760 ; RV64IDZFHMIN-NEXT: fcvt.h.s fa5, fa0
761 ; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa5
762 ; RV64IDZFHMIN-NEXT: fcvt.s.h fa4, fs1
763 ; RV64IDZFHMIN-NEXT: fadd.s fa5, fa4, fa5
764 ; RV64IDZFHMIN-NEXT: fcvt.h.s fa0, fa5
765 ; RV64IDZFHMIN-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
766 ; RV64IDZFHMIN-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
767 ; RV64IDZFHMIN-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
768 ; RV64IDZFHMIN-NEXT: addi sp, sp, 32
769 ; RV64IDZFHMIN-NEXT: ret
770 ;
771 ; RV32IZHINXMIN-LABEL: sincos_f16:
772 ; RV32IZHINXMIN: # %bb.0:
773 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
774 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
775 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
776 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
777 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
778 ; RV32IZHINXMIN-NEXT: mv a0, s0
779 ; RV32IZHINXMIN-NEXT: call sinf
780 ; RV32IZHINXMIN-NEXT: fcvt.h.s s1, a0
781 ; RV32IZHINXMIN-NEXT: mv a0, s0
782 ; RV32IZHINXMIN-NEXT: call cosf
783 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
784 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
785 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, s1
786 ; RV32IZHINXMIN-NEXT: fadd.s a0, a1, a0
787 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
788 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
789 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
790 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
791 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
792 ; RV32IZHINXMIN-NEXT: ret
793 ;
794 ; RV64IZHINXMIN-LABEL: sincos_f16:
795 ; RV64IZHINXMIN: # %bb.0:
796 ; RV64IZHINXMIN-NEXT: addi sp, sp, -32
797 ; RV64IZHINXMIN-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
798 ; RV64IZHINXMIN-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
799 ; RV64IZHINXMIN-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
800 ; RV64IZHINXMIN-NEXT: fcvt.s.h s0, a0
801 ; RV64IZHINXMIN-NEXT: mv a0, s0
802 ; RV64IZHINXMIN-NEXT: call sinf
803 ; RV64IZHINXMIN-NEXT: fcvt.h.s s1, a0
804 ; RV64IZHINXMIN-NEXT: mv a0, s0
805 ; RV64IZHINXMIN-NEXT: call cosf
806 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
807 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
808 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, s1
809 ; RV64IZHINXMIN-NEXT: fadd.s a0, a1, a0
810 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
811 ; RV64IZHINXMIN-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
812 ; RV64IZHINXMIN-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
813 ; RV64IZHINXMIN-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
814 ; RV64IZHINXMIN-NEXT: addi sp, sp, 32
815 ; RV64IZHINXMIN-NEXT: ret
816 %1 = call half @llvm.sin.f16(half %a)
817 %2 = call half @llvm.cos.f16(half %a)
818 %3 = fadd half %1, %2
819 ret half %3
820 }
822 declare half @llvm.pow.f16(half, half)
824 define half @pow_f16(half %a, half %b) nounwind {
825 ; RV32IZFH-LABEL: pow_f16:
826 ; RV32IZFH: # %bb.0:
827 ; RV32IZFH-NEXT: addi sp, sp, -16
828 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
829 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
830 ; RV32IZFH-NEXT: fcvt.s.h fa1, fa1
831 ; RV32IZFH-NEXT: call powf
832 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
833 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
834 ; RV32IZFH-NEXT: addi sp, sp, 16
835 ; RV32IZFH-NEXT: ret
836 ;
837 ; RV64IZFH-LABEL: pow_f16:
838 ; RV64IZFH: # %bb.0:
839 ; RV64IZFH-NEXT: addi sp, sp, -16
840 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
841 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
842 ; RV64IZFH-NEXT: fcvt.s.h fa1, fa1
843 ; RV64IZFH-NEXT: call powf
844 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
845 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
846 ; RV64IZFH-NEXT: addi sp, sp, 16
847 ; RV64IZFH-NEXT: ret
848 ;
849 ; RV32IZHINX-LABEL: pow_f16:
850 ; RV32IZHINX: # %bb.0:
851 ; RV32IZHINX-NEXT: addi sp, sp, -16
852 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
853 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
854 ; RV32IZHINX-NEXT: fcvt.s.h a1, a1
855 ; RV32IZHINX-NEXT: call powf
856 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
857 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
858 ; RV32IZHINX-NEXT: addi sp, sp, 16
859 ; RV32IZHINX-NEXT: ret
860 ;
861 ; RV64IZHINX-LABEL: pow_f16:
862 ; RV64IZHINX: # %bb.0:
863 ; RV64IZHINX-NEXT: addi sp, sp, -16
864 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
865 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
866 ; RV64IZHINX-NEXT: fcvt.s.h a1, a1
867 ; RV64IZHINX-NEXT: call powf
868 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
869 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
870 ; RV64IZHINX-NEXT: addi sp, sp, 16
871 ; RV64IZHINX-NEXT: ret
872 ;
873 ; RV32I-LABEL: pow_f16:
874 ; RV32I: # %bb.0:
875 ; RV32I-NEXT: addi sp, sp, -16
876 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
877 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
878 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
879 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
880 ; RV32I-NEXT: mv s0, a1
881 ; RV32I-NEXT: lui a1, 16
882 ; RV32I-NEXT: addi s2, a1, -1
883 ; RV32I-NEXT: and a0, a0, s2
884 ; RV32I-NEXT: call __extendhfsf2
885 ; RV32I-NEXT: mv s1, a0
886 ; RV32I-NEXT: and a0, s0, s2
887 ; RV32I-NEXT: call __extendhfsf2
888 ; RV32I-NEXT: mv a1, a0
889 ; RV32I-NEXT: mv a0, s1
890 ; RV32I-NEXT: call powf
891 ; RV32I-NEXT: call __truncsfhf2
892 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
893 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
894 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
895 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
896 ; RV32I-NEXT: addi sp, sp, 16
897 ; RV32I-NEXT: ret
898 ;
899 ; RV64I-LABEL: pow_f16:
900 ; RV64I: # %bb.0:
901 ; RV64I-NEXT: addi sp, sp, -32
902 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
903 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
904 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
905 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
906 ; RV64I-NEXT: mv s0, a1
907 ; RV64I-NEXT: lui a1, 16
908 ; RV64I-NEXT: addiw s2, a1, -1
909 ; RV64I-NEXT: and a0, a0, s2
910 ; RV64I-NEXT: call __extendhfsf2
911 ; RV64I-NEXT: mv s1, a0
912 ; RV64I-NEXT: and a0, s0, s2
913 ; RV64I-NEXT: call __extendhfsf2
914 ; RV64I-NEXT: mv a1, a0
915 ; RV64I-NEXT: mv a0, s1
916 ; RV64I-NEXT: call powf
917 ; RV64I-NEXT: call __truncsfhf2
918 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
919 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
920 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
921 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
922 ; RV64I-NEXT: addi sp, sp, 32
923 ; RV64I-NEXT: ret
924 ;
925 ; RV32IZFHMIN-LABEL: pow_f16:
926 ; RV32IZFHMIN: # %bb.0:
927 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
928 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
929 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
930 ; RV32IZFHMIN-NEXT: fcvt.s.h fa1, fa1
931 ; RV32IZFHMIN-NEXT: call powf
932 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
933 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
934 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
935 ; RV32IZFHMIN-NEXT: ret
936 ;
937 ; RV64IZFHMIN-LABEL: pow_f16:
938 ; RV64IZFHMIN: # %bb.0:
939 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
940 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
941 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
942 ; RV64IZFHMIN-NEXT: fcvt.s.h fa1, fa1
943 ; RV64IZFHMIN-NEXT: call powf
944 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
945 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
946 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
947 ; RV64IZFHMIN-NEXT: ret
948 ;
949 ; RV32IZHINXMIN-LABEL: pow_f16:
950 ; RV32IZHINXMIN: # %bb.0:
951 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
952 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
953 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
954 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
955 ; RV32IZHINXMIN-NEXT: call powf
956 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
957 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
958 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
959 ; RV32IZHINXMIN-NEXT: ret
960 ;
961 ; RV64IZHINXMIN-LABEL: pow_f16:
962 ; RV64IZHINXMIN: # %bb.0:
963 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
964 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
965 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
966 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
967 ; RV64IZHINXMIN-NEXT: call powf
968 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
969 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
970 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
971 ; RV64IZHINXMIN-NEXT: ret
972 %1 = call half @llvm.pow.f16(half %a, half %b)
973 ret half %1
974 }
976 declare half @llvm.exp.f16(half)
978 define half @exp_f16(half %a) nounwind {
979 ; RV32IZFH-LABEL: exp_f16:
980 ; RV32IZFH: # %bb.0:
981 ; RV32IZFH-NEXT: addi sp, sp, -16
982 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
983 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
984 ; RV32IZFH-NEXT: call expf
985 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
986 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
987 ; RV32IZFH-NEXT: addi sp, sp, 16
988 ; RV32IZFH-NEXT: ret
989 ;
990 ; RV64IZFH-LABEL: exp_f16:
991 ; RV64IZFH: # %bb.0:
992 ; RV64IZFH-NEXT: addi sp, sp, -16
993 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
994 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
995 ; RV64IZFH-NEXT: call expf
996 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
997 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
998 ; RV64IZFH-NEXT: addi sp, sp, 16
999 ; RV64IZFH-NEXT: ret
1000 ;
1001 ; RV32IZHINX-LABEL: exp_f16:
1002 ; RV32IZHINX: # %bb.0:
1003 ; RV32IZHINX-NEXT: addi sp, sp, -16
1004 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1005 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1006 ; RV32IZHINX-NEXT: call expf
1007 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
1008 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1009 ; RV32IZHINX-NEXT: addi sp, sp, 16
1010 ; RV32IZHINX-NEXT: ret
1011 ;
1012 ; RV64IZHINX-LABEL: exp_f16:
1013 ; RV64IZHINX: # %bb.0:
1014 ; RV64IZHINX-NEXT: addi sp, sp, -16
1015 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1016 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1017 ; RV64IZHINX-NEXT: call expf
1018 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
1019 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1020 ; RV64IZHINX-NEXT: addi sp, sp, 16
1021 ; RV64IZHINX-NEXT: ret
1022 ;
1023 ; RV32I-LABEL: exp_f16:
1024 ; RV32I: # %bb.0:
1025 ; RV32I-NEXT: addi sp, sp, -16
1026 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1027 ; RV32I-NEXT: slli a0, a0, 16
1028 ; RV32I-NEXT: srli a0, a0, 16
1029 ; RV32I-NEXT: call __extendhfsf2
1030 ; RV32I-NEXT: call expf
1031 ; RV32I-NEXT: call __truncsfhf2
1032 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1033 ; RV32I-NEXT: addi sp, sp, 16
1034 ; RV32I-NEXT: ret
1035 ;
1036 ; RV64I-LABEL: exp_f16:
1037 ; RV64I: # %bb.0:
1038 ; RV64I-NEXT: addi sp, sp, -16
1039 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1040 ; RV64I-NEXT: slli a0, a0, 48
1041 ; RV64I-NEXT: srli a0, a0, 48
1042 ; RV64I-NEXT: call __extendhfsf2
1043 ; RV64I-NEXT: call expf
1044 ; RV64I-NEXT: call __truncsfhf2
1045 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1046 ; RV64I-NEXT: addi sp, sp, 16
1047 ; RV64I-NEXT: ret
1048 ;
1049 ; RV32IZFHMIN-LABEL: exp_f16:
1050 ; RV32IZFHMIN: # %bb.0:
1051 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1052 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1053 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1054 ; RV32IZFHMIN-NEXT: call expf
1055 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1056 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1057 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1058 ; RV32IZFHMIN-NEXT: ret
1059 ;
1060 ; RV64IZFHMIN-LABEL: exp_f16:
1061 ; RV64IZFHMIN: # %bb.0:
1062 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
1063 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1064 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1065 ; RV64IZFHMIN-NEXT: call expf
1066 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1067 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1068 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
1069 ; RV64IZFHMIN-NEXT: ret
1070 ;
1071 ; RV32IZHINXMIN-LABEL: exp_f16:
1072 ; RV32IZHINXMIN: # %bb.0:
1073 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1074 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1075 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1076 ; RV32IZHINXMIN-NEXT: call expf
1077 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1078 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1079 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1080 ; RV32IZHINXMIN-NEXT: ret
1081 ;
1082 ; RV64IZHINXMIN-LABEL: exp_f16:
1083 ; RV64IZHINXMIN: # %bb.0:
1084 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
1085 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1086 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1087 ; RV64IZHINXMIN-NEXT: call expf
1088 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1089 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1090 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
1091 ; RV64IZHINXMIN-NEXT: ret
1092 %1 = call half @llvm.exp.f16(half %a)
1093 ret half %1
1094 }
1096 declare half @llvm.exp2.f16(half)
1098 define half @exp2_f16(half %a) nounwind {
1099 ; RV32IZFH-LABEL: exp2_f16:
1100 ; RV32IZFH: # %bb.0:
1101 ; RV32IZFH-NEXT: addi sp, sp, -16
1102 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1103 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1104 ; RV32IZFH-NEXT: call exp2f
1105 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1106 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1107 ; RV32IZFH-NEXT: addi sp, sp, 16
1108 ; RV32IZFH-NEXT: ret
1109 ;
1110 ; RV64IZFH-LABEL: exp2_f16:
1111 ; RV64IZFH: # %bb.0:
1112 ; RV64IZFH-NEXT: addi sp, sp, -16
1113 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1114 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1115 ; RV64IZFH-NEXT: call exp2f
1116 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1117 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1118 ; RV64IZFH-NEXT: addi sp, sp, 16
1119 ; RV64IZFH-NEXT: ret
1120 ;
1121 ; RV32IZHINX-LABEL: exp2_f16:
1122 ; RV32IZHINX: # %bb.0:
1123 ; RV32IZHINX-NEXT: addi sp, sp, -16
1124 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1125 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1126 ; RV32IZHINX-NEXT: call exp2f
1127 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
1128 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1129 ; RV32IZHINX-NEXT: addi sp, sp, 16
1130 ; RV32IZHINX-NEXT: ret
1131 ;
1132 ; RV64IZHINX-LABEL: exp2_f16:
1133 ; RV64IZHINX: # %bb.0:
1134 ; RV64IZHINX-NEXT: addi sp, sp, -16
1135 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1136 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1137 ; RV64IZHINX-NEXT: call exp2f
1138 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
1139 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1140 ; RV64IZHINX-NEXT: addi sp, sp, 16
1141 ; RV64IZHINX-NEXT: ret
1142 ;
1143 ; RV32I-LABEL: exp2_f16:
1144 ; RV32I: # %bb.0:
1145 ; RV32I-NEXT: addi sp, sp, -16
1146 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1147 ; RV32I-NEXT: slli a0, a0, 16
1148 ; RV32I-NEXT: srli a0, a0, 16
1149 ; RV32I-NEXT: call __extendhfsf2
1150 ; RV32I-NEXT: call exp2f
1151 ; RV32I-NEXT: call __truncsfhf2
1152 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1153 ; RV32I-NEXT: addi sp, sp, 16
1154 ; RV32I-NEXT: ret
1155 ;
1156 ; RV64I-LABEL: exp2_f16:
1157 ; RV64I: # %bb.0:
1158 ; RV64I-NEXT: addi sp, sp, -16
1159 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1160 ; RV64I-NEXT: slli a0, a0, 48
1161 ; RV64I-NEXT: srli a0, a0, 48
1162 ; RV64I-NEXT: call __extendhfsf2
1163 ; RV64I-NEXT: call exp2f
1164 ; RV64I-NEXT: call __truncsfhf2
1165 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1166 ; RV64I-NEXT: addi sp, sp, 16
1167 ; RV64I-NEXT: ret
1168 ;
1169 ; RV32IZFHMIN-LABEL: exp2_f16:
1170 ; RV32IZFHMIN: # %bb.0:
1171 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1172 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1173 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1174 ; RV32IZFHMIN-NEXT: call exp2f
1175 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1176 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1177 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1178 ; RV32IZFHMIN-NEXT: ret
1179 ;
1180 ; RV64IZFHMIN-LABEL: exp2_f16:
1181 ; RV64IZFHMIN: # %bb.0:
1182 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
1183 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1184 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1185 ; RV64IZFHMIN-NEXT: call exp2f
1186 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1187 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1188 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
1189 ; RV64IZFHMIN-NEXT: ret
1190 ;
1191 ; RV32IZHINXMIN-LABEL: exp2_f16:
1192 ; RV32IZHINXMIN: # %bb.0:
1193 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1194 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1195 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1196 ; RV32IZHINXMIN-NEXT: call exp2f
1197 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1198 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1199 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1200 ; RV32IZHINXMIN-NEXT: ret
1201 ;
1202 ; RV64IZHINXMIN-LABEL: exp2_f16:
1203 ; RV64IZHINXMIN: # %bb.0:
1204 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
1205 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1206 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1207 ; RV64IZHINXMIN-NEXT: call exp2f
1208 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1209 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1210 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
1211 ; RV64IZHINXMIN-NEXT: ret
1212 %1 = call half @llvm.exp2.f16(half %a)
1213 ret half %1
1214 }
1216 declare half @llvm.log.f16(half)
1218 define half @log_f16(half %a) nounwind {
1219 ; RV32IZFH-LABEL: log_f16:
1220 ; RV32IZFH: # %bb.0:
1221 ; RV32IZFH-NEXT: addi sp, sp, -16
1222 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1223 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1224 ; RV32IZFH-NEXT: call logf
1225 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1226 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1227 ; RV32IZFH-NEXT: addi sp, sp, 16
1228 ; RV32IZFH-NEXT: ret
1229 ;
1230 ; RV64IZFH-LABEL: log_f16:
1231 ; RV64IZFH: # %bb.0:
1232 ; RV64IZFH-NEXT: addi sp, sp, -16
1233 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1234 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1235 ; RV64IZFH-NEXT: call logf
1236 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1237 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1238 ; RV64IZFH-NEXT: addi sp, sp, 16
1239 ; RV64IZFH-NEXT: ret
1240 ;
1241 ; RV32IZHINX-LABEL: log_f16:
1242 ; RV32IZHINX: # %bb.0:
1243 ; RV32IZHINX-NEXT: addi sp, sp, -16
1244 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1245 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1246 ; RV32IZHINX-NEXT: call logf
1247 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
1248 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1249 ; RV32IZHINX-NEXT: addi sp, sp, 16
1250 ; RV32IZHINX-NEXT: ret
1251 ;
1252 ; RV64IZHINX-LABEL: log_f16:
1253 ; RV64IZHINX: # %bb.0:
1254 ; RV64IZHINX-NEXT: addi sp, sp, -16
1255 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1256 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1257 ; RV64IZHINX-NEXT: call logf
1258 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
1259 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1260 ; RV64IZHINX-NEXT: addi sp, sp, 16
1261 ; RV64IZHINX-NEXT: ret
1262 ;
1263 ; RV32I-LABEL: log_f16:
1264 ; RV32I: # %bb.0:
1265 ; RV32I-NEXT: addi sp, sp, -16
1266 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1267 ; RV32I-NEXT: slli a0, a0, 16
1268 ; RV32I-NEXT: srli a0, a0, 16
1269 ; RV32I-NEXT: call __extendhfsf2
1270 ; RV32I-NEXT: call logf
1271 ; RV32I-NEXT: call __truncsfhf2
1272 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1273 ; RV32I-NEXT: addi sp, sp, 16
1274 ; RV32I-NEXT: ret
1275 ;
1276 ; RV64I-LABEL: log_f16:
1277 ; RV64I: # %bb.0:
1278 ; RV64I-NEXT: addi sp, sp, -16
1279 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1280 ; RV64I-NEXT: slli a0, a0, 48
1281 ; RV64I-NEXT: srli a0, a0, 48
1282 ; RV64I-NEXT: call __extendhfsf2
1283 ; RV64I-NEXT: call logf
1284 ; RV64I-NEXT: call __truncsfhf2
1285 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1286 ; RV64I-NEXT: addi sp, sp, 16
1287 ; RV64I-NEXT: ret
1288 ;
1289 ; RV32IZFHMIN-LABEL: log_f16:
1290 ; RV32IZFHMIN: # %bb.0:
1291 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1292 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1293 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1294 ; RV32IZFHMIN-NEXT: call logf
1295 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1296 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1297 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1298 ; RV32IZFHMIN-NEXT: ret
1299 ;
1300 ; RV64IZFHMIN-LABEL: log_f16:
1301 ; RV64IZFHMIN: # %bb.0:
1302 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
1303 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1304 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1305 ; RV64IZFHMIN-NEXT: call logf
1306 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1307 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1308 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
1309 ; RV64IZFHMIN-NEXT: ret
1310 ;
1311 ; RV32IZHINXMIN-LABEL: log_f16:
1312 ; RV32IZHINXMIN: # %bb.0:
1313 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1314 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1315 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1316 ; RV32IZHINXMIN-NEXT: call logf
1317 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1318 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1319 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1320 ; RV32IZHINXMIN-NEXT: ret
1321 ;
1322 ; RV64IZHINXMIN-LABEL: log_f16:
1323 ; RV64IZHINXMIN: # %bb.0:
1324 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
1325 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1326 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1327 ; RV64IZHINXMIN-NEXT: call logf
1328 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1329 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1330 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
1331 ; RV64IZHINXMIN-NEXT: ret
1332 %1 = call half @llvm.log.f16(half %a)
1333 ret half %1
1334 }
1336 declare half @llvm.log10.f16(half)
1338 define half @log10_f16(half %a) nounwind {
1339 ; RV32IZFH-LABEL: log10_f16:
1340 ; RV32IZFH: # %bb.0:
1341 ; RV32IZFH-NEXT: addi sp, sp, -16
1342 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1343 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1344 ; RV32IZFH-NEXT: call log10f
1345 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1346 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1347 ; RV32IZFH-NEXT: addi sp, sp, 16
1348 ; RV32IZFH-NEXT: ret
1349 ;
1350 ; RV64IZFH-LABEL: log10_f16:
1351 ; RV64IZFH: # %bb.0:
1352 ; RV64IZFH-NEXT: addi sp, sp, -16
1353 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1354 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1355 ; RV64IZFH-NEXT: call log10f
1356 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1357 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1358 ; RV64IZFH-NEXT: addi sp, sp, 16
1359 ; RV64IZFH-NEXT: ret
1360 ;
1361 ; RV32IZHINX-LABEL: log10_f16:
1362 ; RV32IZHINX: # %bb.0:
1363 ; RV32IZHINX-NEXT: addi sp, sp, -16
1364 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1365 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1366 ; RV32IZHINX-NEXT: call log10f
1367 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
1368 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1369 ; RV32IZHINX-NEXT: addi sp, sp, 16
1370 ; RV32IZHINX-NEXT: ret
1371 ;
1372 ; RV64IZHINX-LABEL: log10_f16:
1373 ; RV64IZHINX: # %bb.0:
1374 ; RV64IZHINX-NEXT: addi sp, sp, -16
1375 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1376 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1377 ; RV64IZHINX-NEXT: call log10f
1378 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
1379 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1380 ; RV64IZHINX-NEXT: addi sp, sp, 16
1381 ; RV64IZHINX-NEXT: ret
1382 ;
1383 ; RV32I-LABEL: log10_f16:
1384 ; RV32I: # %bb.0:
1385 ; RV32I-NEXT: addi sp, sp, -16
1386 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1387 ; RV32I-NEXT: slli a0, a0, 16
1388 ; RV32I-NEXT: srli a0, a0, 16
1389 ; RV32I-NEXT: call __extendhfsf2
1390 ; RV32I-NEXT: call log10f
1391 ; RV32I-NEXT: call __truncsfhf2
1392 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1393 ; RV32I-NEXT: addi sp, sp, 16
1394 ; RV32I-NEXT: ret
1395 ;
1396 ; RV64I-LABEL: log10_f16:
1397 ; RV64I: # %bb.0:
1398 ; RV64I-NEXT: addi sp, sp, -16
1399 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1400 ; RV64I-NEXT: slli a0, a0, 48
1401 ; RV64I-NEXT: srli a0, a0, 48
1402 ; RV64I-NEXT: call __extendhfsf2
1403 ; RV64I-NEXT: call log10f
1404 ; RV64I-NEXT: call __truncsfhf2
1405 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1406 ; RV64I-NEXT: addi sp, sp, 16
1407 ; RV64I-NEXT: ret
1408 ;
1409 ; RV32IZFHMIN-LABEL: log10_f16:
1410 ; RV32IZFHMIN: # %bb.0:
1411 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1412 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1413 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1414 ; RV32IZFHMIN-NEXT: call log10f
1415 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1416 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1417 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1418 ; RV32IZFHMIN-NEXT: ret
1419 ;
1420 ; RV64IZFHMIN-LABEL: log10_f16:
1421 ; RV64IZFHMIN: # %bb.0:
1422 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
1423 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1424 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1425 ; RV64IZFHMIN-NEXT: call log10f
1426 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1427 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1428 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
1429 ; RV64IZFHMIN-NEXT: ret
1430 ;
1431 ; RV32IZHINXMIN-LABEL: log10_f16:
1432 ; RV32IZHINXMIN: # %bb.0:
1433 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1434 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1435 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1436 ; RV32IZHINXMIN-NEXT: call log10f
1437 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1438 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1439 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1440 ; RV32IZHINXMIN-NEXT: ret
1441 ;
1442 ; RV64IZHINXMIN-LABEL: log10_f16:
1443 ; RV64IZHINXMIN: # %bb.0:
1444 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
1445 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1446 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1447 ; RV64IZHINXMIN-NEXT: call log10f
1448 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1449 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1450 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
1451 ; RV64IZHINXMIN-NEXT: ret
1452 %1 = call half @llvm.log10.f16(half %a)
1453 ret half %1
1454 }
1456 declare half @llvm.log2.f16(half)
1458 define half @log2_f16(half %a) nounwind {
1459 ; RV32IZFH-LABEL: log2_f16:
1460 ; RV32IZFH: # %bb.0:
1461 ; RV32IZFH-NEXT: addi sp, sp, -16
1462 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1463 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1464 ; RV32IZFH-NEXT: call log2f
1465 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1466 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1467 ; RV32IZFH-NEXT: addi sp, sp, 16
1468 ; RV32IZFH-NEXT: ret
1469 ;
1470 ; RV64IZFH-LABEL: log2_f16:
1471 ; RV64IZFH: # %bb.0:
1472 ; RV64IZFH-NEXT: addi sp, sp, -16
1473 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1474 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1475 ; RV64IZFH-NEXT: call log2f
1476 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1477 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1478 ; RV64IZFH-NEXT: addi sp, sp, 16
1479 ; RV64IZFH-NEXT: ret
1480 ;
1481 ; RV32IZHINX-LABEL: log2_f16:
1482 ; RV32IZHINX: # %bb.0:
1483 ; RV32IZHINX-NEXT: addi sp, sp, -16
1484 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1485 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
1486 ; RV32IZHINX-NEXT: call log2f
1487 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
1488 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1489 ; RV32IZHINX-NEXT: addi sp, sp, 16
1490 ; RV32IZHINX-NEXT: ret
1491 ;
1492 ; RV64IZHINX-LABEL: log2_f16:
1493 ; RV64IZHINX: # %bb.0:
1494 ; RV64IZHINX-NEXT: addi sp, sp, -16
1495 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1496 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
1497 ; RV64IZHINX-NEXT: call log2f
1498 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
1499 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1500 ; RV64IZHINX-NEXT: addi sp, sp, 16
1501 ; RV64IZHINX-NEXT: ret
1502 ;
1503 ; RV32I-LABEL: log2_f16:
1504 ; RV32I: # %bb.0:
1505 ; RV32I-NEXT: addi sp, sp, -16
1506 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1507 ; RV32I-NEXT: slli a0, a0, 16
1508 ; RV32I-NEXT: srli a0, a0, 16
1509 ; RV32I-NEXT: call __extendhfsf2
1510 ; RV32I-NEXT: call log2f
1511 ; RV32I-NEXT: call __truncsfhf2
1512 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1513 ; RV32I-NEXT: addi sp, sp, 16
1514 ; RV32I-NEXT: ret
1515 ;
1516 ; RV64I-LABEL: log2_f16:
1517 ; RV64I: # %bb.0:
1518 ; RV64I-NEXT: addi sp, sp, -16
1519 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1520 ; RV64I-NEXT: slli a0, a0, 48
1521 ; RV64I-NEXT: srli a0, a0, 48
1522 ; RV64I-NEXT: call __extendhfsf2
1523 ; RV64I-NEXT: call log2f
1524 ; RV64I-NEXT: call __truncsfhf2
1525 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1526 ; RV64I-NEXT: addi sp, sp, 16
1527 ; RV64I-NEXT: ret
1528 ;
1529 ; RV32IZFHMIN-LABEL: log2_f16:
1530 ; RV32IZFHMIN: # %bb.0:
1531 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1532 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1533 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1534 ; RV32IZFHMIN-NEXT: call log2f
1535 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1536 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1537 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1538 ; RV32IZFHMIN-NEXT: ret
1539 ;
1540 ; RV64IZFHMIN-LABEL: log2_f16:
1541 ; RV64IZFHMIN: # %bb.0:
1542 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
1543 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1544 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
1545 ; RV64IZFHMIN-NEXT: call log2f
1546 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
1547 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1548 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
1549 ; RV64IZFHMIN-NEXT: ret
1550 ;
1551 ; RV32IZHINXMIN-LABEL: log2_f16:
1552 ; RV32IZHINXMIN: # %bb.0:
1553 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1554 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1555 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1556 ; RV32IZHINXMIN-NEXT: call log2f
1557 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1558 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1559 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1560 ; RV32IZHINXMIN-NEXT: ret
1561 ;
1562 ; RV64IZHINXMIN-LABEL: log2_f16:
1563 ; RV64IZHINXMIN: # %bb.0:
1564 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
1565 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1566 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1567 ; RV64IZHINXMIN-NEXT: call log2f
1568 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1569 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1570 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
1571 ; RV64IZHINXMIN-NEXT: ret
1572 %1 = call half @llvm.log2.f16(half %a)
1573 ret half %1
1574 }
1576 declare half @llvm.fma.f16(half, half, half)
1578 define half @fma_f16(half %a, half %b, half %c) nounwind {
1579 ; CHECKIZFH-LABEL: fma_f16:
1580 ; CHECKIZFH: # %bb.0:
1581 ; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
1582 ; CHECKIZFH-NEXT: ret
1583 ;
1584 ; CHECKIZHINX-LABEL: fma_f16:
1585 ; CHECKIZHINX: # %bb.0:
1586 ; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
1587 ; CHECKIZHINX-NEXT: ret
1588 ;
1589 ; RV32I-LABEL: fma_f16:
1590 ; RV32I: # %bb.0:
1591 ; RV32I-NEXT: addi sp, sp, -32
1592 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1593 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1594 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1595 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1596 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1597 ; RV32I-NEXT: mv s0, a2
1598 ; RV32I-NEXT: mv s1, a1
1599 ; RV32I-NEXT: lui a1, 16
1600 ; RV32I-NEXT: addi s3, a1, -1
1601 ; RV32I-NEXT: and a0, a0, s3
1602 ; RV32I-NEXT: call __extendhfsf2
1603 ; RV32I-NEXT: mv s2, a0
1604 ; RV32I-NEXT: and a0, s1, s3
1605 ; RV32I-NEXT: call __extendhfsf2
1606 ; RV32I-NEXT: mv s1, a0
1607 ; RV32I-NEXT: and a0, s0, s3
1608 ; RV32I-NEXT: call __extendhfsf2
1609 ; RV32I-NEXT: mv a2, a0
1610 ; RV32I-NEXT: mv a0, s2
1611 ; RV32I-NEXT: mv a1, s1
1612 ; RV32I-NEXT: call fmaf
1613 ; RV32I-NEXT: call __truncsfhf2
1614 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1615 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1616 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1617 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1618 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1619 ; RV32I-NEXT: addi sp, sp, 32
1620 ; RV32I-NEXT: ret
1621 ;
1622 ; RV64I-LABEL: fma_f16:
1623 ; RV64I: # %bb.0:
1624 ; RV64I-NEXT: addi sp, sp, -48
1625 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
1626 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
1627 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
1628 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
1629 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
1630 ; RV64I-NEXT: mv s0, a2
1631 ; RV64I-NEXT: mv s1, a1
1632 ; RV64I-NEXT: lui a1, 16
1633 ; RV64I-NEXT: addiw s3, a1, -1
1634 ; RV64I-NEXT: and a0, a0, s3
1635 ; RV64I-NEXT: call __extendhfsf2
1636 ; RV64I-NEXT: mv s2, a0
1637 ; RV64I-NEXT: and a0, s1, s3
1638 ; RV64I-NEXT: call __extendhfsf2
1639 ; RV64I-NEXT: mv s1, a0
1640 ; RV64I-NEXT: and a0, s0, s3
1641 ; RV64I-NEXT: call __extendhfsf2
1642 ; RV64I-NEXT: mv a2, a0
1643 ; RV64I-NEXT: mv a0, s2
1644 ; RV64I-NEXT: mv a1, s1
1645 ; RV64I-NEXT: call fmaf
1646 ; RV64I-NEXT: call __truncsfhf2
1647 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
1648 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
1649 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
1650 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
1651 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
1652 ; RV64I-NEXT: addi sp, sp, 48
1653 ; RV64I-NEXT: ret
1654 ;
1655 ; CHECKIZFHMIN-LABEL: fma_f16:
1656 ; CHECKIZFHMIN: # %bb.0:
1657 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa2
1658 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
1659 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa3, fa0
1660 ; CHECKIZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
1661 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
1662 ; CHECKIZFHMIN-NEXT: ret
1663 ;
1664 ; CHECKIZHINXMIN-LABEL: fma_f16:
1665 ; CHECKIZHINXMIN: # %bb.0:
1666 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
1667 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
1668 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1669 ; CHECKIZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
1670 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1671 ; CHECKIZHINXMIN-NEXT: ret
1672 %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
1673 ret half %1
1674 }
1676 declare half @llvm.fmuladd.f16(half, half, half)
1678 define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
1679 ; CHECKIZFH-LABEL: fmuladd_f16:
1680 ; CHECKIZFH: # %bb.0:
1681 ; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
1682 ; CHECKIZFH-NEXT: ret
1683 ;
1684 ; CHECKIZHINX-LABEL: fmuladd_f16:
1685 ; CHECKIZHINX: # %bb.0:
1686 ; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
1687 ; CHECKIZHINX-NEXT: ret
1688 ;
1689 ; RV32I-LABEL: fmuladd_f16:
1690 ; RV32I: # %bb.0:
1691 ; RV32I-NEXT: addi sp, sp, -32
1692 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1693 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1694 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1695 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1696 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1697 ; RV32I-NEXT: mv s0, a2
1698 ; RV32I-NEXT: mv s1, a1
1699 ; RV32I-NEXT: lui a1, 16
1700 ; RV32I-NEXT: addi s3, a1, -1
1701 ; RV32I-NEXT: and a0, a0, s3
1702 ; RV32I-NEXT: call __extendhfsf2
1703 ; RV32I-NEXT: mv s2, a0
1704 ; RV32I-NEXT: and a0, s1, s3
1705 ; RV32I-NEXT: call __extendhfsf2
1706 ; RV32I-NEXT: mv a1, a0
1707 ; RV32I-NEXT: mv a0, s2
1708 ; RV32I-NEXT: call __mulsf3
1709 ; RV32I-NEXT: call __truncsfhf2
1710 ; RV32I-NEXT: mv s1, a0
1711 ; RV32I-NEXT: and a0, s0, s3
1712 ; RV32I-NEXT: call __extendhfsf2
1713 ; RV32I-NEXT: mv s0, a0
1714 ; RV32I-NEXT: and a0, s1, s3
1715 ; RV32I-NEXT: call __extendhfsf2
1716 ; RV32I-NEXT: mv a1, s0
1717 ; RV32I-NEXT: call __addsf3
1718 ; RV32I-NEXT: call __truncsfhf2
1719 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1720 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1721 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1722 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1723 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1724 ; RV32I-NEXT: addi sp, sp, 32
1725 ; RV32I-NEXT: ret
1726 ;
1727 ; RV64I-LABEL: fmuladd_f16:
1728 ; RV64I: # %bb.0:
1729 ; RV64I-NEXT: addi sp, sp, -48
1730 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
1731 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
1732 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
1733 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
1734 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
1735 ; RV64I-NEXT: mv s0, a2
1736 ; RV64I-NEXT: mv s1, a1
1737 ; RV64I-NEXT: lui a1, 16
1738 ; RV64I-NEXT: addiw s3, a1, -1
1739 ; RV64I-NEXT: and a0, a0, s3
1740 ; RV64I-NEXT: call __extendhfsf2
1741 ; RV64I-NEXT: mv s2, a0
1742 ; RV64I-NEXT: and a0, s1, s3
1743 ; RV64I-NEXT: call __extendhfsf2
1744 ; RV64I-NEXT: mv a1, a0
1745 ; RV64I-NEXT: mv a0, s2
1746 ; RV64I-NEXT: call __mulsf3
1747 ; RV64I-NEXT: call __truncsfhf2
1748 ; RV64I-NEXT: mv s1, a0
1749 ; RV64I-NEXT: and a0, s0, s3
1750 ; RV64I-NEXT: call __extendhfsf2
1751 ; RV64I-NEXT: mv s0, a0
1752 ; RV64I-NEXT: and a0, s1, s3
1753 ; RV64I-NEXT: call __extendhfsf2
1754 ; RV64I-NEXT: mv a1, s0
1755 ; RV64I-NEXT: call __addsf3
1756 ; RV64I-NEXT: call __truncsfhf2
1757 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
1758 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
1759 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
1760 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
1761 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
1762 ; RV64I-NEXT: addi sp, sp, 48
1763 ; RV64I-NEXT: ret
1764 ;
1765 ; CHECKIZFHMIN-LABEL: fmuladd_f16:
1766 ; CHECKIZFHMIN: # %bb.0:
1767 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
1768 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
1769 ; CHECKIZFHMIN-NEXT: fmul.s fa5, fa4, fa5
1770 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1771 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1772 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa2
1773 ; CHECKIZFHMIN-NEXT: fadd.s fa5, fa5, fa4
1774 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
1775 ; CHECKIZFHMIN-NEXT: ret
1776 ;
1777 ; CHECKIZHINXMIN-LABEL: fmuladd_f16:
1778 ; CHECKIZHINXMIN: # %bb.0:
1779 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
1780 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1781 ; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
1782 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1783 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1784 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a2
1785 ; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
1786 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1787 ; CHECKIZHINXMIN-NEXT: ret
1788 %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
1789 ret half %1
1790 }
1792 declare half @llvm.fabs.f16(half)
1794 define half @fabs_f16(half %a) nounwind {
1795 ; CHECKIZFH-LABEL: fabs_f16:
1796 ; CHECKIZFH: # %bb.0:
1797 ; CHECKIZFH-NEXT: fabs.h fa0, fa0
1798 ; CHECKIZFH-NEXT: ret
1799 ;
1800 ; RV32IZHINX-LABEL: fabs_f16:
1801 ; RV32IZHINX: # %bb.0:
1802 ; RV32IZHINX-NEXT: slli a0, a0, 17
1803 ; RV32IZHINX-NEXT: srli a0, a0, 17
1804 ; RV32IZHINX-NEXT: ret
1805 ;
1806 ; RV64IZHINX-LABEL: fabs_f16:
1807 ; RV64IZHINX: # %bb.0:
1808 ; RV64IZHINX-NEXT: slli a0, a0, 49
1809 ; RV64IZHINX-NEXT: srli a0, a0, 49
1810 ; RV64IZHINX-NEXT: ret
1811 ;
1812 ; RV32I-LABEL: fabs_f16:
1813 ; RV32I: # %bb.0:
1814 ; RV32I-NEXT: slli a0, a0, 17
1815 ; RV32I-NEXT: srli a0, a0, 17
1816 ; RV32I-NEXT: ret
1817 ;
1818 ; RV64I-LABEL: fabs_f16:
1819 ; RV64I: # %bb.0:
1820 ; RV64I-NEXT: slli a0, a0, 49
1821 ; RV64I-NEXT: srli a0, a0, 49
1822 ; RV64I-NEXT: ret
1823 ;
1824 ; CHECKIZFHMIN-LABEL: fabs_f16:
1825 ; CHECKIZFHMIN: # %bb.0:
1826 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1827 ; CHECKIZFHMIN-NEXT: fabs.s fa5, fa5
1828 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
1829 ; CHECKIZFHMIN-NEXT: ret
1830 ;
1831 ; RV32IZHINXMIN-LABEL: fabs_f16:
1832 ; RV32IZHINXMIN: # %bb.0:
1833 ; RV32IZHINXMIN-NEXT: slli a0, a0, 17
1834 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17
1835 ; RV32IZHINXMIN-NEXT: ret
1836 ;
1837 ; RV64IZHINXMIN-LABEL: fabs_f16:
1838 ; RV64IZHINXMIN: # %bb.0:
1839 ; RV64IZHINXMIN-NEXT: slli a0, a0, 49
1840 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49
1841 ; RV64IZHINXMIN-NEXT: ret
1842 %1 = call half @llvm.fabs.f16(half %a)
1843 ret half %1
1844 }
1846 declare half @llvm.minnum.f16(half, half)
1848 define half @minnum_f16(half %a, half %b) nounwind {
1849 ; CHECKIZFH-LABEL: minnum_f16:
1850 ; CHECKIZFH: # %bb.0:
1851 ; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
1852 ; CHECKIZFH-NEXT: ret
1853 ;
1854 ; CHECKIZHINX-LABEL: minnum_f16:
1855 ; CHECKIZHINX: # %bb.0:
1856 ; CHECKIZHINX-NEXT: fmin.h a0, a0, a1
1857 ; CHECKIZHINX-NEXT: ret
1858 ;
1859 ; RV32I-LABEL: minnum_f16:
1860 ; RV32I: # %bb.0:
1861 ; RV32I-NEXT: addi sp, sp, -16
1862 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1863 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1864 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1865 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1866 ; RV32I-NEXT: mv s0, a1
1867 ; RV32I-NEXT: lui a1, 16
1868 ; RV32I-NEXT: addi s2, a1, -1
1869 ; RV32I-NEXT: and a0, a0, s2
1870 ; RV32I-NEXT: call __extendhfsf2
1871 ; RV32I-NEXT: mv s1, a0
1872 ; RV32I-NEXT: and a0, s0, s2
1873 ; RV32I-NEXT: call __extendhfsf2
1874 ; RV32I-NEXT: mv a1, a0
1875 ; RV32I-NEXT: mv a0, s1
1876 ; RV32I-NEXT: call fminf
1877 ; RV32I-NEXT: call __truncsfhf2
1878 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1879 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1880 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1881 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1882 ; RV32I-NEXT: addi sp, sp, 16
1883 ; RV32I-NEXT: ret
1884 ;
1885 ; RV64I-LABEL: minnum_f16:
1886 ; RV64I: # %bb.0:
1887 ; RV64I-NEXT: addi sp, sp, -32
1888 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1889 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1890 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1891 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1892 ; RV64I-NEXT: mv s0, a1
1893 ; RV64I-NEXT: lui a1, 16
1894 ; RV64I-NEXT: addiw s2, a1, -1
1895 ; RV64I-NEXT: and a0, a0, s2
1896 ; RV64I-NEXT: call __extendhfsf2
1897 ; RV64I-NEXT: mv s1, a0
1898 ; RV64I-NEXT: and a0, s0, s2
1899 ; RV64I-NEXT: call __extendhfsf2
1900 ; RV64I-NEXT: mv a1, a0
1901 ; RV64I-NEXT: mv a0, s1
1902 ; RV64I-NEXT: call fminf
1903 ; RV64I-NEXT: call __truncsfhf2
1904 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1905 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1906 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1907 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1908 ; RV64I-NEXT: addi sp, sp, 32
1909 ; RV64I-NEXT: ret
1910 ;
1911 ; CHECKIZFHMIN-LABEL: minnum_f16:
1912 ; CHECKIZFHMIN: # %bb.0:
1913 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
1914 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
1915 ; CHECKIZFHMIN-NEXT: fmin.s fa5, fa4, fa5
1916 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
1917 ; CHECKIZFHMIN-NEXT: ret
1918 ;
1919 ; CHECKIZHINXMIN-LABEL: minnum_f16:
1920 ; CHECKIZHINXMIN: # %bb.0:
1921 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
1922 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1923 ; CHECKIZHINXMIN-NEXT: fmin.s a0, a0, a1
1924 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1925 ; CHECKIZHINXMIN-NEXT: ret
1926 %1 = call half @llvm.minnum.f16(half %a, half %b)
1927 ret half %1
1928 }
1930 declare half @llvm.maxnum.f16(half, half)
1932 define half @maxnum_f16(half %a, half %b) nounwind {
1933 ; CHECKIZFH-LABEL: maxnum_f16:
1934 ; CHECKIZFH: # %bb.0:
1935 ; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
1936 ; CHECKIZFH-NEXT: ret
1937 ;
1938 ; CHECKIZHINX-LABEL: maxnum_f16:
1939 ; CHECKIZHINX: # %bb.0:
1940 ; CHECKIZHINX-NEXT: fmax.h a0, a0, a1
1941 ; CHECKIZHINX-NEXT: ret
1942 ;
1943 ; RV32I-LABEL: maxnum_f16:
1944 ; RV32I: # %bb.0:
1945 ; RV32I-NEXT: addi sp, sp, -16
1946 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1947 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1948 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1949 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1950 ; RV32I-NEXT: mv s0, a1
1951 ; RV32I-NEXT: lui a1, 16
1952 ; RV32I-NEXT: addi s2, a1, -1
1953 ; RV32I-NEXT: and a0, a0, s2
1954 ; RV32I-NEXT: call __extendhfsf2
1955 ; RV32I-NEXT: mv s1, a0
1956 ; RV32I-NEXT: and a0, s0, s2
1957 ; RV32I-NEXT: call __extendhfsf2
1958 ; RV32I-NEXT: mv a1, a0
1959 ; RV32I-NEXT: mv a0, s1
1960 ; RV32I-NEXT: call fmaxf
1961 ; RV32I-NEXT: call __truncsfhf2
1962 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1963 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1964 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1965 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1966 ; RV32I-NEXT: addi sp, sp, 16
1967 ; RV32I-NEXT: ret
1968 ;
1969 ; RV64I-LABEL: maxnum_f16:
1970 ; RV64I: # %bb.0:
1971 ; RV64I-NEXT: addi sp, sp, -32
1972 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1973 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1974 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1975 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1976 ; RV64I-NEXT: mv s0, a1
1977 ; RV64I-NEXT: lui a1, 16
1978 ; RV64I-NEXT: addiw s2, a1, -1
1979 ; RV64I-NEXT: and a0, a0, s2
1980 ; RV64I-NEXT: call __extendhfsf2
1981 ; RV64I-NEXT: mv s1, a0
1982 ; RV64I-NEXT: and a0, s0, s2
1983 ; RV64I-NEXT: call __extendhfsf2
1984 ; RV64I-NEXT: mv a1, a0
1985 ; RV64I-NEXT: mv a0, s1
1986 ; RV64I-NEXT: call fmaxf
1987 ; RV64I-NEXT: call __truncsfhf2
1988 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1989 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1990 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1991 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1992 ; RV64I-NEXT: addi sp, sp, 32
1993 ; RV64I-NEXT: ret
1994 ;
1995 ; CHECKIZFHMIN-LABEL: maxnum_f16:
1996 ; CHECKIZFHMIN: # %bb.0:
1997 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
1998 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
1999 ; CHECKIZFHMIN-NEXT: fmax.s fa5, fa4, fa5
2000 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2001 ; CHECKIZFHMIN-NEXT: ret
2002 ;
2003 ; CHECKIZHINXMIN-LABEL: maxnum_f16:
2004 ; CHECKIZHINXMIN: # %bb.0:
2005 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
2006 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2007 ; CHECKIZHINXMIN-NEXT: fmax.s a0, a0, a1
2008 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2009 ; CHECKIZHINXMIN-NEXT: ret
2010 %1 = call half @llvm.maxnum.f16(half %a, half %b)
2011 ret half %1
2012 }
2014 ; TODO: FMINNAN and FMAXNAN aren't handled in
2015 ; SelectionDAGLegalize::ExpandNode.
2017 ; declare half @llvm.minimum.f16(half, half)
2019 ; define half @fminimum_f16(half %a, half %b) nounwind {
2020 ; %1 = call half @llvm.minimum.f16(half %a, half %b)
2021 ; ret half %1
2022 ; }
2024 ; declare half @llvm.maximum.f16(half, half)
2026 ; define half @fmaximum_f16(half %a, half %b) nounwind {
2027 ; %1 = call half @llvm.maximum.f16(half %a, half %b)
2028 ; ret half %1
2029 ; }
2031 declare half @llvm.copysign.f16(half, half)
2033 define half @copysign_f16(half %a, half %b) nounwind {
2034 ; CHECKIZFH-LABEL: copysign_f16:
2035 ; CHECKIZFH: # %bb.0:
2036 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
2037 ; CHECKIZFH-NEXT: ret
2038 ;
2039 ; CHECKIZHINX-LABEL: copysign_f16:
2040 ; CHECKIZHINX: # %bb.0:
2041 ; CHECKIZHINX-NEXT: fsgnj.h a0, a0, a1
2042 ; CHECKIZHINX-NEXT: ret
2043 ;
2044 ; RV32I-LABEL: copysign_f16:
2045 ; RV32I: # %bb.0:
2046 ; RV32I-NEXT: lui a2, 1048568
2047 ; RV32I-NEXT: and a1, a1, a2
2048 ; RV32I-NEXT: slli a0, a0, 17
2049 ; RV32I-NEXT: srli a0, a0, 17
2050 ; RV32I-NEXT: or a0, a0, a1
2051 ; RV32I-NEXT: ret
2052 ;
2053 ; RV64I-LABEL: copysign_f16:
2054 ; RV64I: # %bb.0:
2055 ; RV64I-NEXT: lui a2, 1048568
2056 ; RV64I-NEXT: and a1, a1, a2
2057 ; RV64I-NEXT: slli a0, a0, 49
2058 ; RV64I-NEXT: srli a0, a0, 49
2059 ; RV64I-NEXT: or a0, a0, a1
2060 ; RV64I-NEXT: ret
2061 ;
2062 ; RV32IZFHMIN-LABEL: copysign_f16:
2063 ; RV32IZFHMIN: # %bb.0:
2064 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2065 ; RV32IZFHMIN-NEXT: fsh fa1, 12(sp)
2066 ; RV32IZFHMIN-NEXT: fsh fa0, 8(sp)
2067 ; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
2068 ; RV32IZFHMIN-NEXT: lbu a1, 9(sp)
2069 ; RV32IZFHMIN-NEXT: andi a0, a0, 128
2070 ; RV32IZFHMIN-NEXT: andi a1, a1, 127
2071 ; RV32IZFHMIN-NEXT: or a0, a1, a0
2072 ; RV32IZFHMIN-NEXT: sb a0, 9(sp)
2073 ; RV32IZFHMIN-NEXT: flh fa0, 8(sp)
2074 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2075 ; RV32IZFHMIN-NEXT: ret
2076 ;
2077 ; RV64IZFHMIN-LABEL: copysign_f16:
2078 ; RV64IZFHMIN: # %bb.0:
2079 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
2080 ; RV64IZFHMIN-NEXT: fsh fa1, 8(sp)
2081 ; RV64IZFHMIN-NEXT: fsh fa0, 0(sp)
2082 ; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
2083 ; RV64IZFHMIN-NEXT: lbu a1, 1(sp)
2084 ; RV64IZFHMIN-NEXT: andi a0, a0, 128
2085 ; RV64IZFHMIN-NEXT: andi a1, a1, 127
2086 ; RV64IZFHMIN-NEXT: or a0, a1, a0
2087 ; RV64IZFHMIN-NEXT: sb a0, 1(sp)
2088 ; RV64IZFHMIN-NEXT: flh fa0, 0(sp)
2089 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
2090 ; RV64IZFHMIN-NEXT: ret
2091 ;
2092 ; RV32IZHINXMIN-LABEL: copysign_f16:
2093 ; RV32IZHINXMIN: # %bb.0:
2094 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2095 ; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
2096 ; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
2097 ; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
2098 ; RV32IZHINXMIN-NEXT: lbu a1, 9(sp)
2099 ; RV32IZHINXMIN-NEXT: andi a0, a0, 128
2100 ; RV32IZHINXMIN-NEXT: andi a1, a1, 127
2101 ; RV32IZHINXMIN-NEXT: or a0, a1, a0
2102 ; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
2103 ; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
2104 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2105 ; RV32IZHINXMIN-NEXT: ret
2106 ;
2107 ; RV64IZHINXMIN-LABEL: copysign_f16:
2108 ; RV64IZHINXMIN: # %bb.0:
2109 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
2110 ; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
2111 ; RV64IZHINXMIN-NEXT: sh a0, 0(sp)
2112 ; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
2113 ; RV64IZHINXMIN-NEXT: lbu a1, 1(sp)
2114 ; RV64IZHINXMIN-NEXT: andi a0, a0, 128
2115 ; RV64IZHINXMIN-NEXT: andi a1, a1, 127
2116 ; RV64IZHINXMIN-NEXT: or a0, a1, a0
2117 ; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
2118 ; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
2119 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
2120 ; RV64IZHINXMIN-NEXT: ret
2121 %1 = call half @llvm.copysign.f16(half %a, half %b)
2122 ret half %1
2123 }
2125 declare half @llvm.floor.f16(half)
2127 define half @floor_f16(half %a) nounwind {
2128 ; CHECKIZFH-LABEL: floor_f16:
2129 ; CHECKIZFH: # %bb.0:
2130 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI17_0)
2131 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI17_0)(a0)
2132 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2133 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2134 ; CHECKIZFH-NEXT: beqz a0, .LBB17_2
2135 ; CHECKIZFH-NEXT: # %bb.1:
2136 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
2137 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rdn
2138 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2139 ; CHECKIZFH-NEXT: .LBB17_2:
2140 ; CHECKIZFH-NEXT: ret
2141 ;
2142 ; CHECKIZHINX-LABEL: floor_f16:
2143 ; CHECKIZHINX: # %bb.0:
2144 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI17_0)
2145 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
2146 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2147 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2148 ; CHECKIZHINX-NEXT: beqz a1, .LBB17_2
2149 ; CHECKIZHINX-NEXT: # %bb.1:
2150 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
2151 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
2152 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2153 ; CHECKIZHINX-NEXT: .LBB17_2:
2154 ; CHECKIZHINX-NEXT: ret
2155 ;
2156 ; RV32I-LABEL: floor_f16:
2157 ; RV32I: # %bb.0:
2158 ; RV32I-NEXT: addi sp, sp, -16
2159 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2160 ; RV32I-NEXT: slli a0, a0, 16
2161 ; RV32I-NEXT: srli a0, a0, 16
2162 ; RV32I-NEXT: call __extendhfsf2
2163 ; RV32I-NEXT: call floorf
2164 ; RV32I-NEXT: call __truncsfhf2
2165 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2166 ; RV32I-NEXT: addi sp, sp, 16
2167 ; RV32I-NEXT: ret
2168 ;
2169 ; RV64I-LABEL: floor_f16:
2170 ; RV64I: # %bb.0:
2171 ; RV64I-NEXT: addi sp, sp, -16
2172 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2173 ; RV64I-NEXT: slli a0, a0, 48
2174 ; RV64I-NEXT: srli a0, a0, 48
2175 ; RV64I-NEXT: call __extendhfsf2
2176 ; RV64I-NEXT: call floorf
2177 ; RV64I-NEXT: call __truncsfhf2
2178 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2179 ; RV64I-NEXT: addi sp, sp, 16
2180 ; RV64I-NEXT: ret
2181 ;
2182 ; CHECKIZFHMIN-LABEL: floor_f16:
2183 ; CHECKIZFHMIN: # %bb.0:
2184 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2185 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2186 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2187 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2188 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2189 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB17_2
2190 ; CHECKIZFHMIN-NEXT: # %bb.1:
2191 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
2192 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
2193 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2194 ; CHECKIZFHMIN-NEXT: .LBB17_2:
2195 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2196 ; CHECKIZFHMIN-NEXT: ret
2197 ;
2198 ; CHECKIZHINXMIN-LABEL: floor_f16:
2199 ; CHECKIZHINXMIN: # %bb.0:
2200 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2201 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2202 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2203 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2204 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB17_2
2205 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2206 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
2207 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
2208 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2209 ; CHECKIZHINXMIN-NEXT: .LBB17_2:
2210 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2211 ; CHECKIZHINXMIN-NEXT: ret
2212 %1 = call half @llvm.floor.f16(half %a)
2213 ret half %1
2214 }
2216 declare half @llvm.ceil.f16(half)
2218 define half @ceil_f16(half %a) nounwind {
2219 ; CHECKIZFH-LABEL: ceil_f16:
2220 ; CHECKIZFH: # %bb.0:
2221 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI18_0)
2222 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI18_0)(a0)
2223 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2224 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2225 ; CHECKIZFH-NEXT: beqz a0, .LBB18_2
2226 ; CHECKIZFH-NEXT: # %bb.1:
2227 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
2228 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rup
2229 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2230 ; CHECKIZFH-NEXT: .LBB18_2:
2231 ; CHECKIZFH-NEXT: ret
2232 ;
2233 ; CHECKIZHINX-LABEL: ceil_f16:
2234 ; CHECKIZHINX: # %bb.0:
2235 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI18_0)
2236 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
2237 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2238 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2239 ; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
2240 ; CHECKIZHINX-NEXT: # %bb.1:
2241 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
2242 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
2243 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2244 ; CHECKIZHINX-NEXT: .LBB18_2:
2245 ; CHECKIZHINX-NEXT: ret
2246 ;
2247 ; RV32I-LABEL: ceil_f16:
2248 ; RV32I: # %bb.0:
2249 ; RV32I-NEXT: addi sp, sp, -16
2250 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2251 ; RV32I-NEXT: slli a0, a0, 16
2252 ; RV32I-NEXT: srli a0, a0, 16
2253 ; RV32I-NEXT: call __extendhfsf2
2254 ; RV32I-NEXT: call ceilf
2255 ; RV32I-NEXT: call __truncsfhf2
2256 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2257 ; RV32I-NEXT: addi sp, sp, 16
2258 ; RV32I-NEXT: ret
2259 ;
2260 ; RV64I-LABEL: ceil_f16:
2261 ; RV64I: # %bb.0:
2262 ; RV64I-NEXT: addi sp, sp, -16
2263 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2264 ; RV64I-NEXT: slli a0, a0, 48
2265 ; RV64I-NEXT: srli a0, a0, 48
2266 ; RV64I-NEXT: call __extendhfsf2
2267 ; RV64I-NEXT: call ceilf
2268 ; RV64I-NEXT: call __truncsfhf2
2269 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2270 ; RV64I-NEXT: addi sp, sp, 16
2271 ; RV64I-NEXT: ret
2272 ;
2273 ; CHECKIZFHMIN-LABEL: ceil_f16:
2274 ; CHECKIZFHMIN: # %bb.0:
2275 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2276 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2277 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2278 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2279 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2280 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB18_2
2281 ; CHECKIZFHMIN-NEXT: # %bb.1:
2282 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
2283 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
2284 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2285 ; CHECKIZFHMIN-NEXT: .LBB18_2:
2286 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2287 ; CHECKIZFHMIN-NEXT: ret
2288 ;
2289 ; CHECKIZHINXMIN-LABEL: ceil_f16:
2290 ; CHECKIZHINXMIN: # %bb.0:
2291 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2292 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2293 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2294 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2295 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB18_2
2296 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2297 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
2298 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
2299 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2300 ; CHECKIZHINXMIN-NEXT: .LBB18_2:
2301 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2302 ; CHECKIZHINXMIN-NEXT: ret
2303 %1 = call half @llvm.ceil.f16(half %a)
2304 ret half %1
2305 }
2307 declare half @llvm.trunc.f16(half)
2309 define half @trunc_f16(half %a) nounwind {
2310 ; CHECKIZFH-LABEL: trunc_f16:
2311 ; CHECKIZFH: # %bb.0:
2312 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI19_0)
2313 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
2314 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2315 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2316 ; CHECKIZFH-NEXT: beqz a0, .LBB19_2
2317 ; CHECKIZFH-NEXT: # %bb.1:
2318 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
2319 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rtz
2320 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2321 ; CHECKIZFH-NEXT: .LBB19_2:
2322 ; CHECKIZFH-NEXT: ret
2323 ;
2324 ; CHECKIZHINX-LABEL: trunc_f16:
2325 ; CHECKIZHINX: # %bb.0:
2326 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI19_0)
2327 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
2328 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2329 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2330 ; CHECKIZHINX-NEXT: beqz a1, .LBB19_2
2331 ; CHECKIZHINX-NEXT: # %bb.1:
2332 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2333 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
2334 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2335 ; CHECKIZHINX-NEXT: .LBB19_2:
2336 ; CHECKIZHINX-NEXT: ret
2337 ;
2338 ; RV32I-LABEL: trunc_f16:
2339 ; RV32I: # %bb.0:
2340 ; RV32I-NEXT: addi sp, sp, -16
2341 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2342 ; RV32I-NEXT: slli a0, a0, 16
2343 ; RV32I-NEXT: srli a0, a0, 16
2344 ; RV32I-NEXT: call __extendhfsf2
2345 ; RV32I-NEXT: call truncf
2346 ; RV32I-NEXT: call __truncsfhf2
2347 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2348 ; RV32I-NEXT: addi sp, sp, 16
2349 ; RV32I-NEXT: ret
2350 ;
2351 ; RV64I-LABEL: trunc_f16:
2352 ; RV64I: # %bb.0:
2353 ; RV64I-NEXT: addi sp, sp, -16
2354 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2355 ; RV64I-NEXT: slli a0, a0, 48
2356 ; RV64I-NEXT: srli a0, a0, 48
2357 ; RV64I-NEXT: call __extendhfsf2
2358 ; RV64I-NEXT: call truncf
2359 ; RV64I-NEXT: call __truncsfhf2
2360 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2361 ; RV64I-NEXT: addi sp, sp, 16
2362 ; RV64I-NEXT: ret
2363 ;
2364 ; CHECKIZFHMIN-LABEL: trunc_f16:
2365 ; CHECKIZFHMIN: # %bb.0:
2366 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2367 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2368 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2369 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2370 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2371 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB19_2
2372 ; CHECKIZFHMIN-NEXT: # %bb.1:
2373 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2374 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2375 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2376 ; CHECKIZFHMIN-NEXT: .LBB19_2:
2377 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2378 ; CHECKIZFHMIN-NEXT: ret
2379 ;
2380 ; CHECKIZHINXMIN-LABEL: trunc_f16:
2381 ; CHECKIZHINXMIN: # %bb.0:
2382 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2383 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2384 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2385 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2386 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB19_2
2387 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2388 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2389 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2390 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2391 ; CHECKIZHINXMIN-NEXT: .LBB19_2:
2392 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2393 ; CHECKIZHINXMIN-NEXT: ret
2394 %1 = call half @llvm.trunc.f16(half %a)
2395 ret half %1
2396 }
2398 declare half @llvm.rint.f16(half)
2400 define half @rint_f16(half %a) nounwind {
2401 ; CHECKIZFH-LABEL: rint_f16:
2402 ; CHECKIZFH: # %bb.0:
2403 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI20_0)
2404 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
2405 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2406 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2407 ; CHECKIZFH-NEXT: beqz a0, .LBB20_2
2408 ; CHECKIZFH-NEXT: # %bb.1:
2409 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0
2410 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0
2411 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2412 ; CHECKIZFH-NEXT: .LBB20_2:
2413 ; CHECKIZFH-NEXT: ret
2414 ;
2415 ; CHECKIZHINX-LABEL: rint_f16:
2416 ; CHECKIZHINX: # %bb.0:
2417 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI20_0)
2418 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
2419 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2420 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2421 ; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
2422 ; CHECKIZHINX-NEXT: # %bb.1:
2423 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0
2424 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1
2425 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2426 ; CHECKIZHINX-NEXT: .LBB20_2:
2427 ; CHECKIZHINX-NEXT: ret
2428 ;
2429 ; RV32I-LABEL: rint_f16:
2430 ; RV32I: # %bb.0:
2431 ; RV32I-NEXT: addi sp, sp, -16
2432 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2433 ; RV32I-NEXT: slli a0, a0, 16
2434 ; RV32I-NEXT: srli a0, a0, 16
2435 ; RV32I-NEXT: call __extendhfsf2
2436 ; RV32I-NEXT: call rintf
2437 ; RV32I-NEXT: call __truncsfhf2
2438 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2439 ; RV32I-NEXT: addi sp, sp, 16
2440 ; RV32I-NEXT: ret
2441 ;
2442 ; RV64I-LABEL: rint_f16:
2443 ; RV64I: # %bb.0:
2444 ; RV64I-NEXT: addi sp, sp, -16
2445 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2446 ; RV64I-NEXT: slli a0, a0, 48
2447 ; RV64I-NEXT: srli a0, a0, 48
2448 ; RV64I-NEXT: call __extendhfsf2
2449 ; RV64I-NEXT: call rintf
2450 ; RV64I-NEXT: call __truncsfhf2
2451 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2452 ; RV64I-NEXT: addi sp, sp, 16
2453 ; RV64I-NEXT: ret
2454 ;
2455 ; CHECKIZFHMIN-LABEL: rint_f16:
2456 ; CHECKIZFHMIN: # %bb.0:
2457 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2458 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2459 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2460 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2461 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2462 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB20_2
2463 ; CHECKIZFHMIN-NEXT: # %bb.1:
2464 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5
2465 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0
2466 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2467 ; CHECKIZFHMIN-NEXT: .LBB20_2:
2468 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2469 ; CHECKIZFHMIN-NEXT: ret
2470 ;
2471 ; CHECKIZHINXMIN-LABEL: rint_f16:
2472 ; CHECKIZHINXMIN: # %bb.0:
2473 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2474 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2475 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2476 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2477 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB20_2
2478 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2479 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0
2480 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1
2481 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2482 ; CHECKIZHINXMIN-NEXT: .LBB20_2:
2483 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2484 ; CHECKIZHINXMIN-NEXT: ret
2485 %1 = call half @llvm.rint.f16(half %a)
2486 ret half %1
2487 }
2489 declare half @llvm.nearbyint.f16(half)
2491 define half @nearbyint_f16(half %a) nounwind {
2492 ; RV32IZFH-LABEL: nearbyint_f16:
2493 ; RV32IZFH: # %bb.0:
2494 ; RV32IZFH-NEXT: addi sp, sp, -16
2495 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2496 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
2497 ; RV32IZFH-NEXT: call nearbyintf
2498 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
2499 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2500 ; RV32IZFH-NEXT: addi sp, sp, 16
2501 ; RV32IZFH-NEXT: ret
2502 ;
2503 ; RV64IZFH-LABEL: nearbyint_f16:
2504 ; RV64IZFH: # %bb.0:
2505 ; RV64IZFH-NEXT: addi sp, sp, -16
2506 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2507 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
2508 ; RV64IZFH-NEXT: call nearbyintf
2509 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
2510 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2511 ; RV64IZFH-NEXT: addi sp, sp, 16
2512 ; RV64IZFH-NEXT: ret
2513 ;
2514 ; RV32IZHINX-LABEL: nearbyint_f16:
2515 ; RV32IZHINX: # %bb.0:
2516 ; RV32IZHINX-NEXT: addi sp, sp, -16
2517 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2518 ; RV32IZHINX-NEXT: fcvt.s.h a0, a0
2519 ; RV32IZHINX-NEXT: call nearbyintf
2520 ; RV32IZHINX-NEXT: fcvt.h.s a0, a0
2521 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2522 ; RV32IZHINX-NEXT: addi sp, sp, 16
2523 ; RV32IZHINX-NEXT: ret
2524 ;
2525 ; RV64IZHINX-LABEL: nearbyint_f16:
2526 ; RV64IZHINX: # %bb.0:
2527 ; RV64IZHINX-NEXT: addi sp, sp, -16
2528 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2529 ; RV64IZHINX-NEXT: fcvt.s.h a0, a0
2530 ; RV64IZHINX-NEXT: call nearbyintf
2531 ; RV64IZHINX-NEXT: fcvt.h.s a0, a0
2532 ; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2533 ; RV64IZHINX-NEXT: addi sp, sp, 16
2534 ; RV64IZHINX-NEXT: ret
2535 ;
2536 ; RV32I-LABEL: nearbyint_f16:
2537 ; RV32I: # %bb.0:
2538 ; RV32I-NEXT: addi sp, sp, -16
2539 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2540 ; RV32I-NEXT: slli a0, a0, 16
2541 ; RV32I-NEXT: srli a0, a0, 16
2542 ; RV32I-NEXT: call __extendhfsf2
2543 ; RV32I-NEXT: call nearbyintf
2544 ; RV32I-NEXT: call __truncsfhf2
2545 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2546 ; RV32I-NEXT: addi sp, sp, 16
2547 ; RV32I-NEXT: ret
2548 ;
2549 ; RV64I-LABEL: nearbyint_f16:
2550 ; RV64I: # %bb.0:
2551 ; RV64I-NEXT: addi sp, sp, -16
2552 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2553 ; RV64I-NEXT: slli a0, a0, 48
2554 ; RV64I-NEXT: srli a0, a0, 48
2555 ; RV64I-NEXT: call __extendhfsf2
2556 ; RV64I-NEXT: call nearbyintf
2557 ; RV64I-NEXT: call __truncsfhf2
2558 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2559 ; RV64I-NEXT: addi sp, sp, 16
2560 ; RV64I-NEXT: ret
2561 ;
2562 ; RV32IZFHMIN-LABEL: nearbyint_f16:
2563 ; RV32IZFHMIN: # %bb.0:
2564 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2565 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2566 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
2567 ; RV32IZFHMIN-NEXT: call nearbyintf
2568 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
2569 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2570 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2571 ; RV32IZFHMIN-NEXT: ret
2572 ;
2573 ; RV64IZFHMIN-LABEL: nearbyint_f16:
2574 ; RV64IZFHMIN: # %bb.0:
2575 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
2576 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2577 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
2578 ; RV64IZFHMIN-NEXT: call nearbyintf
2579 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
2580 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2581 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
2582 ; RV64IZFHMIN-NEXT: ret
2583 ;
2584 ; RV32IZHINXMIN-LABEL: nearbyint_f16:
2585 ; RV32IZHINXMIN: # %bb.0:
2586 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2587 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2588 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2589 ; RV32IZHINXMIN-NEXT: call nearbyintf
2590 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2591 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2592 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2593 ; RV32IZHINXMIN-NEXT: ret
2594 ;
2595 ; RV64IZHINXMIN-LABEL: nearbyint_f16:
2596 ; RV64IZHINXMIN: # %bb.0:
2597 ; RV64IZHINXMIN-NEXT: addi sp, sp, -16
2598 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2599 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2600 ; RV64IZHINXMIN-NEXT: call nearbyintf
2601 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2602 ; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2603 ; RV64IZHINXMIN-NEXT: addi sp, sp, 16
2604 ; RV64IZHINXMIN-NEXT: ret
2605 %1 = call half @llvm.nearbyint.f16(half %a)
2606 ret half %1
2607 }
2609 declare half @llvm.round.f16(half)
2611 define half @round_f16(half %a) nounwind {
2612 ; CHECKIZFH-LABEL: round_f16:
2613 ; CHECKIZFH: # %bb.0:
2614 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI22_0)
2615 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
2616 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2617 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2618 ; CHECKIZFH-NEXT: beqz a0, .LBB22_2
2619 ; CHECKIZFH-NEXT: # %bb.1:
2620 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
2621 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rmm
2622 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2623 ; CHECKIZFH-NEXT: .LBB22_2:
2624 ; CHECKIZFH-NEXT: ret
2625 ;
2626 ; CHECKIZHINX-LABEL: round_f16:
2627 ; CHECKIZHINX: # %bb.0:
2628 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI22_0)
2629 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
2630 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2631 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2632 ; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
2633 ; CHECKIZHINX-NEXT: # %bb.1:
2634 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
2635 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
2636 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2637 ; CHECKIZHINX-NEXT: .LBB22_2:
2638 ; CHECKIZHINX-NEXT: ret
2639 ;
2640 ; RV32I-LABEL: round_f16:
2641 ; RV32I: # %bb.0:
2642 ; RV32I-NEXT: addi sp, sp, -16
2643 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2644 ; RV32I-NEXT: slli a0, a0, 16
2645 ; RV32I-NEXT: srli a0, a0, 16
2646 ; RV32I-NEXT: call __extendhfsf2
2647 ; RV32I-NEXT: call roundf
2648 ; RV32I-NEXT: call __truncsfhf2
2649 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2650 ; RV32I-NEXT: addi sp, sp, 16
2651 ; RV32I-NEXT: ret
2652 ;
2653 ; RV64I-LABEL: round_f16:
2654 ; RV64I: # %bb.0:
2655 ; RV64I-NEXT: addi sp, sp, -16
2656 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2657 ; RV64I-NEXT: slli a0, a0, 48
2658 ; RV64I-NEXT: srli a0, a0, 48
2659 ; RV64I-NEXT: call __extendhfsf2
2660 ; RV64I-NEXT: call roundf
2661 ; RV64I-NEXT: call __truncsfhf2
2662 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2663 ; RV64I-NEXT: addi sp, sp, 16
2664 ; RV64I-NEXT: ret
2665 ;
2666 ; CHECKIZFHMIN-LABEL: round_f16:
2667 ; CHECKIZFHMIN: # %bb.0:
2668 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2669 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2670 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2671 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2672 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2673 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB22_2
2674 ; CHECKIZFHMIN-NEXT: # %bb.1:
2675 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2676 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2677 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2678 ; CHECKIZFHMIN-NEXT: .LBB22_2:
2679 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2680 ; CHECKIZFHMIN-NEXT: ret
2681 ;
2682 ; CHECKIZHINXMIN-LABEL: round_f16:
2683 ; CHECKIZHINXMIN: # %bb.0:
2684 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2685 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2686 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2687 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2688 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB22_2
2689 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2690 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2691 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2692 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2693 ; CHECKIZHINXMIN-NEXT: .LBB22_2:
2694 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2695 ; CHECKIZHINXMIN-NEXT: ret
2696 %1 = call half @llvm.round.f16(half %a)
2697 ret half %1
2698 }
2700 declare half @llvm.roundeven.f16(half)
2702 define half @roundeven_f16(half %a) nounwind {
2703 ; CHECKIZFH-LABEL: roundeven_f16:
2704 ; CHECKIZFH: # %bb.0:
2705 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI23_0)
2706 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
2707 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
2708 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
2709 ; CHECKIZFH-NEXT: beqz a0, .LBB23_2
2710 ; CHECKIZFH-NEXT: # %bb.1:
2711 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
2712 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rne
2713 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
2714 ; CHECKIZFH-NEXT: .LBB23_2:
2715 ; CHECKIZFH-NEXT: ret
2716 ;
2717 ; CHECKIZHINX-LABEL: roundeven_f16:
2718 ; CHECKIZHINX: # %bb.0:
2719 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI23_0)
2720 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
2721 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2722 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2723 ; CHECKIZHINX-NEXT: beqz a1, .LBB23_2
2724 ; CHECKIZHINX-NEXT: # %bb.1:
2725 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
2726 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
2727 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2728 ; CHECKIZHINX-NEXT: .LBB23_2:
2729 ; CHECKIZHINX-NEXT: ret
2730 ;
2731 ; RV32I-LABEL: roundeven_f16:
2732 ; RV32I: # %bb.0:
2733 ; RV32I-NEXT: addi sp, sp, -16
2734 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2735 ; RV32I-NEXT: slli a0, a0, 16
2736 ; RV32I-NEXT: srli a0, a0, 16
2737 ; RV32I-NEXT: call __extendhfsf2
2738 ; RV32I-NEXT: call roundevenf
2739 ; RV32I-NEXT: call __truncsfhf2
2740 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2741 ; RV32I-NEXT: addi sp, sp, 16
2742 ; RV32I-NEXT: ret
2743 ;
2744 ; RV64I-LABEL: roundeven_f16:
2745 ; RV64I: # %bb.0:
2746 ; RV64I-NEXT: addi sp, sp, -16
2747 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2748 ; RV64I-NEXT: slli a0, a0, 48
2749 ; RV64I-NEXT: srli a0, a0, 48
2750 ; RV64I-NEXT: call __extendhfsf2
2751 ; RV64I-NEXT: call roundevenf
2752 ; RV64I-NEXT: call __truncsfhf2
2753 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2754 ; RV64I-NEXT: addi sp, sp, 16
2755 ; RV64I-NEXT: ret
2756 ;
2757 ; CHECKIZFHMIN-LABEL: roundeven_f16:
2758 ; CHECKIZFHMIN: # %bb.0:
2759 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2760 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2761 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2762 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2763 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2764 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB23_2
2765 ; CHECKIZFHMIN-NEXT: # %bb.1:
2766 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
2767 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
2768 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2769 ; CHECKIZFHMIN-NEXT: .LBB23_2:
2770 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
2771 ; CHECKIZFHMIN-NEXT: ret
2772 ;
2773 ; CHECKIZHINXMIN-LABEL: roundeven_f16:
2774 ; CHECKIZHINXMIN: # %bb.0:
2775 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2776 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2777 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2778 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2779 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB23_2
2780 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2781 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
2782 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
2783 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2784 ; CHECKIZHINXMIN-NEXT: .LBB23_2:
2785 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2786 ; CHECKIZHINXMIN-NEXT: ret
2787 %1 = call half @llvm.roundeven.f16(half %a)
2788 ret half %1
2789 }
2791 declare i1 @llvm.is.fpclass.f16(half, i32)
2792 define i1 @isnan_d_fpclass(half %x) {
2793 ; CHECKIZFH-LABEL: isnan_d_fpclass:
2794 ; CHECKIZFH: # %bb.0:
2795 ; CHECKIZFH-NEXT: fclass.h a0, fa0
2796 ; CHECKIZFH-NEXT: andi a0, a0, 768
2797 ; CHECKIZFH-NEXT: snez a0, a0
2798 ; CHECKIZFH-NEXT: ret
2799 ;
2800 ; CHECKIZHINX-LABEL: isnan_d_fpclass:
2801 ; CHECKIZHINX: # %bb.0:
2802 ; CHECKIZHINX-NEXT: fclass.h a0, a0
2803 ; CHECKIZHINX-NEXT: andi a0, a0, 768
2804 ; CHECKIZHINX-NEXT: snez a0, a0
2805 ; CHECKIZHINX-NEXT: ret
2806 ;
2807 ; RV32I-LABEL: isnan_d_fpclass:
2808 ; RV32I: # %bb.0:
2809 ; RV32I-NEXT: slli a0, a0, 17
2810 ; RV32I-NEXT: srli a0, a0, 17
2811 ; RV32I-NEXT: li a1, 31
2812 ; RV32I-NEXT: slli a1, a1, 10
2813 ; RV32I-NEXT: slt a0, a1, a0
2814 ; RV32I-NEXT: ret
2815 ;
2816 ; RV64I-LABEL: isnan_d_fpclass:
2817 ; RV64I: # %bb.0:
2818 ; RV64I-NEXT: slli a0, a0, 49
2819 ; RV64I-NEXT: srli a0, a0, 49
2820 ; RV64I-NEXT: li a1, 31
2821 ; RV64I-NEXT: slli a1, a1, 10
2822 ; RV64I-NEXT: slt a0, a1, a0
2823 ; RV64I-NEXT: ret
2824 ;
2825 ; RV32IZFHMIN-LABEL: isnan_d_fpclass:
2826 ; RV32IZFHMIN: # %bb.0:
2827 ; RV32IZFHMIN-NEXT: fmv.x.h a0, fa0
2828 ; RV32IZFHMIN-NEXT: slli a0, a0, 17
2829 ; RV32IZFHMIN-NEXT: srli a0, a0, 17
2830 ; RV32IZFHMIN-NEXT: li a1, 31
2831 ; RV32IZFHMIN-NEXT: slli a1, a1, 10
2832 ; RV32IZFHMIN-NEXT: slt a0, a1, a0
2833 ; RV32IZFHMIN-NEXT: ret
2834 ;
2835 ; RV64IZFHMIN-LABEL: isnan_d_fpclass:
2836 ; RV64IZFHMIN: # %bb.0:
2837 ; RV64IZFHMIN-NEXT: fmv.x.h a0, fa0
2838 ; RV64IZFHMIN-NEXT: slli a0, a0, 49
2839 ; RV64IZFHMIN-NEXT: srli a0, a0, 49
2840 ; RV64IZFHMIN-NEXT: li a1, 31
2841 ; RV64IZFHMIN-NEXT: slli a1, a1, 10
2842 ; RV64IZFHMIN-NEXT: slt a0, a1, a0
2843 ; RV64IZFHMIN-NEXT: ret
2844 ;
2845 ; RV32IZHINXMIN-LABEL: isnan_d_fpclass:
2846 ; RV32IZHINXMIN: # %bb.0:
2847 ; RV32IZHINXMIN-NEXT: slli a0, a0, 17
2848 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17
2849 ; RV32IZHINXMIN-NEXT: li a1, 31
2850 ; RV32IZHINXMIN-NEXT: slli a1, a1, 10
2851 ; RV32IZHINXMIN-NEXT: slt a0, a1, a0
2852 ; RV32IZHINXMIN-NEXT: ret
2853 ;
2854 ; RV64IZHINXMIN-LABEL: isnan_d_fpclass:
2855 ; RV64IZHINXMIN: # %bb.0:
2856 ; RV64IZHINXMIN-NEXT: slli a0, a0, 49
2857 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49
2858 ; RV64IZHINXMIN-NEXT: li a1, 31
2859 ; RV64IZHINXMIN-NEXT: slli a1, a1, 10
2860 ; RV64IZHINXMIN-NEXT: slt a0, a1, a0
2861 ; RV64IZHINXMIN-NEXT: ret
2862 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
2863 ret i1 %1
2864 }