| blob | 0e4030049e919c97fcc53a82ed9aca01a008fdd3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
5 ; RUN: -target-abi lp64f < %s | FileCheck %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
7 ; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
9 ; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
10 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
11 ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
13 ; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
14 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
15 ; RUN: -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZHINXMIN %s
16 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
17 ; RUN: -target-abi=lp64 | FileCheck -check-prefix=CHECKIZHINXMIN %s
19 define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
20 ; CHECK-LABEL: select_icmp_eq:
21 ; CHECK: # %bb.0:
22 ; CHECK-NEXT: beq a0, a1, .LBB0_2
23 ; CHECK-NEXT: # %bb.1:
24 ; CHECK-NEXT: fmv.h fa0, fa1
25 ; CHECK-NEXT: .LBB0_2:
26 ; CHECK-NEXT: ret
27 ;
28 ; CHECKIZHINX-LABEL: select_icmp_eq:
29 ; CHECKIZHINX: # %bb.0:
30 ; CHECKIZHINX-NEXT: beq a0, a1, .LBB0_2
31 ; CHECKIZHINX-NEXT: # %bb.1:
32 ; CHECKIZHINX-NEXT: mv a2, a3
33 ; CHECKIZHINX-NEXT: .LBB0_2:
34 ; CHECKIZHINX-NEXT: mv a0, a2
35 ; CHECKIZHINX-NEXT: ret
36 ;
37 ; CHECKIZFHMIN-LABEL: select_icmp_eq:
38 ; CHECKIZFHMIN: # %bb.0:
39 ; CHECKIZFHMIN-NEXT: beq a0, a1, .LBB0_2
40 ; CHECKIZFHMIN-NEXT: # %bb.1:
41 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
42 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
43 ; CHECKIZFHMIN-NEXT: ret
44 ; CHECKIZFHMIN-NEXT: .LBB0_2:
45 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
46 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
47 ; CHECKIZFHMIN-NEXT: ret
48 ;
49 ; CHECKIZHINXMIN-LABEL: select_icmp_eq:
50 ; CHECKIZHINXMIN: # %bb.0:
51 ; CHECKIZHINXMIN-NEXT: beq a0, a1, .LBB0_2
52 ; CHECKIZHINXMIN-NEXT: # %bb.1:
53 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
54 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
55 ; CHECKIZHINXMIN-NEXT: ret
56 ; CHECKIZHINXMIN-NEXT: .LBB0_2:
57 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
58 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
59 ; CHECKIZHINXMIN-NEXT: ret
60 %1 = icmp eq i32 %a, %b
61 %2 = select i1 %1, half %c, half %d
62 ret half %2
63 }
65 define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
66 ; CHECK-LABEL: select_icmp_ne:
67 ; CHECK: # %bb.0:
68 ; CHECK-NEXT: bne a0, a1, .LBB1_2
69 ; CHECK-NEXT: # %bb.1:
70 ; CHECK-NEXT: fmv.h fa0, fa1
71 ; CHECK-NEXT: .LBB1_2:
72 ; CHECK-NEXT: ret
73 ;
74 ; CHECKIZHINX-LABEL: select_icmp_ne:
75 ; CHECKIZHINX: # %bb.0:
76 ; CHECKIZHINX-NEXT: bne a0, a1, .LBB1_2
77 ; CHECKIZHINX-NEXT: # %bb.1:
78 ; CHECKIZHINX-NEXT: mv a2, a3
79 ; CHECKIZHINX-NEXT: .LBB1_2:
80 ; CHECKIZHINX-NEXT: mv a0, a2
81 ; CHECKIZHINX-NEXT: ret
82 ;
83 ; CHECKIZFHMIN-LABEL: select_icmp_ne:
84 ; CHECKIZFHMIN: # %bb.0:
85 ; CHECKIZFHMIN-NEXT: bne a0, a1, .LBB1_2
86 ; CHECKIZFHMIN-NEXT: # %bb.1:
87 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
88 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
89 ; CHECKIZFHMIN-NEXT: ret
90 ; CHECKIZFHMIN-NEXT: .LBB1_2:
91 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
92 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
93 ; CHECKIZFHMIN-NEXT: ret
94 ;
95 ; CHECKIZHINXMIN-LABEL: select_icmp_ne:
96 ; CHECKIZHINXMIN: # %bb.0:
97 ; CHECKIZHINXMIN-NEXT: bne a0, a1, .LBB1_2
98 ; CHECKIZHINXMIN-NEXT: # %bb.1:
99 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
100 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
101 ; CHECKIZHINXMIN-NEXT: ret
102 ; CHECKIZHINXMIN-NEXT: .LBB1_2:
103 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
104 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
105 ; CHECKIZHINXMIN-NEXT: ret
106 %1 = icmp ne i32 %a, %b
107 %2 = select i1 %1, half %c, half %d
108 ret half %2
109 }
111 define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
112 ; CHECK-LABEL: select_icmp_ugt:
113 ; CHECK: # %bb.0:
114 ; CHECK-NEXT: bltu a1, a0, .LBB2_2
115 ; CHECK-NEXT: # %bb.1:
116 ; CHECK-NEXT: fmv.h fa0, fa1
117 ; CHECK-NEXT: .LBB2_2:
118 ; CHECK-NEXT: ret
119 ;
120 ; CHECKIZHINX-LABEL: select_icmp_ugt:
121 ; CHECKIZHINX: # %bb.0:
122 ; CHECKIZHINX-NEXT: bltu a1, a0, .LBB2_2
123 ; CHECKIZHINX-NEXT: # %bb.1:
124 ; CHECKIZHINX-NEXT: mv a2, a3
125 ; CHECKIZHINX-NEXT: .LBB2_2:
126 ; CHECKIZHINX-NEXT: mv a0, a2
127 ; CHECKIZHINX-NEXT: ret
128 ;
129 ; CHECKIZFHMIN-LABEL: select_icmp_ugt:
130 ; CHECKIZFHMIN: # %bb.0:
131 ; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB2_2
132 ; CHECKIZFHMIN-NEXT: # %bb.1:
133 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
134 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
135 ; CHECKIZFHMIN-NEXT: ret
136 ; CHECKIZFHMIN-NEXT: .LBB2_2:
137 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
138 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
139 ; CHECKIZFHMIN-NEXT: ret
140 ;
141 ; CHECKIZHINXMIN-LABEL: select_icmp_ugt:
142 ; CHECKIZHINXMIN: # %bb.0:
143 ; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB2_2
144 ; CHECKIZHINXMIN-NEXT: # %bb.1:
145 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
146 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
147 ; CHECKIZHINXMIN-NEXT: ret
148 ; CHECKIZHINXMIN-NEXT: .LBB2_2:
149 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
150 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
151 ; CHECKIZHINXMIN-NEXT: ret
152 %1 = icmp ugt i32 %a, %b
153 %2 = select i1 %1, half %c, half %d
154 ret half %2
155 }
157 define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
158 ; CHECK-LABEL: select_icmp_uge:
159 ; CHECK: # %bb.0:
160 ; CHECK-NEXT: bgeu a0, a1, .LBB3_2
161 ; CHECK-NEXT: # %bb.1:
162 ; CHECK-NEXT: fmv.h fa0, fa1
163 ; CHECK-NEXT: .LBB3_2:
164 ; CHECK-NEXT: ret
165 ;
166 ; CHECKIZHINX-LABEL: select_icmp_uge:
167 ; CHECKIZHINX: # %bb.0:
168 ; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2
169 ; CHECKIZHINX-NEXT: # %bb.1:
170 ; CHECKIZHINX-NEXT: mv a2, a3
171 ; CHECKIZHINX-NEXT: .LBB3_2:
172 ; CHECKIZHINX-NEXT: mv a0, a2
173 ; CHECKIZHINX-NEXT: ret
174 ;
175 ; CHECKIZFHMIN-LABEL: select_icmp_uge:
176 ; CHECKIZFHMIN: # %bb.0:
177 ; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2
178 ; CHECKIZFHMIN-NEXT: # %bb.1:
179 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
180 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
181 ; CHECKIZFHMIN-NEXT: ret
182 ; CHECKIZFHMIN-NEXT: .LBB3_2:
183 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
184 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
185 ; CHECKIZFHMIN-NEXT: ret
186 ;
187 ; CHECKIZHINXMIN-LABEL: select_icmp_uge:
188 ; CHECKIZHINXMIN: # %bb.0:
189 ; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2
190 ; CHECKIZHINXMIN-NEXT: # %bb.1:
191 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
192 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
193 ; CHECKIZHINXMIN-NEXT: ret
194 ; CHECKIZHINXMIN-NEXT: .LBB3_2:
195 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
196 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
197 ; CHECKIZHINXMIN-NEXT: ret
198 %1 = icmp uge i32 %a, %b
199 %2 = select i1 %1, half %c, half %d
200 ret half %2
201 }
203 define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
204 ; CHECK-LABEL: select_icmp_ult:
205 ; CHECK: # %bb.0:
206 ; CHECK-NEXT: bltu a0, a1, .LBB4_2
207 ; CHECK-NEXT: # %bb.1:
208 ; CHECK-NEXT: fmv.h fa0, fa1
209 ; CHECK-NEXT: .LBB4_2:
210 ; CHECK-NEXT: ret
211 ;
212 ; CHECKIZHINX-LABEL: select_icmp_ult:
213 ; CHECKIZHINX: # %bb.0:
214 ; CHECKIZHINX-NEXT: bltu a0, a1, .LBB4_2
215 ; CHECKIZHINX-NEXT: # %bb.1:
216 ; CHECKIZHINX-NEXT: mv a2, a3
217 ; CHECKIZHINX-NEXT: .LBB4_2:
218 ; CHECKIZHINX-NEXT: mv a0, a2
219 ; CHECKIZHINX-NEXT: ret
220 ;
221 ; CHECKIZFHMIN-LABEL: select_icmp_ult:
222 ; CHECKIZFHMIN: # %bb.0:
223 ; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB4_2
224 ; CHECKIZFHMIN-NEXT: # %bb.1:
225 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
226 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
227 ; CHECKIZFHMIN-NEXT: ret
228 ; CHECKIZFHMIN-NEXT: .LBB4_2:
229 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
230 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
231 ; CHECKIZFHMIN-NEXT: ret
232 ;
233 ; CHECKIZHINXMIN-LABEL: select_icmp_ult:
234 ; CHECKIZHINXMIN: # %bb.0:
235 ; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB4_2
236 ; CHECKIZHINXMIN-NEXT: # %bb.1:
237 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
238 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
239 ; CHECKIZHINXMIN-NEXT: ret
240 ; CHECKIZHINXMIN-NEXT: .LBB4_2:
241 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
242 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
243 ; CHECKIZHINXMIN-NEXT: ret
244 %1 = icmp ult i32 %a, %b
245 %2 = select i1 %1, half %c, half %d
246 ret half %2
247 }
249 define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
250 ; CHECK-LABEL: select_icmp_ule:
251 ; CHECK: # %bb.0:
252 ; CHECK-NEXT: bgeu a1, a0, .LBB5_2
253 ; CHECK-NEXT: # %bb.1:
254 ; CHECK-NEXT: fmv.h fa0, fa1
255 ; CHECK-NEXT: .LBB5_2:
256 ; CHECK-NEXT: ret
257 ;
258 ; CHECKIZHINX-LABEL: select_icmp_ule:
259 ; CHECKIZHINX: # %bb.0:
260 ; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2
261 ; CHECKIZHINX-NEXT: # %bb.1:
262 ; CHECKIZHINX-NEXT: mv a2, a3
263 ; CHECKIZHINX-NEXT: .LBB5_2:
264 ; CHECKIZHINX-NEXT: mv a0, a2
265 ; CHECKIZHINX-NEXT: ret
266 ;
267 ; CHECKIZFHMIN-LABEL: select_icmp_ule:
268 ; CHECKIZFHMIN: # %bb.0:
269 ; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2
270 ; CHECKIZFHMIN-NEXT: # %bb.1:
271 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
272 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
273 ; CHECKIZFHMIN-NEXT: ret
274 ; CHECKIZFHMIN-NEXT: .LBB5_2:
275 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
276 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
277 ; CHECKIZFHMIN-NEXT: ret
278 ;
279 ; CHECKIZHINXMIN-LABEL: select_icmp_ule:
280 ; CHECKIZHINXMIN: # %bb.0:
281 ; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2
282 ; CHECKIZHINXMIN-NEXT: # %bb.1:
283 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
284 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
285 ; CHECKIZHINXMIN-NEXT: ret
286 ; CHECKIZHINXMIN-NEXT: .LBB5_2:
287 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
288 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
289 ; CHECKIZHINXMIN-NEXT: ret
290 %1 = icmp ule i32 %a, %b
291 %2 = select i1 %1, half %c, half %d
292 ret half %2
293 }
295 define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
296 ; CHECK-LABEL: select_icmp_sgt:
297 ; CHECK: # %bb.0:
298 ; CHECK-NEXT: blt a1, a0, .LBB6_2
299 ; CHECK-NEXT: # %bb.1:
300 ; CHECK-NEXT: fmv.h fa0, fa1
301 ; CHECK-NEXT: .LBB6_2:
302 ; CHECK-NEXT: ret
303 ;
304 ; CHECKIZHINX-LABEL: select_icmp_sgt:
305 ; CHECKIZHINX: # %bb.0:
306 ; CHECKIZHINX-NEXT: blt a1, a0, .LBB6_2
307 ; CHECKIZHINX-NEXT: # %bb.1:
308 ; CHECKIZHINX-NEXT: mv a2, a3
309 ; CHECKIZHINX-NEXT: .LBB6_2:
310 ; CHECKIZHINX-NEXT: mv a0, a2
311 ; CHECKIZHINX-NEXT: ret
312 ;
313 ; CHECKIZFHMIN-LABEL: select_icmp_sgt:
314 ; CHECKIZFHMIN: # %bb.0:
315 ; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB6_2
316 ; CHECKIZFHMIN-NEXT: # %bb.1:
317 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
318 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
319 ; CHECKIZFHMIN-NEXT: ret
320 ; CHECKIZFHMIN-NEXT: .LBB6_2:
321 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
322 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
323 ; CHECKIZFHMIN-NEXT: ret
324 ;
325 ; CHECKIZHINXMIN-LABEL: select_icmp_sgt:
326 ; CHECKIZHINXMIN: # %bb.0:
327 ; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB6_2
328 ; CHECKIZHINXMIN-NEXT: # %bb.1:
329 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
330 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
331 ; CHECKIZHINXMIN-NEXT: ret
332 ; CHECKIZHINXMIN-NEXT: .LBB6_2:
333 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
334 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
335 ; CHECKIZHINXMIN-NEXT: ret
336 %1 = icmp sgt i32 %a, %b
337 %2 = select i1 %1, half %c, half %d
338 ret half %2
339 }
341 define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
342 ; CHECK-LABEL: select_icmp_sge:
343 ; CHECK: # %bb.0:
344 ; CHECK-NEXT: bge a0, a1, .LBB7_2
345 ; CHECK-NEXT: # %bb.1:
346 ; CHECK-NEXT: fmv.h fa0, fa1
347 ; CHECK-NEXT: .LBB7_2:
348 ; CHECK-NEXT: ret
349 ;
350 ; CHECKIZHINX-LABEL: select_icmp_sge:
351 ; CHECKIZHINX: # %bb.0:
352 ; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2
353 ; CHECKIZHINX-NEXT: # %bb.1:
354 ; CHECKIZHINX-NEXT: mv a2, a3
355 ; CHECKIZHINX-NEXT: .LBB7_2:
356 ; CHECKIZHINX-NEXT: mv a0, a2
357 ; CHECKIZHINX-NEXT: ret
358 ;
359 ; CHECKIZFHMIN-LABEL: select_icmp_sge:
360 ; CHECKIZFHMIN: # %bb.0:
361 ; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2
362 ; CHECKIZFHMIN-NEXT: # %bb.1:
363 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
364 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
365 ; CHECKIZFHMIN-NEXT: ret
366 ; CHECKIZFHMIN-NEXT: .LBB7_2:
367 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
368 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
369 ; CHECKIZFHMIN-NEXT: ret
370 ;
371 ; CHECKIZHINXMIN-LABEL: select_icmp_sge:
372 ; CHECKIZHINXMIN: # %bb.0:
373 ; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2
374 ; CHECKIZHINXMIN-NEXT: # %bb.1:
375 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
376 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
377 ; CHECKIZHINXMIN-NEXT: ret
378 ; CHECKIZHINXMIN-NEXT: .LBB7_2:
379 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
380 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
381 ; CHECKIZHINXMIN-NEXT: ret
382 %1 = icmp sge i32 %a, %b
383 %2 = select i1 %1, half %c, half %d
384 ret half %2
385 }
387 define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
388 ; CHECK-LABEL: select_icmp_slt:
389 ; CHECK: # %bb.0:
390 ; CHECK-NEXT: blt a0, a1, .LBB8_2
391 ; CHECK-NEXT: # %bb.1:
392 ; CHECK-NEXT: fmv.h fa0, fa1
393 ; CHECK-NEXT: .LBB8_2:
394 ; CHECK-NEXT: ret
395 ;
396 ; CHECKIZHINX-LABEL: select_icmp_slt:
397 ; CHECKIZHINX: # %bb.0:
398 ; CHECKIZHINX-NEXT: blt a0, a1, .LBB8_2
399 ; CHECKIZHINX-NEXT: # %bb.1:
400 ; CHECKIZHINX-NEXT: mv a2, a3
401 ; CHECKIZHINX-NEXT: .LBB8_2:
402 ; CHECKIZHINX-NEXT: mv a0, a2
403 ; CHECKIZHINX-NEXT: ret
404 ;
405 ; CHECKIZFHMIN-LABEL: select_icmp_slt:
406 ; CHECKIZFHMIN: # %bb.0:
407 ; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB8_2
408 ; CHECKIZFHMIN-NEXT: # %bb.1:
409 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
410 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
411 ; CHECKIZFHMIN-NEXT: ret
412 ; CHECKIZFHMIN-NEXT: .LBB8_2:
413 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
414 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
415 ; CHECKIZFHMIN-NEXT: ret
416 ;
417 ; CHECKIZHINXMIN-LABEL: select_icmp_slt:
418 ; CHECKIZHINXMIN: # %bb.0:
419 ; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB8_2
420 ; CHECKIZHINXMIN-NEXT: # %bb.1:
421 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
422 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
423 ; CHECKIZHINXMIN-NEXT: ret
424 ; CHECKIZHINXMIN-NEXT: .LBB8_2:
425 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
426 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
427 ; CHECKIZHINXMIN-NEXT: ret
428 %1 = icmp slt i32 %a, %b
429 %2 = select i1 %1, half %c, half %d
430 ret half %2
431 }
433 define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
434 ; CHECK-LABEL: select_icmp_sle:
435 ; CHECK: # %bb.0:
436 ; CHECK-NEXT: bge a1, a0, .LBB9_2
437 ; CHECK-NEXT: # %bb.1:
438 ; CHECK-NEXT: fmv.h fa0, fa1
439 ; CHECK-NEXT: .LBB9_2:
440 ; CHECK-NEXT: ret
441 ;
442 ; CHECKIZHINX-LABEL: select_icmp_sle:
443 ; CHECKIZHINX: # %bb.0:
444 ; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2
445 ; CHECKIZHINX-NEXT: # %bb.1:
446 ; CHECKIZHINX-NEXT: mv a2, a3
447 ; CHECKIZHINX-NEXT: .LBB9_2:
448 ; CHECKIZHINX-NEXT: mv a0, a2
449 ; CHECKIZHINX-NEXT: ret
450 ;
451 ; CHECKIZFHMIN-LABEL: select_icmp_sle:
452 ; CHECKIZFHMIN: # %bb.0:
453 ; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2
454 ; CHECKIZFHMIN-NEXT: # %bb.1:
455 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
456 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
457 ; CHECKIZFHMIN-NEXT: ret
458 ; CHECKIZFHMIN-NEXT: .LBB9_2:
459 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
460 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
461 ; CHECKIZFHMIN-NEXT: ret
462 ;
463 ; CHECKIZHINXMIN-LABEL: select_icmp_sle:
464 ; CHECKIZHINXMIN: # %bb.0:
465 ; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2
466 ; CHECKIZHINXMIN-NEXT: # %bb.1:
467 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
468 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
469 ; CHECKIZHINXMIN-NEXT: ret
470 ; CHECKIZHINXMIN-NEXT: .LBB9_2:
471 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
472 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
473 ; CHECKIZHINXMIN-NEXT: ret
474 %1 = icmp sle i32 %a, %b
475 %2 = select i1 %1, half %c, half %d
476 ret half %2
477 }
479 define half @select_icmp_slt_one(i32 signext %a) {
480 ; CHECK-LABEL: select_icmp_slt_one:
481 ; CHECK: # %bb.0:
482 ; CHECK-NEXT: slti a0, a0, 1
483 ; CHECK-NEXT: fcvt.h.w fa0, a0
484 ; CHECK-NEXT: ret
485 ;
486 ; CHECKIZHINX-LABEL: select_icmp_slt_one:
487 ; CHECKIZHINX: # %bb.0:
488 ; CHECKIZHINX-NEXT: slti a0, a0, 1
489 ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
490 ; CHECKIZHINX-NEXT: ret
491 ;
492 ; CHECKIZFHMIN-LABEL: select_icmp_slt_one:
493 ; CHECKIZFHMIN: # %bb.0:
494 ; CHECKIZFHMIN-NEXT: slti a0, a0, 1
495 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
496 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
497 ; CHECKIZFHMIN-NEXT: ret
498 ;
499 ; CHECKIZHINXMIN-LABEL: select_icmp_slt_one:
500 ; CHECKIZHINXMIN: # %bb.0:
501 ; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
502 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
503 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
504 ; CHECKIZHINXMIN-NEXT: ret
505 %1 = icmp slt i32 %a, 1
506 %2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
507 ret half %2
508 }
510 define half @select_icmp_sgt_zero(i32 signext %a) {
511 ; CHECK-LABEL: select_icmp_sgt_zero:
512 ; CHECK: # %bb.0:
513 ; CHECK-NEXT: slti a0, a0, 1
514 ; CHECK-NEXT: fcvt.h.w fa0, a0
515 ; CHECK-NEXT: ret
516 ;
517 ; CHECKIZHINX-LABEL: select_icmp_sgt_zero:
518 ; CHECKIZHINX: # %bb.0:
519 ; CHECKIZHINX-NEXT: slti a0, a0, 1
520 ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
521 ; CHECKIZHINX-NEXT: ret
522 ;
523 ; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
524 ; CHECKIZFHMIN: # %bb.0:
525 ; CHECKIZFHMIN-NEXT: slti a0, a0, 1
526 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
527 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
528 ; CHECKIZFHMIN-NEXT: ret
529 ;
530 ; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
531 ; CHECKIZHINXMIN: # %bb.0:
532 ; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
533 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
534 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
535 ; CHECKIZHINXMIN-NEXT: ret
536 %1 = icmp sgt i32 %a, 0
537 %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
538 ret half %2
539 }