| blob | 8caf5956e7a7a736c72a1959a2e9a8d1f14de8e7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s
4 ; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s
6 ; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s
8 ; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s
11 @gh = external global half
13 define half @constraint_f_half(half %a) nounwind {
14 ; RV32ZFH-LABEL: constraint_f_half:
15 ; RV32ZFH: # %bb.0:
16 ; RV32ZFH-NEXT: lui a0, %hi(gh)
17 ; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0)
18 ; RV32ZFH-NEXT: #APP
19 ; RV32ZFH-NEXT: fadd.h fa0, fa0, fa5
20 ; RV32ZFH-NEXT: #NO_APP
21 ; RV32ZFH-NEXT: ret
22 ;
23 ; RV64ZFH-LABEL: constraint_f_half:
24 ; RV64ZFH: # %bb.0:
25 ; RV64ZFH-NEXT: lui a0, %hi(gh)
26 ; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0)
27 ; RV64ZFH-NEXT: #APP
28 ; RV64ZFH-NEXT: fadd.h fa0, fa0, fa5
29 ; RV64ZFH-NEXT: #NO_APP
30 ; RV64ZFH-NEXT: ret
31 ;
32 ; RV32DZFH-LABEL: constraint_f_half:
33 ; RV32DZFH: # %bb.0:
34 ; RV32DZFH-NEXT: lui a0, %hi(gh)
35 ; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0)
36 ; RV32DZFH-NEXT: #APP
37 ; RV32DZFH-NEXT: fadd.h fa0, fa0, fa5
38 ; RV32DZFH-NEXT: #NO_APP
39 ; RV32DZFH-NEXT: ret
40 ;
41 ; RV64DZFH-LABEL: constraint_f_half:
42 ; RV64DZFH: # %bb.0:
43 ; RV64DZFH-NEXT: lui a0, %hi(gh)
44 ; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0)
45 ; RV64DZFH-NEXT: #APP
46 ; RV64DZFH-NEXT: fadd.h fa0, fa0, fa5
47 ; RV64DZFH-NEXT: #NO_APP
48 ; RV64DZFH-NEXT: ret
49 %1 = load half, ptr @gh
50 %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)
51 ret half %2
52 }
54 define half @constraint_f_half_abi_name(half %a) nounwind {
55 ; RV32ZFH-LABEL: constraint_f_half_abi_name:
56 ; RV32ZFH: # %bb.0:
57 ; RV32ZFH-NEXT: addi sp, sp, -16
58 ; RV32ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
59 ; RV32ZFH-NEXT: lui a0, %hi(gh)
60 ; RV32ZFH-NEXT: flh fs0, %lo(gh)(a0)
61 ; RV32ZFH-NEXT: #APP
62 ; RV32ZFH-NEXT: fadd.s ft0, fa0, fs0
63 ; RV32ZFH-NEXT: #NO_APP
64 ; RV32ZFH-NEXT: fmv.h fa0, ft0
65 ; RV32ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
66 ; RV32ZFH-NEXT: addi sp, sp, 16
67 ; RV32ZFH-NEXT: ret
68 ;
69 ; RV64ZFH-LABEL: constraint_f_half_abi_name:
70 ; RV64ZFH: # %bb.0:
71 ; RV64ZFH-NEXT: addi sp, sp, -16
72 ; RV64ZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
73 ; RV64ZFH-NEXT: lui a0, %hi(gh)
74 ; RV64ZFH-NEXT: flh fs0, %lo(gh)(a0)
75 ; RV64ZFH-NEXT: #APP
76 ; RV64ZFH-NEXT: fadd.s ft0, fa0, fs0
77 ; RV64ZFH-NEXT: #NO_APP
78 ; RV64ZFH-NEXT: fmv.h fa0, ft0
79 ; RV64ZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
80 ; RV64ZFH-NEXT: addi sp, sp, 16
81 ; RV64ZFH-NEXT: ret
82 ;
83 ; RV32DZFH-LABEL: constraint_f_half_abi_name:
84 ; RV32DZFH: # %bb.0:
85 ; RV32DZFH-NEXT: addi sp, sp, -16
86 ; RV32DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
87 ; RV32DZFH-NEXT: lui a0, %hi(gh)
88 ; RV32DZFH-NEXT: flh fs0, %lo(gh)(a0)
89 ; RV32DZFH-NEXT: #APP
90 ; RV32DZFH-NEXT: fadd.s ft0, fa0, fs0
91 ; RV32DZFH-NEXT: #NO_APP
92 ; RV32DZFH-NEXT: fmv.h fa0, ft0
93 ; RV32DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
94 ; RV32DZFH-NEXT: addi sp, sp, 16
95 ; RV32DZFH-NEXT: ret
96 ;
97 ; RV64DZFH-LABEL: constraint_f_half_abi_name:
98 ; RV64DZFH: # %bb.0:
99 ; RV64DZFH-NEXT: addi sp, sp, -16
100 ; RV64DZFH-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
101 ; RV64DZFH-NEXT: lui a0, %hi(gh)
102 ; RV64DZFH-NEXT: flh fs0, %lo(gh)(a0)
103 ; RV64DZFH-NEXT: #APP
104 ; RV64DZFH-NEXT: fadd.s ft0, fa0, fs0
105 ; RV64DZFH-NEXT: #NO_APP
106 ; RV64DZFH-NEXT: fmv.h fa0, ft0
107 ; RV64DZFH-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
108 ; RV64DZFH-NEXT: addi sp, sp, 16
109 ; RV64DZFH-NEXT: ret
110 %1 = load half, ptr @gh
111 %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1)
112 ret half %2
113 }
115 define half @constraint_gpr(half %x) {
116 ; RV32ZFH-LABEL: constraint_gpr:
117 ; RV32ZFH: # %bb.0:
118 ; RV32ZFH-NEXT: .cfi_def_cfa_offset 0
119 ; RV32ZFH-NEXT: fmv.x.h a0, fa0
120 ; RV32ZFH-NEXT: #APP
121 ; RV32ZFH-NEXT: mv a0, a0
122 ; RV32ZFH-NEXT: #NO_APP
123 ; RV32ZFH-NEXT: fmv.h.x fa0, a0
124 ; RV32ZFH-NEXT: ret
125 ;
126 ; RV64ZFH-LABEL: constraint_gpr:
127 ; RV64ZFH: # %bb.0:
128 ; RV64ZFH-NEXT: .cfi_def_cfa_offset 0
129 ; RV64ZFH-NEXT: fmv.x.h a0, fa0
130 ; RV64ZFH-NEXT: #APP
131 ; RV64ZFH-NEXT: mv a0, a0
132 ; RV64ZFH-NEXT: #NO_APP
133 ; RV64ZFH-NEXT: fmv.h.x fa0, a0
134 ; RV64ZFH-NEXT: ret
135 ;
136 ; RV32DZFH-LABEL: constraint_gpr:
137 ; RV32DZFH: # %bb.0:
138 ; RV32DZFH-NEXT: .cfi_def_cfa_offset 0
139 ; RV32DZFH-NEXT: fmv.x.h a0, fa0
140 ; RV32DZFH-NEXT: #APP
141 ; RV32DZFH-NEXT: mv a0, a0
142 ; RV32DZFH-NEXT: #NO_APP
143 ; RV32DZFH-NEXT: fmv.h.x fa0, a0
144 ; RV32DZFH-NEXT: ret
145 ;
146 ; RV64DZFH-LABEL: constraint_gpr:
147 ; RV64DZFH: # %bb.0:
148 ; RV64DZFH-NEXT: .cfi_def_cfa_offset 0
149 ; RV64DZFH-NEXT: fmv.x.h a0, fa0
150 ; RV64DZFH-NEXT: #APP
151 ; RV64DZFH-NEXT: mv a0, a0
152 ; RV64DZFH-NEXT: #NO_APP
153 ; RV64DZFH-NEXT: fmv.h.x fa0, a0
154 ; RV64DZFH-NEXT: ret
155 %1 = tail call half asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(half %x)
156 ret half %1
157 }