| blob | bafa92e06834acb2b2cf0b937f0f3b5f06571cda |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2 ; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32
3 ; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64
5 ; WITH VSCALE RANGE
7 define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 {
8 ; RV32-LABEL: ctz_nxv4i32:
9 ; RV32: # %bb.0:
10 ; RV32-NEXT: csrr a0, vlenb
11 ; RV32-NEXT: srli a0, a0, 1
12 ; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
13 ; RV32-NEXT: vmv.v.x v10, a0
14 ; RV32-NEXT: vid.v v11
15 ; RV32-NEXT: li a1, -1
16 ; RV32-NEXT: vmadd.vx v11, a1, v10
17 ; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
18 ; RV32-NEXT: vmsne.vi v0, v8, 0
19 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
20 ; RV32-NEXT: vmv.v.i v8, 0
21 ; RV32-NEXT: vmerge.vim v8, v8, -1, v0
22 ; RV32-NEXT: vand.vv v8, v11, v8
23 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
24 ; RV32-NEXT: vmv.x.s a1, v8
25 ; RV32-NEXT: sub a0, a0, a1
26 ; RV32-NEXT: lui a1, 16
27 ; RV32-NEXT: addi a1, a1, -1
28 ; RV32-NEXT: and a0, a0, a1
29 ; RV32-NEXT: ret
30 ;
31 ; RV64-LABEL: ctz_nxv4i32:
32 ; RV64: # %bb.0:
33 ; RV64-NEXT: csrr a0, vlenb
34 ; RV64-NEXT: srli a0, a0, 1
35 ; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
36 ; RV64-NEXT: vmv.v.x v10, a0
37 ; RV64-NEXT: vid.v v11
38 ; RV64-NEXT: li a1, -1
39 ; RV64-NEXT: vmadd.vx v11, a1, v10
40 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
41 ; RV64-NEXT: vmsne.vi v0, v8, 0
42 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma
43 ; RV64-NEXT: vmv.v.i v8, 0
44 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0
45 ; RV64-NEXT: vand.vv v8, v11, v8
46 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
47 ; RV64-NEXT: vmv.x.s a1, v8
48 ; RV64-NEXT: sub a0, a0, a1
49 ; RV64-NEXT: lui a1, 16
50 ; RV64-NEXT: addiw a1, a1, -1
51 ; RV64-NEXT: and a0, a0, a1
52 ; RV64-NEXT: ret
53 %res = call i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32> %a, i1 0)
54 ret i32 %res
55 }
57 ; NO VSCALE RANGE
59 define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
60 ; RV32-LABEL: ctz_nxv8i1_no_range:
61 ; RV32: # %bb.0:
62 ; RV32-NEXT: addi sp, sp, -48
63 ; RV32-NEXT: .cfi_def_cfa_offset 48
64 ; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
65 ; RV32-NEXT: .cfi_offset ra, -4
66 ; RV32-NEXT: csrr a0, vlenb
67 ; RV32-NEXT: slli a0, a0, 1
68 ; RV32-NEXT: sub sp, sp, a0
69 ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
70 ; RV32-NEXT: addi a0, sp, 32
71 ; RV32-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
72 ; RV32-NEXT: csrr a0, vlenb
73 ; RV32-NEXT: srli a0, a0, 3
74 ; RV32-NEXT: li a2, 8
75 ; RV32-NEXT: li a1, 0
76 ; RV32-NEXT: li a3, 0
77 ; RV32-NEXT: call __muldi3
78 ; RV32-NEXT: sw a1, 20(sp)
79 ; RV32-NEXT: sw a0, 16(sp)
80 ; RV32-NEXT: addi a2, sp, 16
81 ; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma
82 ; RV32-NEXT: vlse64.v v16, (a2), zero
83 ; RV32-NEXT: vid.v v8
84 ; RV32-NEXT: li a2, -1
85 ; RV32-NEXT: vmadd.vx v8, a2, v16
86 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
87 ; RV32-NEXT: addi a2, sp, 32
88 ; RV32-NEXT: vl2r.v v16, (a2) # Unknown-size Folded Reload
89 ; RV32-NEXT: vmsne.vi v0, v16, 0
90 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
91 ; RV32-NEXT: vmv.v.i v16, 0
92 ; RV32-NEXT: vmerge.vim v16, v16, -1, v0
93 ; RV32-NEXT: vand.vv v8, v8, v16
94 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
95 ; RV32-NEXT: vmv.x.s a2, v8
96 ; RV32-NEXT: sltu a3, a0, a2
97 ; RV32-NEXT: li a4, 32
98 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
99 ; RV32-NEXT: vsrl.vx v8, v8, a4
100 ; RV32-NEXT: vmv.x.s a4, v8
101 ; RV32-NEXT: sub a1, a1, a4
102 ; RV32-NEXT: sub a1, a1, a3
103 ; RV32-NEXT: sub a0, a0, a2
104 ; RV32-NEXT: csrr a2, vlenb
105 ; RV32-NEXT: slli a2, a2, 1
106 ; RV32-NEXT: add sp, sp, a2
107 ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
108 ; RV32-NEXT: addi sp, sp, 48
109 ; RV32-NEXT: ret
110 ;
111 ; RV64-LABEL: ctz_nxv8i1_no_range:
112 ; RV64: # %bb.0:
113 ; RV64-NEXT: csrr a0, vlenb
114 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
115 ; RV64-NEXT: vmv.v.x v24, a0
116 ; RV64-NEXT: vid.v v16
117 ; RV64-NEXT: li a1, -1
118 ; RV64-NEXT: vmadd.vx v16, a1, v24
119 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
120 ; RV64-NEXT: vmsne.vi v0, v8, 0
121 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
122 ; RV64-NEXT: vmv.v.i v8, 0
123 ; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
124 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
125 ; RV64-NEXT: vmv.x.s a1, v8
126 ; RV64-NEXT: sub a0, a0, a1
127 ; RV64-NEXT: ret
128 %res = call i64 @llvm.experimental.cttz.elts.i64.nxv8i16(<vscale x 8 x i16> %a, i1 0)
129 ret i64 %res
130 }
132 define i32 @ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
133 ; RV32-LABEL: ctz_nxv16i1:
134 ; RV32: # %bb.0:
135 ; RV32-NEXT: vmv1r.v v0, v8
136 ; RV32-NEXT: csrr a0, vlenb
137 ; RV32-NEXT: slli a0, a0, 1
138 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
139 ; RV32-NEXT: vmv.v.x v8, a0
140 ; RV32-NEXT: vid.v v16
141 ; RV32-NEXT: li a1, -1
142 ; RV32-NEXT: vmadd.vx v16, a1, v8
143 ; RV32-NEXT: vmv.v.i v8, 0
144 ; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
145 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
146 ; RV32-NEXT: vmv.x.s a1, v8
147 ; RV32-NEXT: sub a0, a0, a1
148 ; RV32-NEXT: ret
149 ;
150 ; RV64-LABEL: ctz_nxv16i1:
151 ; RV64: # %bb.0:
152 ; RV64-NEXT: vmv1r.v v0, v8
153 ; RV64-NEXT: csrr a0, vlenb
154 ; RV64-NEXT: slli a0, a0, 1
155 ; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
156 ; RV64-NEXT: vmv.v.x v8, a0
157 ; RV64-NEXT: vid.v v16
158 ; RV64-NEXT: li a1, -1
159 ; RV64-NEXT: vmadd.vx v16, a1, v8
160 ; RV64-NEXT: vmv.v.i v8, 0
161 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0
162 ; RV64-NEXT: vand.vv v8, v16, v8
163 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
164 ; RV64-NEXT: vmv.x.s a1, v8
165 ; RV64-NEXT: subw a0, a0, a1
166 ; RV64-NEXT: ret
167 %res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 0)
168 ret i32 %res
169 }
171 declare i64 @llvm.experimental.cttz.elts.i64.nxv8i16(<vscale x 8 x i16>, i1)
172 declare i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1>, i1)
173 declare i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32>, i1)
175 attributes #0 = { vscale_range(2,1024) }