| blob | 145ce6e917f962ce4b5dfd09d69a5538875b6234 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \
3 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
5 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
6 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
7 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
8 ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
9 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
11 declare <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
13 define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
14 ; CHECK-LABEL: vp_cttz_nxv1i8:
15 ; CHECK: # %bb.0:
16 ; CHECK-NEXT: li a1, 1
17 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
18 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
19 ; CHECK-NEXT: vnot.v v8, v8, v0.t
20 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
21 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
22 ; CHECK-NEXT: li a0, 85
23 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
24 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
25 ; CHECK-NEXT: li a0, 51
26 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
27 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
28 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
29 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
30 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
31 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
32 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
33 ; CHECK-NEXT: ret
34 ;
35 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8:
36 ; CHECK-ZVBB: # %bb.0:
37 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
38 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
39 ; CHECK-ZVBB-NEXT: ret
40 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
41 ret <vscale x 1 x i8> %v
42 }
44 define <vscale x 1 x i8> @vp_cttz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
45 ; CHECK-LABEL: vp_cttz_nxv1i8_unmasked:
46 ; CHECK: # %bb.0:
47 ; CHECK-NEXT: li a1, 1
48 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
49 ; CHECK-NEXT: vsub.vx v9, v8, a1
50 ; CHECK-NEXT: vnot.v v8, v8
51 ; CHECK-NEXT: vand.vv v8, v8, v9
52 ; CHECK-NEXT: vsrl.vi v9, v8, 1
53 ; CHECK-NEXT: li a0, 85
54 ; CHECK-NEXT: vand.vx v9, v9, a0
55 ; CHECK-NEXT: vsub.vv v8, v8, v9
56 ; CHECK-NEXT: li a0, 51
57 ; CHECK-NEXT: vand.vx v9, v8, a0
58 ; CHECK-NEXT: vsrl.vi v8, v8, 2
59 ; CHECK-NEXT: vand.vx v8, v8, a0
60 ; CHECK-NEXT: vadd.vv v8, v9, v8
61 ; CHECK-NEXT: vsrl.vi v9, v8, 4
62 ; CHECK-NEXT: vadd.vv v8, v8, v9
63 ; CHECK-NEXT: vand.vi v8, v8, 15
64 ; CHECK-NEXT: ret
65 ;
66 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8_unmasked:
67 ; CHECK-ZVBB: # %bb.0:
68 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
69 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
70 ; CHECK-ZVBB-NEXT: ret
71 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
72 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
73 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
74 ret <vscale x 1 x i8> %v
75 }
77 declare <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
79 define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
80 ; CHECK-LABEL: vp_cttz_nxv2i8:
81 ; CHECK: # %bb.0:
82 ; CHECK-NEXT: li a1, 1
83 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
84 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
85 ; CHECK-NEXT: vnot.v v8, v8, v0.t
86 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
87 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
88 ; CHECK-NEXT: li a0, 85
89 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
90 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
91 ; CHECK-NEXT: li a0, 51
92 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
93 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
94 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
95 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
96 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
97 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
98 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
99 ; CHECK-NEXT: ret
100 ;
101 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8:
102 ; CHECK-ZVBB: # %bb.0:
103 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
104 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
105 ; CHECK-ZVBB-NEXT: ret
106 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
107 ret <vscale x 2 x i8> %v
108 }
110 define <vscale x 2 x i8> @vp_cttz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
111 ; CHECK-LABEL: vp_cttz_nxv2i8_unmasked:
112 ; CHECK: # %bb.0:
113 ; CHECK-NEXT: li a1, 1
114 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
115 ; CHECK-NEXT: vsub.vx v9, v8, a1
116 ; CHECK-NEXT: vnot.v v8, v8
117 ; CHECK-NEXT: vand.vv v8, v8, v9
118 ; CHECK-NEXT: vsrl.vi v9, v8, 1
119 ; CHECK-NEXT: li a0, 85
120 ; CHECK-NEXT: vand.vx v9, v9, a0
121 ; CHECK-NEXT: vsub.vv v8, v8, v9
122 ; CHECK-NEXT: li a0, 51
123 ; CHECK-NEXT: vand.vx v9, v8, a0
124 ; CHECK-NEXT: vsrl.vi v8, v8, 2
125 ; CHECK-NEXT: vand.vx v8, v8, a0
126 ; CHECK-NEXT: vadd.vv v8, v9, v8
127 ; CHECK-NEXT: vsrl.vi v9, v8, 4
128 ; CHECK-NEXT: vadd.vv v8, v8, v9
129 ; CHECK-NEXT: vand.vi v8, v8, 15
130 ; CHECK-NEXT: ret
131 ;
132 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8_unmasked:
133 ; CHECK-ZVBB: # %bb.0:
134 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
135 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
136 ; CHECK-ZVBB-NEXT: ret
137 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
138 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
139 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
140 ret <vscale x 2 x i8> %v
141 }
143 declare <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
145 define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
146 ; CHECK-LABEL: vp_cttz_nxv4i8:
147 ; CHECK: # %bb.0:
148 ; CHECK-NEXT: li a1, 1
149 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
150 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
151 ; CHECK-NEXT: vnot.v v8, v8, v0.t
152 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
153 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
154 ; CHECK-NEXT: li a0, 85
155 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
156 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
157 ; CHECK-NEXT: li a0, 51
158 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
159 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
160 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
161 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
162 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
163 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
164 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
165 ; CHECK-NEXT: ret
166 ;
167 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8:
168 ; CHECK-ZVBB: # %bb.0:
169 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
170 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
171 ; CHECK-ZVBB-NEXT: ret
172 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
173 ret <vscale x 4 x i8> %v
174 }
176 define <vscale x 4 x i8> @vp_cttz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
177 ; CHECK-LABEL: vp_cttz_nxv4i8_unmasked:
178 ; CHECK: # %bb.0:
179 ; CHECK-NEXT: li a1, 1
180 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
181 ; CHECK-NEXT: vsub.vx v9, v8, a1
182 ; CHECK-NEXT: vnot.v v8, v8
183 ; CHECK-NEXT: vand.vv v8, v8, v9
184 ; CHECK-NEXT: vsrl.vi v9, v8, 1
185 ; CHECK-NEXT: li a0, 85
186 ; CHECK-NEXT: vand.vx v9, v9, a0
187 ; CHECK-NEXT: vsub.vv v8, v8, v9
188 ; CHECK-NEXT: li a0, 51
189 ; CHECK-NEXT: vand.vx v9, v8, a0
190 ; CHECK-NEXT: vsrl.vi v8, v8, 2
191 ; CHECK-NEXT: vand.vx v8, v8, a0
192 ; CHECK-NEXT: vadd.vv v8, v9, v8
193 ; CHECK-NEXT: vsrl.vi v9, v8, 4
194 ; CHECK-NEXT: vadd.vv v8, v8, v9
195 ; CHECK-NEXT: vand.vi v8, v8, 15
196 ; CHECK-NEXT: ret
197 ;
198 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8_unmasked:
199 ; CHECK-ZVBB: # %bb.0:
200 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
201 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
202 ; CHECK-ZVBB-NEXT: ret
203 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
204 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
205 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
206 ret <vscale x 4 x i8> %v
207 }
209 declare <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
211 define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
212 ; CHECK-LABEL: vp_cttz_nxv8i8:
213 ; CHECK: # %bb.0:
214 ; CHECK-NEXT: li a1, 1
215 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
216 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
217 ; CHECK-NEXT: vnot.v v8, v8, v0.t
218 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
219 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
220 ; CHECK-NEXT: li a0, 85
221 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
222 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
223 ; CHECK-NEXT: li a0, 51
224 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
225 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
226 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
227 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
228 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
229 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
230 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
231 ; CHECK-NEXT: ret
232 ;
233 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8:
234 ; CHECK-ZVBB: # %bb.0:
235 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
236 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
237 ; CHECK-ZVBB-NEXT: ret
238 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
239 ret <vscale x 8 x i8> %v
240 }
242 define <vscale x 8 x i8> @vp_cttz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
243 ; CHECK-LABEL: vp_cttz_nxv8i8_unmasked:
244 ; CHECK: # %bb.0:
245 ; CHECK-NEXT: li a1, 1
246 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
247 ; CHECK-NEXT: vsub.vx v9, v8, a1
248 ; CHECK-NEXT: vnot.v v8, v8
249 ; CHECK-NEXT: vand.vv v8, v8, v9
250 ; CHECK-NEXT: vsrl.vi v9, v8, 1
251 ; CHECK-NEXT: li a0, 85
252 ; CHECK-NEXT: vand.vx v9, v9, a0
253 ; CHECK-NEXT: vsub.vv v8, v8, v9
254 ; CHECK-NEXT: li a0, 51
255 ; CHECK-NEXT: vand.vx v9, v8, a0
256 ; CHECK-NEXT: vsrl.vi v8, v8, 2
257 ; CHECK-NEXT: vand.vx v8, v8, a0
258 ; CHECK-NEXT: vadd.vv v8, v9, v8
259 ; CHECK-NEXT: vsrl.vi v9, v8, 4
260 ; CHECK-NEXT: vadd.vv v8, v8, v9
261 ; CHECK-NEXT: vand.vi v8, v8, 15
262 ; CHECK-NEXT: ret
263 ;
264 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8_unmasked:
265 ; CHECK-ZVBB: # %bb.0:
266 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
267 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
268 ; CHECK-ZVBB-NEXT: ret
269 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
270 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
271 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
272 ret <vscale x 8 x i8> %v
273 }
275 declare <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
277 define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
278 ; CHECK-LABEL: vp_cttz_nxv16i8:
279 ; CHECK: # %bb.0:
280 ; CHECK-NEXT: li a1, 1
281 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
282 ; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
283 ; CHECK-NEXT: vnot.v v8, v8, v0.t
284 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
285 ; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
286 ; CHECK-NEXT: li a0, 85
287 ; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
288 ; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t
289 ; CHECK-NEXT: li a0, 51
290 ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
291 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
292 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
293 ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
294 ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
295 ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
296 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
297 ; CHECK-NEXT: ret
298 ;
299 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8:
300 ; CHECK-ZVBB: # %bb.0:
301 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
302 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
303 ; CHECK-ZVBB-NEXT: ret
304 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
305 ret <vscale x 16 x i8> %v
306 }
308 define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
309 ; CHECK-LABEL: vp_cttz_nxv16i8_unmasked:
310 ; CHECK: # %bb.0:
311 ; CHECK-NEXT: li a1, 1
312 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
313 ; CHECK-NEXT: vsub.vx v10, v8, a1
314 ; CHECK-NEXT: vnot.v v8, v8
315 ; CHECK-NEXT: vand.vv v8, v8, v10
316 ; CHECK-NEXT: vsrl.vi v10, v8, 1
317 ; CHECK-NEXT: li a0, 85
318 ; CHECK-NEXT: vand.vx v10, v10, a0
319 ; CHECK-NEXT: vsub.vv v8, v8, v10
320 ; CHECK-NEXT: li a0, 51
321 ; CHECK-NEXT: vand.vx v10, v8, a0
322 ; CHECK-NEXT: vsrl.vi v8, v8, 2
323 ; CHECK-NEXT: vand.vx v8, v8, a0
324 ; CHECK-NEXT: vadd.vv v8, v10, v8
325 ; CHECK-NEXT: vsrl.vi v10, v8, 4
326 ; CHECK-NEXT: vadd.vv v8, v8, v10
327 ; CHECK-NEXT: vand.vi v8, v8, 15
328 ; CHECK-NEXT: ret
329 ;
330 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8_unmasked:
331 ; CHECK-ZVBB: # %bb.0:
332 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
333 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
334 ; CHECK-ZVBB-NEXT: ret
335 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
336 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
337 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
338 ret <vscale x 16 x i8> %v
339 }
341 declare <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
343 define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
344 ; CHECK-LABEL: vp_cttz_nxv32i8:
345 ; CHECK: # %bb.0:
346 ; CHECK-NEXT: li a1, 1
347 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
348 ; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
349 ; CHECK-NEXT: vnot.v v8, v8, v0.t
350 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
351 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
352 ; CHECK-NEXT: li a0, 85
353 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
354 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
355 ; CHECK-NEXT: li a0, 51
356 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
357 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
358 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
359 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
360 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
361 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
362 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
363 ; CHECK-NEXT: ret
364 ;
365 ; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8:
366 ; CHECK-ZVBB: # %bb.0:
367 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
368 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
369 ; CHECK-ZVBB-NEXT: ret
370 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
371 ret <vscale x 32 x i8> %v
372 }
374 define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
375 ; CHECK-LABEL: vp_cttz_nxv32i8_unmasked:
376 ; CHECK: # %bb.0:
377 ; CHECK-NEXT: li a1, 1
378 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
379 ; CHECK-NEXT: vsub.vx v12, v8, a1
380 ; CHECK-NEXT: vnot.v v8, v8
381 ; CHECK-NEXT: vand.vv v8, v8, v12
382 ; CHECK-NEXT: vsrl.vi v12, v8, 1
383 ; CHECK-NEXT: li a0, 85
384 ; CHECK-NEXT: vand.vx v12, v12, a0
385 ; CHECK-NEXT: vsub.vv v8, v8, v12
386 ; CHECK-NEXT: li a0, 51
387 ; CHECK-NEXT: vand.vx v12, v8, a0
388 ; CHECK-NEXT: vsrl.vi v8, v8, 2
389 ; CHECK-NEXT: vand.vx v8, v8, a0
390 ; CHECK-NEXT: vadd.vv v8, v12, v8
391 ; CHECK-NEXT: vsrl.vi v12, v8, 4
392 ; CHECK-NEXT: vadd.vv v8, v8, v12
393 ; CHECK-NEXT: vand.vi v8, v8, 15
394 ; CHECK-NEXT: ret
395 ;
396 ; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8_unmasked:
397 ; CHECK-ZVBB: # %bb.0:
398 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
399 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
400 ; CHECK-ZVBB-NEXT: ret
401 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
402 %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
403 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
404 ret <vscale x 32 x i8> %v
405 }
407 declare <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
409 define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
410 ; CHECK-LABEL: vp_cttz_nxv64i8:
411 ; CHECK: # %bb.0:
412 ; CHECK-NEXT: li a1, 1
413 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
414 ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
415 ; CHECK-NEXT: vnot.v v8, v8, v0.t
416 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
417 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
418 ; CHECK-NEXT: li a0, 85
419 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
420 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
421 ; CHECK-NEXT: li a0, 51
422 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
423 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
424 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
425 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
426 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
427 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
428 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
429 ; CHECK-NEXT: ret
430 ;
431 ; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8:
432 ; CHECK-ZVBB: # %bb.0:
433 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
434 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
435 ; CHECK-ZVBB-NEXT: ret
436 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
437 ret <vscale x 64 x i8> %v
438 }
440 define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
441 ; CHECK-LABEL: vp_cttz_nxv64i8_unmasked:
442 ; CHECK: # %bb.0:
443 ; CHECK-NEXT: li a1, 1
444 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
445 ; CHECK-NEXT: vsub.vx v16, v8, a1
446 ; CHECK-NEXT: vnot.v v8, v8
447 ; CHECK-NEXT: vand.vv v8, v8, v16
448 ; CHECK-NEXT: vsrl.vi v16, v8, 1
449 ; CHECK-NEXT: li a0, 85
450 ; CHECK-NEXT: vand.vx v16, v16, a0
451 ; CHECK-NEXT: vsub.vv v8, v8, v16
452 ; CHECK-NEXT: li a0, 51
453 ; CHECK-NEXT: vand.vx v16, v8, a0
454 ; CHECK-NEXT: vsrl.vi v8, v8, 2
455 ; CHECK-NEXT: vand.vx v8, v8, a0
456 ; CHECK-NEXT: vadd.vv v8, v16, v8
457 ; CHECK-NEXT: vsrl.vi v16, v8, 4
458 ; CHECK-NEXT: vadd.vv v8, v8, v16
459 ; CHECK-NEXT: vand.vi v8, v8, 15
460 ; CHECK-NEXT: ret
461 ;
462 ; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8_unmasked:
463 ; CHECK-ZVBB: # %bb.0:
464 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
465 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
466 ; CHECK-ZVBB-NEXT: ret
467 %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0
468 %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
469 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
470 ret <vscale x 64 x i8> %v
471 }
473 declare <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
475 define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
476 ; CHECK-LABEL: vp_cttz_nxv1i16:
477 ; CHECK: # %bb.0:
478 ; CHECK-NEXT: li a1, 1
479 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
480 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
481 ; CHECK-NEXT: vnot.v v8, v8, v0.t
482 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
483 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
484 ; CHECK-NEXT: lui a0, 5
485 ; CHECK-NEXT: addi a0, a0, 1365
486 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
487 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
488 ; CHECK-NEXT: lui a0, 3
489 ; CHECK-NEXT: addi a0, a0, 819
490 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
491 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
492 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
493 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
494 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
495 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
496 ; CHECK-NEXT: lui a0, 1
497 ; CHECK-NEXT: addi a0, a0, -241
498 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
499 ; CHECK-NEXT: li a0, 257
500 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
501 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
502 ; CHECK-NEXT: ret
503 ;
504 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16:
505 ; CHECK-ZVBB: # %bb.0:
506 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
507 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
508 ; CHECK-ZVBB-NEXT: ret
509 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
510 ret <vscale x 1 x i16> %v
511 }
513 define <vscale x 1 x i16> @vp_cttz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
514 ; CHECK-LABEL: vp_cttz_nxv1i16_unmasked:
515 ; CHECK: # %bb.0:
516 ; CHECK-NEXT: li a1, 1
517 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
518 ; CHECK-NEXT: vsub.vx v9, v8, a1
519 ; CHECK-NEXT: vnot.v v8, v8
520 ; CHECK-NEXT: vand.vv v8, v8, v9
521 ; CHECK-NEXT: vsrl.vi v9, v8, 1
522 ; CHECK-NEXT: lui a0, 5
523 ; CHECK-NEXT: addi a0, a0, 1365
524 ; CHECK-NEXT: vand.vx v9, v9, a0
525 ; CHECK-NEXT: vsub.vv v8, v8, v9
526 ; CHECK-NEXT: lui a0, 3
527 ; CHECK-NEXT: addi a0, a0, 819
528 ; CHECK-NEXT: vand.vx v9, v8, a0
529 ; CHECK-NEXT: vsrl.vi v8, v8, 2
530 ; CHECK-NEXT: vand.vx v8, v8, a0
531 ; CHECK-NEXT: vadd.vv v8, v9, v8
532 ; CHECK-NEXT: vsrl.vi v9, v8, 4
533 ; CHECK-NEXT: vadd.vv v8, v8, v9
534 ; CHECK-NEXT: lui a0, 1
535 ; CHECK-NEXT: addi a0, a0, -241
536 ; CHECK-NEXT: vand.vx v8, v8, a0
537 ; CHECK-NEXT: li a0, 257
538 ; CHECK-NEXT: vmul.vx v8, v8, a0
539 ; CHECK-NEXT: vsrl.vi v8, v8, 8
540 ; CHECK-NEXT: ret
541 ;
542 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16_unmasked:
543 ; CHECK-ZVBB: # %bb.0:
544 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
545 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
546 ; CHECK-ZVBB-NEXT: ret
547 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
548 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
549 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
550 ret <vscale x 1 x i16> %v
551 }
553 declare <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
555 define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
556 ; CHECK-LABEL: vp_cttz_nxv2i16:
557 ; CHECK: # %bb.0:
558 ; CHECK-NEXT: li a1, 1
559 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
560 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
561 ; CHECK-NEXT: vnot.v v8, v8, v0.t
562 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
563 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
564 ; CHECK-NEXT: lui a0, 5
565 ; CHECK-NEXT: addi a0, a0, 1365
566 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
567 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
568 ; CHECK-NEXT: lui a0, 3
569 ; CHECK-NEXT: addi a0, a0, 819
570 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
571 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
572 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
573 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
574 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
575 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
576 ; CHECK-NEXT: lui a0, 1
577 ; CHECK-NEXT: addi a0, a0, -241
578 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
579 ; CHECK-NEXT: li a0, 257
580 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
581 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
582 ; CHECK-NEXT: ret
583 ;
584 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16:
585 ; CHECK-ZVBB: # %bb.0:
586 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
587 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
588 ; CHECK-ZVBB-NEXT: ret
589 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
590 ret <vscale x 2 x i16> %v
591 }
593 define <vscale x 2 x i16> @vp_cttz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
594 ; CHECK-LABEL: vp_cttz_nxv2i16_unmasked:
595 ; CHECK: # %bb.0:
596 ; CHECK-NEXT: li a1, 1
597 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
598 ; CHECK-NEXT: vsub.vx v9, v8, a1
599 ; CHECK-NEXT: vnot.v v8, v8
600 ; CHECK-NEXT: vand.vv v8, v8, v9
601 ; CHECK-NEXT: vsrl.vi v9, v8, 1
602 ; CHECK-NEXT: lui a0, 5
603 ; CHECK-NEXT: addi a0, a0, 1365
604 ; CHECK-NEXT: vand.vx v9, v9, a0
605 ; CHECK-NEXT: vsub.vv v8, v8, v9
606 ; CHECK-NEXT: lui a0, 3
607 ; CHECK-NEXT: addi a0, a0, 819
608 ; CHECK-NEXT: vand.vx v9, v8, a0
609 ; CHECK-NEXT: vsrl.vi v8, v8, 2
610 ; CHECK-NEXT: vand.vx v8, v8, a0
611 ; CHECK-NEXT: vadd.vv v8, v9, v8
612 ; CHECK-NEXT: vsrl.vi v9, v8, 4
613 ; CHECK-NEXT: vadd.vv v8, v8, v9
614 ; CHECK-NEXT: lui a0, 1
615 ; CHECK-NEXT: addi a0, a0, -241
616 ; CHECK-NEXT: vand.vx v8, v8, a0
617 ; CHECK-NEXT: li a0, 257
618 ; CHECK-NEXT: vmul.vx v8, v8, a0
619 ; CHECK-NEXT: vsrl.vi v8, v8, 8
620 ; CHECK-NEXT: ret
621 ;
622 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16_unmasked:
623 ; CHECK-ZVBB: # %bb.0:
624 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
625 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
626 ; CHECK-ZVBB-NEXT: ret
627 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
628 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
629 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
630 ret <vscale x 2 x i16> %v
631 }
633 declare <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
635 define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
636 ; CHECK-LABEL: vp_cttz_nxv4i16:
637 ; CHECK: # %bb.0:
638 ; CHECK-NEXT: li a1, 1
639 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
640 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
641 ; CHECK-NEXT: vnot.v v8, v8, v0.t
642 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
643 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
644 ; CHECK-NEXT: lui a0, 5
645 ; CHECK-NEXT: addi a0, a0, 1365
646 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
647 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
648 ; CHECK-NEXT: lui a0, 3
649 ; CHECK-NEXT: addi a0, a0, 819
650 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
651 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
652 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
653 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
654 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
655 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
656 ; CHECK-NEXT: lui a0, 1
657 ; CHECK-NEXT: addi a0, a0, -241
658 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
659 ; CHECK-NEXT: li a0, 257
660 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
661 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
662 ; CHECK-NEXT: ret
663 ;
664 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16:
665 ; CHECK-ZVBB: # %bb.0:
666 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
667 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
668 ; CHECK-ZVBB-NEXT: ret
669 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
670 ret <vscale x 4 x i16> %v
671 }
673 define <vscale x 4 x i16> @vp_cttz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
674 ; CHECK-LABEL: vp_cttz_nxv4i16_unmasked:
675 ; CHECK: # %bb.0:
676 ; CHECK-NEXT: li a1, 1
677 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
678 ; CHECK-NEXT: vsub.vx v9, v8, a1
679 ; CHECK-NEXT: vnot.v v8, v8
680 ; CHECK-NEXT: vand.vv v8, v8, v9
681 ; CHECK-NEXT: vsrl.vi v9, v8, 1
682 ; CHECK-NEXT: lui a0, 5
683 ; CHECK-NEXT: addi a0, a0, 1365
684 ; CHECK-NEXT: vand.vx v9, v9, a0
685 ; CHECK-NEXT: vsub.vv v8, v8, v9
686 ; CHECK-NEXT: lui a0, 3
687 ; CHECK-NEXT: addi a0, a0, 819
688 ; CHECK-NEXT: vand.vx v9, v8, a0
689 ; CHECK-NEXT: vsrl.vi v8, v8, 2
690 ; CHECK-NEXT: vand.vx v8, v8, a0
691 ; CHECK-NEXT: vadd.vv v8, v9, v8
692 ; CHECK-NEXT: vsrl.vi v9, v8, 4
693 ; CHECK-NEXT: vadd.vv v8, v8, v9
694 ; CHECK-NEXT: lui a0, 1
695 ; CHECK-NEXT: addi a0, a0, -241
696 ; CHECK-NEXT: vand.vx v8, v8, a0
697 ; CHECK-NEXT: li a0, 257
698 ; CHECK-NEXT: vmul.vx v8, v8, a0
699 ; CHECK-NEXT: vsrl.vi v8, v8, 8
700 ; CHECK-NEXT: ret
701 ;
702 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16_unmasked:
703 ; CHECK-ZVBB: # %bb.0:
704 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
705 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
706 ; CHECK-ZVBB-NEXT: ret
707 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
708 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
709 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
710 ret <vscale x 4 x i16> %v
711 }
713 declare <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
715 define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
716 ; CHECK-LABEL: vp_cttz_nxv8i16:
717 ; CHECK: # %bb.0:
718 ; CHECK-NEXT: li a1, 1
719 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
720 ; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
721 ; CHECK-NEXT: vnot.v v8, v8, v0.t
722 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
723 ; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
724 ; CHECK-NEXT: lui a0, 5
725 ; CHECK-NEXT: addi a0, a0, 1365
726 ; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
727 ; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t
728 ; CHECK-NEXT: lui a0, 3
729 ; CHECK-NEXT: addi a0, a0, 819
730 ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
731 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
732 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
733 ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
734 ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
735 ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
736 ; CHECK-NEXT: lui a0, 1
737 ; CHECK-NEXT: addi a0, a0, -241
738 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
739 ; CHECK-NEXT: li a0, 257
740 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
741 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
742 ; CHECK-NEXT: ret
743 ;
744 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16:
745 ; CHECK-ZVBB: # %bb.0:
746 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
747 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
748 ; CHECK-ZVBB-NEXT: ret
749 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
750 ret <vscale x 8 x i16> %v
751 }
753 define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
754 ; CHECK-LABEL: vp_cttz_nxv8i16_unmasked:
755 ; CHECK: # %bb.0:
756 ; CHECK-NEXT: li a1, 1
757 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
758 ; CHECK-NEXT: vsub.vx v10, v8, a1
759 ; CHECK-NEXT: vnot.v v8, v8
760 ; CHECK-NEXT: vand.vv v8, v8, v10
761 ; CHECK-NEXT: vsrl.vi v10, v8, 1
762 ; CHECK-NEXT: lui a0, 5
763 ; CHECK-NEXT: addi a0, a0, 1365
764 ; CHECK-NEXT: vand.vx v10, v10, a0
765 ; CHECK-NEXT: vsub.vv v8, v8, v10
766 ; CHECK-NEXT: lui a0, 3
767 ; CHECK-NEXT: addi a0, a0, 819
768 ; CHECK-NEXT: vand.vx v10, v8, a0
769 ; CHECK-NEXT: vsrl.vi v8, v8, 2
770 ; CHECK-NEXT: vand.vx v8, v8, a0
771 ; CHECK-NEXT: vadd.vv v8, v10, v8
772 ; CHECK-NEXT: vsrl.vi v10, v8, 4
773 ; CHECK-NEXT: vadd.vv v8, v8, v10
774 ; CHECK-NEXT: lui a0, 1
775 ; CHECK-NEXT: addi a0, a0, -241
776 ; CHECK-NEXT: vand.vx v8, v8, a0
777 ; CHECK-NEXT: li a0, 257
778 ; CHECK-NEXT: vmul.vx v8, v8, a0
779 ; CHECK-NEXT: vsrl.vi v8, v8, 8
780 ; CHECK-NEXT: ret
781 ;
782 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16_unmasked:
783 ; CHECK-ZVBB: # %bb.0:
784 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
785 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
786 ; CHECK-ZVBB-NEXT: ret
787 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
788 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
789 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
790 ret <vscale x 8 x i16> %v
791 }
793 declare <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
795 define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
796 ; CHECK-LABEL: vp_cttz_nxv16i16:
797 ; CHECK: # %bb.0:
798 ; CHECK-NEXT: li a1, 1
799 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
800 ; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
801 ; CHECK-NEXT: vnot.v v8, v8, v0.t
802 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
803 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
804 ; CHECK-NEXT: lui a0, 5
805 ; CHECK-NEXT: addi a0, a0, 1365
806 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
807 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
808 ; CHECK-NEXT: lui a0, 3
809 ; CHECK-NEXT: addi a0, a0, 819
810 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
811 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
812 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
813 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
814 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
815 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
816 ; CHECK-NEXT: lui a0, 1
817 ; CHECK-NEXT: addi a0, a0, -241
818 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
819 ; CHECK-NEXT: li a0, 257
820 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
821 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
822 ; CHECK-NEXT: ret
823 ;
824 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16:
825 ; CHECK-ZVBB: # %bb.0:
826 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
827 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
828 ; CHECK-ZVBB-NEXT: ret
829 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
830 ret <vscale x 16 x i16> %v
831 }
833 define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
834 ; CHECK-LABEL: vp_cttz_nxv16i16_unmasked:
835 ; CHECK: # %bb.0:
836 ; CHECK-NEXT: li a1, 1
837 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
838 ; CHECK-NEXT: vsub.vx v12, v8, a1
839 ; CHECK-NEXT: vnot.v v8, v8
840 ; CHECK-NEXT: vand.vv v8, v8, v12
841 ; CHECK-NEXT: vsrl.vi v12, v8, 1
842 ; CHECK-NEXT: lui a0, 5
843 ; CHECK-NEXT: addi a0, a0, 1365
844 ; CHECK-NEXT: vand.vx v12, v12, a0
845 ; CHECK-NEXT: vsub.vv v8, v8, v12
846 ; CHECK-NEXT: lui a0, 3
847 ; CHECK-NEXT: addi a0, a0, 819
848 ; CHECK-NEXT: vand.vx v12, v8, a0
849 ; CHECK-NEXT: vsrl.vi v8, v8, 2
850 ; CHECK-NEXT: vand.vx v8, v8, a0
851 ; CHECK-NEXT: vadd.vv v8, v12, v8
852 ; CHECK-NEXT: vsrl.vi v12, v8, 4
853 ; CHECK-NEXT: vadd.vv v8, v8, v12
854 ; CHECK-NEXT: lui a0, 1
855 ; CHECK-NEXT: addi a0, a0, -241
856 ; CHECK-NEXT: vand.vx v8, v8, a0
857 ; CHECK-NEXT: li a0, 257
858 ; CHECK-NEXT: vmul.vx v8, v8, a0
859 ; CHECK-NEXT: vsrl.vi v8, v8, 8
860 ; CHECK-NEXT: ret
861 ;
862 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16_unmasked:
863 ; CHECK-ZVBB: # %bb.0:
864 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
865 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
866 ; CHECK-ZVBB-NEXT: ret
867 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
868 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
869 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
870 ret <vscale x 16 x i16> %v
871 }
873 declare <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
875 define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
876 ; CHECK-LABEL: vp_cttz_nxv32i16:
877 ; CHECK: # %bb.0:
878 ; CHECK-NEXT: li a1, 1
879 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
880 ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
881 ; CHECK-NEXT: vnot.v v8, v8, v0.t
882 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
883 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
884 ; CHECK-NEXT: lui a0, 5
885 ; CHECK-NEXT: addi a0, a0, 1365
886 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
887 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
888 ; CHECK-NEXT: lui a0, 3
889 ; CHECK-NEXT: addi a0, a0, 819
890 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
891 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
892 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
893 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
894 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
895 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
896 ; CHECK-NEXT: lui a0, 1
897 ; CHECK-NEXT: addi a0, a0, -241
898 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
899 ; CHECK-NEXT: li a0, 257
900 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
901 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
902 ; CHECK-NEXT: ret
903 ;
904 ; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16:
905 ; CHECK-ZVBB: # %bb.0:
906 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
907 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
908 ; CHECK-ZVBB-NEXT: ret
909 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
910 ret <vscale x 32 x i16> %v
911 }
913 define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
914 ; CHECK-LABEL: vp_cttz_nxv32i16_unmasked:
915 ; CHECK: # %bb.0:
916 ; CHECK-NEXT: li a1, 1
917 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
918 ; CHECK-NEXT: vsub.vx v16, v8, a1
919 ; CHECK-NEXT: vnot.v v8, v8
920 ; CHECK-NEXT: vand.vv v8, v8, v16
921 ; CHECK-NEXT: vsrl.vi v16, v8, 1
922 ; CHECK-NEXT: lui a0, 5
923 ; CHECK-NEXT: addi a0, a0, 1365
924 ; CHECK-NEXT: vand.vx v16, v16, a0
925 ; CHECK-NEXT: vsub.vv v8, v8, v16
926 ; CHECK-NEXT: lui a0, 3
927 ; CHECK-NEXT: addi a0, a0, 819
928 ; CHECK-NEXT: vand.vx v16, v8, a0
929 ; CHECK-NEXT: vsrl.vi v8, v8, 2
930 ; CHECK-NEXT: vand.vx v8, v8, a0
931 ; CHECK-NEXT: vadd.vv v8, v16, v8
932 ; CHECK-NEXT: vsrl.vi v16, v8, 4
933 ; CHECK-NEXT: vadd.vv v8, v8, v16
934 ; CHECK-NEXT: lui a0, 1
935 ; CHECK-NEXT: addi a0, a0, -241
936 ; CHECK-NEXT: vand.vx v8, v8, a0
937 ; CHECK-NEXT: li a0, 257
938 ; CHECK-NEXT: vmul.vx v8, v8, a0
939 ; CHECK-NEXT: vsrl.vi v8, v8, 8
940 ; CHECK-NEXT: ret
941 ;
942 ; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16_unmasked:
943 ; CHECK-ZVBB: # %bb.0:
944 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
945 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
946 ; CHECK-ZVBB-NEXT: ret
947 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
948 %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
949 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
950 ret <vscale x 32 x i16> %v
951 }
953 declare <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
955 define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
956 ; CHECK-LABEL: vp_cttz_nxv1i32:
957 ; CHECK: # %bb.0:
958 ; CHECK-NEXT: li a1, 1
959 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
960 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
961 ; CHECK-NEXT: vnot.v v8, v8, v0.t
962 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
963 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
964 ; CHECK-NEXT: lui a0, 349525
965 ; CHECK-NEXT: addi a0, a0, 1365
966 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
967 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
968 ; CHECK-NEXT: lui a0, 209715
969 ; CHECK-NEXT: addi a0, a0, 819
970 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
971 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
972 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
973 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
974 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
975 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
976 ; CHECK-NEXT: lui a0, 61681
977 ; CHECK-NEXT: addi a0, a0, -241
978 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
979 ; CHECK-NEXT: lui a0, 4112
980 ; CHECK-NEXT: addi a0, a0, 257
981 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
982 ; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t
983 ; CHECK-NEXT: ret
984 ;
985 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32:
986 ; CHECK-ZVBB: # %bb.0:
987 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
988 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
989 ; CHECK-ZVBB-NEXT: ret
990 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
991 ret <vscale x 1 x i32> %v
992 }
994 define <vscale x 1 x i32> @vp_cttz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
995 ; CHECK-LABEL: vp_cttz_nxv1i32_unmasked:
996 ; CHECK: # %bb.0:
997 ; CHECK-NEXT: li a1, 1
998 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
999 ; CHECK-NEXT: vsub.vx v9, v8, a1
1000 ; CHECK-NEXT: vnot.v v8, v8
1001 ; CHECK-NEXT: vand.vv v8, v8, v9
1002 ; CHECK-NEXT: vsrl.vi v9, v8, 1
1003 ; CHECK-NEXT: lui a0, 349525
1004 ; CHECK-NEXT: addi a0, a0, 1365
1005 ; CHECK-NEXT: vand.vx v9, v9, a0
1006 ; CHECK-NEXT: vsub.vv v8, v8, v9
1007 ; CHECK-NEXT: lui a0, 209715
1008 ; CHECK-NEXT: addi a0, a0, 819
1009 ; CHECK-NEXT: vand.vx v9, v8, a0
1010 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1011 ; CHECK-NEXT: vand.vx v8, v8, a0
1012 ; CHECK-NEXT: vadd.vv v8, v9, v8
1013 ; CHECK-NEXT: vsrl.vi v9, v8, 4
1014 ; CHECK-NEXT: vadd.vv v8, v8, v9
1015 ; CHECK-NEXT: lui a0, 61681
1016 ; CHECK-NEXT: addi a0, a0, -241
1017 ; CHECK-NEXT: vand.vx v8, v8, a0
1018 ; CHECK-NEXT: lui a0, 4112
1019 ; CHECK-NEXT: addi a0, a0, 257
1020 ; CHECK-NEXT: vmul.vx v8, v8, a0
1021 ; CHECK-NEXT: vsrl.vi v8, v8, 24
1022 ; CHECK-NEXT: ret
1023 ;
1024 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32_unmasked:
1025 ; CHECK-ZVBB: # %bb.0:
1026 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
1027 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1028 ; CHECK-ZVBB-NEXT: ret
1029 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
1030 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
1031 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
1032 ret <vscale x 1 x i32> %v
1033 }
1035 declare <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
1037 define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1038 ; CHECK-LABEL: vp_cttz_nxv2i32:
1039 ; CHECK: # %bb.0:
1040 ; CHECK-NEXT: li a1, 1
1041 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
1042 ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
1043 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1044 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
1045 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
1046 ; CHECK-NEXT: lui a0, 349525
1047 ; CHECK-NEXT: addi a0, a0, 1365
1048 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
1049 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
1050 ; CHECK-NEXT: lui a0, 209715
1051 ; CHECK-NEXT: addi a0, a0, 819
1052 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
1053 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1054 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1055 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
1056 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
1057 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
1058 ; CHECK-NEXT: lui a0, 61681
1059 ; CHECK-NEXT: addi a0, a0, -241
1060 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1061 ; CHECK-NEXT: lui a0, 4112
1062 ; CHECK-NEXT: addi a0, a0, 257
1063 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
1064 ; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t
1065 ; CHECK-NEXT: ret
1066 ;
1067 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32:
1068 ; CHECK-ZVBB: # %bb.0:
1069 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
1070 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1071 ; CHECK-ZVBB-NEXT: ret
1072 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
1073 ret <vscale x 2 x i32> %v
1074 }
1076 define <vscale x 2 x i32> @vp_cttz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
1077 ; CHECK-LABEL: vp_cttz_nxv2i32_unmasked:
1078 ; CHECK: # %bb.0:
1079 ; CHECK-NEXT: li a1, 1
1080 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
1081 ; CHECK-NEXT: vsub.vx v9, v8, a1
1082 ; CHECK-NEXT: vnot.v v8, v8
1083 ; CHECK-NEXT: vand.vv v8, v8, v9
1084 ; CHECK-NEXT: vsrl.vi v9, v8, 1
1085 ; CHECK-NEXT: lui a0, 349525
1086 ; CHECK-NEXT: addi a0, a0, 1365
1087 ; CHECK-NEXT: vand.vx v9, v9, a0
1088 ; CHECK-NEXT: vsub.vv v8, v8, v9
1089 ; CHECK-NEXT: lui a0, 209715
1090 ; CHECK-NEXT: addi a0, a0, 819
1091 ; CHECK-NEXT: vand.vx v9, v8, a0
1092 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1093 ; CHECK-NEXT: vand.vx v8, v8, a0
1094 ; CHECK-NEXT: vadd.vv v8, v9, v8
1095 ; CHECK-NEXT: vsrl.vi v9, v8, 4
1096 ; CHECK-NEXT: vadd.vv v8, v8, v9
1097 ; CHECK-NEXT: lui a0, 61681
1098 ; CHECK-NEXT: addi a0, a0, -241
1099 ; CHECK-NEXT: vand.vx v8, v8, a0
1100 ; CHECK-NEXT: lui a0, 4112
1101 ; CHECK-NEXT: addi a0, a0, 257
1102 ; CHECK-NEXT: vmul.vx v8, v8, a0
1103 ; CHECK-NEXT: vsrl.vi v8, v8, 24
1104 ; CHECK-NEXT: ret
1105 ;
1106 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32_unmasked:
1107 ; CHECK-ZVBB: # %bb.0:
1108 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
1109 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1110 ; CHECK-ZVBB-NEXT: ret
1111 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
1112 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
1113 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
1114 ret <vscale x 2 x i32> %v
1115 }
1117 declare <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
1119 define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1120 ; CHECK-LABEL: vp_cttz_nxv4i32:
1121 ; CHECK: # %bb.0:
1122 ; CHECK-NEXT: li a1, 1
1123 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
1124 ; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
1125 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1126 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
1127 ; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
1128 ; CHECK-NEXT: lui a0, 349525
1129 ; CHECK-NEXT: addi a0, a0, 1365
1130 ; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
1131 ; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t
1132 ; CHECK-NEXT: lui a0, 209715
1133 ; CHECK-NEXT: addi a0, a0, 819
1134 ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
1135 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1136 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1137 ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
1138 ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
1139 ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
1140 ; CHECK-NEXT: lui a0, 61681
1141 ; CHECK-NEXT: addi a0, a0, -241
1142 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1143 ; CHECK-NEXT: lui a0, 4112
1144 ; CHECK-NEXT: addi a0, a0, 257
1145 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
1146 ; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t
1147 ; CHECK-NEXT: ret
1148 ;
1149 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32:
1150 ; CHECK-ZVBB: # %bb.0:
1151 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
1152 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1153 ; CHECK-ZVBB-NEXT: ret
1154 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
1155 ret <vscale x 4 x i32> %v
1156 }
1158 define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
1159 ; CHECK-LABEL: vp_cttz_nxv4i32_unmasked:
1160 ; CHECK: # %bb.0:
1161 ; CHECK-NEXT: li a1, 1
1162 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
1163 ; CHECK-NEXT: vsub.vx v10, v8, a1
1164 ; CHECK-NEXT: vnot.v v8, v8
1165 ; CHECK-NEXT: vand.vv v8, v8, v10
1166 ; CHECK-NEXT: vsrl.vi v10, v8, 1
1167 ; CHECK-NEXT: lui a0, 349525
1168 ; CHECK-NEXT: addi a0, a0, 1365
1169 ; CHECK-NEXT: vand.vx v10, v10, a0
1170 ; CHECK-NEXT: vsub.vv v8, v8, v10
1171 ; CHECK-NEXT: lui a0, 209715
1172 ; CHECK-NEXT: addi a0, a0, 819
1173 ; CHECK-NEXT: vand.vx v10, v8, a0
1174 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1175 ; CHECK-NEXT: vand.vx v8, v8, a0
1176 ; CHECK-NEXT: vadd.vv v8, v10, v8
1177 ; CHECK-NEXT: vsrl.vi v10, v8, 4
1178 ; CHECK-NEXT: vadd.vv v8, v8, v10
1179 ; CHECK-NEXT: lui a0, 61681
1180 ; CHECK-NEXT: addi a0, a0, -241
1181 ; CHECK-NEXT: vand.vx v8, v8, a0
1182 ; CHECK-NEXT: lui a0, 4112
1183 ; CHECK-NEXT: addi a0, a0, 257
1184 ; CHECK-NEXT: vmul.vx v8, v8, a0
1185 ; CHECK-NEXT: vsrl.vi v8, v8, 24
1186 ; CHECK-NEXT: ret
1187 ;
1188 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32_unmasked:
1189 ; CHECK-ZVBB: # %bb.0:
1190 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
1191 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1192 ; CHECK-ZVBB-NEXT: ret
1193 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
1194 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
1195 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
1196 ret <vscale x 4 x i32> %v
1197 }
1199 declare <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
1201 define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1202 ; CHECK-LABEL: vp_cttz_nxv8i32:
1203 ; CHECK: # %bb.0:
1204 ; CHECK-NEXT: li a1, 1
1205 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
1206 ; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
1207 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1208 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
1209 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
1210 ; CHECK-NEXT: lui a0, 349525
1211 ; CHECK-NEXT: addi a0, a0, 1365
1212 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
1213 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
1214 ; CHECK-NEXT: lui a0, 209715
1215 ; CHECK-NEXT: addi a0, a0, 819
1216 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
1217 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1218 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1219 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
1220 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
1221 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
1222 ; CHECK-NEXT: lui a0, 61681
1223 ; CHECK-NEXT: addi a0, a0, -241
1224 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1225 ; CHECK-NEXT: lui a0, 4112
1226 ; CHECK-NEXT: addi a0, a0, 257
1227 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
1228 ; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t
1229 ; CHECK-NEXT: ret
1230 ;
1231 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32:
1232 ; CHECK-ZVBB: # %bb.0:
1233 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
1234 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1235 ; CHECK-ZVBB-NEXT: ret
1236 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
1237 ret <vscale x 8 x i32> %v
1238 }
1240 define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
1241 ; CHECK-LABEL: vp_cttz_nxv8i32_unmasked:
1242 ; CHECK: # %bb.0:
1243 ; CHECK-NEXT: li a1, 1
1244 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
1245 ; CHECK-NEXT: vsub.vx v12, v8, a1
1246 ; CHECK-NEXT: vnot.v v8, v8
1247 ; CHECK-NEXT: vand.vv v8, v8, v12
1248 ; CHECK-NEXT: vsrl.vi v12, v8, 1
1249 ; CHECK-NEXT: lui a0, 349525
1250 ; CHECK-NEXT: addi a0, a0, 1365
1251 ; CHECK-NEXT: vand.vx v12, v12, a0
1252 ; CHECK-NEXT: vsub.vv v8, v8, v12
1253 ; CHECK-NEXT: lui a0, 209715
1254 ; CHECK-NEXT: addi a0, a0, 819
1255 ; CHECK-NEXT: vand.vx v12, v8, a0
1256 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1257 ; CHECK-NEXT: vand.vx v8, v8, a0
1258 ; CHECK-NEXT: vadd.vv v8, v12, v8
1259 ; CHECK-NEXT: vsrl.vi v12, v8, 4
1260 ; CHECK-NEXT: vadd.vv v8, v8, v12
1261 ; CHECK-NEXT: lui a0, 61681
1262 ; CHECK-NEXT: addi a0, a0, -241
1263 ; CHECK-NEXT: vand.vx v8, v8, a0
1264 ; CHECK-NEXT: lui a0, 4112
1265 ; CHECK-NEXT: addi a0, a0, 257
1266 ; CHECK-NEXT: vmul.vx v8, v8, a0
1267 ; CHECK-NEXT: vsrl.vi v8, v8, 24
1268 ; CHECK-NEXT: ret
1269 ;
1270 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32_unmasked:
1271 ; CHECK-ZVBB: # %bb.0:
1272 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
1273 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1274 ; CHECK-ZVBB-NEXT: ret
1275 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
1276 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
1277 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
1278 ret <vscale x 8 x i32> %v
1279 }
1281 declare <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
1283 define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1284 ; CHECK-LABEL: vp_cttz_nxv16i32:
1285 ; CHECK: # %bb.0:
1286 ; CHECK-NEXT: li a1, 1
1287 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
1288 ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
1289 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1290 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
1291 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
1292 ; CHECK-NEXT: lui a0, 349525
1293 ; CHECK-NEXT: addi a0, a0, 1365
1294 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
1295 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
1296 ; CHECK-NEXT: lui a0, 209715
1297 ; CHECK-NEXT: addi a0, a0, 819
1298 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
1299 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1300 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1301 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
1302 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
1303 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
1304 ; CHECK-NEXT: lui a0, 61681
1305 ; CHECK-NEXT: addi a0, a0, -241
1306 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1307 ; CHECK-NEXT: lui a0, 4112
1308 ; CHECK-NEXT: addi a0, a0, 257
1309 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
1310 ; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t
1311 ; CHECK-NEXT: ret
1312 ;
1313 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32:
1314 ; CHECK-ZVBB: # %bb.0:
1315 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
1316 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1317 ; CHECK-ZVBB-NEXT: ret
1318 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
1319 ret <vscale x 16 x i32> %v
1320 }
1322 define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
1323 ; CHECK-LABEL: vp_cttz_nxv16i32_unmasked:
1324 ; CHECK: # %bb.0:
1325 ; CHECK-NEXT: li a1, 1
1326 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
1327 ; CHECK-NEXT: vsub.vx v16, v8, a1
1328 ; CHECK-NEXT: vnot.v v8, v8
1329 ; CHECK-NEXT: vand.vv v8, v8, v16
1330 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1331 ; CHECK-NEXT: lui a0, 349525
1332 ; CHECK-NEXT: addi a0, a0, 1365
1333 ; CHECK-NEXT: vand.vx v16, v16, a0
1334 ; CHECK-NEXT: vsub.vv v8, v8, v16
1335 ; CHECK-NEXT: lui a0, 209715
1336 ; CHECK-NEXT: addi a0, a0, 819
1337 ; CHECK-NEXT: vand.vx v16, v8, a0
1338 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1339 ; CHECK-NEXT: vand.vx v8, v8, a0
1340 ; CHECK-NEXT: vadd.vv v8, v16, v8
1341 ; CHECK-NEXT: vsrl.vi v16, v8, 4
1342 ; CHECK-NEXT: vadd.vv v8, v8, v16
1343 ; CHECK-NEXT: lui a0, 61681
1344 ; CHECK-NEXT: addi a0, a0, -241
1345 ; CHECK-NEXT: vand.vx v8, v8, a0
1346 ; CHECK-NEXT: lui a0, 4112
1347 ; CHECK-NEXT: addi a0, a0, 257
1348 ; CHECK-NEXT: vmul.vx v8, v8, a0
1349 ; CHECK-NEXT: vsrl.vi v8, v8, 24
1350 ; CHECK-NEXT: ret
1351 ;
1352 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32_unmasked:
1353 ; CHECK-ZVBB: # %bb.0:
1354 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
1355 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1356 ; CHECK-ZVBB-NEXT: ret
1357 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
1358 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
1359 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
1360 ret <vscale x 16 x i32> %v
1361 }
1363 declare <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
1365 define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1366 ; RV32-LABEL: vp_cttz_nxv1i64:
1367 ; RV32: # %bb.0:
1368 ; RV32-NEXT: li a1, 1
1369 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1370 ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
1371 ; RV32-NEXT: vnot.v v8, v8, v0.t
1372 ; RV32-NEXT: vand.vv v8, v8, v9, v0.t
1373 ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
1374 ; RV32-NEXT: lui a1, 349525
1375 ; RV32-NEXT: addi a1, a1, 1365
1376 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1377 ; RV32-NEXT: vmv.v.x v10, a1
1378 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1379 ; RV32-NEXT: vand.vv v9, v9, v10, v0.t
1380 ; RV32-NEXT: vsub.vv v8, v8, v9, v0.t
1381 ; RV32-NEXT: lui a1, 209715
1382 ; RV32-NEXT: addi a1, a1, 819
1383 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1384 ; RV32-NEXT: vmv.v.x v9, a1
1385 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1386 ; RV32-NEXT: vand.vv v10, v8, v9, v0.t
1387 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
1388 ; RV32-NEXT: vand.vv v8, v8, v9, v0.t
1389 ; RV32-NEXT: vadd.vv v8, v10, v8, v0.t
1390 ; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t
1391 ; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
1392 ; RV32-NEXT: lui a1, 61681
1393 ; RV32-NEXT: addi a1, a1, -241
1394 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1395 ; RV32-NEXT: vmv.v.x v9, a1
1396 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1397 ; RV32-NEXT: vand.vv v8, v8, v9, v0.t
1398 ; RV32-NEXT: lui a1, 4112
1399 ; RV32-NEXT: addi a1, a1, 257
1400 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1401 ; RV32-NEXT: vmv.v.x v9, a1
1402 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1403 ; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
1404 ; RV32-NEXT: li a0, 56
1405 ; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
1406 ; RV32-NEXT: ret
1407 ;
1408 ; RV64-LABEL: vp_cttz_nxv1i64:
1409 ; RV64: # %bb.0:
1410 ; RV64-NEXT: li a1, 1
1411 ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1412 ; RV64-NEXT: vsub.vx v9, v8, a1, v0.t
1413 ; RV64-NEXT: vnot.v v8, v8, v0.t
1414 ; RV64-NEXT: vand.vv v8, v8, v9, v0.t
1415 ; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t
1416 ; RV64-NEXT: lui a0, 349525
1417 ; RV64-NEXT: addiw a0, a0, 1365
1418 ; RV64-NEXT: slli a1, a0, 32
1419 ; RV64-NEXT: add a0, a0, a1
1420 ; RV64-NEXT: vand.vx v9, v9, a0, v0.t
1421 ; RV64-NEXT: vsub.vv v8, v8, v9, v0.t
1422 ; RV64-NEXT: lui a0, 209715
1423 ; RV64-NEXT: addiw a0, a0, 819
1424 ; RV64-NEXT: slli a1, a0, 32
1425 ; RV64-NEXT: add a0, a0, a1
1426 ; RV64-NEXT: vand.vx v9, v8, a0, v0.t
1427 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
1428 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1429 ; RV64-NEXT: vadd.vv v8, v9, v8, v0.t
1430 ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
1431 ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
1432 ; RV64-NEXT: lui a0, 61681
1433 ; RV64-NEXT: addiw a0, a0, -241
1434 ; RV64-NEXT: slli a1, a0, 32
1435 ; RV64-NEXT: add a0, a0, a1
1436 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1437 ; RV64-NEXT: lui a0, 4112
1438 ; RV64-NEXT: addiw a0, a0, 257
1439 ; RV64-NEXT: slli a1, a0, 32
1440 ; RV64-NEXT: add a0, a0, a1
1441 ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
1442 ; RV64-NEXT: li a0, 56
1443 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
1444 ; RV64-NEXT: ret
1445 ;
1446 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64:
1447 ; CHECK-ZVBB: # %bb.0:
1448 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1449 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1450 ; CHECK-ZVBB-NEXT: ret
1451 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
1452 ret <vscale x 1 x i64> %v
1453 }
1455 define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
1456 ; RV32-LABEL: vp_cttz_nxv1i64_unmasked:
1457 ; RV32: # %bb.0:
1458 ; RV32-NEXT: li a1, 1
1459 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1460 ; RV32-NEXT: vsub.vx v9, v8, a1
1461 ; RV32-NEXT: vnot.v v8, v8
1462 ; RV32-NEXT: vand.vv v8, v8, v9
1463 ; RV32-NEXT: vsrl.vi v9, v8, 1
1464 ; RV32-NEXT: lui a1, 349525
1465 ; RV32-NEXT: addi a1, a1, 1365
1466 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1467 ; RV32-NEXT: vmv.v.x v10, a1
1468 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1469 ; RV32-NEXT: vand.vv v9, v9, v10
1470 ; RV32-NEXT: vsub.vv v8, v8, v9
1471 ; RV32-NEXT: lui a1, 209715
1472 ; RV32-NEXT: addi a1, a1, 819
1473 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1474 ; RV32-NEXT: vmv.v.x v9, a1
1475 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1476 ; RV32-NEXT: vand.vv v10, v8, v9
1477 ; RV32-NEXT: vsrl.vi v8, v8, 2
1478 ; RV32-NEXT: vand.vv v8, v8, v9
1479 ; RV32-NEXT: vadd.vv v8, v10, v8
1480 ; RV32-NEXT: vsrl.vi v9, v8, 4
1481 ; RV32-NEXT: vadd.vv v8, v8, v9
1482 ; RV32-NEXT: lui a1, 61681
1483 ; RV32-NEXT: addi a1, a1, -241
1484 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1485 ; RV32-NEXT: vmv.v.x v9, a1
1486 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1487 ; RV32-NEXT: vand.vv v8, v8, v9
1488 ; RV32-NEXT: lui a1, 4112
1489 ; RV32-NEXT: addi a1, a1, 257
1490 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
1491 ; RV32-NEXT: vmv.v.x v9, a1
1492 ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1493 ; RV32-NEXT: vmul.vv v8, v8, v9
1494 ; RV32-NEXT: li a0, 56
1495 ; RV32-NEXT: vsrl.vx v8, v8, a0
1496 ; RV32-NEXT: ret
1497 ;
1498 ; RV64-LABEL: vp_cttz_nxv1i64_unmasked:
1499 ; RV64: # %bb.0:
1500 ; RV64-NEXT: li a1, 1
1501 ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1502 ; RV64-NEXT: vsub.vx v9, v8, a1
1503 ; RV64-NEXT: vnot.v v8, v8
1504 ; RV64-NEXT: vand.vv v8, v8, v9
1505 ; RV64-NEXT: vsrl.vi v9, v8, 1
1506 ; RV64-NEXT: lui a0, 349525
1507 ; RV64-NEXT: addiw a0, a0, 1365
1508 ; RV64-NEXT: slli a1, a0, 32
1509 ; RV64-NEXT: add a0, a0, a1
1510 ; RV64-NEXT: vand.vx v9, v9, a0
1511 ; RV64-NEXT: vsub.vv v8, v8, v9
1512 ; RV64-NEXT: lui a0, 209715
1513 ; RV64-NEXT: addiw a0, a0, 819
1514 ; RV64-NEXT: slli a1, a0, 32
1515 ; RV64-NEXT: add a0, a0, a1
1516 ; RV64-NEXT: vand.vx v9, v8, a0
1517 ; RV64-NEXT: vsrl.vi v8, v8, 2
1518 ; RV64-NEXT: vand.vx v8, v8, a0
1519 ; RV64-NEXT: vadd.vv v8, v9, v8
1520 ; RV64-NEXT: vsrl.vi v9, v8, 4
1521 ; RV64-NEXT: vadd.vv v8, v8, v9
1522 ; RV64-NEXT: lui a0, 61681
1523 ; RV64-NEXT: addiw a0, a0, -241
1524 ; RV64-NEXT: slli a1, a0, 32
1525 ; RV64-NEXT: add a0, a0, a1
1526 ; RV64-NEXT: vand.vx v8, v8, a0
1527 ; RV64-NEXT: lui a0, 4112
1528 ; RV64-NEXT: addiw a0, a0, 257
1529 ; RV64-NEXT: slli a1, a0, 32
1530 ; RV64-NEXT: add a0, a0, a1
1531 ; RV64-NEXT: vmul.vx v8, v8, a0
1532 ; RV64-NEXT: li a0, 56
1533 ; RV64-NEXT: vsrl.vx v8, v8, a0
1534 ; RV64-NEXT: ret
1535 ;
1536 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64_unmasked:
1537 ; CHECK-ZVBB: # %bb.0:
1538 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1539 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1540 ; CHECK-ZVBB-NEXT: ret
1541 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
1542 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
1543 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
1544 ret <vscale x 1 x i64> %v
1545 }
1547 declare <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
1549 define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1550 ; RV32-LABEL: vp_cttz_nxv2i64:
1551 ; RV32: # %bb.0:
1552 ; RV32-NEXT: li a1, 1
1553 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1554 ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
1555 ; RV32-NEXT: vnot.v v8, v8, v0.t
1556 ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
1557 ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
1558 ; RV32-NEXT: lui a1, 349525
1559 ; RV32-NEXT: addi a1, a1, 1365
1560 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1561 ; RV32-NEXT: vmv.v.x v12, a1
1562 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1563 ; RV32-NEXT: vand.vv v10, v10, v12, v0.t
1564 ; RV32-NEXT: vsub.vv v8, v8, v10, v0.t
1565 ; RV32-NEXT: lui a1, 209715
1566 ; RV32-NEXT: addi a1, a1, 819
1567 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1568 ; RV32-NEXT: vmv.v.x v10, a1
1569 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1570 ; RV32-NEXT: vand.vv v12, v8, v10, v0.t
1571 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
1572 ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
1573 ; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
1574 ; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
1575 ; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
1576 ; RV32-NEXT: lui a1, 61681
1577 ; RV32-NEXT: addi a1, a1, -241
1578 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1579 ; RV32-NEXT: vmv.v.x v10, a1
1580 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1581 ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
1582 ; RV32-NEXT: lui a1, 4112
1583 ; RV32-NEXT: addi a1, a1, 257
1584 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1585 ; RV32-NEXT: vmv.v.x v10, a1
1586 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1587 ; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
1588 ; RV32-NEXT: li a0, 56
1589 ; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
1590 ; RV32-NEXT: ret
1591 ;
1592 ; RV64-LABEL: vp_cttz_nxv2i64:
1593 ; RV64: # %bb.0:
1594 ; RV64-NEXT: li a1, 1
1595 ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1596 ; RV64-NEXT: vsub.vx v10, v8, a1, v0.t
1597 ; RV64-NEXT: vnot.v v8, v8, v0.t
1598 ; RV64-NEXT: vand.vv v8, v8, v10, v0.t
1599 ; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
1600 ; RV64-NEXT: lui a0, 349525
1601 ; RV64-NEXT: addiw a0, a0, 1365
1602 ; RV64-NEXT: slli a1, a0, 32
1603 ; RV64-NEXT: add a0, a0, a1
1604 ; RV64-NEXT: vand.vx v10, v10, a0, v0.t
1605 ; RV64-NEXT: vsub.vv v8, v8, v10, v0.t
1606 ; RV64-NEXT: lui a0, 209715
1607 ; RV64-NEXT: addiw a0, a0, 819
1608 ; RV64-NEXT: slli a1, a0, 32
1609 ; RV64-NEXT: add a0, a0, a1
1610 ; RV64-NEXT: vand.vx v10, v8, a0, v0.t
1611 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
1612 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1613 ; RV64-NEXT: vadd.vv v8, v10, v8, v0.t
1614 ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
1615 ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
1616 ; RV64-NEXT: lui a0, 61681
1617 ; RV64-NEXT: addiw a0, a0, -241
1618 ; RV64-NEXT: slli a1, a0, 32
1619 ; RV64-NEXT: add a0, a0, a1
1620 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1621 ; RV64-NEXT: lui a0, 4112
1622 ; RV64-NEXT: addiw a0, a0, 257
1623 ; RV64-NEXT: slli a1, a0, 32
1624 ; RV64-NEXT: add a0, a0, a1
1625 ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
1626 ; RV64-NEXT: li a0, 56
1627 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
1628 ; RV64-NEXT: ret
1629 ;
1630 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64:
1631 ; CHECK-ZVBB: # %bb.0:
1632 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1633 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1634 ; CHECK-ZVBB-NEXT: ret
1635 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
1636 ret <vscale x 2 x i64> %v
1637 }
1639 define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
1640 ; RV32-LABEL: vp_cttz_nxv2i64_unmasked:
1641 ; RV32: # %bb.0:
1642 ; RV32-NEXT: li a1, 1
1643 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1644 ; RV32-NEXT: vsub.vx v10, v8, a1
1645 ; RV32-NEXT: vnot.v v8, v8
1646 ; RV32-NEXT: vand.vv v8, v8, v10
1647 ; RV32-NEXT: vsrl.vi v10, v8, 1
1648 ; RV32-NEXT: lui a1, 349525
1649 ; RV32-NEXT: addi a1, a1, 1365
1650 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1651 ; RV32-NEXT: vmv.v.x v12, a1
1652 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1653 ; RV32-NEXT: vand.vv v10, v10, v12
1654 ; RV32-NEXT: vsub.vv v8, v8, v10
1655 ; RV32-NEXT: lui a1, 209715
1656 ; RV32-NEXT: addi a1, a1, 819
1657 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1658 ; RV32-NEXT: vmv.v.x v10, a1
1659 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1660 ; RV32-NEXT: vand.vv v12, v8, v10
1661 ; RV32-NEXT: vsrl.vi v8, v8, 2
1662 ; RV32-NEXT: vand.vv v8, v8, v10
1663 ; RV32-NEXT: vadd.vv v8, v12, v8
1664 ; RV32-NEXT: vsrl.vi v10, v8, 4
1665 ; RV32-NEXT: vadd.vv v8, v8, v10
1666 ; RV32-NEXT: lui a1, 61681
1667 ; RV32-NEXT: addi a1, a1, -241
1668 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1669 ; RV32-NEXT: vmv.v.x v10, a1
1670 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1671 ; RV32-NEXT: vand.vv v8, v8, v10
1672 ; RV32-NEXT: lui a1, 4112
1673 ; RV32-NEXT: addi a1, a1, 257
1674 ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
1675 ; RV32-NEXT: vmv.v.x v10, a1
1676 ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1677 ; RV32-NEXT: vmul.vv v8, v8, v10
1678 ; RV32-NEXT: li a0, 56
1679 ; RV32-NEXT: vsrl.vx v8, v8, a0
1680 ; RV32-NEXT: ret
1681 ;
1682 ; RV64-LABEL: vp_cttz_nxv2i64_unmasked:
1683 ; RV64: # %bb.0:
1684 ; RV64-NEXT: li a1, 1
1685 ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1686 ; RV64-NEXT: vsub.vx v10, v8, a1
1687 ; RV64-NEXT: vnot.v v8, v8
1688 ; RV64-NEXT: vand.vv v8, v8, v10
1689 ; RV64-NEXT: vsrl.vi v10, v8, 1
1690 ; RV64-NEXT: lui a0, 349525
1691 ; RV64-NEXT: addiw a0, a0, 1365
1692 ; RV64-NEXT: slli a1, a0, 32
1693 ; RV64-NEXT: add a0, a0, a1
1694 ; RV64-NEXT: vand.vx v10, v10, a0
1695 ; RV64-NEXT: vsub.vv v8, v8, v10
1696 ; RV64-NEXT: lui a0, 209715
1697 ; RV64-NEXT: addiw a0, a0, 819
1698 ; RV64-NEXT: slli a1, a0, 32
1699 ; RV64-NEXT: add a0, a0, a1
1700 ; RV64-NEXT: vand.vx v10, v8, a0
1701 ; RV64-NEXT: vsrl.vi v8, v8, 2
1702 ; RV64-NEXT: vand.vx v8, v8, a0
1703 ; RV64-NEXT: vadd.vv v8, v10, v8
1704 ; RV64-NEXT: vsrl.vi v10, v8, 4
1705 ; RV64-NEXT: vadd.vv v8, v8, v10
1706 ; RV64-NEXT: lui a0, 61681
1707 ; RV64-NEXT: addiw a0, a0, -241
1708 ; RV64-NEXT: slli a1, a0, 32
1709 ; RV64-NEXT: add a0, a0, a1
1710 ; RV64-NEXT: vand.vx v8, v8, a0
1711 ; RV64-NEXT: lui a0, 4112
1712 ; RV64-NEXT: addiw a0, a0, 257
1713 ; RV64-NEXT: slli a1, a0, 32
1714 ; RV64-NEXT: add a0, a0, a1
1715 ; RV64-NEXT: vmul.vx v8, v8, a0
1716 ; RV64-NEXT: li a0, 56
1717 ; RV64-NEXT: vsrl.vx v8, v8, a0
1718 ; RV64-NEXT: ret
1719 ;
1720 ; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64_unmasked:
1721 ; CHECK-ZVBB: # %bb.0:
1722 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1723 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1724 ; CHECK-ZVBB-NEXT: ret
1725 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
1726 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
1727 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
1728 ret <vscale x 2 x i64> %v
1729 }
1731 declare <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
1733 define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1734 ; RV32-LABEL: vp_cttz_nxv4i64:
1735 ; RV32: # %bb.0:
1736 ; RV32-NEXT: li a1, 1
1737 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1738 ; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
1739 ; RV32-NEXT: vnot.v v8, v8, v0.t
1740 ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
1741 ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
1742 ; RV32-NEXT: lui a1, 349525
1743 ; RV32-NEXT: addi a1, a1, 1365
1744 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1745 ; RV32-NEXT: vmv.v.x v16, a1
1746 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1747 ; RV32-NEXT: vand.vv v12, v12, v16, v0.t
1748 ; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
1749 ; RV32-NEXT: lui a1, 209715
1750 ; RV32-NEXT: addi a1, a1, 819
1751 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1752 ; RV32-NEXT: vmv.v.x v12, a1
1753 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1754 ; RV32-NEXT: vand.vv v16, v8, v12, v0.t
1755 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
1756 ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
1757 ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
1758 ; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
1759 ; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
1760 ; RV32-NEXT: lui a1, 61681
1761 ; RV32-NEXT: addi a1, a1, -241
1762 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1763 ; RV32-NEXT: vmv.v.x v12, a1
1764 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1765 ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
1766 ; RV32-NEXT: lui a1, 4112
1767 ; RV32-NEXT: addi a1, a1, 257
1768 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1769 ; RV32-NEXT: vmv.v.x v12, a1
1770 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1771 ; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
1772 ; RV32-NEXT: li a0, 56
1773 ; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
1774 ; RV32-NEXT: ret
1775 ;
1776 ; RV64-LABEL: vp_cttz_nxv4i64:
1777 ; RV64: # %bb.0:
1778 ; RV64-NEXT: li a1, 1
1779 ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1780 ; RV64-NEXT: vsub.vx v12, v8, a1, v0.t
1781 ; RV64-NEXT: vnot.v v8, v8, v0.t
1782 ; RV64-NEXT: vand.vv v8, v8, v12, v0.t
1783 ; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
1784 ; RV64-NEXT: lui a0, 349525
1785 ; RV64-NEXT: addiw a0, a0, 1365
1786 ; RV64-NEXT: slli a1, a0, 32
1787 ; RV64-NEXT: add a0, a0, a1
1788 ; RV64-NEXT: vand.vx v12, v12, a0, v0.t
1789 ; RV64-NEXT: vsub.vv v8, v8, v12, v0.t
1790 ; RV64-NEXT: lui a0, 209715
1791 ; RV64-NEXT: addiw a0, a0, 819
1792 ; RV64-NEXT: slli a1, a0, 32
1793 ; RV64-NEXT: add a0, a0, a1
1794 ; RV64-NEXT: vand.vx v12, v8, a0, v0.t
1795 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
1796 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1797 ; RV64-NEXT: vadd.vv v8, v12, v8, v0.t
1798 ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
1799 ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
1800 ; RV64-NEXT: lui a0, 61681
1801 ; RV64-NEXT: addiw a0, a0, -241
1802 ; RV64-NEXT: slli a1, a0, 32
1803 ; RV64-NEXT: add a0, a0, a1
1804 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1805 ; RV64-NEXT: lui a0, 4112
1806 ; RV64-NEXT: addiw a0, a0, 257
1807 ; RV64-NEXT: slli a1, a0, 32
1808 ; RV64-NEXT: add a0, a0, a1
1809 ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
1810 ; RV64-NEXT: li a0, 56
1811 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
1812 ; RV64-NEXT: ret
1813 ;
1814 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64:
1815 ; CHECK-ZVBB: # %bb.0:
1816 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1817 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
1818 ; CHECK-ZVBB-NEXT: ret
1819 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
1820 ret <vscale x 4 x i64> %v
1821 }
1823 define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
1824 ; RV32-LABEL: vp_cttz_nxv4i64_unmasked:
1825 ; RV32: # %bb.0:
1826 ; RV32-NEXT: li a1, 1
1827 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1828 ; RV32-NEXT: vsub.vx v12, v8, a1
1829 ; RV32-NEXT: vnot.v v8, v8
1830 ; RV32-NEXT: vand.vv v8, v8, v12
1831 ; RV32-NEXT: vsrl.vi v12, v8, 1
1832 ; RV32-NEXT: lui a1, 349525
1833 ; RV32-NEXT: addi a1, a1, 1365
1834 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1835 ; RV32-NEXT: vmv.v.x v16, a1
1836 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1837 ; RV32-NEXT: vand.vv v12, v12, v16
1838 ; RV32-NEXT: vsub.vv v8, v8, v12
1839 ; RV32-NEXT: lui a1, 209715
1840 ; RV32-NEXT: addi a1, a1, 819
1841 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1842 ; RV32-NEXT: vmv.v.x v12, a1
1843 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1844 ; RV32-NEXT: vand.vv v16, v8, v12
1845 ; RV32-NEXT: vsrl.vi v8, v8, 2
1846 ; RV32-NEXT: vand.vv v8, v8, v12
1847 ; RV32-NEXT: vadd.vv v8, v16, v8
1848 ; RV32-NEXT: vsrl.vi v12, v8, 4
1849 ; RV32-NEXT: vadd.vv v8, v8, v12
1850 ; RV32-NEXT: lui a1, 61681
1851 ; RV32-NEXT: addi a1, a1, -241
1852 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1853 ; RV32-NEXT: vmv.v.x v12, a1
1854 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1855 ; RV32-NEXT: vand.vv v8, v8, v12
1856 ; RV32-NEXT: lui a1, 4112
1857 ; RV32-NEXT: addi a1, a1, 257
1858 ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
1859 ; RV32-NEXT: vmv.v.x v12, a1
1860 ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1861 ; RV32-NEXT: vmul.vv v8, v8, v12
1862 ; RV32-NEXT: li a0, 56
1863 ; RV32-NEXT: vsrl.vx v8, v8, a0
1864 ; RV32-NEXT: ret
1865 ;
1866 ; RV64-LABEL: vp_cttz_nxv4i64_unmasked:
1867 ; RV64: # %bb.0:
1868 ; RV64-NEXT: li a1, 1
1869 ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1870 ; RV64-NEXT: vsub.vx v12, v8, a1
1871 ; RV64-NEXT: vnot.v v8, v8
1872 ; RV64-NEXT: vand.vv v8, v8, v12
1873 ; RV64-NEXT: vsrl.vi v12, v8, 1
1874 ; RV64-NEXT: lui a0, 349525
1875 ; RV64-NEXT: addiw a0, a0, 1365
1876 ; RV64-NEXT: slli a1, a0, 32
1877 ; RV64-NEXT: add a0, a0, a1
1878 ; RV64-NEXT: vand.vx v12, v12, a0
1879 ; RV64-NEXT: vsub.vv v8, v8, v12
1880 ; RV64-NEXT: lui a0, 209715
1881 ; RV64-NEXT: addiw a0, a0, 819
1882 ; RV64-NEXT: slli a1, a0, 32
1883 ; RV64-NEXT: add a0, a0, a1
1884 ; RV64-NEXT: vand.vx v12, v8, a0
1885 ; RV64-NEXT: vsrl.vi v8, v8, 2
1886 ; RV64-NEXT: vand.vx v8, v8, a0
1887 ; RV64-NEXT: vadd.vv v8, v12, v8
1888 ; RV64-NEXT: vsrl.vi v12, v8, 4
1889 ; RV64-NEXT: vadd.vv v8, v8, v12
1890 ; RV64-NEXT: lui a0, 61681
1891 ; RV64-NEXT: addiw a0, a0, -241
1892 ; RV64-NEXT: slli a1, a0, 32
1893 ; RV64-NEXT: add a0, a0, a1
1894 ; RV64-NEXT: vand.vx v8, v8, a0
1895 ; RV64-NEXT: lui a0, 4112
1896 ; RV64-NEXT: addiw a0, a0, 257
1897 ; RV64-NEXT: slli a1, a0, 32
1898 ; RV64-NEXT: add a0, a0, a1
1899 ; RV64-NEXT: vmul.vx v8, v8, a0
1900 ; RV64-NEXT: li a0, 56
1901 ; RV64-NEXT: vsrl.vx v8, v8, a0
1902 ; RV64-NEXT: ret
1903 ;
1904 ; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64_unmasked:
1905 ; CHECK-ZVBB: # %bb.0:
1906 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1907 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1908 ; CHECK-ZVBB-NEXT: ret
1909 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
1910 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
1911 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
1912 ret <vscale x 4 x i64> %v
1913 }
1915 declare <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64>, i1 immarg, <vscale x 7 x i1>, i32)
1917 define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
1918 ; RV32-LABEL: vp_cttz_nxv7i64:
1919 ; RV32: # %bb.0:
1920 ; RV32-NEXT: li a1, 1
1921 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1922 ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
1923 ; RV32-NEXT: vnot.v v8, v8, v0.t
1924 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
1925 ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
1926 ; RV32-NEXT: lui a1, 349525
1927 ; RV32-NEXT: addi a1, a1, 1365
1928 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
1929 ; RV32-NEXT: vmv.v.x v24, a1
1930 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1931 ; RV32-NEXT: vand.vv v16, v16, v24, v0.t
1932 ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
1933 ; RV32-NEXT: lui a1, 209715
1934 ; RV32-NEXT: addi a1, a1, 819
1935 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
1936 ; RV32-NEXT: vmv.v.x v16, a1
1937 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1938 ; RV32-NEXT: vand.vv v24, v8, v16, v0.t
1939 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
1940 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
1941 ; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
1942 ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
1943 ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
1944 ; RV32-NEXT: lui a1, 61681
1945 ; RV32-NEXT: addi a1, a1, -241
1946 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
1947 ; RV32-NEXT: vmv.v.x v16, a1
1948 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1949 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
1950 ; RV32-NEXT: lui a1, 4112
1951 ; RV32-NEXT: addi a1, a1, 257
1952 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
1953 ; RV32-NEXT: vmv.v.x v16, a1
1954 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1955 ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
1956 ; RV32-NEXT: li a0, 56
1957 ; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
1958 ; RV32-NEXT: ret
1959 ;
1960 ; RV64-LABEL: vp_cttz_nxv7i64:
1961 ; RV64: # %bb.0:
1962 ; RV64-NEXT: li a1, 1
1963 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1964 ; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
1965 ; RV64-NEXT: vnot.v v8, v8, v0.t
1966 ; RV64-NEXT: vand.vv v8, v8, v16, v0.t
1967 ; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
1968 ; RV64-NEXT: lui a0, 349525
1969 ; RV64-NEXT: addiw a0, a0, 1365
1970 ; RV64-NEXT: slli a1, a0, 32
1971 ; RV64-NEXT: add a0, a0, a1
1972 ; RV64-NEXT: vand.vx v16, v16, a0, v0.t
1973 ; RV64-NEXT: vsub.vv v8, v8, v16, v0.t
1974 ; RV64-NEXT: lui a0, 209715
1975 ; RV64-NEXT: addiw a0, a0, 819
1976 ; RV64-NEXT: slli a1, a0, 32
1977 ; RV64-NEXT: add a0, a0, a1
1978 ; RV64-NEXT: vand.vx v16, v8, a0, v0.t
1979 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
1980 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1981 ; RV64-NEXT: vadd.vv v8, v16, v8, v0.t
1982 ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
1983 ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
1984 ; RV64-NEXT: lui a0, 61681
1985 ; RV64-NEXT: addiw a0, a0, -241
1986 ; RV64-NEXT: slli a1, a0, 32
1987 ; RV64-NEXT: add a0, a0, a1
1988 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
1989 ; RV64-NEXT: lui a0, 4112
1990 ; RV64-NEXT: addiw a0, a0, 257
1991 ; RV64-NEXT: slli a1, a0, 32
1992 ; RV64-NEXT: add a0, a0, a1
1993 ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
1994 ; RV64-NEXT: li a0, 56
1995 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
1996 ; RV64-NEXT: ret
1997 ;
1998 ; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64:
1999 ; CHECK-ZVBB: # %bb.0:
2000 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2001 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2002 ; CHECK-ZVBB-NEXT: ret
2003 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
2004 ret <vscale x 7 x i64> %v
2005 }
2007 define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
2008 ; RV32-LABEL: vp_cttz_nxv7i64_unmasked:
2009 ; RV32: # %bb.0:
2010 ; RV32-NEXT: li a1, 1
2011 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2012 ; RV32-NEXT: vsub.vx v16, v8, a1
2013 ; RV32-NEXT: vnot.v v8, v8
2014 ; RV32-NEXT: vand.vv v8, v8, v16
2015 ; RV32-NEXT: vsrl.vi v16, v8, 1
2016 ; RV32-NEXT: lui a1, 349525
2017 ; RV32-NEXT: addi a1, a1, 1365
2018 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2019 ; RV32-NEXT: vmv.v.x v24, a1
2020 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2021 ; RV32-NEXT: vand.vv v16, v16, v24
2022 ; RV32-NEXT: vsub.vv v8, v8, v16
2023 ; RV32-NEXT: lui a1, 209715
2024 ; RV32-NEXT: addi a1, a1, 819
2025 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2026 ; RV32-NEXT: vmv.v.x v16, a1
2027 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2028 ; RV32-NEXT: vand.vv v24, v8, v16
2029 ; RV32-NEXT: vsrl.vi v8, v8, 2
2030 ; RV32-NEXT: vand.vv v8, v8, v16
2031 ; RV32-NEXT: vadd.vv v8, v24, v8
2032 ; RV32-NEXT: vsrl.vi v16, v8, 4
2033 ; RV32-NEXT: vadd.vv v8, v8, v16
2034 ; RV32-NEXT: lui a1, 61681
2035 ; RV32-NEXT: addi a1, a1, -241
2036 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2037 ; RV32-NEXT: vmv.v.x v16, a1
2038 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2039 ; RV32-NEXT: vand.vv v8, v8, v16
2040 ; RV32-NEXT: lui a1, 4112
2041 ; RV32-NEXT: addi a1, a1, 257
2042 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2043 ; RV32-NEXT: vmv.v.x v16, a1
2044 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2045 ; RV32-NEXT: vmul.vv v8, v8, v16
2046 ; RV32-NEXT: li a0, 56
2047 ; RV32-NEXT: vsrl.vx v8, v8, a0
2048 ; RV32-NEXT: ret
2049 ;
2050 ; RV64-LABEL: vp_cttz_nxv7i64_unmasked:
2051 ; RV64: # %bb.0:
2052 ; RV64-NEXT: li a1, 1
2053 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2054 ; RV64-NEXT: vsub.vx v16, v8, a1
2055 ; RV64-NEXT: vnot.v v8, v8
2056 ; RV64-NEXT: vand.vv v8, v8, v16
2057 ; RV64-NEXT: vsrl.vi v16, v8, 1
2058 ; RV64-NEXT: lui a0, 349525
2059 ; RV64-NEXT: addiw a0, a0, 1365
2060 ; RV64-NEXT: slli a1, a0, 32
2061 ; RV64-NEXT: add a0, a0, a1
2062 ; RV64-NEXT: vand.vx v16, v16, a0
2063 ; RV64-NEXT: vsub.vv v8, v8, v16
2064 ; RV64-NEXT: lui a0, 209715
2065 ; RV64-NEXT: addiw a0, a0, 819
2066 ; RV64-NEXT: slli a1, a0, 32
2067 ; RV64-NEXT: add a0, a0, a1
2068 ; RV64-NEXT: vand.vx v16, v8, a0
2069 ; RV64-NEXT: vsrl.vi v8, v8, 2
2070 ; RV64-NEXT: vand.vx v8, v8, a0
2071 ; RV64-NEXT: vadd.vv v8, v16, v8
2072 ; RV64-NEXT: vsrl.vi v16, v8, 4
2073 ; RV64-NEXT: vadd.vv v8, v8, v16
2074 ; RV64-NEXT: lui a0, 61681
2075 ; RV64-NEXT: addiw a0, a0, -241
2076 ; RV64-NEXT: slli a1, a0, 32
2077 ; RV64-NEXT: add a0, a0, a1
2078 ; RV64-NEXT: vand.vx v8, v8, a0
2079 ; RV64-NEXT: lui a0, 4112
2080 ; RV64-NEXT: addiw a0, a0, 257
2081 ; RV64-NEXT: slli a1, a0, 32
2082 ; RV64-NEXT: add a0, a0, a1
2083 ; RV64-NEXT: vmul.vx v8, v8, a0
2084 ; RV64-NEXT: li a0, 56
2085 ; RV64-NEXT: vsrl.vx v8, v8, a0
2086 ; RV64-NEXT: ret
2087 ;
2088 ; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64_unmasked:
2089 ; CHECK-ZVBB: # %bb.0:
2090 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2091 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2092 ; CHECK-ZVBB-NEXT: ret
2093 %head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
2094 %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
2095 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
2096 ret <vscale x 7 x i64> %v
2097 }
2099 declare <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
2101 define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
2102 ; RV32-LABEL: vp_cttz_nxv8i64:
2103 ; RV32: # %bb.0:
2104 ; RV32-NEXT: li a1, 1
2105 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2106 ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
2107 ; RV32-NEXT: vnot.v v8, v8, v0.t
2108 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2109 ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
2110 ; RV32-NEXT: lui a1, 349525
2111 ; RV32-NEXT: addi a1, a1, 1365
2112 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2113 ; RV32-NEXT: vmv.v.x v24, a1
2114 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2115 ; RV32-NEXT: vand.vv v16, v16, v24, v0.t
2116 ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
2117 ; RV32-NEXT: lui a1, 209715
2118 ; RV32-NEXT: addi a1, a1, 819
2119 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2120 ; RV32-NEXT: vmv.v.x v16, a1
2121 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2122 ; RV32-NEXT: vand.vv v24, v8, v16, v0.t
2123 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
2124 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2125 ; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
2126 ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
2127 ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
2128 ; RV32-NEXT: lui a1, 61681
2129 ; RV32-NEXT: addi a1, a1, -241
2130 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2131 ; RV32-NEXT: vmv.v.x v16, a1
2132 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2133 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2134 ; RV32-NEXT: lui a1, 4112
2135 ; RV32-NEXT: addi a1, a1, 257
2136 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2137 ; RV32-NEXT: vmv.v.x v16, a1
2138 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2139 ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
2140 ; RV32-NEXT: li a0, 56
2141 ; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
2142 ; RV32-NEXT: ret
2143 ;
2144 ; RV64-LABEL: vp_cttz_nxv8i64:
2145 ; RV64: # %bb.0:
2146 ; RV64-NEXT: li a1, 1
2147 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2148 ; RV64-NEXT: vsub.vx v16, v8, a1, v0.t
2149 ; RV64-NEXT: vnot.v v8, v8, v0.t
2150 ; RV64-NEXT: vand.vv v8, v8, v16, v0.t
2151 ; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
2152 ; RV64-NEXT: lui a0, 349525
2153 ; RV64-NEXT: addiw a0, a0, 1365
2154 ; RV64-NEXT: slli a1, a0, 32
2155 ; RV64-NEXT: add a0, a0, a1
2156 ; RV64-NEXT: vand.vx v16, v16, a0, v0.t
2157 ; RV64-NEXT: vsub.vv v8, v8, v16, v0.t
2158 ; RV64-NEXT: lui a0, 209715
2159 ; RV64-NEXT: addiw a0, a0, 819
2160 ; RV64-NEXT: slli a1, a0, 32
2161 ; RV64-NEXT: add a0, a0, a1
2162 ; RV64-NEXT: vand.vx v16, v8, a0, v0.t
2163 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
2164 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
2165 ; RV64-NEXT: vadd.vv v8, v16, v8, v0.t
2166 ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
2167 ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
2168 ; RV64-NEXT: lui a0, 61681
2169 ; RV64-NEXT: addiw a0, a0, -241
2170 ; RV64-NEXT: slli a1, a0, 32
2171 ; RV64-NEXT: add a0, a0, a1
2172 ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
2173 ; RV64-NEXT: lui a0, 4112
2174 ; RV64-NEXT: addiw a0, a0, 257
2175 ; RV64-NEXT: slli a1, a0, 32
2176 ; RV64-NEXT: add a0, a0, a1
2177 ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
2178 ; RV64-NEXT: li a0, 56
2179 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
2180 ; RV64-NEXT: ret
2181 ;
2182 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64:
2183 ; CHECK-ZVBB: # %bb.0:
2184 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2185 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2186 ; CHECK-ZVBB-NEXT: ret
2187 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
2188 ret <vscale x 8 x i64> %v
2189 }
2191 define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
2192 ; RV32-LABEL: vp_cttz_nxv8i64_unmasked:
2193 ; RV32: # %bb.0:
2194 ; RV32-NEXT: li a1, 1
2195 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2196 ; RV32-NEXT: vsub.vx v16, v8, a1
2197 ; RV32-NEXT: vnot.v v8, v8
2198 ; RV32-NEXT: vand.vv v8, v8, v16
2199 ; RV32-NEXT: vsrl.vi v16, v8, 1
2200 ; RV32-NEXT: lui a1, 349525
2201 ; RV32-NEXT: addi a1, a1, 1365
2202 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2203 ; RV32-NEXT: vmv.v.x v24, a1
2204 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2205 ; RV32-NEXT: vand.vv v16, v16, v24
2206 ; RV32-NEXT: vsub.vv v8, v8, v16
2207 ; RV32-NEXT: lui a1, 209715
2208 ; RV32-NEXT: addi a1, a1, 819
2209 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2210 ; RV32-NEXT: vmv.v.x v16, a1
2211 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2212 ; RV32-NEXT: vand.vv v24, v8, v16
2213 ; RV32-NEXT: vsrl.vi v8, v8, 2
2214 ; RV32-NEXT: vand.vv v8, v8, v16
2215 ; RV32-NEXT: vadd.vv v8, v24, v8
2216 ; RV32-NEXT: vsrl.vi v16, v8, 4
2217 ; RV32-NEXT: vadd.vv v8, v8, v16
2218 ; RV32-NEXT: lui a1, 61681
2219 ; RV32-NEXT: addi a1, a1, -241
2220 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2221 ; RV32-NEXT: vmv.v.x v16, a1
2222 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2223 ; RV32-NEXT: vand.vv v8, v8, v16
2224 ; RV32-NEXT: lui a1, 4112
2225 ; RV32-NEXT: addi a1, a1, 257
2226 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
2227 ; RV32-NEXT: vmv.v.x v16, a1
2228 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2229 ; RV32-NEXT: vmul.vv v8, v8, v16
2230 ; RV32-NEXT: li a0, 56
2231 ; RV32-NEXT: vsrl.vx v8, v8, a0
2232 ; RV32-NEXT: ret
2233 ;
2234 ; RV64-LABEL: vp_cttz_nxv8i64_unmasked:
2235 ; RV64: # %bb.0:
2236 ; RV64-NEXT: li a1, 1
2237 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2238 ; RV64-NEXT: vsub.vx v16, v8, a1
2239 ; RV64-NEXT: vnot.v v8, v8
2240 ; RV64-NEXT: vand.vv v8, v8, v16
2241 ; RV64-NEXT: vsrl.vi v16, v8, 1
2242 ; RV64-NEXT: lui a0, 349525
2243 ; RV64-NEXT: addiw a0, a0, 1365
2244 ; RV64-NEXT: slli a1, a0, 32
2245 ; RV64-NEXT: add a0, a0, a1
2246 ; RV64-NEXT: vand.vx v16, v16, a0
2247 ; RV64-NEXT: vsub.vv v8, v8, v16
2248 ; RV64-NEXT: lui a0, 209715
2249 ; RV64-NEXT: addiw a0, a0, 819
2250 ; RV64-NEXT: slli a1, a0, 32
2251 ; RV64-NEXT: add a0, a0, a1
2252 ; RV64-NEXT: vand.vx v16, v8, a0
2253 ; RV64-NEXT: vsrl.vi v8, v8, 2
2254 ; RV64-NEXT: vand.vx v8, v8, a0
2255 ; RV64-NEXT: vadd.vv v8, v16, v8
2256 ; RV64-NEXT: vsrl.vi v16, v8, 4
2257 ; RV64-NEXT: vadd.vv v8, v8, v16
2258 ; RV64-NEXT: lui a0, 61681
2259 ; RV64-NEXT: addiw a0, a0, -241
2260 ; RV64-NEXT: slli a1, a0, 32
2261 ; RV64-NEXT: add a0, a0, a1
2262 ; RV64-NEXT: vand.vx v8, v8, a0
2263 ; RV64-NEXT: lui a0, 4112
2264 ; RV64-NEXT: addiw a0, a0, 257
2265 ; RV64-NEXT: slli a1, a0, 32
2266 ; RV64-NEXT: add a0, a0, a1
2267 ; RV64-NEXT: vmul.vx v8, v8, a0
2268 ; RV64-NEXT: li a0, 56
2269 ; RV64-NEXT: vsrl.vx v8, v8, a0
2270 ; RV64-NEXT: ret
2271 ;
2272 ; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64_unmasked:
2273 ; CHECK-ZVBB: # %bb.0:
2274 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2275 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2276 ; CHECK-ZVBB-NEXT: ret
2277 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
2278 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
2279 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
2280 ret <vscale x 8 x i64> %v
2281 }
2283 declare <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
2285 define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
2286 ; RV32-LABEL: vp_cttz_nxv16i64:
2287 ; RV32: # %bb.0:
2288 ; RV32-NEXT: addi sp, sp, -16
2289 ; RV32-NEXT: .cfi_def_cfa_offset 16
2290 ; RV32-NEXT: csrr a1, vlenb
2291 ; RV32-NEXT: li a2, 56
2292 ; RV32-NEXT: mul a1, a1, a2
2293 ; RV32-NEXT: sub sp, sp, a1
2294 ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
2295 ; RV32-NEXT: vmv1r.v v24, v0
2296 ; RV32-NEXT: csrr a1, vlenb
2297 ; RV32-NEXT: slli a1, a1, 5
2298 ; RV32-NEXT: add a1, sp, a1
2299 ; RV32-NEXT: addi a1, a1, 16
2300 ; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
2301 ; RV32-NEXT: csrr a1, vlenb
2302 ; RV32-NEXT: srli a2, a1, 3
2303 ; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
2304 ; RV32-NEXT: vslidedown.vx v0, v0, a2
2305 ; RV32-NEXT: sub a2, a0, a1
2306 ; RV32-NEXT: sltu a3, a0, a2
2307 ; RV32-NEXT: addi a3, a3, -1
2308 ; RV32-NEXT: and a3, a3, a2
2309 ; RV32-NEXT: li a2, 1
2310 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2311 ; RV32-NEXT: vsub.vx v8, v16, a2, v0.t
2312 ; RV32-NEXT: vnot.v v16, v16, v0.t
2313 ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
2314 ; RV32-NEXT: csrr a4, vlenb
2315 ; RV32-NEXT: li a5, 40
2316 ; RV32-NEXT: mul a4, a4, a5
2317 ; RV32-NEXT: add a4, sp, a4
2318 ; RV32-NEXT: addi a4, a4, 16
2319 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2320 ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
2321 ; RV32-NEXT: csrr a4, vlenb
2322 ; RV32-NEXT: li a5, 48
2323 ; RV32-NEXT: mul a4, a4, a5
2324 ; RV32-NEXT: add a4, sp, a4
2325 ; RV32-NEXT: addi a4, a4, 16
2326 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2327 ; RV32-NEXT: lui a4, 349525
2328 ; RV32-NEXT: addi a4, a4, 1365
2329 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2330 ; RV32-NEXT: vmv.v.x v8, a4
2331 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2332 ; RV32-NEXT: csrr a4, vlenb
2333 ; RV32-NEXT: li a5, 24
2334 ; RV32-NEXT: mul a4, a4, a5
2335 ; RV32-NEXT: add a4, sp, a4
2336 ; RV32-NEXT: addi a4, a4, 16
2337 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2338 ; RV32-NEXT: csrr a4, vlenb
2339 ; RV32-NEXT: li a5, 48
2340 ; RV32-NEXT: mul a4, a4, a5
2341 ; RV32-NEXT: add a4, sp, a4
2342 ; RV32-NEXT: addi a4, a4, 16
2343 ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
2344 ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
2345 ; RV32-NEXT: csrr a4, vlenb
2346 ; RV32-NEXT: li a5, 40
2347 ; RV32-NEXT: mul a4, a4, a5
2348 ; RV32-NEXT: add a4, sp, a4
2349 ; RV32-NEXT: addi a4, a4, 16
2350 ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
2351 ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
2352 ; RV32-NEXT: csrr a4, vlenb
2353 ; RV32-NEXT: li a5, 40
2354 ; RV32-NEXT: mul a4, a4, a5
2355 ; RV32-NEXT: add a4, sp, a4
2356 ; RV32-NEXT: addi a4, a4, 16
2357 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2358 ; RV32-NEXT: lui a4, 209715
2359 ; RV32-NEXT: addi a4, a4, 819
2360 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2361 ; RV32-NEXT: vmv.v.x v8, a4
2362 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2363 ; RV32-NEXT: csrr a4, vlenb
2364 ; RV32-NEXT: li a5, 40
2365 ; RV32-NEXT: mul a4, a4, a5
2366 ; RV32-NEXT: add a4, sp, a4
2367 ; RV32-NEXT: addi a4, a4, 16
2368 ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
2369 ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
2370 ; RV32-NEXT: csrr a4, vlenb
2371 ; RV32-NEXT: slli a4, a4, 4
2372 ; RV32-NEXT: add a4, sp, a4
2373 ; RV32-NEXT: addi a4, a4, 16
2374 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
2375 ; RV32-NEXT: csrr a4, vlenb
2376 ; RV32-NEXT: li a5, 40
2377 ; RV32-NEXT: mul a4, a4, a5
2378 ; RV32-NEXT: add a4, sp, a4
2379 ; RV32-NEXT: addi a4, a4, 16
2380 ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
2381 ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
2382 ; RV32-NEXT: csrr a4, vlenb
2383 ; RV32-NEXT: li a5, 48
2384 ; RV32-NEXT: mul a4, a4, a5
2385 ; RV32-NEXT: add a4, sp, a4
2386 ; RV32-NEXT: addi a4, a4, 16
2387 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2388 ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
2389 ; RV32-NEXT: csrr a4, vlenb
2390 ; RV32-NEXT: slli a4, a4, 4
2391 ; RV32-NEXT: add a4, sp, a4
2392 ; RV32-NEXT: addi a4, a4, 16
2393 ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
2394 ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
2395 ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
2396 ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
2397 ; RV32-NEXT: lui a4, 61681
2398 ; RV32-NEXT: addi a4, a4, -241
2399 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2400 ; RV32-NEXT: vmv.v.x v8, a4
2401 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2402 ; RV32-NEXT: csrr a4, vlenb
2403 ; RV32-NEXT: slli a4, a4, 4
2404 ; RV32-NEXT: add a4, sp, a4
2405 ; RV32-NEXT: addi a4, a4, 16
2406 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2407 ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
2408 ; RV32-NEXT: lui a4, 4112
2409 ; RV32-NEXT: addi a4, a4, 257
2410 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2411 ; RV32-NEXT: vmv.v.x v8, a4
2412 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2413 ; RV32-NEXT: csrr a3, vlenb
2414 ; RV32-NEXT: slli a3, a3, 3
2415 ; RV32-NEXT: add a3, sp, a3
2416 ; RV32-NEXT: addi a3, a3, 16
2417 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
2418 ; RV32-NEXT: vmul.vv v8, v16, v8, v0.t
2419 ; RV32-NEXT: li a3, 56
2420 ; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
2421 ; RV32-NEXT: addi a4, sp, 16
2422 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2423 ; RV32-NEXT: bltu a0, a1, .LBB46_2
2424 ; RV32-NEXT: # %bb.1:
2425 ; RV32-NEXT: mv a0, a1
2426 ; RV32-NEXT: .LBB46_2:
2427 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2428 ; RV32-NEXT: vmv1r.v v0, v24
2429 ; RV32-NEXT: csrr a0, vlenb
2430 ; RV32-NEXT: slli a0, a0, 5
2431 ; RV32-NEXT: add a0, sp, a0
2432 ; RV32-NEXT: addi a0, a0, 16
2433 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2434 ; RV32-NEXT: vsub.vx v8, v16, a2, v0.t
2435 ; RV32-NEXT: vnot.v v16, v16, v0.t
2436 ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
2437 ; RV32-NEXT: csrr a0, vlenb
2438 ; RV32-NEXT: slli a0, a0, 5
2439 ; RV32-NEXT: add a0, sp, a0
2440 ; RV32-NEXT: addi a0, a0, 16
2441 ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
2442 ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
2443 ; RV32-NEXT: csrr a0, vlenb
2444 ; RV32-NEXT: li a1, 40
2445 ; RV32-NEXT: mul a0, a0, a1
2446 ; RV32-NEXT: add a0, sp, a0
2447 ; RV32-NEXT: addi a0, a0, 16
2448 ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
2449 ; RV32-NEXT: csrr a0, vlenb
2450 ; RV32-NEXT: li a1, 24
2451 ; RV32-NEXT: mul a0, a0, a1
2452 ; RV32-NEXT: add a0, sp, a0
2453 ; RV32-NEXT: addi a0, a0, 16
2454 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2455 ; RV32-NEXT: csrr a0, vlenb
2456 ; RV32-NEXT: li a1, 40
2457 ; RV32-NEXT: mul a0, a0, a1
2458 ; RV32-NEXT: add a0, sp, a0
2459 ; RV32-NEXT: addi a0, a0, 16
2460 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2461 ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
2462 ; RV32-NEXT: csrr a0, vlenb
2463 ; RV32-NEXT: slli a0, a0, 5
2464 ; RV32-NEXT: add a0, sp, a0
2465 ; RV32-NEXT: addi a0, a0, 16
2466 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2467 ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
2468 ; RV32-NEXT: csrr a0, vlenb
2469 ; RV32-NEXT: li a1, 40
2470 ; RV32-NEXT: mul a0, a0, a1
2471 ; RV32-NEXT: add a0, sp, a0
2472 ; RV32-NEXT: addi a0, a0, 16
2473 ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
2474 ; RV32-NEXT: csrr a0, vlenb
2475 ; RV32-NEXT: li a1, 48
2476 ; RV32-NEXT: mul a0, a0, a1
2477 ; RV32-NEXT: add a0, sp, a0
2478 ; RV32-NEXT: addi a0, a0, 16
2479 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2480 ; RV32-NEXT: csrr a0, vlenb
2481 ; RV32-NEXT: li a1, 40
2482 ; RV32-NEXT: mul a0, a0, a1
2483 ; RV32-NEXT: add a0, sp, a0
2484 ; RV32-NEXT: addi a0, a0, 16
2485 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2486 ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
2487 ; RV32-NEXT: csrr a0, vlenb
2488 ; RV32-NEXT: slli a0, a0, 5
2489 ; RV32-NEXT: add a0, sp, a0
2490 ; RV32-NEXT: addi a0, a0, 16
2491 ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
2492 ; RV32-NEXT: csrr a0, vlenb
2493 ; RV32-NEXT: li a1, 40
2494 ; RV32-NEXT: mul a0, a0, a1
2495 ; RV32-NEXT: add a0, sp, a0
2496 ; RV32-NEXT: addi a0, a0, 16
2497 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2498 ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
2499 ; RV32-NEXT: csrr a0, vlenb
2500 ; RV32-NEXT: li a1, 48
2501 ; RV32-NEXT: mul a0, a0, a1
2502 ; RV32-NEXT: add a0, sp, a0
2503 ; RV32-NEXT: addi a0, a0, 16
2504 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2505 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2506 ; RV32-NEXT: csrr a0, vlenb
2507 ; RV32-NEXT: slli a0, a0, 5
2508 ; RV32-NEXT: add a0, sp, a0
2509 ; RV32-NEXT: addi a0, a0, 16
2510 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2511 ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
2512 ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
2513 ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
2514 ; RV32-NEXT: csrr a0, vlenb
2515 ; RV32-NEXT: slli a0, a0, 4
2516 ; RV32-NEXT: add a0, sp, a0
2517 ; RV32-NEXT: addi a0, a0, 16
2518 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2519 ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2520 ; RV32-NEXT: csrr a0, vlenb
2521 ; RV32-NEXT: slli a0, a0, 3
2522 ; RV32-NEXT: add a0, sp, a0
2523 ; RV32-NEXT: addi a0, a0, 16
2524 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2525 ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
2526 ; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
2527 ; RV32-NEXT: addi a0, sp, 16
2528 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2529 ; RV32-NEXT: csrr a0, vlenb
2530 ; RV32-NEXT: li a1, 56
2531 ; RV32-NEXT: mul a0, a0, a1
2532 ; RV32-NEXT: add sp, sp, a0
2533 ; RV32-NEXT: addi sp, sp, 16
2534 ; RV32-NEXT: ret
2535 ;
2536 ; RV64-LABEL: vp_cttz_nxv16i64:
2537 ; RV64: # %bb.0:
2538 ; RV64-NEXT: addi sp, sp, -16
2539 ; RV64-NEXT: .cfi_def_cfa_offset 16
2540 ; RV64-NEXT: csrr a1, vlenb
2541 ; RV64-NEXT: slli a1, a1, 4
2542 ; RV64-NEXT: sub sp, sp, a1
2543 ; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
2544 ; RV64-NEXT: vmv1r.v v24, v0
2545 ; RV64-NEXT: csrr a1, vlenb
2546 ; RV64-NEXT: slli a1, a1, 3
2547 ; RV64-NEXT: add a1, sp, a1
2548 ; RV64-NEXT: addi a1, a1, 16
2549 ; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
2550 ; RV64-NEXT: csrr a1, vlenb
2551 ; RV64-NEXT: srli a2, a1, 3
2552 ; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
2553 ; RV64-NEXT: vslidedown.vx v0, v0, a2
2554 ; RV64-NEXT: sub a2, a0, a1
2555 ; RV64-NEXT: sltu a3, a0, a2
2556 ; RV64-NEXT: addi a3, a3, -1
2557 ; RV64-NEXT: and a3, a3, a2
2558 ; RV64-NEXT: li a2, 1
2559 ; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2560 ; RV64-NEXT: vsub.vx v8, v16, a2, v0.t
2561 ; RV64-NEXT: vnot.v v16, v16, v0.t
2562 ; RV64-NEXT: vand.vv v16, v16, v8, v0.t
2563 ; RV64-NEXT: vsrl.vi v8, v16, 1, v0.t
2564 ; RV64-NEXT: lui a3, 349525
2565 ; RV64-NEXT: addiw a3, a3, 1365
2566 ; RV64-NEXT: slli a4, a3, 32
2567 ; RV64-NEXT: add a3, a3, a4
2568 ; RV64-NEXT: vand.vx v8, v8, a3, v0.t
2569 ; RV64-NEXT: vsub.vv v16, v16, v8, v0.t
2570 ; RV64-NEXT: lui a4, 209715
2571 ; RV64-NEXT: addiw a4, a4, 819
2572 ; RV64-NEXT: slli a5, a4, 32
2573 ; RV64-NEXT: add a4, a4, a5
2574 ; RV64-NEXT: vand.vx v8, v16, a4, v0.t
2575 ; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
2576 ; RV64-NEXT: vand.vx v16, v16, a4, v0.t
2577 ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
2578 ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
2579 ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
2580 ; RV64-NEXT: lui a5, 61681
2581 ; RV64-NEXT: addiw a5, a5, -241
2582 ; RV64-NEXT: slli a6, a5, 32
2583 ; RV64-NEXT: add a5, a5, a6
2584 ; RV64-NEXT: vand.vx v8, v8, a5, v0.t
2585 ; RV64-NEXT: lui a6, 4112
2586 ; RV64-NEXT: addiw a6, a6, 257
2587 ; RV64-NEXT: slli a7, a6, 32
2588 ; RV64-NEXT: add a6, a6, a7
2589 ; RV64-NEXT: vmul.vx v8, v8, a6, v0.t
2590 ; RV64-NEXT: li a7, 56
2591 ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
2592 ; RV64-NEXT: addi t0, sp, 16
2593 ; RV64-NEXT: vs8r.v v8, (t0) # Unknown-size Folded Spill
2594 ; RV64-NEXT: bltu a0, a1, .LBB46_2
2595 ; RV64-NEXT: # %bb.1:
2596 ; RV64-NEXT: mv a0, a1
2597 ; RV64-NEXT: .LBB46_2:
2598 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2599 ; RV64-NEXT: vmv1r.v v0, v24
2600 ; RV64-NEXT: csrr a0, vlenb
2601 ; RV64-NEXT: slli a0, a0, 3
2602 ; RV64-NEXT: add a0, sp, a0
2603 ; RV64-NEXT: addi a0, a0, 16
2604 ; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2605 ; RV64-NEXT: vsub.vx v16, v8, a2, v0.t
2606 ; RV64-NEXT: vnot.v v8, v8, v0.t
2607 ; RV64-NEXT: vand.vv v8, v8, v16, v0.t
2608 ; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
2609 ; RV64-NEXT: vand.vx v16, v16, a3, v0.t
2610 ; RV64-NEXT: vsub.vv v8, v8, v16, v0.t
2611 ; RV64-NEXT: vand.vx v16, v8, a4, v0.t
2612 ; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
2613 ; RV64-NEXT: vand.vx v8, v8, a4, v0.t
2614 ; RV64-NEXT: vadd.vv v8, v16, v8, v0.t
2615 ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
2616 ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
2617 ; RV64-NEXT: vand.vx v8, v8, a5, v0.t
2618 ; RV64-NEXT: vmul.vx v8, v8, a6, v0.t
2619 ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
2620 ; RV64-NEXT: addi a0, sp, 16
2621 ; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2622 ; RV64-NEXT: csrr a0, vlenb
2623 ; RV64-NEXT: slli a0, a0, 4
2624 ; RV64-NEXT: add sp, sp, a0
2625 ; RV64-NEXT: addi sp, sp, 16
2626 ; RV64-NEXT: ret
2627 ;
2628 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
2629 ; CHECK-ZVBB: # %bb.0:
2630 ; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
2631 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
2632 ; CHECK-ZVBB-NEXT: srli a2, a1, 3
2633 ; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
2634 ; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
2635 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
2636 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
2637 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
2638 ; CHECK-ZVBB-NEXT: and a2, a3, a2
2639 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
2640 ; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
2641 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
2642 ; CHECK-ZVBB-NEXT: # %bb.1:
2643 ; CHECK-ZVBB-NEXT: mv a0, a1
2644 ; CHECK-ZVBB-NEXT: .LBB46_2:
2645 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2646 ; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
2647 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2648 ; CHECK-ZVBB-NEXT: ret
2649 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
2650 ret <vscale x 16 x i64> %v
2651 }
2653 define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
2654 ; RV32-LABEL: vp_cttz_nxv16i64_unmasked:
2655 ; RV32: # %bb.0:
2656 ; RV32-NEXT: addi sp, sp, -16
2657 ; RV32-NEXT: .cfi_def_cfa_offset 16
2658 ; RV32-NEXT: csrr a1, vlenb
2659 ; RV32-NEXT: li a2, 40
2660 ; RV32-NEXT: mul a1, a1, a2
2661 ; RV32-NEXT: sub sp, sp, a1
2662 ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
2663 ; RV32-NEXT: csrr a1, vlenb
2664 ; RV32-NEXT: slli a1, a1, 5
2665 ; RV32-NEXT: add a1, sp, a1
2666 ; RV32-NEXT: addi a1, a1, 16
2667 ; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
2668 ; RV32-NEXT: csrr a1, vlenb
2669 ; RV32-NEXT: sub a2, a0, a1
2670 ; RV32-NEXT: sltu a3, a0, a2
2671 ; RV32-NEXT: addi a3, a3, -1
2672 ; RV32-NEXT: and a3, a3, a2
2673 ; RV32-NEXT: li a2, 1
2674 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2675 ; RV32-NEXT: vsub.vx v8, v16, a2
2676 ; RV32-NEXT: vnot.v v16, v16
2677 ; RV32-NEXT: vand.vv v8, v16, v8
2678 ; RV32-NEXT: vsrl.vi v24, v8, 1
2679 ; RV32-NEXT: lui a4, 349525
2680 ; RV32-NEXT: addi a4, a4, 1365
2681 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2682 ; RV32-NEXT: vmv.v.x v16, a4
2683 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2684 ; RV32-NEXT: csrr a4, vlenb
2685 ; RV32-NEXT: li a5, 24
2686 ; RV32-NEXT: mul a4, a4, a5
2687 ; RV32-NEXT: add a4, sp, a4
2688 ; RV32-NEXT: addi a4, a4, 16
2689 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
2690 ; RV32-NEXT: vand.vv v24, v24, v16
2691 ; RV32-NEXT: vsub.vv v8, v8, v24
2692 ; RV32-NEXT: lui a4, 209715
2693 ; RV32-NEXT: addi a4, a4, 819
2694 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2695 ; RV32-NEXT: vmv.v.x v0, a4
2696 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2697 ; RV32-NEXT: vand.vv v24, v8, v0
2698 ; RV32-NEXT: vsrl.vi v8, v8, 2
2699 ; RV32-NEXT: vand.vv v8, v8, v0
2700 ; RV32-NEXT: vadd.vv v8, v24, v8
2701 ; RV32-NEXT: vsrl.vi v24, v8, 4
2702 ; RV32-NEXT: vadd.vv v8, v8, v24
2703 ; RV32-NEXT: lui a4, 61681
2704 ; RV32-NEXT: addi a4, a4, -241
2705 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2706 ; RV32-NEXT: vmv.v.x v16, a4
2707 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2708 ; RV32-NEXT: csrr a4, vlenb
2709 ; RV32-NEXT: slli a4, a4, 4
2710 ; RV32-NEXT: add a4, sp, a4
2711 ; RV32-NEXT: addi a4, a4, 16
2712 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
2713 ; RV32-NEXT: vand.vv v16, v8, v16
2714 ; RV32-NEXT: lui a4, 4112
2715 ; RV32-NEXT: addi a4, a4, 257
2716 ; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
2717 ; RV32-NEXT: vmv.v.x v8, a4
2718 ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2719 ; RV32-NEXT: csrr a3, vlenb
2720 ; RV32-NEXT: slli a3, a3, 3
2721 ; RV32-NEXT: add a3, sp, a3
2722 ; RV32-NEXT: addi a3, a3, 16
2723 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
2724 ; RV32-NEXT: vmul.vv v16, v16, v8
2725 ; RV32-NEXT: li a3, 56
2726 ; RV32-NEXT: vsrl.vx v8, v16, a3
2727 ; RV32-NEXT: addi a4, sp, 16
2728 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2729 ; RV32-NEXT: bltu a0, a1, .LBB47_2
2730 ; RV32-NEXT: # %bb.1:
2731 ; RV32-NEXT: mv a0, a1
2732 ; RV32-NEXT: .LBB47_2:
2733 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2734 ; RV32-NEXT: csrr a0, vlenb
2735 ; RV32-NEXT: slli a0, a0, 5
2736 ; RV32-NEXT: add a0, sp, a0
2737 ; RV32-NEXT: addi a0, a0, 16
2738 ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
2739 ; RV32-NEXT: vsub.vx v16, v24, a2
2740 ; RV32-NEXT: vnot.v v24, v24
2741 ; RV32-NEXT: vand.vv v16, v24, v16
2742 ; RV32-NEXT: vsrl.vi v24, v16, 1
2743 ; RV32-NEXT: csrr a0, vlenb
2744 ; RV32-NEXT: li a1, 24
2745 ; RV32-NEXT: mul a0, a0, a1
2746 ; RV32-NEXT: add a0, sp, a0
2747 ; RV32-NEXT: addi a0, a0, 16
2748 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2749 ; RV32-NEXT: vand.vv v24, v24, v8
2750 ; RV32-NEXT: vsub.vv v16, v16, v24
2751 ; RV32-NEXT: vand.vv v24, v16, v0
2752 ; RV32-NEXT: vsrl.vi v16, v16, 2
2753 ; RV32-NEXT: vand.vv v16, v16, v0
2754 ; RV32-NEXT: vadd.vv v16, v24, v16
2755 ; RV32-NEXT: vsrl.vi v24, v16, 4
2756 ; RV32-NEXT: vadd.vv v16, v16, v24
2757 ; RV32-NEXT: csrr a0, vlenb
2758 ; RV32-NEXT: slli a0, a0, 4
2759 ; RV32-NEXT: add a0, sp, a0
2760 ; RV32-NEXT: addi a0, a0, 16
2761 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2762 ; RV32-NEXT: vand.vv v16, v16, v8
2763 ; RV32-NEXT: csrr a0, vlenb
2764 ; RV32-NEXT: slli a0, a0, 3
2765 ; RV32-NEXT: add a0, sp, a0
2766 ; RV32-NEXT: addi a0, a0, 16
2767 ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2768 ; RV32-NEXT: vmul.vv v8, v16, v8
2769 ; RV32-NEXT: vsrl.vx v8, v8, a3
2770 ; RV32-NEXT: addi a0, sp, 16
2771 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2772 ; RV32-NEXT: csrr a0, vlenb
2773 ; RV32-NEXT: li a1, 40
2774 ; RV32-NEXT: mul a0, a0, a1
2775 ; RV32-NEXT: add sp, sp, a0
2776 ; RV32-NEXT: addi sp, sp, 16
2777 ; RV32-NEXT: ret
2778 ;
2779 ; RV64-LABEL: vp_cttz_nxv16i64_unmasked:
2780 ; RV64: # %bb.0:
2781 ; RV64-NEXT: csrr a1, vlenb
2782 ; RV64-NEXT: sub a2, a0, a1
2783 ; RV64-NEXT: sltu a3, a0, a2
2784 ; RV64-NEXT: addi a3, a3, -1
2785 ; RV64-NEXT: and a3, a3, a2
2786 ; RV64-NEXT: li a2, 1
2787 ; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
2788 ; RV64-NEXT: vsub.vx v24, v16, a2
2789 ; RV64-NEXT: vnot.v v16, v16
2790 ; RV64-NEXT: vand.vv v16, v16, v24
2791 ; RV64-NEXT: vsrl.vi v24, v16, 1
2792 ; RV64-NEXT: lui a3, 349525
2793 ; RV64-NEXT: addiw a3, a3, 1365
2794 ; RV64-NEXT: slli a4, a3, 32
2795 ; RV64-NEXT: add a3, a3, a4
2796 ; RV64-NEXT: vand.vx v24, v24, a3
2797 ; RV64-NEXT: vsub.vv v16, v16, v24
2798 ; RV64-NEXT: lui a4, 209715
2799 ; RV64-NEXT: addiw a4, a4, 819
2800 ; RV64-NEXT: slli a5, a4, 32
2801 ; RV64-NEXT: add a4, a4, a5
2802 ; RV64-NEXT: vand.vx v24, v16, a4
2803 ; RV64-NEXT: vsrl.vi v16, v16, 2
2804 ; RV64-NEXT: vand.vx v16, v16, a4
2805 ; RV64-NEXT: vadd.vv v16, v24, v16
2806 ; RV64-NEXT: vsrl.vi v24, v16, 4
2807 ; RV64-NEXT: vadd.vv v16, v16, v24
2808 ; RV64-NEXT: lui a5, 61681
2809 ; RV64-NEXT: addiw a5, a5, -241
2810 ; RV64-NEXT: slli a6, a5, 32
2811 ; RV64-NEXT: add a5, a5, a6
2812 ; RV64-NEXT: vand.vx v16, v16, a5
2813 ; RV64-NEXT: lui a6, 4112
2814 ; RV64-NEXT: addiw a6, a6, 257
2815 ; RV64-NEXT: slli a7, a6, 32
2816 ; RV64-NEXT: add a6, a6, a7
2817 ; RV64-NEXT: vmul.vx v16, v16, a6
2818 ; RV64-NEXT: li a7, 56
2819 ; RV64-NEXT: vsrl.vx v16, v16, a7
2820 ; RV64-NEXT: bltu a0, a1, .LBB47_2
2821 ; RV64-NEXT: # %bb.1:
2822 ; RV64-NEXT: mv a0, a1
2823 ; RV64-NEXT: .LBB47_2:
2824 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2825 ; RV64-NEXT: vsub.vx v24, v8, a2
2826 ; RV64-NEXT: vnot.v v8, v8
2827 ; RV64-NEXT: vand.vv v8, v8, v24
2828 ; RV64-NEXT: vsrl.vi v24, v8, 1
2829 ; RV64-NEXT: vand.vx v24, v24, a3
2830 ; RV64-NEXT: vsub.vv v8, v8, v24
2831 ; RV64-NEXT: vand.vx v24, v8, a4
2832 ; RV64-NEXT: vsrl.vi v8, v8, 2
2833 ; RV64-NEXT: vand.vx v8, v8, a4
2834 ; RV64-NEXT: vadd.vv v8, v24, v8
2835 ; RV64-NEXT: vsrl.vi v24, v8, 4
2836 ; RV64-NEXT: vadd.vv v8, v8, v24
2837 ; RV64-NEXT: vand.vx v8, v8, a5
2838 ; RV64-NEXT: vmul.vx v8, v8, a6
2839 ; RV64-NEXT: vsrl.vx v8, v8, a7
2840 ; RV64-NEXT: ret
2841 ;
2842 ; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64_unmasked:
2843 ; CHECK-ZVBB: # %bb.0:
2844 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
2845 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
2846 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
2847 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
2848 ; CHECK-ZVBB-NEXT: and a2, a3, a2
2849 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
2850 ; CHECK-ZVBB-NEXT: vctz.v v16, v16
2851 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_2
2852 ; CHECK-ZVBB-NEXT: # %bb.1:
2853 ; CHECK-ZVBB-NEXT: mv a0, a1
2854 ; CHECK-ZVBB-NEXT: .LBB47_2:
2855 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2856 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2857 ; CHECK-ZVBB-NEXT: ret
2858 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
2859 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
2860 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
2861 ret <vscale x 16 x i64> %v
2862 }
2864 define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2865 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8:
2866 ; CHECK: # %bb.0:
2867 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
2868 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
2869 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
2870 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2871 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
2872 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
2873 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2874 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
2875 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2876 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2877 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
2878 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2879 ; CHECK-NEXT: li a0, 127
2880 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2881 ; CHECK-NEXT: ret
2882 ;
2883 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8:
2884 ; CHECK-ZVBB: # %bb.0:
2885 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
2886 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2887 ; CHECK-ZVBB-NEXT: ret
2888 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2889 ret <vscale x 1 x i8> %v
2890 }
2892 define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
2893 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
2894 ; CHECK: # %bb.0:
2895 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
2896 ; CHECK-NEXT: vrsub.vi v9, v8, 0
2897 ; CHECK-NEXT: vand.vv v8, v8, v9
2898 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2899 ; CHECK-NEXT: vzext.vf2 v9, v8
2900 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
2901 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
2902 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
2903 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
2904 ; CHECK-NEXT: li a0, 127
2905 ; CHECK-NEXT: vsub.vx v8, v8, a0
2906 ; CHECK-NEXT: ret
2907 ;
2908 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
2909 ; CHECK-ZVBB: # %bb.0:
2910 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
2911 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2912 ; CHECK-ZVBB-NEXT: ret
2913 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
2914 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
2915 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2916 ret <vscale x 1 x i8> %v
2917 }
2920 define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
2921 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8:
2922 ; CHECK: # %bb.0:
2923 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
2924 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
2925 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
2926 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
2927 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
2928 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
2929 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2930 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
2931 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
2932 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2933 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
2934 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2935 ; CHECK-NEXT: li a0, 127
2936 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2937 ; CHECK-NEXT: ret
2938 ;
2939 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8:
2940 ; CHECK-ZVBB: # %bb.0:
2941 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
2942 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2943 ; CHECK-ZVBB-NEXT: ret
2944 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
2945 ret <vscale x 2 x i8> %v
2946 }
2948 define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
2949 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
2950 ; CHECK: # %bb.0:
2951 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
2952 ; CHECK-NEXT: vrsub.vi v9, v8, 0
2953 ; CHECK-NEXT: vand.vv v8, v8, v9
2954 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
2955 ; CHECK-NEXT: vzext.vf2 v9, v8
2956 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
2957 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
2958 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
2959 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
2960 ; CHECK-NEXT: li a0, 127
2961 ; CHECK-NEXT: vsub.vx v8, v8, a0
2962 ; CHECK-NEXT: ret
2963 ;
2964 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
2965 ; CHECK-ZVBB: # %bb.0:
2966 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
2967 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2968 ; CHECK-ZVBB-NEXT: ret
2969 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
2970 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
2971 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
2972 ret <vscale x 2 x i8> %v
2973 }
2976 define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
2977 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8:
2978 ; CHECK: # %bb.0:
2979 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
2980 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
2981 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
2982 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
2983 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
2984 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9, v0.t
2985 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
2986 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
2987 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
2988 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
2989 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
2990 ; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
2991 ; CHECK-NEXT: li a0, 127
2992 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2993 ; CHECK-NEXT: ret
2994 ;
2995 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8:
2996 ; CHECK-ZVBB: # %bb.0:
2997 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
2998 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
2999 ; CHECK-ZVBB-NEXT: ret
3000 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3001 ret <vscale x 4 x i8> %v
3002 }
3004 define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
3005 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
3006 ; CHECK: # %bb.0:
3007 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
3008 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3009 ; CHECK-NEXT: vand.vv v8, v8, v9
3010 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
3011 ; CHECK-NEXT: vzext.vf2 v9, v8
3012 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
3013 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
3014 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
3015 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
3016 ; CHECK-NEXT: li a0, 127
3017 ; CHECK-NEXT: vsub.vx v8, v8, a0
3018 ; CHECK-NEXT: ret
3019 ;
3020 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
3021 ; CHECK-ZVBB: # %bb.0:
3022 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
3023 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3024 ; CHECK-ZVBB-NEXT: ret
3025 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
3026 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
3027 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3028 ret <vscale x 4 x i8> %v
3029 }
3032 define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
3033 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8:
3034 ; CHECK: # %bb.0:
3035 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
3036 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3037 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3038 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
3039 ; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
3040 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10, v0.t
3041 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3042 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
3043 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
3044 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
3045 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
3046 ; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
3047 ; CHECK-NEXT: li a0, 127
3048 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
3049 ; CHECK-NEXT: ret
3050 ;
3051 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8:
3052 ; CHECK-ZVBB: # %bb.0:
3053 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
3054 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3055 ; CHECK-ZVBB-NEXT: ret
3056 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3057 ret <vscale x 8 x i8> %v
3058 }
3060 define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
3061 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
3062 ; CHECK: # %bb.0:
3063 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
3064 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3065 ; CHECK-NEXT: vand.vv v8, v8, v9
3066 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
3067 ; CHECK-NEXT: vzext.vf2 v10, v8
3068 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
3069 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
3070 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
3071 ; CHECK-NEXT: vnsrl.wi v10, v8, 0
3072 ; CHECK-NEXT: li a0, 127
3073 ; CHECK-NEXT: vsub.vx v8, v10, a0
3074 ; CHECK-NEXT: ret
3075 ;
3076 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
3077 ; CHECK-ZVBB: # %bb.0:
3078 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
3079 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3080 ; CHECK-ZVBB-NEXT: ret
3081 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
3082 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
3083 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3084 ret <vscale x 8 x i8> %v
3085 }
3088 define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
3089 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8:
3090 ; CHECK: # %bb.0:
3091 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
3092 ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
3093 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
3094 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
3095 ; CHECK-NEXT: vzext.vf2 v12, v8, v0.t
3096 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12, v0.t
3097 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
3098 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
3099 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
3100 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
3101 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
3102 ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
3103 ; CHECK-NEXT: li a0, 127
3104 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
3105 ; CHECK-NEXT: ret
3106 ;
3107 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8:
3108 ; CHECK-ZVBB: # %bb.0:
3109 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
3110 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3111 ; CHECK-ZVBB-NEXT: ret
3112 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3113 ret <vscale x 16 x i8> %v
3114 }
3116 define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
3117 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
3118 ; CHECK: # %bb.0:
3119 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
3120 ; CHECK-NEXT: vrsub.vi v10, v8, 0
3121 ; CHECK-NEXT: vand.vv v8, v8, v10
3122 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
3123 ; CHECK-NEXT: vzext.vf2 v12, v8
3124 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
3125 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
3126 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
3127 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
3128 ; CHECK-NEXT: li a0, 127
3129 ; CHECK-NEXT: vsub.vx v8, v12, a0
3130 ; CHECK-NEXT: ret
3131 ;
3132 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
3133 ; CHECK-ZVBB: # %bb.0:
3134 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
3135 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3136 ; CHECK-ZVBB-NEXT: ret
3137 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
3138 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
3139 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3140 ret <vscale x 16 x i8> %v
3141 }
3144 define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
3145 ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8:
3146 ; CHECK: # %bb.0:
3147 ; CHECK-NEXT: li a1, 1
3148 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
3149 ; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
3150 ; CHECK-NEXT: vnot.v v8, v8, v0.t
3151 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
3152 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
3153 ; CHECK-NEXT: li a0, 85
3154 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
3155 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
3156 ; CHECK-NEXT: li a0, 51
3157 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
3158 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
3159 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
3160 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
3161 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
3162 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
3163 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
3164 ; CHECK-NEXT: ret
3165 ;
3166 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8:
3167 ; CHECK-ZVBB: # %bb.0:
3168 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
3169 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3170 ; CHECK-ZVBB-NEXT: ret
3171 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
3172 ret <vscale x 32 x i8> %v
3173 }
3175 define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
3176 ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
3177 ; CHECK: # %bb.0:
3178 ; CHECK-NEXT: li a1, 1
3179 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
3180 ; CHECK-NEXT: vsub.vx v12, v8, a1
3181 ; CHECK-NEXT: vnot.v v8, v8
3182 ; CHECK-NEXT: vand.vv v8, v8, v12
3183 ; CHECK-NEXT: vsrl.vi v12, v8, 1
3184 ; CHECK-NEXT: li a0, 85
3185 ; CHECK-NEXT: vand.vx v12, v12, a0
3186 ; CHECK-NEXT: vsub.vv v8, v8, v12
3187 ; CHECK-NEXT: li a0, 51
3188 ; CHECK-NEXT: vand.vx v12, v8, a0
3189 ; CHECK-NEXT: vsrl.vi v8, v8, 2
3190 ; CHECK-NEXT: vand.vx v8, v8, a0
3191 ; CHECK-NEXT: vadd.vv v8, v12, v8
3192 ; CHECK-NEXT: vsrl.vi v12, v8, 4
3193 ; CHECK-NEXT: vadd.vv v8, v8, v12
3194 ; CHECK-NEXT: vand.vi v8, v8, 15
3195 ; CHECK-NEXT: ret
3196 ;
3197 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
3198 ; CHECK-ZVBB: # %bb.0:
3199 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
3200 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3201 ; CHECK-ZVBB-NEXT: ret
3202 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
3203 %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
3204 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
3205 ret <vscale x 32 x i8> %v
3206 }
3209 define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
3210 ; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8:
3211 ; CHECK: # %bb.0:
3212 ; CHECK-NEXT: li a1, 1
3213 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
3214 ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
3215 ; CHECK-NEXT: vnot.v v8, v8, v0.t
3216 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
3217 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
3218 ; CHECK-NEXT: li a0, 85
3219 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
3220 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
3221 ; CHECK-NEXT: li a0, 51
3222 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
3223 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
3224 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
3225 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
3226 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3227 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
3228 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
3229 ; CHECK-NEXT: ret
3230 ;
3231 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8:
3232 ; CHECK-ZVBB: # %bb.0:
3233 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
3234 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3235 ; CHECK-ZVBB-NEXT: ret
3236 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
3237 ret <vscale x 64 x i8> %v
3238 }
3240 define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
3241 ; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
3242 ; CHECK: # %bb.0:
3243 ; CHECK-NEXT: li a1, 1
3244 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
3245 ; CHECK-NEXT: vsub.vx v16, v8, a1
3246 ; CHECK-NEXT: vnot.v v8, v8
3247 ; CHECK-NEXT: vand.vv v8, v8, v16
3248 ; CHECK-NEXT: vsrl.vi v16, v8, 1
3249 ; CHECK-NEXT: li a0, 85
3250 ; CHECK-NEXT: vand.vx v16, v16, a0
3251 ; CHECK-NEXT: vsub.vv v8, v8, v16
3252 ; CHECK-NEXT: li a0, 51
3253 ; CHECK-NEXT: vand.vx v16, v8, a0
3254 ; CHECK-NEXT: vsrl.vi v8, v8, 2
3255 ; CHECK-NEXT: vand.vx v8, v8, a0
3256 ; CHECK-NEXT: vadd.vv v8, v16, v8
3257 ; CHECK-NEXT: vsrl.vi v16, v8, 4
3258 ; CHECK-NEXT: vadd.vv v8, v8, v16
3259 ; CHECK-NEXT: vand.vi v8, v8, 15
3260 ; CHECK-NEXT: ret
3261 ;
3262 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
3263 ; CHECK-ZVBB: # %bb.0:
3264 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
3265 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3266 ; CHECK-ZVBB-NEXT: ret
3267 %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0
3268 %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
3269 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
3270 ret <vscale x 64 x i8> %v
3271 }
3274 define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
3275 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16:
3276 ; CHECK: # %bb.0:
3277 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
3278 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3279 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3280 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
3281 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3282 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
3283 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
3284 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
3285 ; CHECK-NEXT: li a0, 127
3286 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
3287 ; CHECK-NEXT: ret
3288 ;
3289 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16:
3290 ; CHECK-ZVBB: # %bb.0:
3291 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
3292 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3293 ; CHECK-ZVBB-NEXT: ret
3294 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3295 ret <vscale x 1 x i16> %v
3296 }
3298 define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
3299 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
3300 ; CHECK: # %bb.0:
3301 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
3302 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3303 ; CHECK-NEXT: vand.vv v8, v8, v9
3304 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
3305 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
3306 ; CHECK-NEXT: li a0, 127
3307 ; CHECK-NEXT: vsub.vx v8, v8, a0
3308 ; CHECK-NEXT: ret
3309 ;
3310 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
3311 ; CHECK-ZVBB: # %bb.0:
3312 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
3313 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3314 ; CHECK-ZVBB-NEXT: ret
3315 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
3316 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
3317 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3318 ret <vscale x 1 x i16> %v
3319 }
3322 define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
3323 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16:
3324 ; CHECK: # %bb.0:
3325 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
3326 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3327 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3328 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
3329 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3330 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
3331 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
3332 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
3333 ; CHECK-NEXT: li a0, 127
3334 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
3335 ; CHECK-NEXT: ret
3336 ;
3337 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16:
3338 ; CHECK-ZVBB: # %bb.0:
3339 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
3340 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3341 ; CHECK-ZVBB-NEXT: ret
3342 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3343 ret <vscale x 2 x i16> %v
3344 }
3346 define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
3347 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
3348 ; CHECK: # %bb.0:
3349 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
3350 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3351 ; CHECK-NEXT: vand.vv v8, v8, v9
3352 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
3353 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
3354 ; CHECK-NEXT: li a0, 127
3355 ; CHECK-NEXT: vsub.vx v8, v8, a0
3356 ; CHECK-NEXT: ret
3357 ;
3358 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
3359 ; CHECK-ZVBB: # %bb.0:
3360 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
3361 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3362 ; CHECK-ZVBB-NEXT: ret
3363 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
3364 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
3365 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3366 ret <vscale x 2 x i16> %v
3367 }
3370 define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
3371 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16:
3372 ; CHECK: # %bb.0:
3373 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
3374 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3375 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3376 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
3377 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3378 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
3379 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
3380 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
3381 ; CHECK-NEXT: li a0, 127
3382 ; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
3383 ; CHECK-NEXT: ret
3384 ;
3385 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16:
3386 ; CHECK-ZVBB: # %bb.0:
3387 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
3388 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3389 ; CHECK-ZVBB-NEXT: ret
3390 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3391 ret <vscale x 4 x i16> %v
3392 }
3394 define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
3395 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
3396 ; CHECK: # %bb.0:
3397 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
3398 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3399 ; CHECK-NEXT: vand.vv v8, v8, v9
3400 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
3401 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
3402 ; CHECK-NEXT: li a0, 127
3403 ; CHECK-NEXT: vsub.vx v8, v8, a0
3404 ; CHECK-NEXT: ret
3405 ;
3406 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
3407 ; CHECK-ZVBB: # %bb.0:
3408 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
3409 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3410 ; CHECK-ZVBB-NEXT: ret
3411 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
3412 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
3413 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3414 ret <vscale x 4 x i16> %v
3415 }
3418 define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
3419 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16:
3420 ; CHECK: # %bb.0:
3421 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
3422 ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
3423 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
3424 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
3425 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3426 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
3427 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
3428 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
3429 ; CHECK-NEXT: li a0, 127
3430 ; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
3431 ; CHECK-NEXT: ret
3432 ;
3433 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16:
3434 ; CHECK-ZVBB: # %bb.0:
3435 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
3436 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3437 ; CHECK-ZVBB-NEXT: ret
3438 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3439 ret <vscale x 8 x i16> %v
3440 }
3442 define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
3443 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
3444 ; CHECK: # %bb.0:
3445 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
3446 ; CHECK-NEXT: vrsub.vi v10, v8, 0
3447 ; CHECK-NEXT: vand.vv v8, v8, v10
3448 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
3449 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
3450 ; CHECK-NEXT: li a0, 127
3451 ; CHECK-NEXT: vsub.vx v8, v8, a0
3452 ; CHECK-NEXT: ret
3453 ;
3454 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
3455 ; CHECK-ZVBB: # %bb.0:
3456 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
3457 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3458 ; CHECK-ZVBB-NEXT: ret
3459 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
3460 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
3461 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3462 ret <vscale x 8 x i16> %v
3463 }
3466 define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
3467 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16:
3468 ; CHECK: # %bb.0:
3469 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
3470 ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
3471 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
3472 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
3473 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
3474 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
3475 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
3476 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
3477 ; CHECK-NEXT: li a0, 127
3478 ; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
3479 ; CHECK-NEXT: ret
3480 ;
3481 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16:
3482 ; CHECK-ZVBB: # %bb.0:
3483 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
3484 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3485 ; CHECK-ZVBB-NEXT: ret
3486 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3487 ret <vscale x 16 x i16> %v
3488 }
3490 define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
3491 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
3492 ; CHECK: # %bb.0:
3493 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
3494 ; CHECK-NEXT: vrsub.vi v12, v8, 0
3495 ; CHECK-NEXT: vand.vv v8, v8, v12
3496 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
3497 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
3498 ; CHECK-NEXT: li a0, 127
3499 ; CHECK-NEXT: vsub.vx v8, v8, a0
3500 ; CHECK-NEXT: ret
3501 ;
3502 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
3503 ; CHECK-ZVBB: # %bb.0:
3504 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
3505 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3506 ; CHECK-ZVBB-NEXT: ret
3507 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
3508 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
3509 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3510 ret <vscale x 16 x i16> %v
3511 }
3514 define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
3515 ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16:
3516 ; CHECK: # %bb.0:
3517 ; CHECK-NEXT: li a1, 1
3518 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3519 ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
3520 ; CHECK-NEXT: vnot.v v8, v8, v0.t
3521 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
3522 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
3523 ; CHECK-NEXT: lui a0, 5
3524 ; CHECK-NEXT: addi a0, a0, 1365
3525 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
3526 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
3527 ; CHECK-NEXT: lui a0, 3
3528 ; CHECK-NEXT: addi a0, a0, 819
3529 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
3530 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
3531 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
3532 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
3533 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3534 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
3535 ; CHECK-NEXT: lui a0, 1
3536 ; CHECK-NEXT: addi a0, a0, -241
3537 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
3538 ; CHECK-NEXT: li a0, 257
3539 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
3540 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
3541 ; CHECK-NEXT: ret
3542 ;
3543 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16:
3544 ; CHECK-ZVBB: # %bb.0:
3545 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3546 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3547 ; CHECK-ZVBB-NEXT: ret
3548 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
3549 ret <vscale x 32 x i16> %v
3550 }
3552 define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
3553 ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
3554 ; CHECK: # %bb.0:
3555 ; CHECK-NEXT: li a1, 1
3556 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3557 ; CHECK-NEXT: vsub.vx v16, v8, a1
3558 ; CHECK-NEXT: vnot.v v8, v8
3559 ; CHECK-NEXT: vand.vv v8, v8, v16
3560 ; CHECK-NEXT: vsrl.vi v16, v8, 1
3561 ; CHECK-NEXT: lui a0, 5
3562 ; CHECK-NEXT: addi a0, a0, 1365
3563 ; CHECK-NEXT: vand.vx v16, v16, a0
3564 ; CHECK-NEXT: vsub.vv v8, v8, v16
3565 ; CHECK-NEXT: lui a0, 3
3566 ; CHECK-NEXT: addi a0, a0, 819
3567 ; CHECK-NEXT: vand.vx v16, v8, a0
3568 ; CHECK-NEXT: vsrl.vi v8, v8, 2
3569 ; CHECK-NEXT: vand.vx v8, v8, a0
3570 ; CHECK-NEXT: vadd.vv v8, v16, v8
3571 ; CHECK-NEXT: vsrl.vi v16, v8, 4
3572 ; CHECK-NEXT: vadd.vv v8, v8, v16
3573 ; CHECK-NEXT: lui a0, 1
3574 ; CHECK-NEXT: addi a0, a0, -241
3575 ; CHECK-NEXT: vand.vx v8, v8, a0
3576 ; CHECK-NEXT: li a0, 257
3577 ; CHECK-NEXT: vmul.vx v8, v8, a0
3578 ; CHECK-NEXT: vsrl.vi v8, v8, 8
3579 ; CHECK-NEXT: ret
3580 ;
3581 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
3582 ; CHECK-ZVBB: # %bb.0:
3583 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3584 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3585 ; CHECK-ZVBB-NEXT: ret
3586 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
3587 %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
3588 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
3589 ret <vscale x 32 x i16> %v
3590 }
3593 define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
3594 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32:
3595 ; CHECK: # %bb.0:
3596 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
3597 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3598 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3599 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
3600 ; CHECK-NEXT: li a0, 52
3601 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
3602 ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
3603 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3604 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
3605 ; CHECK-NEXT: li a0, 1023
3606 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
3607 ; CHECK-NEXT: ret
3608 ;
3609 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32:
3610 ; CHECK-ZVBB: # %bb.0:
3611 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
3612 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3613 ; CHECK-ZVBB-NEXT: ret
3614 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3615 ret <vscale x 1 x i32> %v
3616 }
3618 define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
3619 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
3620 ; CHECK: # %bb.0:
3621 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
3622 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3623 ; CHECK-NEXT: vand.vv v8, v8, v9
3624 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
3625 ; CHECK-NEXT: li a0, 52
3626 ; CHECK-NEXT: vnsrl.wx v8, v9, a0
3627 ; CHECK-NEXT: li a0, 1023
3628 ; CHECK-NEXT: vsub.vx v8, v8, a0
3629 ; CHECK-NEXT: ret
3630 ;
3631 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
3632 ; CHECK-ZVBB: # %bb.0:
3633 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
3634 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3635 ; CHECK-ZVBB-NEXT: ret
3636 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
3637 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
3638 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3639 ret <vscale x 1 x i32> %v
3640 }
3643 define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
3644 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32:
3645 ; CHECK: # %bb.0:
3646 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
3647 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3648 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3649 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
3650 ; CHECK-NEXT: li a0, 52
3651 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3652 ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
3653 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3654 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
3655 ; CHECK-NEXT: li a0, 1023
3656 ; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
3657 ; CHECK-NEXT: ret
3658 ;
3659 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32:
3660 ; CHECK-ZVBB: # %bb.0:
3661 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
3662 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3663 ; CHECK-ZVBB-NEXT: ret
3664 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3665 ret <vscale x 2 x i32> %v
3666 }
3668 define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
3669 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
3670 ; CHECK: # %bb.0:
3671 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
3672 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3673 ; CHECK-NEXT: vand.vv v8, v8, v9
3674 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
3675 ; CHECK-NEXT: li a0, 52
3676 ; CHECK-NEXT: vnsrl.wx v8, v10, a0
3677 ; CHECK-NEXT: li a0, 1023
3678 ; CHECK-NEXT: vsub.vx v8, v8, a0
3679 ; CHECK-NEXT: ret
3680 ;
3681 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
3682 ; CHECK-ZVBB: # %bb.0:
3683 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
3684 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3685 ; CHECK-ZVBB-NEXT: ret
3686 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
3687 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
3688 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3689 ret <vscale x 2 x i32> %v
3690 }
3693 define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
3694 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32:
3695 ; CHECK: # %bb.0:
3696 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3697 ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
3698 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
3699 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
3700 ; CHECK-NEXT: li a0, 52
3701 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
3702 ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
3703 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3704 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
3705 ; CHECK-NEXT: li a0, 1023
3706 ; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
3707 ; CHECK-NEXT: ret
3708 ;
3709 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32:
3710 ; CHECK-ZVBB: # %bb.0:
3711 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3712 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3713 ; CHECK-ZVBB-NEXT: ret
3714 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3715 ret <vscale x 4 x i32> %v
3716 }
3718 define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
3719 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
3720 ; CHECK: # %bb.0:
3721 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3722 ; CHECK-NEXT: vrsub.vi v10, v8, 0
3723 ; CHECK-NEXT: vand.vv v8, v8, v10
3724 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
3725 ; CHECK-NEXT: li a0, 52
3726 ; CHECK-NEXT: vnsrl.wx v8, v12, a0
3727 ; CHECK-NEXT: li a0, 1023
3728 ; CHECK-NEXT: vsub.vx v8, v8, a0
3729 ; CHECK-NEXT: ret
3730 ;
3731 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
3732 ; CHECK-ZVBB: # %bb.0:
3733 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3734 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3735 ; CHECK-ZVBB-NEXT: ret
3736 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
3737 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
3738 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3739 ret <vscale x 4 x i32> %v
3740 }
3743 define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
3744 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32:
3745 ; CHECK: # %bb.0:
3746 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
3747 ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
3748 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
3749 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
3750 ; CHECK-NEXT: li a0, 52
3751 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3752 ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
3753 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3754 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
3755 ; CHECK-NEXT: li a0, 1023
3756 ; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
3757 ; CHECK-NEXT: ret
3758 ;
3759 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32:
3760 ; CHECK-ZVBB: # %bb.0:
3761 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
3762 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3763 ; CHECK-ZVBB-NEXT: ret
3764 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3765 ret <vscale x 8 x i32> %v
3766 }
3768 define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
3769 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
3770 ; CHECK: # %bb.0:
3771 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
3772 ; CHECK-NEXT: vrsub.vi v12, v8, 0
3773 ; CHECK-NEXT: vand.vv v8, v8, v12
3774 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
3775 ; CHECK-NEXT: li a0, 52
3776 ; CHECK-NEXT: vnsrl.wx v8, v16, a0
3777 ; CHECK-NEXT: li a0, 1023
3778 ; CHECK-NEXT: vsub.vx v8, v8, a0
3779 ; CHECK-NEXT: ret
3780 ;
3781 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
3782 ; CHECK-ZVBB: # %bb.0:
3783 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
3784 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3785 ; CHECK-ZVBB-NEXT: ret
3786 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
3787 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
3788 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
3789 ret <vscale x 8 x i32> %v
3790 }
3793 define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
3794 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32:
3795 ; CHECK: # %bb.0:
3796 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
3797 ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
3798 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
3799 ; CHECK-NEXT: fsrmi a0, 1
3800 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
3801 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
3802 ; CHECK-NEXT: li a1, 127
3803 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
3804 ; CHECK-NEXT: fsrm a0
3805 ; CHECK-NEXT: ret
3806 ;
3807 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32:
3808 ; CHECK-ZVBB: # %bb.0:
3809 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
3810 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3811 ; CHECK-ZVBB-NEXT: ret
3812 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3813 ret <vscale x 16 x i32> %v
3814 }
3816 define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
3817 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
3818 ; CHECK: # %bb.0:
3819 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
3820 ; CHECK-NEXT: vrsub.vi v16, v8, 0
3821 ; CHECK-NEXT: vand.vv v8, v8, v16
3822 ; CHECK-NEXT: fsrmi a0, 1
3823 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
3824 ; CHECK-NEXT: vsrl.vi v8, v8, 23
3825 ; CHECK-NEXT: li a1, 127
3826 ; CHECK-NEXT: vsub.vx v8, v8, a1
3827 ; CHECK-NEXT: fsrm a0
3828 ; CHECK-NEXT: ret
3829 ;
3830 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
3831 ; CHECK-ZVBB: # %bb.0:
3832 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
3833 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3834 ; CHECK-ZVBB-NEXT: ret
3835 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
3836 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
3837 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
3838 ret <vscale x 16 x i32> %v
3839 }
3842 define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
3843 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64:
3844 ; CHECK: # %bb.0:
3845 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
3846 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
3847 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
3848 ; CHECK-NEXT: fsrmi a0, 1
3849 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
3850 ; CHECK-NEXT: li a1, 52
3851 ; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t
3852 ; CHECK-NEXT: li a1, 1023
3853 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
3854 ; CHECK-NEXT: fsrm a0
3855 ; CHECK-NEXT: ret
3856 ;
3857 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64:
3858 ; CHECK-ZVBB: # %bb.0:
3859 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
3860 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3861 ; CHECK-ZVBB-NEXT: ret
3862 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3863 ret <vscale x 1 x i64> %v
3864 }
3866 define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
3867 ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
3868 ; CHECK: # %bb.0:
3869 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
3870 ; CHECK-NEXT: vrsub.vi v9, v8, 0
3871 ; CHECK-NEXT: vand.vv v8, v8, v9
3872 ; CHECK-NEXT: fsrmi a0, 1
3873 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
3874 ; CHECK-NEXT: li a1, 52
3875 ; CHECK-NEXT: vsrl.vx v8, v8, a1
3876 ; CHECK-NEXT: li a1, 1023
3877 ; CHECK-NEXT: vsub.vx v8, v8, a1
3878 ; CHECK-NEXT: fsrm a0
3879 ; CHECK-NEXT: ret
3880 ;
3881 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
3882 ; CHECK-ZVBB: # %bb.0:
3883 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
3884 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3885 ; CHECK-ZVBB-NEXT: ret
3886 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
3887 %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
3888 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
3889 ret <vscale x 1 x i64> %v
3890 }
3893 define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
3894 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64:
3895 ; CHECK: # %bb.0:
3896 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3897 ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
3898 ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
3899 ; CHECK-NEXT: fsrmi a0, 1
3900 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
3901 ; CHECK-NEXT: li a1, 52
3902 ; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t
3903 ; CHECK-NEXT: li a1, 1023
3904 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
3905 ; CHECK-NEXT: fsrm a0
3906 ; CHECK-NEXT: ret
3907 ;
3908 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64:
3909 ; CHECK-ZVBB: # %bb.0:
3910 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3911 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3912 ; CHECK-ZVBB-NEXT: ret
3913 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3914 ret <vscale x 2 x i64> %v
3915 }
3917 define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
3918 ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
3919 ; CHECK: # %bb.0:
3920 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3921 ; CHECK-NEXT: vrsub.vi v10, v8, 0
3922 ; CHECK-NEXT: vand.vv v8, v8, v10
3923 ; CHECK-NEXT: fsrmi a0, 1
3924 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
3925 ; CHECK-NEXT: li a1, 52
3926 ; CHECK-NEXT: vsrl.vx v8, v8, a1
3927 ; CHECK-NEXT: li a1, 1023
3928 ; CHECK-NEXT: vsub.vx v8, v8, a1
3929 ; CHECK-NEXT: fsrm a0
3930 ; CHECK-NEXT: ret
3931 ;
3932 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
3933 ; CHECK-ZVBB: # %bb.0:
3934 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3935 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3936 ; CHECK-ZVBB-NEXT: ret
3937 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
3938 %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
3939 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
3940 ret <vscale x 2 x i64> %v
3941 }
3944 define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
3945 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64:
3946 ; CHECK: # %bb.0:
3947 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
3948 ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
3949 ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
3950 ; CHECK-NEXT: fsrmi a0, 1
3951 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
3952 ; CHECK-NEXT: li a1, 52
3953 ; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t
3954 ; CHECK-NEXT: li a1, 1023
3955 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
3956 ; CHECK-NEXT: fsrm a0
3957 ; CHECK-NEXT: ret
3958 ;
3959 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64:
3960 ; CHECK-ZVBB: # %bb.0:
3961 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
3962 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
3963 ; CHECK-ZVBB-NEXT: ret
3964 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3965 ret <vscale x 4 x i64> %v
3966 }
3968 define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
3969 ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
3970 ; CHECK: # %bb.0:
3971 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
3972 ; CHECK-NEXT: vrsub.vi v12, v8, 0
3973 ; CHECK-NEXT: vand.vv v8, v8, v12
3974 ; CHECK-NEXT: fsrmi a0, 1
3975 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
3976 ; CHECK-NEXT: li a1, 52
3977 ; CHECK-NEXT: vsrl.vx v8, v8, a1
3978 ; CHECK-NEXT: li a1, 1023
3979 ; CHECK-NEXT: vsub.vx v8, v8, a1
3980 ; CHECK-NEXT: fsrm a0
3981 ; CHECK-NEXT: ret
3982 ;
3983 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
3984 ; CHECK-ZVBB: # %bb.0:
3985 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
3986 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3987 ; CHECK-ZVBB-NEXT: ret
3988 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
3989 %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
3990 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
3991 ret <vscale x 4 x i64> %v
3992 }
3995 define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
3996 ; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64:
3997 ; CHECK: # %bb.0:
3998 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
3999 ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
4000 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
4001 ; CHECK-NEXT: fsrmi a0, 1
4002 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
4003 ; CHECK-NEXT: li a1, 52
4004 ; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t
4005 ; CHECK-NEXT: li a1, 1023
4006 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
4007 ; CHECK-NEXT: fsrm a0
4008 ; CHECK-NEXT: ret
4009 ;
4010 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64:
4011 ; CHECK-ZVBB: # %bb.0:
4012 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4013 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
4014 ; CHECK-ZVBB-NEXT: ret
4015 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
4016 ret <vscale x 7 x i64> %v
4017 }
4019 define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
4020 ; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
4021 ; CHECK: # %bb.0:
4022 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4023 ; CHECK-NEXT: vrsub.vi v16, v8, 0
4024 ; CHECK-NEXT: vand.vv v8, v8, v16
4025 ; CHECK-NEXT: fsrmi a0, 1
4026 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
4027 ; CHECK-NEXT: li a1, 52
4028 ; CHECK-NEXT: vsrl.vx v8, v8, a1
4029 ; CHECK-NEXT: li a1, 1023
4030 ; CHECK-NEXT: vsub.vx v8, v8, a1
4031 ; CHECK-NEXT: fsrm a0
4032 ; CHECK-NEXT: ret
4033 ;
4034 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
4035 ; CHECK-ZVBB: # %bb.0:
4036 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4037 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
4038 ; CHECK-ZVBB-NEXT: ret
4039 %head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
4040 %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
4041 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
4042 ret <vscale x 7 x i64> %v
4043 }
4046 define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
4047 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64:
4048 ; CHECK: # %bb.0:
4049 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4050 ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
4051 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
4052 ; CHECK-NEXT: fsrmi a0, 1
4053 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
4054 ; CHECK-NEXT: li a1, 52
4055 ; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t
4056 ; CHECK-NEXT: li a1, 1023
4057 ; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
4058 ; CHECK-NEXT: fsrm a0
4059 ; CHECK-NEXT: ret
4060 ;
4061 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64:
4062 ; CHECK-ZVBB: # %bb.0:
4063 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4064 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
4065 ; CHECK-ZVBB-NEXT: ret
4066 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
4067 ret <vscale x 8 x i64> %v
4068 }
4070 define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
4071 ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
4072 ; CHECK: # %bb.0:
4073 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4074 ; CHECK-NEXT: vrsub.vi v16, v8, 0
4075 ; CHECK-NEXT: vand.vv v8, v8, v16
4076 ; CHECK-NEXT: fsrmi a0, 1
4077 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
4078 ; CHECK-NEXT: li a1, 52
4079 ; CHECK-NEXT: vsrl.vx v8, v8, a1
4080 ; CHECK-NEXT: li a1, 1023
4081 ; CHECK-NEXT: vsub.vx v8, v8, a1
4082 ; CHECK-NEXT: fsrm a0
4083 ; CHECK-NEXT: ret
4084 ;
4085 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
4086 ; CHECK-ZVBB: # %bb.0:
4087 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4088 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
4089 ; CHECK-ZVBB-NEXT: ret
4090 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
4091 %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
4092 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
4093 ret <vscale x 8 x i64> %v
4094 }
4096 define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
4097 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
4098 ; CHECK: # %bb.0:
4099 ; CHECK-NEXT: addi sp, sp, -16
4100 ; CHECK-NEXT: .cfi_def_cfa_offset 16
4101 ; CHECK-NEXT: csrr a1, vlenb
4102 ; CHECK-NEXT: slli a1, a1, 4
4103 ; CHECK-NEXT: sub sp, sp, a1
4104 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
4105 ; CHECK-NEXT: vmv1r.v v24, v0
4106 ; CHECK-NEXT: csrr a1, vlenb
4107 ; CHECK-NEXT: slli a1, a1, 3
4108 ; CHECK-NEXT: add a1, sp, a1
4109 ; CHECK-NEXT: addi a1, a1, 16
4110 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
4111 ; CHECK-NEXT: csrr a1, vlenb
4112 ; CHECK-NEXT: srli a2, a1, 3
4113 ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
4114 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
4115 ; CHECK-NEXT: sub a2, a0, a1
4116 ; CHECK-NEXT: sltu a3, a0, a2
4117 ; CHECK-NEXT: addi a3, a3, -1
4118 ; CHECK-NEXT: and a2, a3, a2
4119 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
4120 ; CHECK-NEXT: vrsub.vi v8, v16, 0, v0.t
4121 ; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
4122 ; CHECK-NEXT: fsrmi a2, 1
4123 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
4124 ; CHECK-NEXT: fsrm a2
4125 ; CHECK-NEXT: li a2, 52
4126 ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t
4127 ; CHECK-NEXT: li a3, 1023
4128 ; CHECK-NEXT: vsub.vx v8, v8, a3, v0.t
4129 ; CHECK-NEXT: addi a4, sp, 16
4130 ; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
4131 ; CHECK-NEXT: bltu a0, a1, .LBB94_2
4132 ; CHECK-NEXT: # %bb.1:
4133 ; CHECK-NEXT: mv a0, a1
4134 ; CHECK-NEXT: .LBB94_2:
4135 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4136 ; CHECK-NEXT: vmv1r.v v0, v24
4137 ; CHECK-NEXT: csrr a0, vlenb
4138 ; CHECK-NEXT: slli a0, a0, 3
4139 ; CHECK-NEXT: add a0, sp, a0
4140 ; CHECK-NEXT: addi a0, a0, 16
4141 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
4142 ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
4143 ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
4144 ; CHECK-NEXT: fsrmi a0, 1
4145 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
4146 ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t
4147 ; CHECK-NEXT: vsub.vx v8, v8, a3, v0.t
4148 ; CHECK-NEXT: fsrm a0
4149 ; CHECK-NEXT: addi a0, sp, 16
4150 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
4151 ; CHECK-NEXT: csrr a0, vlenb
4152 ; CHECK-NEXT: slli a0, a0, 4
4153 ; CHECK-NEXT: add sp, sp, a0
4154 ; CHECK-NEXT: addi sp, sp, 16
4155 ; CHECK-NEXT: ret
4156 ;
4157 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
4158 ; CHECK-ZVBB: # %bb.0:
4159 ; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
4160 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
4161 ; CHECK-ZVBB-NEXT: srli a2, a1, 3
4162 ; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
4163 ; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
4164 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
4165 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
4166 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
4167 ; CHECK-ZVBB-NEXT: and a2, a3, a2
4168 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
4169 ; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
4170 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
4171 ; CHECK-ZVBB-NEXT: # %bb.1:
4172 ; CHECK-ZVBB-NEXT: mv a0, a1
4173 ; CHECK-ZVBB-NEXT: .LBB94_2:
4174 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4175 ; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
4176 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
4177 ; CHECK-ZVBB-NEXT: ret
4178 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
4179 ret <vscale x 16 x i64> %v
4180 }
4182 define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
4183 ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
4184 ; CHECK: # %bb.0:
4185 ; CHECK-NEXT: csrr a1, vlenb
4186 ; CHECK-NEXT: sub a2, a0, a1
4187 ; CHECK-NEXT: sltu a3, a0, a2
4188 ; CHECK-NEXT: addi a3, a3, -1
4189 ; CHECK-NEXT: and a2, a3, a2
4190 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
4191 ; CHECK-NEXT: vrsub.vi v24, v16, 0
4192 ; CHECK-NEXT: vand.vv v16, v16, v24
4193 ; CHECK-NEXT: fsrmi a2, 1
4194 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16
4195 ; CHECK-NEXT: fsrm a2
4196 ; CHECK-NEXT: li a2, 52
4197 ; CHECK-NEXT: vsrl.vx v16, v16, a2
4198 ; CHECK-NEXT: li a3, 1023
4199 ; CHECK-NEXT: vsub.vx v16, v16, a3
4200 ; CHECK-NEXT: bltu a0, a1, .LBB95_2
4201 ; CHECK-NEXT: # %bb.1:
4202 ; CHECK-NEXT: mv a0, a1
4203 ; CHECK-NEXT: .LBB95_2:
4204 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4205 ; CHECK-NEXT: vrsub.vi v24, v8, 0
4206 ; CHECK-NEXT: vand.vv v8, v8, v24
4207 ; CHECK-NEXT: fsrmi a0, 1
4208 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
4209 ; CHECK-NEXT: vsrl.vx v8, v8, a2
4210 ; CHECK-NEXT: vsub.vx v8, v8, a3
4211 ; CHECK-NEXT: fsrm a0
4212 ; CHECK-NEXT: ret
4213 ;
4214 ; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
4215 ; CHECK-ZVBB: # %bb.0:
4216 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
4217 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
4218 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
4219 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
4220 ; CHECK-ZVBB-NEXT: and a2, a3, a2
4221 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
4222 ; CHECK-ZVBB-NEXT: vctz.v v16, v16
4223 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB95_2
4224 ; CHECK-ZVBB-NEXT: # %bb.1:
4225 ; CHECK-ZVBB-NEXT: mv a0, a1
4226 ; CHECK-ZVBB-NEXT: .LBB95_2:
4227 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
4228 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
4229 ; CHECK-ZVBB-NEXT: ret
4230 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
4231 %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
4232 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
4233 ret <vscale x 16 x i64> %v
4234 }
4236 ; Test promotion.
4237 declare <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9>, i1 immarg, <vscale x 1 x i1>, i32)
4238 define <vscale x 1 x i9> @vp_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
4239 ; CHECK-LABEL: vp_cttz_nxv1i9:
4240 ; CHECK: # %bb.0:
4241 ; CHECK-NEXT: li a1, 512
4242 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
4243 ; CHECK-NEXT: vor.vx v8, v8, a1, v0.t
4244 ; CHECK-NEXT: li a0, 1
4245 ; CHECK-NEXT: vsub.vx v9, v8, a0, v0.t
4246 ; CHECK-NEXT: vnot.v v8, v8, v0.t
4247 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
4248 ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
4249 ; CHECK-NEXT: lui a0, 5
4250 ; CHECK-NEXT: addi a0, a0, 1365
4251 ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
4252 ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
4253 ; CHECK-NEXT: lui a0, 3
4254 ; CHECK-NEXT: addi a0, a0, 819
4255 ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
4256 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
4257 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
4258 ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
4259 ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
4260 ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
4261 ; CHECK-NEXT: lui a0, 1
4262 ; CHECK-NEXT: addi a0, a0, -241
4263 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
4264 ; CHECK-NEXT: li a0, 257
4265 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
4266 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
4267 ; CHECK-NEXT: ret
4268 ;
4269 ; CHECK-ZVBB-LABEL: vp_cttz_nxv1i9:
4270 ; CHECK-ZVBB: # %bb.0:
4271 ; CHECK-ZVBB-NEXT: li a1, 512
4272 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
4273 ; CHECK-ZVBB-NEXT: vor.vx v8, v8, a1, v0.t
4274 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
4275 ; CHECK-ZVBB-NEXT: ret
4276 %v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
4277 ret <vscale x 1 x i9> %v
4278 }
4279 define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
4280 ; CHECK-LABEL: vp_zero_undef_cttz_nxv1i9:
4281 ; CHECK: # %bb.0:
4282 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
4283 ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
4284 ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
4285 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
4286 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
4287 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
4288 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
4289 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
4290 ; CHECK-NEXT: li a0, 127
4291 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
4292 ; CHECK-NEXT: ret
4293 ;
4294 ; CHECK-ZVBB-LABEL: vp_zero_undef_cttz_nxv1i9:
4295 ; CHECK-ZVBB: # %bb.0:
4296 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
4297 ; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t
4298 ; CHECK-ZVBB-NEXT: ret
4299 %v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
4300 ret <vscale x 1 x i9> %v
4301 }