| blob | 5a74108c90da7197a5a567684175c126df361332 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
3 ; RUN: < %s | FileCheck %s
5 define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, <vscale x 16 x i32> %v0, i32 signext %x2, i32 signext %x3, i32 signext %x4, i32 signext %x5, i32 signext %x6, i32 %x7, i32 %x8, i32 %x9) #0 {
6 ; CHECK-LABEL: lots_args:
7 ; CHECK: # %bb.0: # %entry
8 ; CHECK-NEXT: addi sp, sp, -64
9 ; CHECK-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
10 ; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
11 ; CHECK-NEXT: addi s0, sp, 64
12 ; CHECK-NEXT: csrr t0, vlenb
13 ; CHECK-NEXT: slli t0, t0, 3
14 ; CHECK-NEXT: sub sp, sp, t0
15 ; CHECK-NEXT: ld t0, 8(s0)
16 ; CHECK-NEXT: ld t1, 0(s0)
17 ; CHECK-NEXT: sw a0, -28(s0)
18 ; CHECK-NEXT: sw a1, -32(s0)
19 ; CHECK-NEXT: csrr a0, vlenb
20 ; CHECK-NEXT: slli a0, a0, 3
21 ; CHECK-NEXT: sub a0, s0, a0
22 ; CHECK-NEXT: addi a0, a0, -64
23 ; CHECK-NEXT: vs8r.v v8, (a0)
24 ; CHECK-NEXT: sw a2, -36(s0)
25 ; CHECK-NEXT: sw a3, -40(s0)
26 ; CHECK-NEXT: sw a4, -44(s0)
27 ; CHECK-NEXT: sw a5, -48(s0)
28 ; CHECK-NEXT: sw a6, -52(s0)
29 ; CHECK-NEXT: sw a7, -56(s0)
30 ; CHECK-NEXT: sw t1, -60(s0)
31 ; CHECK-NEXT: sw t0, -64(s0)
32 ; CHECK-NEXT: addi sp, s0, -64
33 ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
34 ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
35 ; CHECK-NEXT: addi sp, sp, 64
36 ; CHECK-NEXT: ret
37 entry:
38 %x0.addr = alloca i32, align 4
39 %x1.addr = alloca i32, align 4
40 %v0.addr = alloca <vscale x 16 x i32>, align 4
41 %x2.addr = alloca i32, align 4
42 %x3.addr = alloca i32, align 4
43 %x4.addr = alloca i32, align 4
44 %x5.addr = alloca i32, align 4
45 %x6.addr = alloca i32, align 4
46 %x7.addr = alloca i32, align 4
47 %x8.addr = alloca i32, align 4
48 %x9.addr = alloca i32, align 4
49 store i32 %x0, ptr %x0.addr, align 4
50 store i32 %x1, ptr %x1.addr, align 4
51 store <vscale x 16 x i32> %v0, <vscale x 16 x i32>* %v0.addr, align 4
52 store i32 %x2, ptr %x2.addr, align 4
53 store i32 %x3, ptr %x3.addr, align 4
54 store i32 %x4, ptr %x4.addr, align 4
55 store i32 %x5, ptr %x5.addr, align 4
56 store i32 %x6, ptr %x6.addr, align 4
57 store i32 %x7, ptr %x7.addr, align 4
58 store i32 %x8, ptr %x8.addr, align 4
59 store i32 %x9, ptr %x9.addr, align 4
60 ret void
61 }
63 define dso_local signext i32 @main() #0 {
64 ; CHECK-LABEL: main:
65 ; CHECK: # %bb.0: # %entry
66 ; CHECK-NEXT: addi sp, sp, -112
67 ; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
68 ; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
69 ; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
70 ; CHECK-NEXT: addi s0, sp, 112
71 ; CHECK-NEXT: csrr a0, vlenb
72 ; CHECK-NEXT: slli a0, a0, 3
73 ; CHECK-NEXT: sub sp, sp, a0
74 ; CHECK-NEXT: sw zero, -36(s0)
75 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
76 ; CHECK-NEXT: vmv.v.i v8, 0
77 ; CHECK-NEXT: addi a0, s0, -64
78 ; CHECK-NEXT: vse64.v v8, (a0)
79 ; CHECK-NEXT: vsetivli a1, 4, e32, m8, ta, ma
80 ; CHECK-NEXT: sd a1, -72(s0)
81 ; CHECK-NEXT: ld a1, -72(s0)
82 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
83 ; CHECK-NEXT: vle32.v v8, (a0)
84 ; CHECK-NEXT: csrr s1, vlenb
85 ; CHECK-NEXT: slli s1, s1, 3
86 ; CHECK-NEXT: sub s1, s0, s1
87 ; CHECK-NEXT: addi s1, s1, -112
88 ; CHECK-NEXT: vs8r.v v8, (s1)
89 ; CHECK-NEXT: li a0, 1
90 ; CHECK-NEXT: sw a0, -76(s0)
91 ; CHECK-NEXT: sw a0, -80(s0)
92 ; CHECK-NEXT: sw a0, -84(s0)
93 ; CHECK-NEXT: sw a0, -88(s0)
94 ; CHECK-NEXT: sw a0, -92(s0)
95 ; CHECK-NEXT: sw a0, -96(s0)
96 ; CHECK-NEXT: sw a0, -100(s0)
97 ; CHECK-NEXT: sw a0, -104(s0)
98 ; CHECK-NEXT: sw a0, -108(s0)
99 ; CHECK-NEXT: sw a0, -112(s0)
100 ; CHECK-NEXT: lw a0, -76(s0)
101 ; CHECK-NEXT: lw a1, -80(s0)
102 ; CHECK-NEXT: vl8re32.v v8, (s1)
103 ; CHECK-NEXT: lw a2, -84(s0)
104 ; CHECK-NEXT: lw a3, -88(s0)
105 ; CHECK-NEXT: lw a4, -92(s0)
106 ; CHECK-NEXT: lw a5, -96(s0)
107 ; CHECK-NEXT: lw a6, -100(s0)
108 ; CHECK-NEXT: lw a7, -104(s0)
109 ; CHECK-NEXT: lw t0, -108(s0)
110 ; CHECK-NEXT: lw t1, -112(s0)
111 ; CHECK-NEXT: addi sp, sp, -16
112 ; CHECK-NEXT: sd t1, 8(sp)
113 ; CHECK-NEXT: sd t0, 0(sp)
114 ; CHECK-NEXT: call lots_args
115 ; CHECK-NEXT: addi sp, sp, 16
116 ; CHECK-NEXT: lw a0, -76(s0)
117 ; CHECK-NEXT: lw a1, -80(s0)
118 ; CHECK-NEXT: vl8re32.v v8, (s1)
119 ; CHECK-NEXT: lw a2, -84(s0)
120 ; CHECK-NEXT: lw a3, -88(s0)
121 ; CHECK-NEXT: lw a4, -92(s0)
122 ; CHECK-NEXT: lw a5, -96(s0)
123 ; CHECK-NEXT: lw a6, -100(s0)
124 ; CHECK-NEXT: lw a7, -104(s0)
125 ; CHECK-NEXT: lw t0, -108(s0)
126 ; CHECK-NEXT: lw t1, -112(s0)
127 ; CHECK-NEXT: addi sp, sp, -16
128 ; CHECK-NEXT: sd t1, 8(sp)
129 ; CHECK-NEXT: sd t0, 0(sp)
130 ; CHECK-NEXT: call lots_args
131 ; CHECK-NEXT: addi sp, sp, 16
132 ; CHECK-NEXT: li a0, 0
133 ; CHECK-NEXT: addi sp, s0, -112
134 ; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
135 ; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
136 ; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
137 ; CHECK-NEXT: addi sp, sp, 112
138 ; CHECK-NEXT: ret
139 entry:
140 %retval = alloca i32, align 4
141 %input = alloca [4 x i32], align 4
142 %vl = alloca i64, align 8
143 %v0 = alloca <vscale x 16 x i32>, align 4
144 %x0 = alloca i32, align 4
145 %x1 = alloca i32, align 4
146 %x2 = alloca i32, align 4
147 %x3 = alloca i32, align 4
148 %x4 = alloca i32, align 4
149 %x5 = alloca i32, align 4
150 %x6 = alloca i32, align 4
151 %x7 = alloca i32, align 4
152 %x8 = alloca i32, align 4
153 %x9 = alloca i32, align 4
154 store i32 0, ptr %retval, align 4
155 call void @llvm.memset.p0.i64(ptr align 4 %input, i8 0, i64 16, i1 false)
156 %0 = call i64 @llvm.riscv.vsetvli.i64(i64 4, i64 2, i64 3)
157 store i64 %0, ptr %vl, align 8
158 %1 = load i64, ptr %vl, align 8
159 %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* %input, i64 %1)
160 store <vscale x 16 x i32> %2, <vscale x 16 x i32>* %v0, align 4
161 store i32 1, ptr %x0, align 4
162 store i32 1, ptr %x1, align 4
163 store i32 1, ptr %x2, align 4
164 store i32 1, ptr %x3, align 4
165 store i32 1, ptr %x4, align 4
166 store i32 1, ptr %x5, align 4
167 store i32 1, ptr %x6, align 4
168 store i32 1, ptr %x7, align 4
169 store i32 1, ptr %x8, align 4
170 store i32 1, ptr %x9, align 4
171 %3 = load i32, ptr %x0, align 4
172 %4 = load i32, ptr %x1, align 4
173 %5 = load <vscale x 16 x i32>, <vscale x 16 x i32>* %v0, align 4
174 %6 = load i32, ptr %x2, align 4
175 %7 = load i32, ptr %x3, align 4
176 %8 = load i32, ptr %x4, align 4
177 %9 = load i32, ptr %x5, align 4
178 %10 = load i32, ptr %x6, align 4
179 %11 = load i32, ptr %x7, align 4
180 %12 = load i32, ptr %x8, align 4
181 %13 = load i32, ptr %x9, align 4
182 call void @lots_args(i32 signext %3, i32 signext %4, <vscale x 16 x i32> %5, i32 signext %6, i32 signext %7, i32 signext %8, i32 signext %9, i32 signext %10, i32 %11, i32 %12, i32 %13)
183 %14 = load i32, ptr %x0, align 4
184 %15 = load i32, ptr %x1, align 4
185 %16 = load <vscale x 16 x i32>, <vscale x 16 x i32>* %v0, align 4
186 %17 = load i32, ptr %x2, align 4
187 %18 = load i32, ptr %x3, align 4
188 %19 = load i32, ptr %x4, align 4
189 %20 = load i32, ptr %x5, align 4
190 %21 = load i32, ptr %x6, align 4
191 %22 = load i32, ptr %x7, align 4
192 %23 = load i32, ptr %x8, align 4
193 %24 = load i32, ptr %x9, align 4
194 call void @lots_args(i32 signext %14, i32 signext %15, <vscale x 16 x i32> %16, i32 signext %17, i32 signext %18, i32 signext %19, i32 signext %20, i32 signext %21, i32 %22, i32 %23, i32 %24)
195 ret i32 0
196 }
198 declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
200 declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
202 declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>* nocapture, i64)
204 attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }