| blob | 1128eb2c44b9a7ebdcc0532b8e3d01e1b17efc14 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh \
3 ; RUN: -verify-machineinstrs < %s | FileCheck %s
5 declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i16>, i64)
6 declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
8 define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {
9 ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
10 ; CHECK: # %bb.0: # %entry
11 ; CHECK-NEXT: vmv4r.v v16, v12
12 ; CHECK-NEXT: vmv4r.v v12, v8
13 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
14 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
15 ; CHECK-NEXT: ret
16 entry:
17 tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl)
18 ret void
19 }
21 define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
22 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
23 ; CHECK: # %bb.0: # %entry
24 ; CHECK-NEXT: vmv4r.v v16, v12
25 ; CHECK-NEXT: vmv4r.v v12, v8
26 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
27 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
28 ; CHECK-NEXT: ret
29 entry:
30 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
31 ret void
32 }
34 declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i8>, i64)
35 declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
37 define void @test_vsoxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {
38 ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i8:
39 ; CHECK: # %bb.0: # %entry
40 ; CHECK-NEXT: vmv2r.v v16, v12
41 ; CHECK-NEXT: vmv4r.v v12, v8
42 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
43 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
44 ; CHECK-NEXT: ret
45 entry:
46 tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl)
47 ret void
48 }
50 define void @test_vsoxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
51 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i8:
52 ; CHECK: # %bb.0: # %entry
53 ; CHECK-NEXT: vmv2r.v v16, v12
54 ; CHECK-NEXT: vmv4r.v v12, v8
55 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
56 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
57 ; CHECK-NEXT: ret
58 entry:
59 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
60 ret void
61 }
63 declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i32>, i64)
64 declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
66 define void @test_vsoxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {
67 ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i32:
68 ; CHECK: # %bb.0: # %entry
69 ; CHECK-NEXT: vmv4r.v v12, v8
70 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
71 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
72 ; CHECK-NEXT: ret
73 entry:
74 tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl)
75 ret void
76 }
78 define void @test_vsoxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
79 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i32:
80 ; CHECK: # %bb.0: # %entry
81 ; CHECK-NEXT: vmv4r.v v12, v8
82 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
83 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
84 ; CHECK-NEXT: ret
85 entry:
86 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
87 ret void
88 }
90 declare void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, i64)
91 declare void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
93 define void @test_vsoxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
94 ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i32:
95 ; CHECK: # %bb.0: # %entry
96 ; CHECK-NEXT: vmv2r.v v12, v10
97 ; CHECK-NEXT: vmv2r.v v10, v8
98 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
99 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
100 ; CHECK-NEXT: ret
101 entry:
102 tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
103 ret void
104 }
106 define void @test_vsoxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
107 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i32:
108 ; CHECK: # %bb.0: # %entry
109 ; CHECK-NEXT: vmv2r.v v12, v10
110 ; CHECK-NEXT: vmv2r.v v10, v8
111 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
112 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
113 ; CHECK-NEXT: ret
114 entry:
115 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
116 ret void
117 }
119 declare void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, i64)
120 declare void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
122 define void @test_vsoxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
123 ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i8:
124 ; CHECK: # %bb.0: # %entry
125 ; CHECK-NEXT: vmv1r.v v12, v10
126 ; CHECK-NEXT: vmv2r.v v10, v8
127 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
128 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
129 ; CHECK-NEXT: ret
130 entry:
131 tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
132 ret void
133 }
135 define void @test_vsoxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
136 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i8:
137 ; CHECK: # %bb.0: # %entry
138 ; CHECK-NEXT: vmv1r.v v12, v10
139 ; CHECK-NEXT: vmv2r.v v10, v8
140 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
141 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
142 ; CHECK-NEXT: ret
143 entry:
144 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
145 ret void
146 }
148 declare void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, i64)
149 declare void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
151 define void @test_vsoxseg2_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
152 ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i64:
153 ; CHECK: # %bb.0: # %entry
154 ; CHECK-NEXT: vmv2r.v v10, v8
155 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
156 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
157 ; CHECK-NEXT: ret
158 entry:
159 tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
160 ret void
161 }
163 define void @test_vsoxseg2_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
164 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i64:
165 ; CHECK: # %bb.0: # %entry
166 ; CHECK-NEXT: vmv2r.v v10, v8
167 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
168 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
169 ; CHECK-NEXT: ret
170 entry:
171 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
172 ret void
173 }
175 declare void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, i64)
176 declare void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
178 define void @test_vsoxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
179 ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i16:
180 ; CHECK: # %bb.0: # %entry
181 ; CHECK-NEXT: vmv1r.v v12, v10
182 ; CHECK-NEXT: vmv2r.v v10, v8
183 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
184 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
185 ; CHECK-NEXT: ret
186 entry:
187 tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
188 ret void
189 }
191 define void @test_vsoxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
192 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i16:
193 ; CHECK: # %bb.0: # %entry
194 ; CHECK-NEXT: vmv1r.v v12, v10
195 ; CHECK-NEXT: vmv2r.v v10, v8
196 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
197 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
198 ; CHECK-NEXT: ret
199 entry:
200 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
201 ret void
202 }
204 declare void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, i64)
205 declare void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
207 define void @test_vsoxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
208 ; CHECK-LABEL: test_vsoxseg3_nxv4i32_nxv4i32:
209 ; CHECK: # %bb.0: # %entry
210 ; CHECK-NEXT: vmv2r.v v12, v8
211 ; CHECK-NEXT: vmv2r.v v14, v8
212 ; CHECK-NEXT: vmv2r.v v16, v8
213 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
214 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10
215 ; CHECK-NEXT: ret
216 entry:
217 tail call void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
218 ret void
219 }
221 define void @test_vsoxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
222 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_nxv4i32:
223 ; CHECK: # %bb.0: # %entry
224 ; CHECK-NEXT: vmv2r.v v12, v8
225 ; CHECK-NEXT: vmv2r.v v14, v8
226 ; CHECK-NEXT: vmv2r.v v16, v8
227 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
228 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10, v0.t
229 ; CHECK-NEXT: ret
230 entry:
231 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
232 ret void
233 }
235 declare void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, i64)
236 declare void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
238 define void @test_vsoxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
239 ; CHECK-LABEL: test_vsoxseg3_nxv4i32_nxv4i8:
240 ; CHECK: # %bb.0: # %entry
241 ; CHECK-NEXT: vmv2r.v v12, v8
242 ; CHECK-NEXT: vmv2r.v v14, v8
243 ; CHECK-NEXT: vmv2r.v v16, v8
244 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
245 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
246 ; CHECK-NEXT: ret
247 entry:
248 tail call void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
249 ret void
250 }
252 define void @test_vsoxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
253 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_nxv4i8:
254 ; CHECK: # %bb.0: # %entry
255 ; CHECK-NEXT: vmv2r.v v12, v8
256 ; CHECK-NEXT: vmv2r.v v14, v8
257 ; CHECK-NEXT: vmv2r.v v16, v8
258 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
259 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
260 ; CHECK-NEXT: ret
261 entry:
262 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
263 ret void
264 }
266 declare void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, i64)
267 declare void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
269 define void @test_vsoxseg3_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
270 ; CHECK-LABEL: test_vsoxseg3_nxv4i32_nxv4i64:
271 ; CHECK: # %bb.0: # %entry
272 ; CHECK-NEXT: vmv2r.v v10, v8
273 ; CHECK-NEXT: vmv4r.v v16, v12
274 ; CHECK-NEXT: vmv2r.v v12, v8
275 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
276 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16
277 ; CHECK-NEXT: ret
278 entry:
279 tail call void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
280 ret void
281 }
283 define void @test_vsoxseg3_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
284 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_nxv4i64:
285 ; CHECK: # %bb.0: # %entry
286 ; CHECK-NEXT: vmv2r.v v10, v8
287 ; CHECK-NEXT: vmv4r.v v16, v12
288 ; CHECK-NEXT: vmv2r.v v12, v8
289 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
290 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16, v0.t
291 ; CHECK-NEXT: ret
292 entry:
293 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
294 ret void
295 }
297 declare void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, i64)
298 declare void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
300 define void @test_vsoxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
301 ; CHECK-LABEL: test_vsoxseg3_nxv4i32_nxv4i16:
302 ; CHECK: # %bb.0: # %entry
303 ; CHECK-NEXT: vmv2r.v v12, v8
304 ; CHECK-NEXT: vmv2r.v v14, v8
305 ; CHECK-NEXT: vmv2r.v v16, v8
306 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
307 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
308 ; CHECK-NEXT: ret
309 entry:
310 tail call void @llvm.riscv.vsoxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
311 ret void
312 }
314 define void @test_vsoxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
315 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_nxv4i16:
316 ; CHECK: # %bb.0: # %entry
317 ; CHECK-NEXT: vmv2r.v v12, v8
318 ; CHECK-NEXT: vmv2r.v v14, v8
319 ; CHECK-NEXT: vmv2r.v v16, v8
320 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
321 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
322 ; CHECK-NEXT: ret
323 entry:
324 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
325 ret void
326 }
328 declare void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, i64)
329 declare void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
331 define void @test_vsoxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
332 ; CHECK-LABEL: test_vsoxseg4_nxv4i32_nxv4i32:
333 ; CHECK: # %bb.0: # %entry
334 ; CHECK-NEXT: vmv2r.v v12, v8
335 ; CHECK-NEXT: vmv2r.v v14, v8
336 ; CHECK-NEXT: vmv2r.v v16, v8
337 ; CHECK-NEXT: vmv2r.v v18, v8
338 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
339 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
340 ; CHECK-NEXT: ret
341 entry:
342 tail call void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
343 ret void
344 }
346 define void @test_vsoxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
347 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_nxv4i32:
348 ; CHECK: # %bb.0: # %entry
349 ; CHECK-NEXT: vmv2r.v v12, v8
350 ; CHECK-NEXT: vmv2r.v v14, v8
351 ; CHECK-NEXT: vmv2r.v v16, v8
352 ; CHECK-NEXT: vmv2r.v v18, v8
353 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
354 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
355 ; CHECK-NEXT: ret
356 entry:
357 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
358 ret void
359 }
361 declare void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, i64)
362 declare void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
364 define void @test_vsoxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
365 ; CHECK-LABEL: test_vsoxseg4_nxv4i32_nxv4i8:
366 ; CHECK: # %bb.0: # %entry
367 ; CHECK-NEXT: vmv2r.v v12, v8
368 ; CHECK-NEXT: vmv2r.v v14, v8
369 ; CHECK-NEXT: vmv2r.v v16, v8
370 ; CHECK-NEXT: vmv2r.v v18, v8
371 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
372 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
373 ; CHECK-NEXT: ret
374 entry:
375 tail call void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
376 ret void
377 }
379 define void @test_vsoxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
380 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_nxv4i8:
381 ; CHECK: # %bb.0: # %entry
382 ; CHECK-NEXT: vmv2r.v v12, v8
383 ; CHECK-NEXT: vmv2r.v v14, v8
384 ; CHECK-NEXT: vmv2r.v v16, v8
385 ; CHECK-NEXT: vmv2r.v v18, v8
386 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
387 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
388 ; CHECK-NEXT: ret
389 entry:
390 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
391 ret void
392 }
394 declare void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, i64)
395 declare void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
397 define void @test_vsoxseg4_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
398 ; CHECK-LABEL: test_vsoxseg4_nxv4i32_nxv4i64:
399 ; CHECK: # %bb.0: # %entry
400 ; CHECK-NEXT: vmv2r.v v16, v8
401 ; CHECK-NEXT: vmv2r.v v18, v8
402 ; CHECK-NEXT: vmv2r.v v20, v8
403 ; CHECK-NEXT: vmv2r.v v22, v8
404 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
405 ; CHECK-NEXT: vsoxseg4ei64.v v16, (a0), v12
406 ; CHECK-NEXT: ret
407 entry:
408 tail call void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
409 ret void
410 }
412 define void @test_vsoxseg4_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
413 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_nxv4i64:
414 ; CHECK: # %bb.0: # %entry
415 ; CHECK-NEXT: vmv2r.v v16, v8
416 ; CHECK-NEXT: vmv2r.v v18, v8
417 ; CHECK-NEXT: vmv2r.v v20, v8
418 ; CHECK-NEXT: vmv2r.v v22, v8
419 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
420 ; CHECK-NEXT: vsoxseg4ei64.v v16, (a0), v12, v0.t
421 ; CHECK-NEXT: ret
422 entry:
423 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
424 ret void
425 }
427 declare void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, i64)
428 declare void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
430 define void @test_vsoxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
431 ; CHECK-LABEL: test_vsoxseg4_nxv4i32_nxv4i16:
432 ; CHECK: # %bb.0: # %entry
433 ; CHECK-NEXT: vmv2r.v v12, v8
434 ; CHECK-NEXT: vmv2r.v v14, v8
435 ; CHECK-NEXT: vmv2r.v v16, v8
436 ; CHECK-NEXT: vmv2r.v v18, v8
437 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
438 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
439 ; CHECK-NEXT: ret
440 entry:
441 tail call void @llvm.riscv.vsoxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
442 ret void
443 }
445 define void @test_vsoxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
446 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_nxv4i16:
447 ; CHECK: # %bb.0: # %entry
448 ; CHECK-NEXT: vmv2r.v v12, v8
449 ; CHECK-NEXT: vmv2r.v v14, v8
450 ; CHECK-NEXT: vmv2r.v v16, v8
451 ; CHECK-NEXT: vmv2r.v v18, v8
452 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
453 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
454 ; CHECK-NEXT: ret
455 entry:
456 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
457 ret void
458 }
460 declare void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, i64)
461 declare void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
463 define void @test_vsoxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {
464 ; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i16:
465 ; CHECK: # %bb.0: # %entry
466 ; CHECK-NEXT: vmv2r.v v10, v8
467 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
468 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
469 ; CHECK-NEXT: ret
470 entry:
471 tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl)
472 ret void
473 }
475 define void @test_vsoxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
476 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i16:
477 ; CHECK: # %bb.0: # %entry
478 ; CHECK-NEXT: vmv2r.v v10, v8
479 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
480 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
481 ; CHECK-NEXT: ret
482 entry:
483 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
484 ret void
485 }
487 declare void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, i64)
488 declare void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
490 define void @test_vsoxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {
491 ; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i8:
492 ; CHECK: # %bb.0: # %entry
493 ; CHECK-NEXT: vmv2r.v v12, v10
494 ; CHECK-NEXT: vmv2r.v v10, v8
495 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
496 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
497 ; CHECK-NEXT: ret
498 entry:
499 tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl)
500 ret void
501 }
503 define void @test_vsoxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
504 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i8:
505 ; CHECK: # %bb.0: # %entry
506 ; CHECK-NEXT: vmv2r.v v12, v10
507 ; CHECK-NEXT: vmv2r.v v10, v8
508 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
509 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
510 ; CHECK-NEXT: ret
511 entry:
512 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
513 ret void
514 }
516 declare void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, i64)
517 declare void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
519 define void @test_vsoxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {
520 ; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i32:
521 ; CHECK: # %bb.0: # %entry
522 ; CHECK-NEXT: vmv2r.v v10, v8
523 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
524 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
525 ; CHECK-NEXT: ret
526 entry:
527 tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl)
528 ret void
529 }
531 define void @test_vsoxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
532 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i32:
533 ; CHECK: # %bb.0: # %entry
534 ; CHECK-NEXT: vmv2r.v v10, v8
535 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
536 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
537 ; CHECK-NEXT: ret
538 entry:
539 tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
540 ret void
541 }
543 declare void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, i64)
544 declare void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
546 define void @test_vsoxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {
547 ; CHECK-LABEL: test_vsoxseg3_nxv16i8_nxv16i16:
548 ; CHECK: # %bb.0: # %entry
549 ; CHECK-NEXT: vmv2r.v v10, v8
550 ; CHECK-NEXT: vmv4r.v v16, v12
551 ; CHECK-NEXT: vmv2r.v v12, v8
552 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
553 ; CHECK-NEXT: vsoxseg3ei16.v v8, (a0), v16
554 ; CHECK-NEXT: ret
555 entry:
556 tail call void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl)
557 ret void
558 }
560 define void @test_vsoxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
561 ; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_nxv16i16:
562 ; CHECK: # %bb.0: # %entry
563 ; CHECK-NEXT: vmv2r.v v10, v8
564 ; CHECK-NEXT: vmv4r.v v16, v12
565 ; CHECK-NEXT: vmv2r.v v12, v8
566 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
567 ; CHECK-NEXT: vsoxseg3ei16.v v8, (a0), v16, v0.t
568 ; CHECK-NEXT: ret
569 entry:
570 tail call void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
571 ret void
572 }
574 declare void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, i64)
575 declare void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
577 define void @test_vsoxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {
578 ; CHECK-LABEL: test_vsoxseg3_nxv16i8_nxv16i8:
579 ; CHECK: # %bb.0: # %entry
580 ; CHECK-NEXT: vmv2r.v v12, v8
581 ; CHECK-NEXT: vmv2r.v v14, v8
582 ; CHECK-NEXT: vmv2r.v v16, v8
583 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
584 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
585 ; CHECK-NEXT: ret
586 entry:
587 tail call void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl)
588 ret void
589 }
591 define void @test_vsoxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
592 ; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_nxv16i8:
593 ; CHECK: # %bb.0: # %entry
594 ; CHECK-NEXT: vmv2r.v v12, v8
595 ; CHECK-NEXT: vmv2r.v v14, v8
596 ; CHECK-NEXT: vmv2r.v v16, v8
597 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
598 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
599 ; CHECK-NEXT: ret
600 entry:
601 tail call void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
602 ret void
603 }
605 declare void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, i64)
606 declare void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
608 define void @test_vsoxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {
609 ; CHECK-LABEL: test_vsoxseg3_nxv16i8_nxv16i32:
610 ; CHECK: # %bb.0: # %entry
611 ; CHECK-NEXT: vmv2r.v v10, v8
612 ; CHECK-NEXT: vmv2r.v v12, v8
613 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
614 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16
615 ; CHECK-NEXT: ret
616 entry:
617 tail call void @llvm.riscv.vsoxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl)
618 ret void
619 }
621 define void @test_vsoxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
622 ; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_nxv16i32:
623 ; CHECK: # %bb.0: # %entry
624 ; CHECK-NEXT: vmv2r.v v10, v8
625 ; CHECK-NEXT: vmv2r.v v12, v8
626 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
627 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16, v0.t
628 ; CHECK-NEXT: ret
629 entry:
630 tail call void @llvm.riscv.vsoxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
631 ret void
632 }
634 declare void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, i64)
635 declare void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
637 define void @test_vsoxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {
638 ; CHECK-LABEL: test_vsoxseg4_nxv16i8_nxv16i16:
639 ; CHECK: # %bb.0: # %entry
640 ; CHECK-NEXT: vmv2r.v v16, v8
641 ; CHECK-NEXT: vmv2r.v v18, v8
642 ; CHECK-NEXT: vmv2r.v v20, v8
643 ; CHECK-NEXT: vmv2r.v v22, v8
644 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
645 ; CHECK-NEXT: vsoxseg4ei16.v v16, (a0), v12
646 ; CHECK-NEXT: ret
647 entry:
648 tail call void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl)
649 ret void
650 }
652 define void @test_vsoxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
653 ; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_nxv16i16:
654 ; CHECK: # %bb.0: # %entry
655 ; CHECK-NEXT: vmv2r.v v16, v8
656 ; CHECK-NEXT: vmv2r.v v18, v8
657 ; CHECK-NEXT: vmv2r.v v20, v8
658 ; CHECK-NEXT: vmv2r.v v22, v8
659 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
660 ; CHECK-NEXT: vsoxseg4ei16.v v16, (a0), v12, v0.t
661 ; CHECK-NEXT: ret
662 entry:
663 tail call void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
664 ret void
665 }
667 declare void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, i64)
668 declare void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
670 define void @test_vsoxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {
671 ; CHECK-LABEL: test_vsoxseg4_nxv16i8_nxv16i8:
672 ; CHECK: # %bb.0: # %entry
673 ; CHECK-NEXT: vmv2r.v v12, v8
674 ; CHECK-NEXT: vmv2r.v v14, v8
675 ; CHECK-NEXT: vmv2r.v v16, v8
676 ; CHECK-NEXT: vmv2r.v v18, v8
677 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
678 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
679 ; CHECK-NEXT: ret
680 entry:
681 tail call void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl)
682 ret void
683 }
685 define void @test_vsoxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
686 ; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_nxv16i8:
687 ; CHECK: # %bb.0: # %entry
688 ; CHECK-NEXT: vmv2r.v v12, v8
689 ; CHECK-NEXT: vmv2r.v v14, v8
690 ; CHECK-NEXT: vmv2r.v v16, v8
691 ; CHECK-NEXT: vmv2r.v v18, v8
692 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
693 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
694 ; CHECK-NEXT: ret
695 entry:
696 tail call void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
697 ret void
698 }
700 declare void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, i64)
701 declare void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
703 define void @test_vsoxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {
704 ; CHECK-LABEL: test_vsoxseg4_nxv16i8_nxv16i32:
705 ; CHECK: # %bb.0: # %entry
706 ; CHECK-NEXT: vmv2r.v v10, v8
707 ; CHECK-NEXT: vmv2r.v v12, v8
708 ; CHECK-NEXT: vmv2r.v v14, v8
709 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
710 ; CHECK-NEXT: vsoxseg4ei32.v v8, (a0), v16
711 ; CHECK-NEXT: ret
712 entry:
713 tail call void @llvm.riscv.vsoxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl)
714 ret void
715 }
717 define void @test_vsoxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
718 ; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_nxv16i32:
719 ; CHECK: # %bb.0: # %entry
720 ; CHECK-NEXT: vmv2r.v v10, v8
721 ; CHECK-NEXT: vmv2r.v v12, v8
722 ; CHECK-NEXT: vmv2r.v v14, v8
723 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
724 ; CHECK-NEXT: vsoxseg4ei32.v v8, (a0), v16, v0.t
725 ; CHECK-NEXT: ret
726 entry:
727 tail call void @llvm.riscv.vsoxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
728 ret void
729 }
731 declare void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
732 declare void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
734 define void @test_vsoxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
735 ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i64:
736 ; CHECK: # %bb.0: # %entry
737 ; CHECK-NEXT: vmv1r.v v10, v9
738 ; CHECK-NEXT: vmv1r.v v9, v8
739 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
740 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
741 ; CHECK-NEXT: ret
742 entry:
743 tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
744 ret void
745 }
747 define void @test_vsoxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
748 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i64:
749 ; CHECK: # %bb.0: # %entry
750 ; CHECK-NEXT: vmv1r.v v10, v9
751 ; CHECK-NEXT: vmv1r.v v9, v8
752 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
753 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
754 ; CHECK-NEXT: ret
755 entry:
756 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
757 ret void
758 }
760 declare void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
761 declare void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
763 define void @test_vsoxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
764 ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i32:
765 ; CHECK: # %bb.0: # %entry
766 ; CHECK-NEXT: vmv1r.v v10, v9
767 ; CHECK-NEXT: vmv1r.v v9, v8
768 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
769 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
770 ; CHECK-NEXT: ret
771 entry:
772 tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
773 ret void
774 }
776 define void @test_vsoxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
777 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i32:
778 ; CHECK: # %bb.0: # %entry
779 ; CHECK-NEXT: vmv1r.v v10, v9
780 ; CHECK-NEXT: vmv1r.v v9, v8
781 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
782 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
783 ; CHECK-NEXT: ret
784 entry:
785 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
786 ret void
787 }
789 declare void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
790 declare void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
792 define void @test_vsoxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
793 ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i16:
794 ; CHECK: # %bb.0: # %entry
795 ; CHECK-NEXT: vmv1r.v v10, v9
796 ; CHECK-NEXT: vmv1r.v v9, v8
797 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
798 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
799 ; CHECK-NEXT: ret
800 entry:
801 tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
802 ret void
803 }
805 define void @test_vsoxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
806 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i16:
807 ; CHECK: # %bb.0: # %entry
808 ; CHECK-NEXT: vmv1r.v v10, v9
809 ; CHECK-NEXT: vmv1r.v v9, v8
810 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
811 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
812 ; CHECK-NEXT: ret
813 entry:
814 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
815 ret void
816 }
818 declare void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
819 declare void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
821 define void @test_vsoxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
822 ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i8:
823 ; CHECK: # %bb.0: # %entry
824 ; CHECK-NEXT: vmv1r.v v10, v9
825 ; CHECK-NEXT: vmv1r.v v9, v8
826 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
827 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
828 ; CHECK-NEXT: ret
829 entry:
830 tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
831 ret void
832 }
834 define void @test_vsoxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
835 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i8:
836 ; CHECK: # %bb.0: # %entry
837 ; CHECK-NEXT: vmv1r.v v10, v9
838 ; CHECK-NEXT: vmv1r.v v9, v8
839 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
840 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
841 ; CHECK-NEXT: ret
842 entry:
843 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
844 ret void
845 }
847 declare void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
848 declare void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
850 define void @test_vsoxseg3_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
851 ; CHECK-LABEL: test_vsoxseg3_nxv1i64_nxv1i64:
852 ; CHECK: # %bb.0: # %entry
853 ; CHECK-NEXT: vmv1r.v v10, v8
854 ; CHECK-NEXT: vmv1r.v v11, v8
855 ; CHECK-NEXT: vmv1r.v v12, v8
856 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
857 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
858 ; CHECK-NEXT: ret
859 entry:
860 tail call void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
861 ret void
862 }
864 define void @test_vsoxseg3_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
865 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_nxv1i64:
866 ; CHECK: # %bb.0: # %entry
867 ; CHECK-NEXT: vmv1r.v v10, v8
868 ; CHECK-NEXT: vmv1r.v v11, v8
869 ; CHECK-NEXT: vmv1r.v v12, v8
870 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
871 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
872 ; CHECK-NEXT: ret
873 entry:
874 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
875 ret void
876 }
878 declare void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
879 declare void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
881 define void @test_vsoxseg3_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
882 ; CHECK-LABEL: test_vsoxseg3_nxv1i64_nxv1i32:
883 ; CHECK: # %bb.0: # %entry
884 ; CHECK-NEXT: vmv1r.v v10, v8
885 ; CHECK-NEXT: vmv1r.v v11, v8
886 ; CHECK-NEXT: vmv1r.v v12, v8
887 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
888 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
889 ; CHECK-NEXT: ret
890 entry:
891 tail call void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
892 ret void
893 }
895 define void @test_vsoxseg3_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
896 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_nxv1i32:
897 ; CHECK: # %bb.0: # %entry
898 ; CHECK-NEXT: vmv1r.v v10, v8
899 ; CHECK-NEXT: vmv1r.v v11, v8
900 ; CHECK-NEXT: vmv1r.v v12, v8
901 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
902 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
903 ; CHECK-NEXT: ret
904 entry:
905 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
906 ret void
907 }
909 declare void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
910 declare void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
912 define void @test_vsoxseg3_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
913 ; CHECK-LABEL: test_vsoxseg3_nxv1i64_nxv1i16:
914 ; CHECK: # %bb.0: # %entry
915 ; CHECK-NEXT: vmv1r.v v10, v8
916 ; CHECK-NEXT: vmv1r.v v11, v8
917 ; CHECK-NEXT: vmv1r.v v12, v8
918 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
919 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
920 ; CHECK-NEXT: ret
921 entry:
922 tail call void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
923 ret void
924 }
926 define void @test_vsoxseg3_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
927 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_nxv1i16:
928 ; CHECK: # %bb.0: # %entry
929 ; CHECK-NEXT: vmv1r.v v10, v8
930 ; CHECK-NEXT: vmv1r.v v11, v8
931 ; CHECK-NEXT: vmv1r.v v12, v8
932 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
933 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
934 ; CHECK-NEXT: ret
935 entry:
936 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
937 ret void
938 }
940 declare void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
941 declare void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
943 define void @test_vsoxseg3_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
944 ; CHECK-LABEL: test_vsoxseg3_nxv1i64_nxv1i8:
945 ; CHECK: # %bb.0: # %entry
946 ; CHECK-NEXT: vmv1r.v v10, v8
947 ; CHECK-NEXT: vmv1r.v v11, v8
948 ; CHECK-NEXT: vmv1r.v v12, v8
949 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
950 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
951 ; CHECK-NEXT: ret
952 entry:
953 tail call void @llvm.riscv.vsoxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
954 ret void
955 }
957 define void @test_vsoxseg3_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
958 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_nxv1i8:
959 ; CHECK: # %bb.0: # %entry
960 ; CHECK-NEXT: vmv1r.v v10, v8
961 ; CHECK-NEXT: vmv1r.v v11, v8
962 ; CHECK-NEXT: vmv1r.v v12, v8
963 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
964 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
965 ; CHECK-NEXT: ret
966 entry:
967 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
968 ret void
969 }
971 declare void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
972 declare void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
974 define void @test_vsoxseg4_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
975 ; CHECK-LABEL: test_vsoxseg4_nxv1i64_nxv1i64:
976 ; CHECK: # %bb.0: # %entry
977 ; CHECK-NEXT: vmv1r.v v10, v8
978 ; CHECK-NEXT: vmv1r.v v11, v8
979 ; CHECK-NEXT: vmv1r.v v12, v8
980 ; CHECK-NEXT: vmv1r.v v13, v8
981 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
982 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
983 ; CHECK-NEXT: ret
984 entry:
985 tail call void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
986 ret void
987 }
989 define void @test_vsoxseg4_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
990 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_nxv1i64:
991 ; CHECK: # %bb.0: # %entry
992 ; CHECK-NEXT: vmv1r.v v10, v8
993 ; CHECK-NEXT: vmv1r.v v11, v8
994 ; CHECK-NEXT: vmv1r.v v12, v8
995 ; CHECK-NEXT: vmv1r.v v13, v8
996 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
997 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
998 ; CHECK-NEXT: ret
999 entry:
1000 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1001 ret void
1002 }
1004 declare void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
1005 declare void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1007 define void @test_vsoxseg4_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1008 ; CHECK-LABEL: test_vsoxseg4_nxv1i64_nxv1i32:
1009 ; CHECK: # %bb.0: # %entry
1010 ; CHECK-NEXT: vmv1r.v v10, v8
1011 ; CHECK-NEXT: vmv1r.v v11, v8
1012 ; CHECK-NEXT: vmv1r.v v12, v8
1013 ; CHECK-NEXT: vmv1r.v v13, v8
1014 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1015 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
1016 ; CHECK-NEXT: ret
1017 entry:
1018 tail call void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1019 ret void
1020 }
1022 define void @test_vsoxseg4_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1023 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_nxv1i32:
1024 ; CHECK: # %bb.0: # %entry
1025 ; CHECK-NEXT: vmv1r.v v10, v8
1026 ; CHECK-NEXT: vmv1r.v v11, v8
1027 ; CHECK-NEXT: vmv1r.v v12, v8
1028 ; CHECK-NEXT: vmv1r.v v13, v8
1029 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1030 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
1031 ; CHECK-NEXT: ret
1032 entry:
1033 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1034 ret void
1035 }
1037 declare void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
1038 declare void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1040 define void @test_vsoxseg4_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1041 ; CHECK-LABEL: test_vsoxseg4_nxv1i64_nxv1i16:
1042 ; CHECK: # %bb.0: # %entry
1043 ; CHECK-NEXT: vmv1r.v v10, v8
1044 ; CHECK-NEXT: vmv1r.v v11, v8
1045 ; CHECK-NEXT: vmv1r.v v12, v8
1046 ; CHECK-NEXT: vmv1r.v v13, v8
1047 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1048 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
1049 ; CHECK-NEXT: ret
1050 entry:
1051 tail call void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1052 ret void
1053 }
1055 define void @test_vsoxseg4_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1056 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_nxv1i16:
1057 ; CHECK: # %bb.0: # %entry
1058 ; CHECK-NEXT: vmv1r.v v10, v8
1059 ; CHECK-NEXT: vmv1r.v v11, v8
1060 ; CHECK-NEXT: vmv1r.v v12, v8
1061 ; CHECK-NEXT: vmv1r.v v13, v8
1062 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1063 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
1064 ; CHECK-NEXT: ret
1065 entry:
1066 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1067 ret void
1068 }
1070 declare void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
1071 declare void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1073 define void @test_vsoxseg4_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1074 ; CHECK-LABEL: test_vsoxseg4_nxv1i64_nxv1i8:
1075 ; CHECK: # %bb.0: # %entry
1076 ; CHECK-NEXT: vmv1r.v v10, v8
1077 ; CHECK-NEXT: vmv1r.v v11, v8
1078 ; CHECK-NEXT: vmv1r.v v12, v8
1079 ; CHECK-NEXT: vmv1r.v v13, v8
1080 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1081 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
1082 ; CHECK-NEXT: ret
1083 entry:
1084 tail call void @llvm.riscv.vsoxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1085 ret void
1086 }
1088 define void @test_vsoxseg4_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1089 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_nxv1i8:
1090 ; CHECK: # %bb.0: # %entry
1091 ; CHECK-NEXT: vmv1r.v v10, v8
1092 ; CHECK-NEXT: vmv1r.v v11, v8
1093 ; CHECK-NEXT: vmv1r.v v12, v8
1094 ; CHECK-NEXT: vmv1r.v v13, v8
1095 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1096 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
1097 ; CHECK-NEXT: ret
1098 entry:
1099 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1100 ret void
1101 }
1103 declare void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
1104 declare void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1106 define void @test_vsoxseg5_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1107 ; CHECK-LABEL: test_vsoxseg5_nxv1i64_nxv1i64:
1108 ; CHECK: # %bb.0: # %entry
1109 ; CHECK-NEXT: vmv1r.v v10, v8
1110 ; CHECK-NEXT: vmv1r.v v11, v8
1111 ; CHECK-NEXT: vmv1r.v v12, v8
1112 ; CHECK-NEXT: vmv1r.v v13, v8
1113 ; CHECK-NEXT: vmv1r.v v14, v8
1114 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1115 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
1116 ; CHECK-NEXT: ret
1117 entry:
1118 tail call void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1119 ret void
1120 }
1122 define void @test_vsoxseg5_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1123 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_nxv1i64:
1124 ; CHECK: # %bb.0: # %entry
1125 ; CHECK-NEXT: vmv1r.v v10, v8
1126 ; CHECK-NEXT: vmv1r.v v11, v8
1127 ; CHECK-NEXT: vmv1r.v v12, v8
1128 ; CHECK-NEXT: vmv1r.v v13, v8
1129 ; CHECK-NEXT: vmv1r.v v14, v8
1130 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1131 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
1132 ; CHECK-NEXT: ret
1133 entry:
1134 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1135 ret void
1136 }
1138 declare void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
1139 declare void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1141 define void @test_vsoxseg5_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1142 ; CHECK-LABEL: test_vsoxseg5_nxv1i64_nxv1i32:
1143 ; CHECK: # %bb.0: # %entry
1144 ; CHECK-NEXT: vmv1r.v v10, v8
1145 ; CHECK-NEXT: vmv1r.v v11, v8
1146 ; CHECK-NEXT: vmv1r.v v12, v8
1147 ; CHECK-NEXT: vmv1r.v v13, v8
1148 ; CHECK-NEXT: vmv1r.v v14, v8
1149 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1150 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
1151 ; CHECK-NEXT: ret
1152 entry:
1153 tail call void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1154 ret void
1155 }
1157 define void @test_vsoxseg5_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1158 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_nxv1i32:
1159 ; CHECK: # %bb.0: # %entry
1160 ; CHECK-NEXT: vmv1r.v v10, v8
1161 ; CHECK-NEXT: vmv1r.v v11, v8
1162 ; CHECK-NEXT: vmv1r.v v12, v8
1163 ; CHECK-NEXT: vmv1r.v v13, v8
1164 ; CHECK-NEXT: vmv1r.v v14, v8
1165 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1166 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
1167 ; CHECK-NEXT: ret
1168 entry:
1169 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1170 ret void
1171 }
1173 declare void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
1174 declare void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1176 define void @test_vsoxseg5_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1177 ; CHECK-LABEL: test_vsoxseg5_nxv1i64_nxv1i16:
1178 ; CHECK: # %bb.0: # %entry
1179 ; CHECK-NEXT: vmv1r.v v10, v8
1180 ; CHECK-NEXT: vmv1r.v v11, v8
1181 ; CHECK-NEXT: vmv1r.v v12, v8
1182 ; CHECK-NEXT: vmv1r.v v13, v8
1183 ; CHECK-NEXT: vmv1r.v v14, v8
1184 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1185 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
1186 ; CHECK-NEXT: ret
1187 entry:
1188 tail call void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1189 ret void
1190 }
1192 define void @test_vsoxseg5_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1193 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_nxv1i16:
1194 ; CHECK: # %bb.0: # %entry
1195 ; CHECK-NEXT: vmv1r.v v10, v8
1196 ; CHECK-NEXT: vmv1r.v v11, v8
1197 ; CHECK-NEXT: vmv1r.v v12, v8
1198 ; CHECK-NEXT: vmv1r.v v13, v8
1199 ; CHECK-NEXT: vmv1r.v v14, v8
1200 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1201 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
1202 ; CHECK-NEXT: ret
1203 entry:
1204 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1205 ret void
1206 }
1208 declare void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
1209 declare void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1211 define void @test_vsoxseg5_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1212 ; CHECK-LABEL: test_vsoxseg5_nxv1i64_nxv1i8:
1213 ; CHECK: # %bb.0: # %entry
1214 ; CHECK-NEXT: vmv1r.v v10, v8
1215 ; CHECK-NEXT: vmv1r.v v11, v8
1216 ; CHECK-NEXT: vmv1r.v v12, v8
1217 ; CHECK-NEXT: vmv1r.v v13, v8
1218 ; CHECK-NEXT: vmv1r.v v14, v8
1219 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1220 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
1221 ; CHECK-NEXT: ret
1222 entry:
1223 tail call void @llvm.riscv.vsoxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1224 ret void
1225 }
1227 define void @test_vsoxseg5_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1228 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_nxv1i8:
1229 ; CHECK: # %bb.0: # %entry
1230 ; CHECK-NEXT: vmv1r.v v10, v8
1231 ; CHECK-NEXT: vmv1r.v v11, v8
1232 ; CHECK-NEXT: vmv1r.v v12, v8
1233 ; CHECK-NEXT: vmv1r.v v13, v8
1234 ; CHECK-NEXT: vmv1r.v v14, v8
1235 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1236 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
1237 ; CHECK-NEXT: ret
1238 entry:
1239 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1240 ret void
1241 }
1243 declare void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
1244 declare void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1246 define void @test_vsoxseg6_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1247 ; CHECK-LABEL: test_vsoxseg6_nxv1i64_nxv1i64:
1248 ; CHECK: # %bb.0: # %entry
1249 ; CHECK-NEXT: vmv1r.v v10, v8
1250 ; CHECK-NEXT: vmv1r.v v11, v8
1251 ; CHECK-NEXT: vmv1r.v v12, v8
1252 ; CHECK-NEXT: vmv1r.v v13, v8
1253 ; CHECK-NEXT: vmv1r.v v14, v8
1254 ; CHECK-NEXT: vmv1r.v v15, v8
1255 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1256 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
1257 ; CHECK-NEXT: ret
1258 entry:
1259 tail call void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1260 ret void
1261 }
1263 define void @test_vsoxseg6_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1264 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_nxv1i64:
1265 ; CHECK: # %bb.0: # %entry
1266 ; CHECK-NEXT: vmv1r.v v10, v8
1267 ; CHECK-NEXT: vmv1r.v v11, v8
1268 ; CHECK-NEXT: vmv1r.v v12, v8
1269 ; CHECK-NEXT: vmv1r.v v13, v8
1270 ; CHECK-NEXT: vmv1r.v v14, v8
1271 ; CHECK-NEXT: vmv1r.v v15, v8
1272 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1273 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
1274 ; CHECK-NEXT: ret
1275 entry:
1276 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1277 ret void
1278 }
1280 declare void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
1281 declare void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1283 define void @test_vsoxseg6_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1284 ; CHECK-LABEL: test_vsoxseg6_nxv1i64_nxv1i32:
1285 ; CHECK: # %bb.0: # %entry
1286 ; CHECK-NEXT: vmv1r.v v10, v8
1287 ; CHECK-NEXT: vmv1r.v v11, v8
1288 ; CHECK-NEXT: vmv1r.v v12, v8
1289 ; CHECK-NEXT: vmv1r.v v13, v8
1290 ; CHECK-NEXT: vmv1r.v v14, v8
1291 ; CHECK-NEXT: vmv1r.v v15, v8
1292 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1293 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
1294 ; CHECK-NEXT: ret
1295 entry:
1296 tail call void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1297 ret void
1298 }
1300 define void @test_vsoxseg6_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1301 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_nxv1i32:
1302 ; CHECK: # %bb.0: # %entry
1303 ; CHECK-NEXT: vmv1r.v v10, v8
1304 ; CHECK-NEXT: vmv1r.v v11, v8
1305 ; CHECK-NEXT: vmv1r.v v12, v8
1306 ; CHECK-NEXT: vmv1r.v v13, v8
1307 ; CHECK-NEXT: vmv1r.v v14, v8
1308 ; CHECK-NEXT: vmv1r.v v15, v8
1309 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1310 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
1311 ; CHECK-NEXT: ret
1312 entry:
1313 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1314 ret void
1315 }
1317 declare void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
1318 declare void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1320 define void @test_vsoxseg6_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1321 ; CHECK-LABEL: test_vsoxseg6_nxv1i64_nxv1i16:
1322 ; CHECK: # %bb.0: # %entry
1323 ; CHECK-NEXT: vmv1r.v v10, v8
1324 ; CHECK-NEXT: vmv1r.v v11, v8
1325 ; CHECK-NEXT: vmv1r.v v12, v8
1326 ; CHECK-NEXT: vmv1r.v v13, v8
1327 ; CHECK-NEXT: vmv1r.v v14, v8
1328 ; CHECK-NEXT: vmv1r.v v15, v8
1329 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1330 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
1331 ; CHECK-NEXT: ret
1332 entry:
1333 tail call void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1334 ret void
1335 }
1337 define void @test_vsoxseg6_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1338 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_nxv1i16:
1339 ; CHECK: # %bb.0: # %entry
1340 ; CHECK-NEXT: vmv1r.v v10, v8
1341 ; CHECK-NEXT: vmv1r.v v11, v8
1342 ; CHECK-NEXT: vmv1r.v v12, v8
1343 ; CHECK-NEXT: vmv1r.v v13, v8
1344 ; CHECK-NEXT: vmv1r.v v14, v8
1345 ; CHECK-NEXT: vmv1r.v v15, v8
1346 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1347 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
1348 ; CHECK-NEXT: ret
1349 entry:
1350 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1351 ret void
1352 }
1354 declare void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
1355 declare void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1357 define void @test_vsoxseg6_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1358 ; CHECK-LABEL: test_vsoxseg6_nxv1i64_nxv1i8:
1359 ; CHECK: # %bb.0: # %entry
1360 ; CHECK-NEXT: vmv1r.v v10, v8
1361 ; CHECK-NEXT: vmv1r.v v11, v8
1362 ; CHECK-NEXT: vmv1r.v v12, v8
1363 ; CHECK-NEXT: vmv1r.v v13, v8
1364 ; CHECK-NEXT: vmv1r.v v14, v8
1365 ; CHECK-NEXT: vmv1r.v v15, v8
1366 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1367 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
1368 ; CHECK-NEXT: ret
1369 entry:
1370 tail call void @llvm.riscv.vsoxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1371 ret void
1372 }
1374 define void @test_vsoxseg6_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1375 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_nxv1i8:
1376 ; CHECK: # %bb.0: # %entry
1377 ; CHECK-NEXT: vmv1r.v v10, v8
1378 ; CHECK-NEXT: vmv1r.v v11, v8
1379 ; CHECK-NEXT: vmv1r.v v12, v8
1380 ; CHECK-NEXT: vmv1r.v v13, v8
1381 ; CHECK-NEXT: vmv1r.v v14, v8
1382 ; CHECK-NEXT: vmv1r.v v15, v8
1383 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1384 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
1385 ; CHECK-NEXT: ret
1386 entry:
1387 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1388 ret void
1389 }
1391 declare void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
1392 declare void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1394 define void @test_vsoxseg7_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1395 ; CHECK-LABEL: test_vsoxseg7_nxv1i64_nxv1i64:
1396 ; CHECK: # %bb.0: # %entry
1397 ; CHECK-NEXT: vmv1r.v v10, v8
1398 ; CHECK-NEXT: vmv1r.v v11, v8
1399 ; CHECK-NEXT: vmv1r.v v12, v8
1400 ; CHECK-NEXT: vmv1r.v v13, v8
1401 ; CHECK-NEXT: vmv1r.v v14, v8
1402 ; CHECK-NEXT: vmv1r.v v15, v8
1403 ; CHECK-NEXT: vmv1r.v v16, v8
1404 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1405 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
1406 ; CHECK-NEXT: ret
1407 entry:
1408 tail call void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1409 ret void
1410 }
1412 define void @test_vsoxseg7_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1413 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_nxv1i64:
1414 ; CHECK: # %bb.0: # %entry
1415 ; CHECK-NEXT: vmv1r.v v10, v8
1416 ; CHECK-NEXT: vmv1r.v v11, v8
1417 ; CHECK-NEXT: vmv1r.v v12, v8
1418 ; CHECK-NEXT: vmv1r.v v13, v8
1419 ; CHECK-NEXT: vmv1r.v v14, v8
1420 ; CHECK-NEXT: vmv1r.v v15, v8
1421 ; CHECK-NEXT: vmv1r.v v16, v8
1422 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1423 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
1424 ; CHECK-NEXT: ret
1425 entry:
1426 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1427 ret void
1428 }
1430 declare void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
1431 declare void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1433 define void @test_vsoxseg7_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1434 ; CHECK-LABEL: test_vsoxseg7_nxv1i64_nxv1i32:
1435 ; CHECK: # %bb.0: # %entry
1436 ; CHECK-NEXT: vmv1r.v v10, v8
1437 ; CHECK-NEXT: vmv1r.v v11, v8
1438 ; CHECK-NEXT: vmv1r.v v12, v8
1439 ; CHECK-NEXT: vmv1r.v v13, v8
1440 ; CHECK-NEXT: vmv1r.v v14, v8
1441 ; CHECK-NEXT: vmv1r.v v15, v8
1442 ; CHECK-NEXT: vmv1r.v v16, v8
1443 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1444 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
1445 ; CHECK-NEXT: ret
1446 entry:
1447 tail call void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1448 ret void
1449 }
1451 define void @test_vsoxseg7_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1452 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_nxv1i32:
1453 ; CHECK: # %bb.0: # %entry
1454 ; CHECK-NEXT: vmv1r.v v10, v8
1455 ; CHECK-NEXT: vmv1r.v v11, v8
1456 ; CHECK-NEXT: vmv1r.v v12, v8
1457 ; CHECK-NEXT: vmv1r.v v13, v8
1458 ; CHECK-NEXT: vmv1r.v v14, v8
1459 ; CHECK-NEXT: vmv1r.v v15, v8
1460 ; CHECK-NEXT: vmv1r.v v16, v8
1461 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1462 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
1463 ; CHECK-NEXT: ret
1464 entry:
1465 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1466 ret void
1467 }
1469 declare void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
1470 declare void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1472 define void @test_vsoxseg7_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1473 ; CHECK-LABEL: test_vsoxseg7_nxv1i64_nxv1i16:
1474 ; CHECK: # %bb.0: # %entry
1475 ; CHECK-NEXT: vmv1r.v v10, v8
1476 ; CHECK-NEXT: vmv1r.v v11, v8
1477 ; CHECK-NEXT: vmv1r.v v12, v8
1478 ; CHECK-NEXT: vmv1r.v v13, v8
1479 ; CHECK-NEXT: vmv1r.v v14, v8
1480 ; CHECK-NEXT: vmv1r.v v15, v8
1481 ; CHECK-NEXT: vmv1r.v v16, v8
1482 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1483 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
1484 ; CHECK-NEXT: ret
1485 entry:
1486 tail call void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1487 ret void
1488 }
1490 define void @test_vsoxseg7_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1491 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_nxv1i16:
1492 ; CHECK: # %bb.0: # %entry
1493 ; CHECK-NEXT: vmv1r.v v10, v8
1494 ; CHECK-NEXT: vmv1r.v v11, v8
1495 ; CHECK-NEXT: vmv1r.v v12, v8
1496 ; CHECK-NEXT: vmv1r.v v13, v8
1497 ; CHECK-NEXT: vmv1r.v v14, v8
1498 ; CHECK-NEXT: vmv1r.v v15, v8
1499 ; CHECK-NEXT: vmv1r.v v16, v8
1500 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1501 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
1502 ; CHECK-NEXT: ret
1503 entry:
1504 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1505 ret void
1506 }
1508 declare void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
1509 declare void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1511 define void @test_vsoxseg7_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1512 ; CHECK-LABEL: test_vsoxseg7_nxv1i64_nxv1i8:
1513 ; CHECK: # %bb.0: # %entry
1514 ; CHECK-NEXT: vmv1r.v v10, v8
1515 ; CHECK-NEXT: vmv1r.v v11, v8
1516 ; CHECK-NEXT: vmv1r.v v12, v8
1517 ; CHECK-NEXT: vmv1r.v v13, v8
1518 ; CHECK-NEXT: vmv1r.v v14, v8
1519 ; CHECK-NEXT: vmv1r.v v15, v8
1520 ; CHECK-NEXT: vmv1r.v v16, v8
1521 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1522 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
1523 ; CHECK-NEXT: ret
1524 entry:
1525 tail call void @llvm.riscv.vsoxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1526 ret void
1527 }
1529 define void @test_vsoxseg7_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1530 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_nxv1i8:
1531 ; CHECK: # %bb.0: # %entry
1532 ; CHECK-NEXT: vmv1r.v v10, v8
1533 ; CHECK-NEXT: vmv1r.v v11, v8
1534 ; CHECK-NEXT: vmv1r.v v12, v8
1535 ; CHECK-NEXT: vmv1r.v v13, v8
1536 ; CHECK-NEXT: vmv1r.v v14, v8
1537 ; CHECK-NEXT: vmv1r.v v15, v8
1538 ; CHECK-NEXT: vmv1r.v v16, v8
1539 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1540 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
1541 ; CHECK-NEXT: ret
1542 entry:
1543 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1544 ret void
1545 }
1547 declare void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, i64)
1548 declare void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1550 define void @test_vsoxseg8_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1551 ; CHECK-LABEL: test_vsoxseg8_nxv1i64_nxv1i64:
1552 ; CHECK: # %bb.0: # %entry
1553 ; CHECK-NEXT: vmv1r.v v10, v8
1554 ; CHECK-NEXT: vmv1r.v v11, v8
1555 ; CHECK-NEXT: vmv1r.v v12, v8
1556 ; CHECK-NEXT: vmv1r.v v13, v8
1557 ; CHECK-NEXT: vmv1r.v v14, v8
1558 ; CHECK-NEXT: vmv1r.v v15, v8
1559 ; CHECK-NEXT: vmv1r.v v16, v8
1560 ; CHECK-NEXT: vmv1r.v v17, v8
1561 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1562 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
1563 ; CHECK-NEXT: ret
1564 entry:
1565 tail call void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1566 ret void
1567 }
1569 define void @test_vsoxseg8_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1570 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_nxv1i64:
1571 ; CHECK: # %bb.0: # %entry
1572 ; CHECK-NEXT: vmv1r.v v10, v8
1573 ; CHECK-NEXT: vmv1r.v v11, v8
1574 ; CHECK-NEXT: vmv1r.v v12, v8
1575 ; CHECK-NEXT: vmv1r.v v13, v8
1576 ; CHECK-NEXT: vmv1r.v v14, v8
1577 ; CHECK-NEXT: vmv1r.v v15, v8
1578 ; CHECK-NEXT: vmv1r.v v16, v8
1579 ; CHECK-NEXT: vmv1r.v v17, v8
1580 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1581 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
1582 ; CHECK-NEXT: ret
1583 entry:
1584 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1585 ret void
1586 }
1588 declare void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, i64)
1589 declare void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1591 define void @test_vsoxseg8_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1592 ; CHECK-LABEL: test_vsoxseg8_nxv1i64_nxv1i32:
1593 ; CHECK: # %bb.0: # %entry
1594 ; CHECK-NEXT: vmv1r.v v10, v8
1595 ; CHECK-NEXT: vmv1r.v v11, v8
1596 ; CHECK-NEXT: vmv1r.v v12, v8
1597 ; CHECK-NEXT: vmv1r.v v13, v8
1598 ; CHECK-NEXT: vmv1r.v v14, v8
1599 ; CHECK-NEXT: vmv1r.v v15, v8
1600 ; CHECK-NEXT: vmv1r.v v16, v8
1601 ; CHECK-NEXT: vmv1r.v v17, v8
1602 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1603 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
1604 ; CHECK-NEXT: ret
1605 entry:
1606 tail call void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1607 ret void
1608 }
1610 define void @test_vsoxseg8_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1611 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_nxv1i32:
1612 ; CHECK: # %bb.0: # %entry
1613 ; CHECK-NEXT: vmv1r.v v10, v8
1614 ; CHECK-NEXT: vmv1r.v v11, v8
1615 ; CHECK-NEXT: vmv1r.v v12, v8
1616 ; CHECK-NEXT: vmv1r.v v13, v8
1617 ; CHECK-NEXT: vmv1r.v v14, v8
1618 ; CHECK-NEXT: vmv1r.v v15, v8
1619 ; CHECK-NEXT: vmv1r.v v16, v8
1620 ; CHECK-NEXT: vmv1r.v v17, v8
1621 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1622 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
1623 ; CHECK-NEXT: ret
1624 entry:
1625 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1626 ret void
1627 }
1629 declare void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, i64)
1630 declare void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1632 define void @test_vsoxseg8_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1633 ; CHECK-LABEL: test_vsoxseg8_nxv1i64_nxv1i16:
1634 ; CHECK: # %bb.0: # %entry
1635 ; CHECK-NEXT: vmv1r.v v10, v8
1636 ; CHECK-NEXT: vmv1r.v v11, v8
1637 ; CHECK-NEXT: vmv1r.v v12, v8
1638 ; CHECK-NEXT: vmv1r.v v13, v8
1639 ; CHECK-NEXT: vmv1r.v v14, v8
1640 ; CHECK-NEXT: vmv1r.v v15, v8
1641 ; CHECK-NEXT: vmv1r.v v16, v8
1642 ; CHECK-NEXT: vmv1r.v v17, v8
1643 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1644 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
1645 ; CHECK-NEXT: ret
1646 entry:
1647 tail call void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1648 ret void
1649 }
1651 define void @test_vsoxseg8_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1652 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_nxv1i16:
1653 ; CHECK: # %bb.0: # %entry
1654 ; CHECK-NEXT: vmv1r.v v10, v8
1655 ; CHECK-NEXT: vmv1r.v v11, v8
1656 ; CHECK-NEXT: vmv1r.v v12, v8
1657 ; CHECK-NEXT: vmv1r.v v13, v8
1658 ; CHECK-NEXT: vmv1r.v v14, v8
1659 ; CHECK-NEXT: vmv1r.v v15, v8
1660 ; CHECK-NEXT: vmv1r.v v16, v8
1661 ; CHECK-NEXT: vmv1r.v v17, v8
1662 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1663 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
1664 ; CHECK-NEXT: ret
1665 entry:
1666 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1667 ret void
1668 }
1670 declare void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, i64)
1671 declare void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1673 define void @test_vsoxseg8_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1674 ; CHECK-LABEL: test_vsoxseg8_nxv1i64_nxv1i8:
1675 ; CHECK: # %bb.0: # %entry
1676 ; CHECK-NEXT: vmv1r.v v10, v8
1677 ; CHECK-NEXT: vmv1r.v v11, v8
1678 ; CHECK-NEXT: vmv1r.v v12, v8
1679 ; CHECK-NEXT: vmv1r.v v13, v8
1680 ; CHECK-NEXT: vmv1r.v v14, v8
1681 ; CHECK-NEXT: vmv1r.v v15, v8
1682 ; CHECK-NEXT: vmv1r.v v16, v8
1683 ; CHECK-NEXT: vmv1r.v v17, v8
1684 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1685 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
1686 ; CHECK-NEXT: ret
1687 entry:
1688 tail call void @llvm.riscv.vsoxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1689 ret void
1690 }
1692 define void @test_vsoxseg8_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1693 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_nxv1i8:
1694 ; CHECK: # %bb.0: # %entry
1695 ; CHECK-NEXT: vmv1r.v v10, v8
1696 ; CHECK-NEXT: vmv1r.v v11, v8
1697 ; CHECK-NEXT: vmv1r.v v12, v8
1698 ; CHECK-NEXT: vmv1r.v v13, v8
1699 ; CHECK-NEXT: vmv1r.v v14, v8
1700 ; CHECK-NEXT: vmv1r.v v15, v8
1701 ; CHECK-NEXT: vmv1r.v v16, v8
1702 ; CHECK-NEXT: vmv1r.v v17, v8
1703 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1704 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
1705 ; CHECK-NEXT: ret
1706 entry:
1707 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1708 ret void
1709 }
1711 declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
1712 declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1714 define void @test_vsoxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1715 ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i64:
1716 ; CHECK: # %bb.0: # %entry
1717 ; CHECK-NEXT: vmv1r.v v10, v9
1718 ; CHECK-NEXT: vmv1r.v v9, v8
1719 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1720 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
1721 ; CHECK-NEXT: ret
1722 entry:
1723 tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1724 ret void
1725 }
1727 define void @test_vsoxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1728 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i64:
1729 ; CHECK: # %bb.0: # %entry
1730 ; CHECK-NEXT: vmv1r.v v10, v9
1731 ; CHECK-NEXT: vmv1r.v v9, v8
1732 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1733 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
1734 ; CHECK-NEXT: ret
1735 entry:
1736 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1737 ret void
1738 }
1740 declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
1741 declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1743 define void @test_vsoxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1744 ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i32:
1745 ; CHECK: # %bb.0: # %entry
1746 ; CHECK-NEXT: vmv1r.v v10, v9
1747 ; CHECK-NEXT: vmv1r.v v9, v8
1748 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1749 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
1750 ; CHECK-NEXT: ret
1751 entry:
1752 tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1753 ret void
1754 }
1756 define void @test_vsoxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1757 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i32:
1758 ; CHECK: # %bb.0: # %entry
1759 ; CHECK-NEXT: vmv1r.v v10, v9
1760 ; CHECK-NEXT: vmv1r.v v9, v8
1761 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1762 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
1763 ; CHECK-NEXT: ret
1764 entry:
1765 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1766 ret void
1767 }
1769 declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
1770 declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1772 define void @test_vsoxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1773 ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i16:
1774 ; CHECK: # %bb.0: # %entry
1775 ; CHECK-NEXT: vmv1r.v v10, v9
1776 ; CHECK-NEXT: vmv1r.v v9, v8
1777 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1778 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
1779 ; CHECK-NEXT: ret
1780 entry:
1781 tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1782 ret void
1783 }
1785 define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1786 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i16:
1787 ; CHECK: # %bb.0: # %entry
1788 ; CHECK-NEXT: vmv1r.v v10, v9
1789 ; CHECK-NEXT: vmv1r.v v9, v8
1790 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1791 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
1792 ; CHECK-NEXT: ret
1793 entry:
1794 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1795 ret void
1796 }
1798 declare void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
1799 declare void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1801 define void @test_vsoxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1802 ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i8:
1803 ; CHECK: # %bb.0: # %entry
1804 ; CHECK-NEXT: vmv1r.v v10, v9
1805 ; CHECK-NEXT: vmv1r.v v9, v8
1806 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1807 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
1808 ; CHECK-NEXT: ret
1809 entry:
1810 tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1811 ret void
1812 }
1814 define void @test_vsoxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1815 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i8:
1816 ; CHECK: # %bb.0: # %entry
1817 ; CHECK-NEXT: vmv1r.v v10, v9
1818 ; CHECK-NEXT: vmv1r.v v9, v8
1819 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1820 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
1821 ; CHECK-NEXT: ret
1822 entry:
1823 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1824 ret void
1825 }
1827 declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
1828 declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1830 define void @test_vsoxseg3_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1831 ; CHECK-LABEL: test_vsoxseg3_nxv1i32_nxv1i64:
1832 ; CHECK: # %bb.0: # %entry
1833 ; CHECK-NEXT: vmv1r.v v10, v8
1834 ; CHECK-NEXT: vmv1r.v v11, v8
1835 ; CHECK-NEXT: vmv1r.v v12, v8
1836 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1837 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
1838 ; CHECK-NEXT: ret
1839 entry:
1840 tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1841 ret void
1842 }
1844 define void @test_vsoxseg3_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1845 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_nxv1i64:
1846 ; CHECK: # %bb.0: # %entry
1847 ; CHECK-NEXT: vmv1r.v v10, v8
1848 ; CHECK-NEXT: vmv1r.v v11, v8
1849 ; CHECK-NEXT: vmv1r.v v12, v8
1850 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1851 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
1852 ; CHECK-NEXT: ret
1853 entry:
1854 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1855 ret void
1856 }
1858 declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
1859 declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1861 define void @test_vsoxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1862 ; CHECK-LABEL: test_vsoxseg3_nxv1i32_nxv1i32:
1863 ; CHECK: # %bb.0: # %entry
1864 ; CHECK-NEXT: vmv1r.v v10, v8
1865 ; CHECK-NEXT: vmv1r.v v11, v8
1866 ; CHECK-NEXT: vmv1r.v v12, v8
1867 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1868 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
1869 ; CHECK-NEXT: ret
1870 entry:
1871 tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1872 ret void
1873 }
1875 define void @test_vsoxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1876 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_nxv1i32:
1877 ; CHECK: # %bb.0: # %entry
1878 ; CHECK-NEXT: vmv1r.v v10, v8
1879 ; CHECK-NEXT: vmv1r.v v11, v8
1880 ; CHECK-NEXT: vmv1r.v v12, v8
1881 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1882 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
1883 ; CHECK-NEXT: ret
1884 entry:
1885 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
1886 ret void
1887 }
1889 declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
1890 declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
1892 define void @test_vsoxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
1893 ; CHECK-LABEL: test_vsoxseg3_nxv1i32_nxv1i16:
1894 ; CHECK: # %bb.0: # %entry
1895 ; CHECK-NEXT: vmv1r.v v10, v8
1896 ; CHECK-NEXT: vmv1r.v v11, v8
1897 ; CHECK-NEXT: vmv1r.v v12, v8
1898 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1899 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
1900 ; CHECK-NEXT: ret
1901 entry:
1902 tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
1903 ret void
1904 }
1906 define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1907 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_nxv1i16:
1908 ; CHECK: # %bb.0: # %entry
1909 ; CHECK-NEXT: vmv1r.v v10, v8
1910 ; CHECK-NEXT: vmv1r.v v11, v8
1911 ; CHECK-NEXT: vmv1r.v v12, v8
1912 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1913 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
1914 ; CHECK-NEXT: ret
1915 entry:
1916 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
1917 ret void
1918 }
1920 declare void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
1921 declare void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
1923 define void @test_vsoxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
1924 ; CHECK-LABEL: test_vsoxseg3_nxv1i32_nxv1i8:
1925 ; CHECK: # %bb.0: # %entry
1926 ; CHECK-NEXT: vmv1r.v v10, v8
1927 ; CHECK-NEXT: vmv1r.v v11, v8
1928 ; CHECK-NEXT: vmv1r.v v12, v8
1929 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1930 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
1931 ; CHECK-NEXT: ret
1932 entry:
1933 tail call void @llvm.riscv.vsoxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
1934 ret void
1935 }
1937 define void @test_vsoxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1938 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_nxv1i8:
1939 ; CHECK: # %bb.0: # %entry
1940 ; CHECK-NEXT: vmv1r.v v10, v8
1941 ; CHECK-NEXT: vmv1r.v v11, v8
1942 ; CHECK-NEXT: vmv1r.v v12, v8
1943 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1944 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
1945 ; CHECK-NEXT: ret
1946 entry:
1947 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
1948 ret void
1949 }
1951 declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
1952 declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
1954 define void @test_vsoxseg4_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
1955 ; CHECK-LABEL: test_vsoxseg4_nxv1i32_nxv1i64:
1956 ; CHECK: # %bb.0: # %entry
1957 ; CHECK-NEXT: vmv1r.v v10, v8
1958 ; CHECK-NEXT: vmv1r.v v11, v8
1959 ; CHECK-NEXT: vmv1r.v v12, v8
1960 ; CHECK-NEXT: vmv1r.v v13, v8
1961 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1962 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
1963 ; CHECK-NEXT: ret
1964 entry:
1965 tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
1966 ret void
1967 }
1969 define void @test_vsoxseg4_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
1970 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_nxv1i64:
1971 ; CHECK: # %bb.0: # %entry
1972 ; CHECK-NEXT: vmv1r.v v10, v8
1973 ; CHECK-NEXT: vmv1r.v v11, v8
1974 ; CHECK-NEXT: vmv1r.v v12, v8
1975 ; CHECK-NEXT: vmv1r.v v13, v8
1976 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1977 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
1978 ; CHECK-NEXT: ret
1979 entry:
1980 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
1981 ret void
1982 }
1984 declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
1985 declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
1987 define void @test_vsoxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
1988 ; CHECK-LABEL: test_vsoxseg4_nxv1i32_nxv1i32:
1989 ; CHECK: # %bb.0: # %entry
1990 ; CHECK-NEXT: vmv1r.v v10, v8
1991 ; CHECK-NEXT: vmv1r.v v11, v8
1992 ; CHECK-NEXT: vmv1r.v v12, v8
1993 ; CHECK-NEXT: vmv1r.v v13, v8
1994 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1995 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
1996 ; CHECK-NEXT: ret
1997 entry:
1998 tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
1999 ret void
2000 }
2002 define void @test_vsoxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2003 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_nxv1i32:
2004 ; CHECK: # %bb.0: # %entry
2005 ; CHECK-NEXT: vmv1r.v v10, v8
2006 ; CHECK-NEXT: vmv1r.v v11, v8
2007 ; CHECK-NEXT: vmv1r.v v12, v8
2008 ; CHECK-NEXT: vmv1r.v v13, v8
2009 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2010 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
2011 ; CHECK-NEXT: ret
2012 entry:
2013 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
2014 ret void
2015 }
2017 declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
2018 declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
2020 define void @test_vsoxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
2021 ; CHECK-LABEL: test_vsoxseg4_nxv1i32_nxv1i16:
2022 ; CHECK: # %bb.0: # %entry
2023 ; CHECK-NEXT: vmv1r.v v10, v8
2024 ; CHECK-NEXT: vmv1r.v v11, v8
2025 ; CHECK-NEXT: vmv1r.v v12, v8
2026 ; CHECK-NEXT: vmv1r.v v13, v8
2027 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2028 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
2029 ; CHECK-NEXT: ret
2030 entry:
2031 tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
2032 ret void
2033 }
2035 define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2036 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_nxv1i16:
2037 ; CHECK: # %bb.0: # %entry
2038 ; CHECK-NEXT: vmv1r.v v10, v8
2039 ; CHECK-NEXT: vmv1r.v v11, v8
2040 ; CHECK-NEXT: vmv1r.v v12, v8
2041 ; CHECK-NEXT: vmv1r.v v13, v8
2042 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2043 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
2044 ; CHECK-NEXT: ret
2045 entry:
2046 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
2047 ret void
2048 }
2050 declare void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
2051 declare void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
2053 define void @test_vsoxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
2054 ; CHECK-LABEL: test_vsoxseg4_nxv1i32_nxv1i8:
2055 ; CHECK: # %bb.0: # %entry
2056 ; CHECK-NEXT: vmv1r.v v10, v8
2057 ; CHECK-NEXT: vmv1r.v v11, v8
2058 ; CHECK-NEXT: vmv1r.v v12, v8
2059 ; CHECK-NEXT: vmv1r.v v13, v8
2060 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2061 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
2062 ; CHECK-NEXT: ret
2063 entry:
2064 tail call void @llvm.riscv.vsoxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
2065 ret void
2066 }
2068 define void @test_vsoxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2069 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_nxv1i8:
2070 ; CHECK: # %bb.0: # %entry
2071 ; CHECK-NEXT: vmv1r.v v10, v8
2072 ; CHECK-NEXT: vmv1r.v v11, v8
2073 ; CHECK-NEXT: vmv1r.v v12, v8
2074 ; CHECK-NEXT: vmv1r.v v13, v8
2075 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2076 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
2077 ; CHECK-NEXT: ret
2078 entry:
2079 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
2080 ret void
2081 }
2083 declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
2084 declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
2086 define void @test_vsoxseg5_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
2087 ; CHECK-LABEL: test_vsoxseg5_nxv1i32_nxv1i64:
2088 ; CHECK: # %bb.0: # %entry
2089 ; CHECK-NEXT: vmv1r.v v10, v8
2090 ; CHECK-NEXT: vmv1r.v v11, v8
2091 ; CHECK-NEXT: vmv1r.v v12, v8
2092 ; CHECK-NEXT: vmv1r.v v13, v8
2093 ; CHECK-NEXT: vmv1r.v v14, v8
2094 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2095 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
2096 ; CHECK-NEXT: ret
2097 entry:
2098 tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
2099 ret void
2100 }
2102 define void @test_vsoxseg5_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2103 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_nxv1i64:
2104 ; CHECK: # %bb.0: # %entry
2105 ; CHECK-NEXT: vmv1r.v v10, v8
2106 ; CHECK-NEXT: vmv1r.v v11, v8
2107 ; CHECK-NEXT: vmv1r.v v12, v8
2108 ; CHECK-NEXT: vmv1r.v v13, v8
2109 ; CHECK-NEXT: vmv1r.v v14, v8
2110 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2111 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
2112 ; CHECK-NEXT: ret
2113 entry:
2114 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
2115 ret void
2116 }
2118 declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
2119 declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
2121 define void @test_vsoxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
2122 ; CHECK-LABEL: test_vsoxseg5_nxv1i32_nxv1i32:
2123 ; CHECK: # %bb.0: # %entry
2124 ; CHECK-NEXT: vmv1r.v v10, v8
2125 ; CHECK-NEXT: vmv1r.v v11, v8
2126 ; CHECK-NEXT: vmv1r.v v12, v8
2127 ; CHECK-NEXT: vmv1r.v v13, v8
2128 ; CHECK-NEXT: vmv1r.v v14, v8
2129 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2130 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
2131 ; CHECK-NEXT: ret
2132 entry:
2133 tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
2134 ret void
2135 }
2137 define void @test_vsoxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2138 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_nxv1i32:
2139 ; CHECK: # %bb.0: # %entry
2140 ; CHECK-NEXT: vmv1r.v v10, v8
2141 ; CHECK-NEXT: vmv1r.v v11, v8
2142 ; CHECK-NEXT: vmv1r.v v12, v8
2143 ; CHECK-NEXT: vmv1r.v v13, v8
2144 ; CHECK-NEXT: vmv1r.v v14, v8
2145 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2146 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
2147 ; CHECK-NEXT: ret
2148 entry:
2149 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
2150 ret void
2151 }
2153 declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
2154 declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
2156 define void @test_vsoxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
2157 ; CHECK-LABEL: test_vsoxseg5_nxv1i32_nxv1i16:
2158 ; CHECK: # %bb.0: # %entry
2159 ; CHECK-NEXT: vmv1r.v v10, v8
2160 ; CHECK-NEXT: vmv1r.v v11, v8
2161 ; CHECK-NEXT: vmv1r.v v12, v8
2162 ; CHECK-NEXT: vmv1r.v v13, v8
2163 ; CHECK-NEXT: vmv1r.v v14, v8
2164 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2165 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
2166 ; CHECK-NEXT: ret
2167 entry:
2168 tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
2169 ret void
2170 }
2172 define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2173 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_nxv1i16:
2174 ; CHECK: # %bb.0: # %entry
2175 ; CHECK-NEXT: vmv1r.v v10, v8
2176 ; CHECK-NEXT: vmv1r.v v11, v8
2177 ; CHECK-NEXT: vmv1r.v v12, v8
2178 ; CHECK-NEXT: vmv1r.v v13, v8
2179 ; CHECK-NEXT: vmv1r.v v14, v8
2180 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2181 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
2182 ; CHECK-NEXT: ret
2183 entry:
2184 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
2185 ret void
2186 }
2188 declare void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
2189 declare void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
2191 define void @test_vsoxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
2192 ; CHECK-LABEL: test_vsoxseg5_nxv1i32_nxv1i8:
2193 ; CHECK: # %bb.0: # %entry
2194 ; CHECK-NEXT: vmv1r.v v10, v8
2195 ; CHECK-NEXT: vmv1r.v v11, v8
2196 ; CHECK-NEXT: vmv1r.v v12, v8
2197 ; CHECK-NEXT: vmv1r.v v13, v8
2198 ; CHECK-NEXT: vmv1r.v v14, v8
2199 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2200 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
2201 ; CHECK-NEXT: ret
2202 entry:
2203 tail call void @llvm.riscv.vsoxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
2204 ret void
2205 }
2207 define void @test_vsoxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2208 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_nxv1i8:
2209 ; CHECK: # %bb.0: # %entry
2210 ; CHECK-NEXT: vmv1r.v v10, v8
2211 ; CHECK-NEXT: vmv1r.v v11, v8
2212 ; CHECK-NEXT: vmv1r.v v12, v8
2213 ; CHECK-NEXT: vmv1r.v v13, v8
2214 ; CHECK-NEXT: vmv1r.v v14, v8
2215 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2216 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
2217 ; CHECK-NEXT: ret
2218 entry:
2219 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
2220 ret void
2221 }
2223 declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
2224 declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
2226 define void @test_vsoxseg6_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
2227 ; CHECK-LABEL: test_vsoxseg6_nxv1i32_nxv1i64:
2228 ; CHECK: # %bb.0: # %entry
2229 ; CHECK-NEXT: vmv1r.v v10, v8
2230 ; CHECK-NEXT: vmv1r.v v11, v8
2231 ; CHECK-NEXT: vmv1r.v v12, v8
2232 ; CHECK-NEXT: vmv1r.v v13, v8
2233 ; CHECK-NEXT: vmv1r.v v14, v8
2234 ; CHECK-NEXT: vmv1r.v v15, v8
2235 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2236 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
2237 ; CHECK-NEXT: ret
2238 entry:
2239 tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
2240 ret void
2241 }
2243 define void @test_vsoxseg6_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2244 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_nxv1i64:
2245 ; CHECK: # %bb.0: # %entry
2246 ; CHECK-NEXT: vmv1r.v v10, v8
2247 ; CHECK-NEXT: vmv1r.v v11, v8
2248 ; CHECK-NEXT: vmv1r.v v12, v8
2249 ; CHECK-NEXT: vmv1r.v v13, v8
2250 ; CHECK-NEXT: vmv1r.v v14, v8
2251 ; CHECK-NEXT: vmv1r.v v15, v8
2252 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2253 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
2254 ; CHECK-NEXT: ret
2255 entry:
2256 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
2257 ret void
2258 }
2260 declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
2261 declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
2263 define void @test_vsoxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
2264 ; CHECK-LABEL: test_vsoxseg6_nxv1i32_nxv1i32:
2265 ; CHECK: # %bb.0: # %entry
2266 ; CHECK-NEXT: vmv1r.v v10, v8
2267 ; CHECK-NEXT: vmv1r.v v11, v8
2268 ; CHECK-NEXT: vmv1r.v v12, v8
2269 ; CHECK-NEXT: vmv1r.v v13, v8
2270 ; CHECK-NEXT: vmv1r.v v14, v8
2271 ; CHECK-NEXT: vmv1r.v v15, v8
2272 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2273 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
2274 ; CHECK-NEXT: ret
2275 entry:
2276 tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
2277 ret void
2278 }
2280 define void @test_vsoxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2281 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_nxv1i32:
2282 ; CHECK: # %bb.0: # %entry
2283 ; CHECK-NEXT: vmv1r.v v10, v8
2284 ; CHECK-NEXT: vmv1r.v v11, v8
2285 ; CHECK-NEXT: vmv1r.v v12, v8
2286 ; CHECK-NEXT: vmv1r.v v13, v8
2287 ; CHECK-NEXT: vmv1r.v v14, v8
2288 ; CHECK-NEXT: vmv1r.v v15, v8
2289 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2290 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
2291 ; CHECK-NEXT: ret
2292 entry:
2293 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
2294 ret void
2295 }
2297 declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
2298 declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
2300 define void @test_vsoxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
2301 ; CHECK-LABEL: test_vsoxseg6_nxv1i32_nxv1i16:
2302 ; CHECK: # %bb.0: # %entry
2303 ; CHECK-NEXT: vmv1r.v v10, v8
2304 ; CHECK-NEXT: vmv1r.v v11, v8
2305 ; CHECK-NEXT: vmv1r.v v12, v8
2306 ; CHECK-NEXT: vmv1r.v v13, v8
2307 ; CHECK-NEXT: vmv1r.v v14, v8
2308 ; CHECK-NEXT: vmv1r.v v15, v8
2309 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2310 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
2311 ; CHECK-NEXT: ret
2312 entry:
2313 tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
2314 ret void
2315 }
2317 define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2318 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_nxv1i16:
2319 ; CHECK: # %bb.0: # %entry
2320 ; CHECK-NEXT: vmv1r.v v10, v8
2321 ; CHECK-NEXT: vmv1r.v v11, v8
2322 ; CHECK-NEXT: vmv1r.v v12, v8
2323 ; CHECK-NEXT: vmv1r.v v13, v8
2324 ; CHECK-NEXT: vmv1r.v v14, v8
2325 ; CHECK-NEXT: vmv1r.v v15, v8
2326 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2327 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
2328 ; CHECK-NEXT: ret
2329 entry:
2330 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
2331 ret void
2332 }
2334 declare void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
2335 declare void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
2337 define void @test_vsoxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
2338 ; CHECK-LABEL: test_vsoxseg6_nxv1i32_nxv1i8:
2339 ; CHECK: # %bb.0: # %entry
2340 ; CHECK-NEXT: vmv1r.v v10, v8
2341 ; CHECK-NEXT: vmv1r.v v11, v8
2342 ; CHECK-NEXT: vmv1r.v v12, v8
2343 ; CHECK-NEXT: vmv1r.v v13, v8
2344 ; CHECK-NEXT: vmv1r.v v14, v8
2345 ; CHECK-NEXT: vmv1r.v v15, v8
2346 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2347 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
2348 ; CHECK-NEXT: ret
2349 entry:
2350 tail call void @llvm.riscv.vsoxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
2351 ret void
2352 }
2354 define void @test_vsoxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2355 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_nxv1i8:
2356 ; CHECK: # %bb.0: # %entry
2357 ; CHECK-NEXT: vmv1r.v v10, v8
2358 ; CHECK-NEXT: vmv1r.v v11, v8
2359 ; CHECK-NEXT: vmv1r.v v12, v8
2360 ; CHECK-NEXT: vmv1r.v v13, v8
2361 ; CHECK-NEXT: vmv1r.v v14, v8
2362 ; CHECK-NEXT: vmv1r.v v15, v8
2363 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2364 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
2365 ; CHECK-NEXT: ret
2366 entry:
2367 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
2368 ret void
2369 }
2371 declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
2372 declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
2374 define void @test_vsoxseg7_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
2375 ; CHECK-LABEL: test_vsoxseg7_nxv1i32_nxv1i64:
2376 ; CHECK: # %bb.0: # %entry
2377 ; CHECK-NEXT: vmv1r.v v10, v8
2378 ; CHECK-NEXT: vmv1r.v v11, v8
2379 ; CHECK-NEXT: vmv1r.v v12, v8
2380 ; CHECK-NEXT: vmv1r.v v13, v8
2381 ; CHECK-NEXT: vmv1r.v v14, v8
2382 ; CHECK-NEXT: vmv1r.v v15, v8
2383 ; CHECK-NEXT: vmv1r.v v16, v8
2384 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2385 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
2386 ; CHECK-NEXT: ret
2387 entry:
2388 tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
2389 ret void
2390 }
2392 define void @test_vsoxseg7_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2393 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_nxv1i64:
2394 ; CHECK: # %bb.0: # %entry
2395 ; CHECK-NEXT: vmv1r.v v10, v8
2396 ; CHECK-NEXT: vmv1r.v v11, v8
2397 ; CHECK-NEXT: vmv1r.v v12, v8
2398 ; CHECK-NEXT: vmv1r.v v13, v8
2399 ; CHECK-NEXT: vmv1r.v v14, v8
2400 ; CHECK-NEXT: vmv1r.v v15, v8
2401 ; CHECK-NEXT: vmv1r.v v16, v8
2402 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2403 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
2404 ; CHECK-NEXT: ret
2405 entry:
2406 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
2407 ret void
2408 }
2410 declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
2411 declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
2413 define void @test_vsoxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
2414 ; CHECK-LABEL: test_vsoxseg7_nxv1i32_nxv1i32:
2415 ; CHECK: # %bb.0: # %entry
2416 ; CHECK-NEXT: vmv1r.v v10, v8
2417 ; CHECK-NEXT: vmv1r.v v11, v8
2418 ; CHECK-NEXT: vmv1r.v v12, v8
2419 ; CHECK-NEXT: vmv1r.v v13, v8
2420 ; CHECK-NEXT: vmv1r.v v14, v8
2421 ; CHECK-NEXT: vmv1r.v v15, v8
2422 ; CHECK-NEXT: vmv1r.v v16, v8
2423 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2424 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
2425 ; CHECK-NEXT: ret
2426 entry:
2427 tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
2428 ret void
2429 }
2431 define void @test_vsoxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2432 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_nxv1i32:
2433 ; CHECK: # %bb.0: # %entry
2434 ; CHECK-NEXT: vmv1r.v v10, v8
2435 ; CHECK-NEXT: vmv1r.v v11, v8
2436 ; CHECK-NEXT: vmv1r.v v12, v8
2437 ; CHECK-NEXT: vmv1r.v v13, v8
2438 ; CHECK-NEXT: vmv1r.v v14, v8
2439 ; CHECK-NEXT: vmv1r.v v15, v8
2440 ; CHECK-NEXT: vmv1r.v v16, v8
2441 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2442 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
2443 ; CHECK-NEXT: ret
2444 entry:
2445 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
2446 ret void
2447 }
2449 declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
2450 declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
2452 define void @test_vsoxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
2453 ; CHECK-LABEL: test_vsoxseg7_nxv1i32_nxv1i16:
2454 ; CHECK: # %bb.0: # %entry
2455 ; CHECK-NEXT: vmv1r.v v10, v8
2456 ; CHECK-NEXT: vmv1r.v v11, v8
2457 ; CHECK-NEXT: vmv1r.v v12, v8
2458 ; CHECK-NEXT: vmv1r.v v13, v8
2459 ; CHECK-NEXT: vmv1r.v v14, v8
2460 ; CHECK-NEXT: vmv1r.v v15, v8
2461 ; CHECK-NEXT: vmv1r.v v16, v8
2462 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2463 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
2464 ; CHECK-NEXT: ret
2465 entry:
2466 tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
2467 ret void
2468 }
2470 define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2471 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_nxv1i16:
2472 ; CHECK: # %bb.0: # %entry
2473 ; CHECK-NEXT: vmv1r.v v10, v8
2474 ; CHECK-NEXT: vmv1r.v v11, v8
2475 ; CHECK-NEXT: vmv1r.v v12, v8
2476 ; CHECK-NEXT: vmv1r.v v13, v8
2477 ; CHECK-NEXT: vmv1r.v v14, v8
2478 ; CHECK-NEXT: vmv1r.v v15, v8
2479 ; CHECK-NEXT: vmv1r.v v16, v8
2480 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2481 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
2482 ; CHECK-NEXT: ret
2483 entry:
2484 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
2485 ret void
2486 }
2488 declare void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
2489 declare void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
2491 define void @test_vsoxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
2492 ; CHECK-LABEL: test_vsoxseg7_nxv1i32_nxv1i8:
2493 ; CHECK: # %bb.0: # %entry
2494 ; CHECK-NEXT: vmv1r.v v10, v8
2495 ; CHECK-NEXT: vmv1r.v v11, v8
2496 ; CHECK-NEXT: vmv1r.v v12, v8
2497 ; CHECK-NEXT: vmv1r.v v13, v8
2498 ; CHECK-NEXT: vmv1r.v v14, v8
2499 ; CHECK-NEXT: vmv1r.v v15, v8
2500 ; CHECK-NEXT: vmv1r.v v16, v8
2501 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2502 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
2503 ; CHECK-NEXT: ret
2504 entry:
2505 tail call void @llvm.riscv.vsoxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
2506 ret void
2507 }
2509 define void @test_vsoxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2510 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_nxv1i8:
2511 ; CHECK: # %bb.0: # %entry
2512 ; CHECK-NEXT: vmv1r.v v10, v8
2513 ; CHECK-NEXT: vmv1r.v v11, v8
2514 ; CHECK-NEXT: vmv1r.v v12, v8
2515 ; CHECK-NEXT: vmv1r.v v13, v8
2516 ; CHECK-NEXT: vmv1r.v v14, v8
2517 ; CHECK-NEXT: vmv1r.v v15, v8
2518 ; CHECK-NEXT: vmv1r.v v16, v8
2519 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2520 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
2521 ; CHECK-NEXT: ret
2522 entry:
2523 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
2524 ret void
2525 }
2527 declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, i64)
2528 declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
2530 define void @test_vsoxseg8_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
2531 ; CHECK-LABEL: test_vsoxseg8_nxv1i32_nxv1i64:
2532 ; CHECK: # %bb.0: # %entry
2533 ; CHECK-NEXT: vmv1r.v v10, v8
2534 ; CHECK-NEXT: vmv1r.v v11, v8
2535 ; CHECK-NEXT: vmv1r.v v12, v8
2536 ; CHECK-NEXT: vmv1r.v v13, v8
2537 ; CHECK-NEXT: vmv1r.v v14, v8
2538 ; CHECK-NEXT: vmv1r.v v15, v8
2539 ; CHECK-NEXT: vmv1r.v v16, v8
2540 ; CHECK-NEXT: vmv1r.v v17, v8
2541 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2542 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
2543 ; CHECK-NEXT: ret
2544 entry:
2545 tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
2546 ret void
2547 }
2549 define void @test_vsoxseg8_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2550 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_nxv1i64:
2551 ; CHECK: # %bb.0: # %entry
2552 ; CHECK-NEXT: vmv1r.v v10, v8
2553 ; CHECK-NEXT: vmv1r.v v11, v8
2554 ; CHECK-NEXT: vmv1r.v v12, v8
2555 ; CHECK-NEXT: vmv1r.v v13, v8
2556 ; CHECK-NEXT: vmv1r.v v14, v8
2557 ; CHECK-NEXT: vmv1r.v v15, v8
2558 ; CHECK-NEXT: vmv1r.v v16, v8
2559 ; CHECK-NEXT: vmv1r.v v17, v8
2560 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2561 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
2562 ; CHECK-NEXT: ret
2563 entry:
2564 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
2565 ret void
2566 }
2568 declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, i64)
2569 declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
2571 define void @test_vsoxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
2572 ; CHECK-LABEL: test_vsoxseg8_nxv1i32_nxv1i32:
2573 ; CHECK: # %bb.0: # %entry
2574 ; CHECK-NEXT: vmv1r.v v10, v8
2575 ; CHECK-NEXT: vmv1r.v v11, v8
2576 ; CHECK-NEXT: vmv1r.v v12, v8
2577 ; CHECK-NEXT: vmv1r.v v13, v8
2578 ; CHECK-NEXT: vmv1r.v v14, v8
2579 ; CHECK-NEXT: vmv1r.v v15, v8
2580 ; CHECK-NEXT: vmv1r.v v16, v8
2581 ; CHECK-NEXT: vmv1r.v v17, v8
2582 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2583 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
2584 ; CHECK-NEXT: ret
2585 entry:
2586 tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
2587 ret void
2588 }
2590 define void @test_vsoxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2591 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_nxv1i32:
2592 ; CHECK: # %bb.0: # %entry
2593 ; CHECK-NEXT: vmv1r.v v10, v8
2594 ; CHECK-NEXT: vmv1r.v v11, v8
2595 ; CHECK-NEXT: vmv1r.v v12, v8
2596 ; CHECK-NEXT: vmv1r.v v13, v8
2597 ; CHECK-NEXT: vmv1r.v v14, v8
2598 ; CHECK-NEXT: vmv1r.v v15, v8
2599 ; CHECK-NEXT: vmv1r.v v16, v8
2600 ; CHECK-NEXT: vmv1r.v v17, v8
2601 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2602 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
2603 ; CHECK-NEXT: ret
2604 entry:
2605 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
2606 ret void
2607 }
2609 declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, i64)
2610 declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
2612 define void @test_vsoxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
2613 ; CHECK-LABEL: test_vsoxseg8_nxv1i32_nxv1i16:
2614 ; CHECK: # %bb.0: # %entry
2615 ; CHECK-NEXT: vmv1r.v v10, v8
2616 ; CHECK-NEXT: vmv1r.v v11, v8
2617 ; CHECK-NEXT: vmv1r.v v12, v8
2618 ; CHECK-NEXT: vmv1r.v v13, v8
2619 ; CHECK-NEXT: vmv1r.v v14, v8
2620 ; CHECK-NEXT: vmv1r.v v15, v8
2621 ; CHECK-NEXT: vmv1r.v v16, v8
2622 ; CHECK-NEXT: vmv1r.v v17, v8
2623 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2624 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
2625 ; CHECK-NEXT: ret
2626 entry:
2627 tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
2628 ret void
2629 }
2631 define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2632 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_nxv1i16:
2633 ; CHECK: # %bb.0: # %entry
2634 ; CHECK-NEXT: vmv1r.v v10, v8
2635 ; CHECK-NEXT: vmv1r.v v11, v8
2636 ; CHECK-NEXT: vmv1r.v v12, v8
2637 ; CHECK-NEXT: vmv1r.v v13, v8
2638 ; CHECK-NEXT: vmv1r.v v14, v8
2639 ; CHECK-NEXT: vmv1r.v v15, v8
2640 ; CHECK-NEXT: vmv1r.v v16, v8
2641 ; CHECK-NEXT: vmv1r.v v17, v8
2642 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2643 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
2644 ; CHECK-NEXT: ret
2645 entry:
2646 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
2647 ret void
2648 }
2650 declare void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, i64)
2651 declare void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
2653 define void @test_vsoxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
2654 ; CHECK-LABEL: test_vsoxseg8_nxv1i32_nxv1i8:
2655 ; CHECK: # %bb.0: # %entry
2656 ; CHECK-NEXT: vmv1r.v v10, v8
2657 ; CHECK-NEXT: vmv1r.v v11, v8
2658 ; CHECK-NEXT: vmv1r.v v12, v8
2659 ; CHECK-NEXT: vmv1r.v v13, v8
2660 ; CHECK-NEXT: vmv1r.v v14, v8
2661 ; CHECK-NEXT: vmv1r.v v15, v8
2662 ; CHECK-NEXT: vmv1r.v v16, v8
2663 ; CHECK-NEXT: vmv1r.v v17, v8
2664 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2665 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
2666 ; CHECK-NEXT: ret
2667 entry:
2668 tail call void @llvm.riscv.vsoxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
2669 ret void
2670 }
2672 define void @test_vsoxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
2673 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_nxv1i8:
2674 ; CHECK: # %bb.0: # %entry
2675 ; CHECK-NEXT: vmv1r.v v10, v8
2676 ; CHECK-NEXT: vmv1r.v v11, v8
2677 ; CHECK-NEXT: vmv1r.v v12, v8
2678 ; CHECK-NEXT: vmv1r.v v13, v8
2679 ; CHECK-NEXT: vmv1r.v v14, v8
2680 ; CHECK-NEXT: vmv1r.v v15, v8
2681 ; CHECK-NEXT: vmv1r.v v16, v8
2682 ; CHECK-NEXT: vmv1r.v v17, v8
2683 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
2684 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
2685 ; CHECK-NEXT: ret
2686 entry:
2687 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
2688 ret void
2689 }
2691 declare void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, i64)
2692 declare void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
2694 define void @test_vsoxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
2695 ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i16:
2696 ; CHECK: # %bb.0: # %entry
2697 ; CHECK-NEXT: vmv2r.v v12, v10
2698 ; CHECK-NEXT: vmv2r.v v10, v8
2699 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2700 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
2701 ; CHECK-NEXT: ret
2702 entry:
2703 tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
2704 ret void
2705 }
2707 define void @test_vsoxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2708 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i16:
2709 ; CHECK: # %bb.0: # %entry
2710 ; CHECK-NEXT: vmv2r.v v12, v10
2711 ; CHECK-NEXT: vmv2r.v v10, v8
2712 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2713 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
2714 ; CHECK-NEXT: ret
2715 entry:
2716 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
2717 ret void
2718 }
2720 declare void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, i64)
2721 declare void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
2723 define void @test_vsoxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
2724 ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i8:
2725 ; CHECK: # %bb.0: # %entry
2726 ; CHECK-NEXT: vmv1r.v v12, v10
2727 ; CHECK-NEXT: vmv2r.v v10, v8
2728 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2729 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
2730 ; CHECK-NEXT: ret
2731 entry:
2732 tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
2733 ret void
2734 }
2736 define void @test_vsoxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2737 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i8:
2738 ; CHECK: # %bb.0: # %entry
2739 ; CHECK-NEXT: vmv1r.v v12, v10
2740 ; CHECK-NEXT: vmv2r.v v10, v8
2741 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2742 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
2743 ; CHECK-NEXT: ret
2744 entry:
2745 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
2746 ret void
2747 }
2749 declare void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, i64)
2750 declare void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
2752 define void @test_vsoxseg2_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
2753 ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i64:
2754 ; CHECK: # %bb.0: # %entry
2755 ; CHECK-NEXT: vmv2r.v v10, v8
2756 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2757 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
2758 ; CHECK-NEXT: ret
2759 entry:
2760 tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
2761 ret void
2762 }
2764 define void @test_vsoxseg2_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2765 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i64:
2766 ; CHECK: # %bb.0: # %entry
2767 ; CHECK-NEXT: vmv2r.v v10, v8
2768 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2769 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
2770 ; CHECK-NEXT: ret
2771 entry:
2772 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
2773 ret void
2774 }
2776 declare void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, i64)
2777 declare void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
2779 define void @test_vsoxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
2780 ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i32:
2781 ; CHECK: # %bb.0: # %entry
2782 ; CHECK-NEXT: vmv2r.v v10, v8
2783 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2784 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
2785 ; CHECK-NEXT: ret
2786 entry:
2787 tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
2788 ret void
2789 }
2791 define void @test_vsoxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2792 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i32:
2793 ; CHECK: # %bb.0: # %entry
2794 ; CHECK-NEXT: vmv2r.v v10, v8
2795 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2796 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
2797 ; CHECK-NEXT: ret
2798 entry:
2799 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
2800 ret void
2801 }
2803 declare void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, i64)
2804 declare void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
2806 define void @test_vsoxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
2807 ; CHECK-LABEL: test_vsoxseg3_nxv8i16_nxv8i16:
2808 ; CHECK: # %bb.0: # %entry
2809 ; CHECK-NEXT: vmv2r.v v12, v8
2810 ; CHECK-NEXT: vmv2r.v v14, v8
2811 ; CHECK-NEXT: vmv2r.v v16, v8
2812 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2813 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
2814 ; CHECK-NEXT: ret
2815 entry:
2816 tail call void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
2817 ret void
2818 }
2820 define void @test_vsoxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2821 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_nxv8i16:
2822 ; CHECK: # %bb.0: # %entry
2823 ; CHECK-NEXT: vmv2r.v v12, v8
2824 ; CHECK-NEXT: vmv2r.v v14, v8
2825 ; CHECK-NEXT: vmv2r.v v16, v8
2826 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2827 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
2828 ; CHECK-NEXT: ret
2829 entry:
2830 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
2831 ret void
2832 }
2834 declare void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, i64)
2835 declare void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
2837 define void @test_vsoxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
2838 ; CHECK-LABEL: test_vsoxseg3_nxv8i16_nxv8i8:
2839 ; CHECK: # %bb.0: # %entry
2840 ; CHECK-NEXT: vmv2r.v v12, v8
2841 ; CHECK-NEXT: vmv2r.v v14, v8
2842 ; CHECK-NEXT: vmv2r.v v16, v8
2843 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2844 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
2845 ; CHECK-NEXT: ret
2846 entry:
2847 tail call void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
2848 ret void
2849 }
2851 define void @test_vsoxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2852 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_nxv8i8:
2853 ; CHECK: # %bb.0: # %entry
2854 ; CHECK-NEXT: vmv2r.v v12, v8
2855 ; CHECK-NEXT: vmv2r.v v14, v8
2856 ; CHECK-NEXT: vmv2r.v v16, v8
2857 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2858 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
2859 ; CHECK-NEXT: ret
2860 entry:
2861 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
2862 ret void
2863 }
2865 declare void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, i64)
2866 declare void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
2868 define void @test_vsoxseg3_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
2869 ; CHECK-LABEL: test_vsoxseg3_nxv8i16_nxv8i64:
2870 ; CHECK: # %bb.0: # %entry
2871 ; CHECK-NEXT: vmv2r.v v10, v8
2872 ; CHECK-NEXT: vmv2r.v v12, v8
2873 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2874 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16
2875 ; CHECK-NEXT: ret
2876 entry:
2877 tail call void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
2878 ret void
2879 }
2881 define void @test_vsoxseg3_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2882 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_nxv8i64:
2883 ; CHECK: # %bb.0: # %entry
2884 ; CHECK-NEXT: vmv2r.v v10, v8
2885 ; CHECK-NEXT: vmv2r.v v12, v8
2886 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2887 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16, v0.t
2888 ; CHECK-NEXT: ret
2889 entry:
2890 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
2891 ret void
2892 }
2894 declare void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, i64)
2895 declare void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
2897 define void @test_vsoxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
2898 ; CHECK-LABEL: test_vsoxseg3_nxv8i16_nxv8i32:
2899 ; CHECK: # %bb.0: # %entry
2900 ; CHECK-NEXT: vmv2r.v v10, v8
2901 ; CHECK-NEXT: vmv4r.v v16, v12
2902 ; CHECK-NEXT: vmv2r.v v12, v8
2903 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2904 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16
2905 ; CHECK-NEXT: ret
2906 entry:
2907 tail call void @llvm.riscv.vsoxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
2908 ret void
2909 }
2911 define void @test_vsoxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2912 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_nxv8i32:
2913 ; CHECK: # %bb.0: # %entry
2914 ; CHECK-NEXT: vmv2r.v v10, v8
2915 ; CHECK-NEXT: vmv4r.v v16, v12
2916 ; CHECK-NEXT: vmv2r.v v12, v8
2917 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2918 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16, v0.t
2919 ; CHECK-NEXT: ret
2920 entry:
2921 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
2922 ret void
2923 }
2925 declare void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, i64)
2926 declare void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
2928 define void @test_vsoxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
2929 ; CHECK-LABEL: test_vsoxseg4_nxv8i16_nxv8i16:
2930 ; CHECK: # %bb.0: # %entry
2931 ; CHECK-NEXT: vmv2r.v v12, v8
2932 ; CHECK-NEXT: vmv2r.v v14, v8
2933 ; CHECK-NEXT: vmv2r.v v16, v8
2934 ; CHECK-NEXT: vmv2r.v v18, v8
2935 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2936 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
2937 ; CHECK-NEXT: ret
2938 entry:
2939 tail call void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
2940 ret void
2941 }
2943 define void @test_vsoxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2944 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_nxv8i16:
2945 ; CHECK: # %bb.0: # %entry
2946 ; CHECK-NEXT: vmv2r.v v12, v8
2947 ; CHECK-NEXT: vmv2r.v v14, v8
2948 ; CHECK-NEXT: vmv2r.v v16, v8
2949 ; CHECK-NEXT: vmv2r.v v18, v8
2950 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2951 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
2952 ; CHECK-NEXT: ret
2953 entry:
2954 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
2955 ret void
2956 }
2958 declare void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, i64)
2959 declare void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
2961 define void @test_vsoxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
2962 ; CHECK-LABEL: test_vsoxseg4_nxv8i16_nxv8i8:
2963 ; CHECK: # %bb.0: # %entry
2964 ; CHECK-NEXT: vmv2r.v v12, v8
2965 ; CHECK-NEXT: vmv2r.v v14, v8
2966 ; CHECK-NEXT: vmv2r.v v16, v8
2967 ; CHECK-NEXT: vmv2r.v v18, v8
2968 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2969 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
2970 ; CHECK-NEXT: ret
2971 entry:
2972 tail call void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
2973 ret void
2974 }
2976 define void @test_vsoxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
2977 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_nxv8i8:
2978 ; CHECK: # %bb.0: # %entry
2979 ; CHECK-NEXT: vmv2r.v v12, v8
2980 ; CHECK-NEXT: vmv2r.v v14, v8
2981 ; CHECK-NEXT: vmv2r.v v16, v8
2982 ; CHECK-NEXT: vmv2r.v v18, v8
2983 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2984 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
2985 ; CHECK-NEXT: ret
2986 entry:
2987 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
2988 ret void
2989 }
2991 declare void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, i64)
2992 declare void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
2994 define void @test_vsoxseg4_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
2995 ; CHECK-LABEL: test_vsoxseg4_nxv8i16_nxv8i64:
2996 ; CHECK: # %bb.0: # %entry
2997 ; CHECK-NEXT: vmv2r.v v10, v8
2998 ; CHECK-NEXT: vmv2r.v v12, v8
2999 ; CHECK-NEXT: vmv2r.v v14, v8
3000 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
3001 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16
3002 ; CHECK-NEXT: ret
3003 entry:
3004 tail call void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
3005 ret void
3006 }
3008 define void @test_vsoxseg4_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
3009 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_nxv8i64:
3010 ; CHECK: # %bb.0: # %entry
3011 ; CHECK-NEXT: vmv2r.v v10, v8
3012 ; CHECK-NEXT: vmv2r.v v12, v8
3013 ; CHECK-NEXT: vmv2r.v v14, v8
3014 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
3015 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16, v0.t
3016 ; CHECK-NEXT: ret
3017 entry:
3018 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
3019 ret void
3020 }
3022 declare void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, i64)
3023 declare void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
3025 define void @test_vsoxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
3026 ; CHECK-LABEL: test_vsoxseg4_nxv8i16_nxv8i32:
3027 ; CHECK: # %bb.0: # %entry
3028 ; CHECK-NEXT: vmv2r.v v16, v8
3029 ; CHECK-NEXT: vmv2r.v v18, v8
3030 ; CHECK-NEXT: vmv2r.v v20, v8
3031 ; CHECK-NEXT: vmv2r.v v22, v8
3032 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
3033 ; CHECK-NEXT: vsoxseg4ei32.v v16, (a0), v12
3034 ; CHECK-NEXT: ret
3035 entry:
3036 tail call void @llvm.riscv.vsoxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
3037 ret void
3038 }
3040 define void @test_vsoxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
3041 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_nxv8i32:
3042 ; CHECK: # %bb.0: # %entry
3043 ; CHECK-NEXT: vmv2r.v v16, v8
3044 ; CHECK-NEXT: vmv2r.v v18, v8
3045 ; CHECK-NEXT: vmv2r.v v20, v8
3046 ; CHECK-NEXT: vmv2r.v v22, v8
3047 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
3048 ; CHECK-NEXT: vsoxseg4ei32.v v16, (a0), v12, v0.t
3049 ; CHECK-NEXT: ret
3050 entry:
3051 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
3052 ret void
3053 }
3055 declare void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3056 declare void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3058 define void @test_vsoxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3059 ; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i32:
3060 ; CHECK: # %bb.0: # %entry
3061 ; CHECK-NEXT: vmv1r.v v9, v8
3062 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3063 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
3064 ; CHECK-NEXT: ret
3065 entry:
3066 tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3067 ret void
3068 }
3070 define void @test_vsoxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3071 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i32:
3072 ; CHECK: # %bb.0: # %entry
3073 ; CHECK-NEXT: vmv1r.v v9, v8
3074 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3075 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
3076 ; CHECK-NEXT: ret
3077 entry:
3078 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3079 ret void
3080 }
3082 declare void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3083 declare void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3085 define void @test_vsoxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3086 ; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i8:
3087 ; CHECK: # %bb.0: # %entry
3088 ; CHECK-NEXT: vmv1r.v v10, v9
3089 ; CHECK-NEXT: vmv1r.v v9, v8
3090 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3091 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
3092 ; CHECK-NEXT: ret
3093 entry:
3094 tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3095 ret void
3096 }
3098 define void @test_vsoxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3099 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i8:
3100 ; CHECK: # %bb.0: # %entry
3101 ; CHECK-NEXT: vmv1r.v v10, v9
3102 ; CHECK-NEXT: vmv1r.v v9, v8
3103 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3104 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
3105 ; CHECK-NEXT: ret
3106 entry:
3107 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3108 ret void
3109 }
3111 declare void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3112 declare void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3114 define void @test_vsoxseg2_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3115 ; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i64:
3116 ; CHECK: # %bb.0: # %entry
3117 ; CHECK-NEXT: vmv1r.v v9, v8
3118 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3119 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
3120 ; CHECK-NEXT: ret
3121 entry:
3122 tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3123 ret void
3124 }
3126 define void @test_vsoxseg2_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3127 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i64:
3128 ; CHECK: # %bb.0: # %entry
3129 ; CHECK-NEXT: vmv1r.v v9, v8
3130 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3131 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
3132 ; CHECK-NEXT: ret
3133 entry:
3134 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3135 ret void
3136 }
3138 declare void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3139 declare void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3141 define void @test_vsoxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3142 ; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i16:
3143 ; CHECK: # %bb.0: # %entry
3144 ; CHECK-NEXT: vmv1r.v v10, v9
3145 ; CHECK-NEXT: vmv1r.v v9, v8
3146 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3147 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
3148 ; CHECK-NEXT: ret
3149 entry:
3150 tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3151 ret void
3152 }
3154 define void @test_vsoxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3155 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i16:
3156 ; CHECK: # %bb.0: # %entry
3157 ; CHECK-NEXT: vmv1r.v v10, v9
3158 ; CHECK-NEXT: vmv1r.v v9, v8
3159 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3160 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
3161 ; CHECK-NEXT: ret
3162 entry:
3163 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3164 ret void
3165 }
3167 declare void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3168 declare void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3170 define void @test_vsoxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3171 ; CHECK-LABEL: test_vsoxseg3_nxv4i8_nxv4i32:
3172 ; CHECK: # %bb.0: # %entry
3173 ; CHECK-NEXT: vmv1r.v v9, v8
3174 ; CHECK-NEXT: vmv2r.v v12, v10
3175 ; CHECK-NEXT: vmv1r.v v10, v8
3176 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3177 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12
3178 ; CHECK-NEXT: ret
3179 entry:
3180 tail call void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3181 ret void
3182 }
3184 define void @test_vsoxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3185 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_nxv4i32:
3186 ; CHECK: # %bb.0: # %entry
3187 ; CHECK-NEXT: vmv1r.v v9, v8
3188 ; CHECK-NEXT: vmv2r.v v12, v10
3189 ; CHECK-NEXT: vmv1r.v v10, v8
3190 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3191 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12, v0.t
3192 ; CHECK-NEXT: ret
3193 entry:
3194 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3195 ret void
3196 }
3198 declare void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3199 declare void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3201 define void @test_vsoxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3202 ; CHECK-LABEL: test_vsoxseg3_nxv4i8_nxv4i8:
3203 ; CHECK: # %bb.0: # %entry
3204 ; CHECK-NEXT: vmv1r.v v10, v8
3205 ; CHECK-NEXT: vmv1r.v v11, v8
3206 ; CHECK-NEXT: vmv1r.v v12, v8
3207 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3208 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
3209 ; CHECK-NEXT: ret
3210 entry:
3211 tail call void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3212 ret void
3213 }
3215 define void @test_vsoxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3216 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_nxv4i8:
3217 ; CHECK: # %bb.0: # %entry
3218 ; CHECK-NEXT: vmv1r.v v10, v8
3219 ; CHECK-NEXT: vmv1r.v v11, v8
3220 ; CHECK-NEXT: vmv1r.v v12, v8
3221 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3222 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
3223 ; CHECK-NEXT: ret
3224 entry:
3225 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3226 ret void
3227 }
3229 declare void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3230 declare void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3232 define void @test_vsoxseg3_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3233 ; CHECK-LABEL: test_vsoxseg3_nxv4i8_nxv4i64:
3234 ; CHECK: # %bb.0: # %entry
3235 ; CHECK-NEXT: vmv1r.v v9, v8
3236 ; CHECK-NEXT: vmv1r.v v10, v8
3237 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3238 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
3239 ; CHECK-NEXT: ret
3240 entry:
3241 tail call void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3242 ret void
3243 }
3245 define void @test_vsoxseg3_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3246 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_nxv4i64:
3247 ; CHECK: # %bb.0: # %entry
3248 ; CHECK-NEXT: vmv1r.v v9, v8
3249 ; CHECK-NEXT: vmv1r.v v10, v8
3250 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3251 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
3252 ; CHECK-NEXT: ret
3253 entry:
3254 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3255 ret void
3256 }
3258 declare void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3259 declare void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3261 define void @test_vsoxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3262 ; CHECK-LABEL: test_vsoxseg3_nxv4i8_nxv4i16:
3263 ; CHECK: # %bb.0: # %entry
3264 ; CHECK-NEXT: vmv1r.v v10, v8
3265 ; CHECK-NEXT: vmv1r.v v11, v8
3266 ; CHECK-NEXT: vmv1r.v v12, v8
3267 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3268 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
3269 ; CHECK-NEXT: ret
3270 entry:
3271 tail call void @llvm.riscv.vsoxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3272 ret void
3273 }
3275 define void @test_vsoxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3276 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_nxv4i16:
3277 ; CHECK: # %bb.0: # %entry
3278 ; CHECK-NEXT: vmv1r.v v10, v8
3279 ; CHECK-NEXT: vmv1r.v v11, v8
3280 ; CHECK-NEXT: vmv1r.v v12, v8
3281 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3282 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
3283 ; CHECK-NEXT: ret
3284 entry:
3285 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3286 ret void
3287 }
3289 declare void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3290 declare void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3292 define void @test_vsoxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3293 ; CHECK-LABEL: test_vsoxseg4_nxv4i8_nxv4i32:
3294 ; CHECK: # %bb.0: # %entry
3295 ; CHECK-NEXT: vmv1r.v v12, v8
3296 ; CHECK-NEXT: vmv1r.v v13, v8
3297 ; CHECK-NEXT: vmv1r.v v14, v8
3298 ; CHECK-NEXT: vmv1r.v v15, v8
3299 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3300 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
3301 ; CHECK-NEXT: ret
3302 entry:
3303 tail call void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3304 ret void
3305 }
3307 define void @test_vsoxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3308 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_nxv4i32:
3309 ; CHECK: # %bb.0: # %entry
3310 ; CHECK-NEXT: vmv1r.v v12, v8
3311 ; CHECK-NEXT: vmv1r.v v13, v8
3312 ; CHECK-NEXT: vmv1r.v v14, v8
3313 ; CHECK-NEXT: vmv1r.v v15, v8
3314 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3315 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
3316 ; CHECK-NEXT: ret
3317 entry:
3318 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3319 ret void
3320 }
3322 declare void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3323 declare void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3325 define void @test_vsoxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3326 ; CHECK-LABEL: test_vsoxseg4_nxv4i8_nxv4i8:
3327 ; CHECK: # %bb.0: # %entry
3328 ; CHECK-NEXT: vmv1r.v v10, v8
3329 ; CHECK-NEXT: vmv1r.v v11, v8
3330 ; CHECK-NEXT: vmv1r.v v12, v8
3331 ; CHECK-NEXT: vmv1r.v v13, v8
3332 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3333 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
3334 ; CHECK-NEXT: ret
3335 entry:
3336 tail call void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3337 ret void
3338 }
3340 define void @test_vsoxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3341 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_nxv4i8:
3342 ; CHECK: # %bb.0: # %entry
3343 ; CHECK-NEXT: vmv1r.v v10, v8
3344 ; CHECK-NEXT: vmv1r.v v11, v8
3345 ; CHECK-NEXT: vmv1r.v v12, v8
3346 ; CHECK-NEXT: vmv1r.v v13, v8
3347 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3348 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
3349 ; CHECK-NEXT: ret
3350 entry:
3351 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3352 ret void
3353 }
3355 declare void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3356 declare void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3358 define void @test_vsoxseg4_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3359 ; CHECK-LABEL: test_vsoxseg4_nxv4i8_nxv4i64:
3360 ; CHECK: # %bb.0: # %entry
3361 ; CHECK-NEXT: vmv1r.v v9, v8
3362 ; CHECK-NEXT: vmv1r.v v10, v8
3363 ; CHECK-NEXT: vmv1r.v v11, v8
3364 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3365 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12
3366 ; CHECK-NEXT: ret
3367 entry:
3368 tail call void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3369 ret void
3370 }
3372 define void @test_vsoxseg4_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3373 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_nxv4i64:
3374 ; CHECK: # %bb.0: # %entry
3375 ; CHECK-NEXT: vmv1r.v v9, v8
3376 ; CHECK-NEXT: vmv1r.v v10, v8
3377 ; CHECK-NEXT: vmv1r.v v11, v8
3378 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3379 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12, v0.t
3380 ; CHECK-NEXT: ret
3381 entry:
3382 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3383 ret void
3384 }
3386 declare void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3387 declare void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3389 define void @test_vsoxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3390 ; CHECK-LABEL: test_vsoxseg4_nxv4i8_nxv4i16:
3391 ; CHECK: # %bb.0: # %entry
3392 ; CHECK-NEXT: vmv1r.v v10, v8
3393 ; CHECK-NEXT: vmv1r.v v11, v8
3394 ; CHECK-NEXT: vmv1r.v v12, v8
3395 ; CHECK-NEXT: vmv1r.v v13, v8
3396 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3397 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
3398 ; CHECK-NEXT: ret
3399 entry:
3400 tail call void @llvm.riscv.vsoxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3401 ret void
3402 }
3404 define void @test_vsoxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3405 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_nxv4i16:
3406 ; CHECK: # %bb.0: # %entry
3407 ; CHECK-NEXT: vmv1r.v v10, v8
3408 ; CHECK-NEXT: vmv1r.v v11, v8
3409 ; CHECK-NEXT: vmv1r.v v12, v8
3410 ; CHECK-NEXT: vmv1r.v v13, v8
3411 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3412 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
3413 ; CHECK-NEXT: ret
3414 entry:
3415 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3416 ret void
3417 }
3419 declare void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3420 declare void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3422 define void @test_vsoxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3423 ; CHECK-LABEL: test_vsoxseg5_nxv4i8_nxv4i32:
3424 ; CHECK: # %bb.0: # %entry
3425 ; CHECK-NEXT: vmv1r.v v12, v8
3426 ; CHECK-NEXT: vmv1r.v v13, v8
3427 ; CHECK-NEXT: vmv1r.v v14, v8
3428 ; CHECK-NEXT: vmv1r.v v15, v8
3429 ; CHECK-NEXT: vmv1r.v v16, v8
3430 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3431 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10
3432 ; CHECK-NEXT: ret
3433 entry:
3434 tail call void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3435 ret void
3436 }
3438 define void @test_vsoxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3439 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_nxv4i32:
3440 ; CHECK: # %bb.0: # %entry
3441 ; CHECK-NEXT: vmv1r.v v12, v8
3442 ; CHECK-NEXT: vmv1r.v v13, v8
3443 ; CHECK-NEXT: vmv1r.v v14, v8
3444 ; CHECK-NEXT: vmv1r.v v15, v8
3445 ; CHECK-NEXT: vmv1r.v v16, v8
3446 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3447 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10, v0.t
3448 ; CHECK-NEXT: ret
3449 entry:
3450 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3451 ret void
3452 }
3454 declare void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3455 declare void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3457 define void @test_vsoxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3458 ; CHECK-LABEL: test_vsoxseg5_nxv4i8_nxv4i8:
3459 ; CHECK: # %bb.0: # %entry
3460 ; CHECK-NEXT: vmv1r.v v10, v8
3461 ; CHECK-NEXT: vmv1r.v v11, v8
3462 ; CHECK-NEXT: vmv1r.v v12, v8
3463 ; CHECK-NEXT: vmv1r.v v13, v8
3464 ; CHECK-NEXT: vmv1r.v v14, v8
3465 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3466 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
3467 ; CHECK-NEXT: ret
3468 entry:
3469 tail call void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3470 ret void
3471 }
3473 define void @test_vsoxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3474 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_nxv4i8:
3475 ; CHECK: # %bb.0: # %entry
3476 ; CHECK-NEXT: vmv1r.v v10, v8
3477 ; CHECK-NEXT: vmv1r.v v11, v8
3478 ; CHECK-NEXT: vmv1r.v v12, v8
3479 ; CHECK-NEXT: vmv1r.v v13, v8
3480 ; CHECK-NEXT: vmv1r.v v14, v8
3481 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3482 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
3483 ; CHECK-NEXT: ret
3484 entry:
3485 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3486 ret void
3487 }
3489 declare void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3490 declare void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3492 define void @test_vsoxseg5_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3493 ; CHECK-LABEL: test_vsoxseg5_nxv4i8_nxv4i64:
3494 ; CHECK: # %bb.0: # %entry
3495 ; CHECK-NEXT: vmv1r.v v9, v8
3496 ; CHECK-NEXT: vmv1r.v v10, v8
3497 ; CHECK-NEXT: vmv1r.v v11, v8
3498 ; CHECK-NEXT: vmv4r.v v16, v12
3499 ; CHECK-NEXT: vmv1r.v v12, v8
3500 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3501 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16
3502 ; CHECK-NEXT: ret
3503 entry:
3504 tail call void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3505 ret void
3506 }
3508 define void @test_vsoxseg5_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3509 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_nxv4i64:
3510 ; CHECK: # %bb.0: # %entry
3511 ; CHECK-NEXT: vmv1r.v v9, v8
3512 ; CHECK-NEXT: vmv1r.v v10, v8
3513 ; CHECK-NEXT: vmv1r.v v11, v8
3514 ; CHECK-NEXT: vmv4r.v v16, v12
3515 ; CHECK-NEXT: vmv1r.v v12, v8
3516 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3517 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16, v0.t
3518 ; CHECK-NEXT: ret
3519 entry:
3520 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3521 ret void
3522 }
3524 declare void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3525 declare void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3527 define void @test_vsoxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3528 ; CHECK-LABEL: test_vsoxseg5_nxv4i8_nxv4i16:
3529 ; CHECK: # %bb.0: # %entry
3530 ; CHECK-NEXT: vmv1r.v v10, v8
3531 ; CHECK-NEXT: vmv1r.v v11, v8
3532 ; CHECK-NEXT: vmv1r.v v12, v8
3533 ; CHECK-NEXT: vmv1r.v v13, v8
3534 ; CHECK-NEXT: vmv1r.v v14, v8
3535 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3536 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
3537 ; CHECK-NEXT: ret
3538 entry:
3539 tail call void @llvm.riscv.vsoxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3540 ret void
3541 }
3543 define void @test_vsoxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3544 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_nxv4i16:
3545 ; CHECK: # %bb.0: # %entry
3546 ; CHECK-NEXT: vmv1r.v v10, v8
3547 ; CHECK-NEXT: vmv1r.v v11, v8
3548 ; CHECK-NEXT: vmv1r.v v12, v8
3549 ; CHECK-NEXT: vmv1r.v v13, v8
3550 ; CHECK-NEXT: vmv1r.v v14, v8
3551 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3552 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
3553 ; CHECK-NEXT: ret
3554 entry:
3555 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3556 ret void
3557 }
3559 declare void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3560 declare void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3562 define void @test_vsoxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3563 ; CHECK-LABEL: test_vsoxseg6_nxv4i8_nxv4i32:
3564 ; CHECK: # %bb.0: # %entry
3565 ; CHECK-NEXT: vmv1r.v v12, v8
3566 ; CHECK-NEXT: vmv1r.v v13, v8
3567 ; CHECK-NEXT: vmv1r.v v14, v8
3568 ; CHECK-NEXT: vmv1r.v v15, v8
3569 ; CHECK-NEXT: vmv1r.v v16, v8
3570 ; CHECK-NEXT: vmv1r.v v17, v8
3571 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3572 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10
3573 ; CHECK-NEXT: ret
3574 entry:
3575 tail call void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3576 ret void
3577 }
3579 define void @test_vsoxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3580 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_nxv4i32:
3581 ; CHECK: # %bb.0: # %entry
3582 ; CHECK-NEXT: vmv1r.v v12, v8
3583 ; CHECK-NEXT: vmv1r.v v13, v8
3584 ; CHECK-NEXT: vmv1r.v v14, v8
3585 ; CHECK-NEXT: vmv1r.v v15, v8
3586 ; CHECK-NEXT: vmv1r.v v16, v8
3587 ; CHECK-NEXT: vmv1r.v v17, v8
3588 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3589 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10, v0.t
3590 ; CHECK-NEXT: ret
3591 entry:
3592 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3593 ret void
3594 }
3596 declare void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3597 declare void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3599 define void @test_vsoxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3600 ; CHECK-LABEL: test_vsoxseg6_nxv4i8_nxv4i8:
3601 ; CHECK: # %bb.0: # %entry
3602 ; CHECK-NEXT: vmv1r.v v10, v8
3603 ; CHECK-NEXT: vmv1r.v v11, v8
3604 ; CHECK-NEXT: vmv1r.v v12, v8
3605 ; CHECK-NEXT: vmv1r.v v13, v8
3606 ; CHECK-NEXT: vmv1r.v v14, v8
3607 ; CHECK-NEXT: vmv1r.v v15, v8
3608 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3609 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
3610 ; CHECK-NEXT: ret
3611 entry:
3612 tail call void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3613 ret void
3614 }
3616 define void @test_vsoxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3617 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_nxv4i8:
3618 ; CHECK: # %bb.0: # %entry
3619 ; CHECK-NEXT: vmv1r.v v10, v8
3620 ; CHECK-NEXT: vmv1r.v v11, v8
3621 ; CHECK-NEXT: vmv1r.v v12, v8
3622 ; CHECK-NEXT: vmv1r.v v13, v8
3623 ; CHECK-NEXT: vmv1r.v v14, v8
3624 ; CHECK-NEXT: vmv1r.v v15, v8
3625 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3626 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
3627 ; CHECK-NEXT: ret
3628 entry:
3629 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3630 ret void
3631 }
3633 declare void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3634 declare void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3636 define void @test_vsoxseg6_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3637 ; CHECK-LABEL: test_vsoxseg6_nxv4i8_nxv4i64:
3638 ; CHECK: # %bb.0: # %entry
3639 ; CHECK-NEXT: vmv1r.v v16, v8
3640 ; CHECK-NEXT: vmv1r.v v17, v8
3641 ; CHECK-NEXT: vmv1r.v v18, v8
3642 ; CHECK-NEXT: vmv1r.v v19, v8
3643 ; CHECK-NEXT: vmv1r.v v20, v8
3644 ; CHECK-NEXT: vmv1r.v v21, v8
3645 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3646 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12
3647 ; CHECK-NEXT: ret
3648 entry:
3649 tail call void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3650 ret void
3651 }
3653 define void @test_vsoxseg6_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3654 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_nxv4i64:
3655 ; CHECK: # %bb.0: # %entry
3656 ; CHECK-NEXT: vmv1r.v v16, v8
3657 ; CHECK-NEXT: vmv1r.v v17, v8
3658 ; CHECK-NEXT: vmv1r.v v18, v8
3659 ; CHECK-NEXT: vmv1r.v v19, v8
3660 ; CHECK-NEXT: vmv1r.v v20, v8
3661 ; CHECK-NEXT: vmv1r.v v21, v8
3662 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3663 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12, v0.t
3664 ; CHECK-NEXT: ret
3665 entry:
3666 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3667 ret void
3668 }
3670 declare void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3671 declare void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3673 define void @test_vsoxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3674 ; CHECK-LABEL: test_vsoxseg6_nxv4i8_nxv4i16:
3675 ; CHECK: # %bb.0: # %entry
3676 ; CHECK-NEXT: vmv1r.v v10, v8
3677 ; CHECK-NEXT: vmv1r.v v11, v8
3678 ; CHECK-NEXT: vmv1r.v v12, v8
3679 ; CHECK-NEXT: vmv1r.v v13, v8
3680 ; CHECK-NEXT: vmv1r.v v14, v8
3681 ; CHECK-NEXT: vmv1r.v v15, v8
3682 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3683 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
3684 ; CHECK-NEXT: ret
3685 entry:
3686 tail call void @llvm.riscv.vsoxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3687 ret void
3688 }
3690 define void @test_vsoxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3691 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_nxv4i16:
3692 ; CHECK: # %bb.0: # %entry
3693 ; CHECK-NEXT: vmv1r.v v10, v8
3694 ; CHECK-NEXT: vmv1r.v v11, v8
3695 ; CHECK-NEXT: vmv1r.v v12, v8
3696 ; CHECK-NEXT: vmv1r.v v13, v8
3697 ; CHECK-NEXT: vmv1r.v v14, v8
3698 ; CHECK-NEXT: vmv1r.v v15, v8
3699 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3700 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
3701 ; CHECK-NEXT: ret
3702 entry:
3703 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3704 ret void
3705 }
3707 declare void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3708 declare void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3710 define void @test_vsoxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3711 ; CHECK-LABEL: test_vsoxseg7_nxv4i8_nxv4i32:
3712 ; CHECK: # %bb.0: # %entry
3713 ; CHECK-NEXT: vmv1r.v v12, v8
3714 ; CHECK-NEXT: vmv1r.v v13, v8
3715 ; CHECK-NEXT: vmv1r.v v14, v8
3716 ; CHECK-NEXT: vmv1r.v v15, v8
3717 ; CHECK-NEXT: vmv1r.v v16, v8
3718 ; CHECK-NEXT: vmv1r.v v17, v8
3719 ; CHECK-NEXT: vmv1r.v v18, v8
3720 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3721 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10
3722 ; CHECK-NEXT: ret
3723 entry:
3724 tail call void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3725 ret void
3726 }
3728 define void @test_vsoxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3729 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_nxv4i32:
3730 ; CHECK: # %bb.0: # %entry
3731 ; CHECK-NEXT: vmv1r.v v12, v8
3732 ; CHECK-NEXT: vmv1r.v v13, v8
3733 ; CHECK-NEXT: vmv1r.v v14, v8
3734 ; CHECK-NEXT: vmv1r.v v15, v8
3735 ; CHECK-NEXT: vmv1r.v v16, v8
3736 ; CHECK-NEXT: vmv1r.v v17, v8
3737 ; CHECK-NEXT: vmv1r.v v18, v8
3738 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3739 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10, v0.t
3740 ; CHECK-NEXT: ret
3741 entry:
3742 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3743 ret void
3744 }
3746 declare void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3747 declare void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3749 define void @test_vsoxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3750 ; CHECK-LABEL: test_vsoxseg7_nxv4i8_nxv4i8:
3751 ; CHECK: # %bb.0: # %entry
3752 ; CHECK-NEXT: vmv1r.v v10, v8
3753 ; CHECK-NEXT: vmv1r.v v11, v8
3754 ; CHECK-NEXT: vmv1r.v v12, v8
3755 ; CHECK-NEXT: vmv1r.v v13, v8
3756 ; CHECK-NEXT: vmv1r.v v14, v8
3757 ; CHECK-NEXT: vmv1r.v v15, v8
3758 ; CHECK-NEXT: vmv1r.v v16, v8
3759 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3760 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
3761 ; CHECK-NEXT: ret
3762 entry:
3763 tail call void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3764 ret void
3765 }
3767 define void @test_vsoxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3768 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_nxv4i8:
3769 ; CHECK: # %bb.0: # %entry
3770 ; CHECK-NEXT: vmv1r.v v10, v8
3771 ; CHECK-NEXT: vmv1r.v v11, v8
3772 ; CHECK-NEXT: vmv1r.v v12, v8
3773 ; CHECK-NEXT: vmv1r.v v13, v8
3774 ; CHECK-NEXT: vmv1r.v v14, v8
3775 ; CHECK-NEXT: vmv1r.v v15, v8
3776 ; CHECK-NEXT: vmv1r.v v16, v8
3777 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3778 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
3779 ; CHECK-NEXT: ret
3780 entry:
3781 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3782 ret void
3783 }
3785 declare void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3786 declare void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3788 define void @test_vsoxseg7_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3789 ; CHECK-LABEL: test_vsoxseg7_nxv4i8_nxv4i64:
3790 ; CHECK: # %bb.0: # %entry
3791 ; CHECK-NEXT: vmv1r.v v16, v8
3792 ; CHECK-NEXT: vmv1r.v v17, v8
3793 ; CHECK-NEXT: vmv1r.v v18, v8
3794 ; CHECK-NEXT: vmv1r.v v19, v8
3795 ; CHECK-NEXT: vmv1r.v v20, v8
3796 ; CHECK-NEXT: vmv1r.v v21, v8
3797 ; CHECK-NEXT: vmv1r.v v22, v8
3798 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3799 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12
3800 ; CHECK-NEXT: ret
3801 entry:
3802 tail call void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3803 ret void
3804 }
3806 define void @test_vsoxseg7_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3807 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_nxv4i64:
3808 ; CHECK: # %bb.0: # %entry
3809 ; CHECK-NEXT: vmv1r.v v16, v8
3810 ; CHECK-NEXT: vmv1r.v v17, v8
3811 ; CHECK-NEXT: vmv1r.v v18, v8
3812 ; CHECK-NEXT: vmv1r.v v19, v8
3813 ; CHECK-NEXT: vmv1r.v v20, v8
3814 ; CHECK-NEXT: vmv1r.v v21, v8
3815 ; CHECK-NEXT: vmv1r.v v22, v8
3816 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3817 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12, v0.t
3818 ; CHECK-NEXT: ret
3819 entry:
3820 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3821 ret void
3822 }
3824 declare void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3825 declare void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3827 define void @test_vsoxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3828 ; CHECK-LABEL: test_vsoxseg7_nxv4i8_nxv4i16:
3829 ; CHECK: # %bb.0: # %entry
3830 ; CHECK-NEXT: vmv1r.v v10, v8
3831 ; CHECK-NEXT: vmv1r.v v11, v8
3832 ; CHECK-NEXT: vmv1r.v v12, v8
3833 ; CHECK-NEXT: vmv1r.v v13, v8
3834 ; CHECK-NEXT: vmv1r.v v14, v8
3835 ; CHECK-NEXT: vmv1r.v v15, v8
3836 ; CHECK-NEXT: vmv1r.v v16, v8
3837 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3838 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
3839 ; CHECK-NEXT: ret
3840 entry:
3841 tail call void @llvm.riscv.vsoxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
3842 ret void
3843 }
3845 define void @test_vsoxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3846 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_nxv4i16:
3847 ; CHECK: # %bb.0: # %entry
3848 ; CHECK-NEXT: vmv1r.v v10, v8
3849 ; CHECK-NEXT: vmv1r.v v11, v8
3850 ; CHECK-NEXT: vmv1r.v v12, v8
3851 ; CHECK-NEXT: vmv1r.v v13, v8
3852 ; CHECK-NEXT: vmv1r.v v14, v8
3853 ; CHECK-NEXT: vmv1r.v v15, v8
3854 ; CHECK-NEXT: vmv1r.v v16, v8
3855 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3856 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
3857 ; CHECK-NEXT: ret
3858 entry:
3859 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
3860 ret void
3861 }
3863 declare void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, i64)
3864 declare void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
3866 define void @test_vsoxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
3867 ; CHECK-LABEL: test_vsoxseg8_nxv4i8_nxv4i32:
3868 ; CHECK: # %bb.0: # %entry
3869 ; CHECK-NEXT: vmv1r.v v12, v8
3870 ; CHECK-NEXT: vmv1r.v v13, v8
3871 ; CHECK-NEXT: vmv1r.v v14, v8
3872 ; CHECK-NEXT: vmv1r.v v15, v8
3873 ; CHECK-NEXT: vmv1r.v v16, v8
3874 ; CHECK-NEXT: vmv1r.v v17, v8
3875 ; CHECK-NEXT: vmv1r.v v18, v8
3876 ; CHECK-NEXT: vmv1r.v v19, v8
3877 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3878 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10
3879 ; CHECK-NEXT: ret
3880 entry:
3881 tail call void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
3882 ret void
3883 }
3885 define void @test_vsoxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3886 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_nxv4i32:
3887 ; CHECK: # %bb.0: # %entry
3888 ; CHECK-NEXT: vmv1r.v v12, v8
3889 ; CHECK-NEXT: vmv1r.v v13, v8
3890 ; CHECK-NEXT: vmv1r.v v14, v8
3891 ; CHECK-NEXT: vmv1r.v v15, v8
3892 ; CHECK-NEXT: vmv1r.v v16, v8
3893 ; CHECK-NEXT: vmv1r.v v17, v8
3894 ; CHECK-NEXT: vmv1r.v v18, v8
3895 ; CHECK-NEXT: vmv1r.v v19, v8
3896 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3897 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10, v0.t
3898 ; CHECK-NEXT: ret
3899 entry:
3900 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
3901 ret void
3902 }
3904 declare void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, i64)
3905 declare void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
3907 define void @test_vsoxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
3908 ; CHECK-LABEL: test_vsoxseg8_nxv4i8_nxv4i8:
3909 ; CHECK: # %bb.0: # %entry
3910 ; CHECK-NEXT: vmv1r.v v10, v8
3911 ; CHECK-NEXT: vmv1r.v v11, v8
3912 ; CHECK-NEXT: vmv1r.v v12, v8
3913 ; CHECK-NEXT: vmv1r.v v13, v8
3914 ; CHECK-NEXT: vmv1r.v v14, v8
3915 ; CHECK-NEXT: vmv1r.v v15, v8
3916 ; CHECK-NEXT: vmv1r.v v16, v8
3917 ; CHECK-NEXT: vmv1r.v v17, v8
3918 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3919 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
3920 ; CHECK-NEXT: ret
3921 entry:
3922 tail call void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
3923 ret void
3924 }
3926 define void @test_vsoxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3927 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_nxv4i8:
3928 ; CHECK: # %bb.0: # %entry
3929 ; CHECK-NEXT: vmv1r.v v10, v8
3930 ; CHECK-NEXT: vmv1r.v v11, v8
3931 ; CHECK-NEXT: vmv1r.v v12, v8
3932 ; CHECK-NEXT: vmv1r.v v13, v8
3933 ; CHECK-NEXT: vmv1r.v v14, v8
3934 ; CHECK-NEXT: vmv1r.v v15, v8
3935 ; CHECK-NEXT: vmv1r.v v16, v8
3936 ; CHECK-NEXT: vmv1r.v v17, v8
3937 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3938 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
3939 ; CHECK-NEXT: ret
3940 entry:
3941 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
3942 ret void
3943 }
3945 declare void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, i64)
3946 declare void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
3948 define void @test_vsoxseg8_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
3949 ; CHECK-LABEL: test_vsoxseg8_nxv4i8_nxv4i64:
3950 ; CHECK: # %bb.0: # %entry
3951 ; CHECK-NEXT: vmv1r.v v16, v8
3952 ; CHECK-NEXT: vmv1r.v v17, v8
3953 ; CHECK-NEXT: vmv1r.v v18, v8
3954 ; CHECK-NEXT: vmv1r.v v19, v8
3955 ; CHECK-NEXT: vmv1r.v v20, v8
3956 ; CHECK-NEXT: vmv1r.v v21, v8
3957 ; CHECK-NEXT: vmv1r.v v22, v8
3958 ; CHECK-NEXT: vmv1r.v v23, v8
3959 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3960 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12
3961 ; CHECK-NEXT: ret
3962 entry:
3963 tail call void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
3964 ret void
3965 }
3967 define void @test_vsoxseg8_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
3968 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_nxv4i64:
3969 ; CHECK: # %bb.0: # %entry
3970 ; CHECK-NEXT: vmv1r.v v16, v8
3971 ; CHECK-NEXT: vmv1r.v v17, v8
3972 ; CHECK-NEXT: vmv1r.v v18, v8
3973 ; CHECK-NEXT: vmv1r.v v19, v8
3974 ; CHECK-NEXT: vmv1r.v v20, v8
3975 ; CHECK-NEXT: vmv1r.v v21, v8
3976 ; CHECK-NEXT: vmv1r.v v22, v8
3977 ; CHECK-NEXT: vmv1r.v v23, v8
3978 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
3979 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12, v0.t
3980 ; CHECK-NEXT: ret
3981 entry:
3982 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
3983 ret void
3984 }
3986 declare void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, i64)
3987 declare void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
3989 define void @test_vsoxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
3990 ; CHECK-LABEL: test_vsoxseg8_nxv4i8_nxv4i16:
3991 ; CHECK: # %bb.0: # %entry
3992 ; CHECK-NEXT: vmv1r.v v10, v8
3993 ; CHECK-NEXT: vmv1r.v v11, v8
3994 ; CHECK-NEXT: vmv1r.v v12, v8
3995 ; CHECK-NEXT: vmv1r.v v13, v8
3996 ; CHECK-NEXT: vmv1r.v v14, v8
3997 ; CHECK-NEXT: vmv1r.v v15, v8
3998 ; CHECK-NEXT: vmv1r.v v16, v8
3999 ; CHECK-NEXT: vmv1r.v v17, v8
4000 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
4001 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
4002 ; CHECK-NEXT: ret
4003 entry:
4004 tail call void @llvm.riscv.vsoxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
4005 ret void
4006 }
4008 define void @test_vsoxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
4009 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_nxv4i16:
4010 ; CHECK: # %bb.0: # %entry
4011 ; CHECK-NEXT: vmv1r.v v10, v8
4012 ; CHECK-NEXT: vmv1r.v v11, v8
4013 ; CHECK-NEXT: vmv1r.v v12, v8
4014 ; CHECK-NEXT: vmv1r.v v13, v8
4015 ; CHECK-NEXT: vmv1r.v v14, v8
4016 ; CHECK-NEXT: vmv1r.v v15, v8
4017 ; CHECK-NEXT: vmv1r.v v16, v8
4018 ; CHECK-NEXT: vmv1r.v v17, v8
4019 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
4020 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
4021 ; CHECK-NEXT: ret
4022 entry:
4023 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
4024 ret void
4025 }
4027 declare void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4028 declare void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4030 define void @test_vsoxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4031 ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i64:
4032 ; CHECK: # %bb.0: # %entry
4033 ; CHECK-NEXT: vmv1r.v v10, v9
4034 ; CHECK-NEXT: vmv1r.v v9, v8
4035 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4036 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
4037 ; CHECK-NEXT: ret
4038 entry:
4039 tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4040 ret void
4041 }
4043 define void @test_vsoxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4044 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i64:
4045 ; CHECK: # %bb.0: # %entry
4046 ; CHECK-NEXT: vmv1r.v v10, v9
4047 ; CHECK-NEXT: vmv1r.v v9, v8
4048 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4049 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
4050 ; CHECK-NEXT: ret
4051 entry:
4052 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4053 ret void
4054 }
4056 declare void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4057 declare void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4059 define void @test_vsoxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4060 ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i32:
4061 ; CHECK: # %bb.0: # %entry
4062 ; CHECK-NEXT: vmv1r.v v10, v9
4063 ; CHECK-NEXT: vmv1r.v v9, v8
4064 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4065 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
4066 ; CHECK-NEXT: ret
4067 entry:
4068 tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4069 ret void
4070 }
4072 define void @test_vsoxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4073 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i32:
4074 ; CHECK: # %bb.0: # %entry
4075 ; CHECK-NEXT: vmv1r.v v10, v9
4076 ; CHECK-NEXT: vmv1r.v v9, v8
4077 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4078 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
4079 ; CHECK-NEXT: ret
4080 entry:
4081 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4082 ret void
4083 }
4085 declare void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4086 declare void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4088 define void @test_vsoxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4089 ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i16:
4090 ; CHECK: # %bb.0: # %entry
4091 ; CHECK-NEXT: vmv1r.v v10, v9
4092 ; CHECK-NEXT: vmv1r.v v9, v8
4093 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4094 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
4095 ; CHECK-NEXT: ret
4096 entry:
4097 tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4098 ret void
4099 }
4101 define void @test_vsoxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4102 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i16:
4103 ; CHECK: # %bb.0: # %entry
4104 ; CHECK-NEXT: vmv1r.v v10, v9
4105 ; CHECK-NEXT: vmv1r.v v9, v8
4106 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4107 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
4108 ; CHECK-NEXT: ret
4109 entry:
4110 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4111 ret void
4112 }
4114 declare void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4115 declare void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4117 define void @test_vsoxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4118 ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i8:
4119 ; CHECK: # %bb.0: # %entry
4120 ; CHECK-NEXT: vmv1r.v v10, v9
4121 ; CHECK-NEXT: vmv1r.v v9, v8
4122 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4123 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
4124 ; CHECK-NEXT: ret
4125 entry:
4126 tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4127 ret void
4128 }
4130 define void @test_vsoxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4131 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i8:
4132 ; CHECK: # %bb.0: # %entry
4133 ; CHECK-NEXT: vmv1r.v v10, v9
4134 ; CHECK-NEXT: vmv1r.v v9, v8
4135 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4136 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
4137 ; CHECK-NEXT: ret
4138 entry:
4139 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4140 ret void
4141 }
4143 declare void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4144 declare void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4146 define void @test_vsoxseg3_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4147 ; CHECK-LABEL: test_vsoxseg3_nxv1i16_nxv1i64:
4148 ; CHECK: # %bb.0: # %entry
4149 ; CHECK-NEXT: vmv1r.v v10, v8
4150 ; CHECK-NEXT: vmv1r.v v11, v8
4151 ; CHECK-NEXT: vmv1r.v v12, v8
4152 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4153 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
4154 ; CHECK-NEXT: ret
4155 entry:
4156 tail call void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4157 ret void
4158 }
4160 define void @test_vsoxseg3_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4161 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_nxv1i64:
4162 ; CHECK: # %bb.0: # %entry
4163 ; CHECK-NEXT: vmv1r.v v10, v8
4164 ; CHECK-NEXT: vmv1r.v v11, v8
4165 ; CHECK-NEXT: vmv1r.v v12, v8
4166 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4167 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
4168 ; CHECK-NEXT: ret
4169 entry:
4170 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4171 ret void
4172 }
4174 declare void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4175 declare void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4177 define void @test_vsoxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4178 ; CHECK-LABEL: test_vsoxseg3_nxv1i16_nxv1i32:
4179 ; CHECK: # %bb.0: # %entry
4180 ; CHECK-NEXT: vmv1r.v v10, v8
4181 ; CHECK-NEXT: vmv1r.v v11, v8
4182 ; CHECK-NEXT: vmv1r.v v12, v8
4183 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4184 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
4185 ; CHECK-NEXT: ret
4186 entry:
4187 tail call void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4188 ret void
4189 }
4191 define void @test_vsoxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4192 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_nxv1i32:
4193 ; CHECK: # %bb.0: # %entry
4194 ; CHECK-NEXT: vmv1r.v v10, v8
4195 ; CHECK-NEXT: vmv1r.v v11, v8
4196 ; CHECK-NEXT: vmv1r.v v12, v8
4197 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4198 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
4199 ; CHECK-NEXT: ret
4200 entry:
4201 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4202 ret void
4203 }
4205 declare void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4206 declare void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4208 define void @test_vsoxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4209 ; CHECK-LABEL: test_vsoxseg3_nxv1i16_nxv1i16:
4210 ; CHECK: # %bb.0: # %entry
4211 ; CHECK-NEXT: vmv1r.v v10, v8
4212 ; CHECK-NEXT: vmv1r.v v11, v8
4213 ; CHECK-NEXT: vmv1r.v v12, v8
4214 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4215 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
4216 ; CHECK-NEXT: ret
4217 entry:
4218 tail call void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4219 ret void
4220 }
4222 define void @test_vsoxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4223 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_nxv1i16:
4224 ; CHECK: # %bb.0: # %entry
4225 ; CHECK-NEXT: vmv1r.v v10, v8
4226 ; CHECK-NEXT: vmv1r.v v11, v8
4227 ; CHECK-NEXT: vmv1r.v v12, v8
4228 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4229 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
4230 ; CHECK-NEXT: ret
4231 entry:
4232 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4233 ret void
4234 }
4236 declare void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4237 declare void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4239 define void @test_vsoxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4240 ; CHECK-LABEL: test_vsoxseg3_nxv1i16_nxv1i8:
4241 ; CHECK: # %bb.0: # %entry
4242 ; CHECK-NEXT: vmv1r.v v10, v8
4243 ; CHECK-NEXT: vmv1r.v v11, v8
4244 ; CHECK-NEXT: vmv1r.v v12, v8
4245 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4246 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
4247 ; CHECK-NEXT: ret
4248 entry:
4249 tail call void @llvm.riscv.vsoxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4250 ret void
4251 }
4253 define void @test_vsoxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4254 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_nxv1i8:
4255 ; CHECK: # %bb.0: # %entry
4256 ; CHECK-NEXT: vmv1r.v v10, v8
4257 ; CHECK-NEXT: vmv1r.v v11, v8
4258 ; CHECK-NEXT: vmv1r.v v12, v8
4259 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4260 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
4261 ; CHECK-NEXT: ret
4262 entry:
4263 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4264 ret void
4265 }
4267 declare void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4268 declare void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4270 define void @test_vsoxseg4_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4271 ; CHECK-LABEL: test_vsoxseg4_nxv1i16_nxv1i64:
4272 ; CHECK: # %bb.0: # %entry
4273 ; CHECK-NEXT: vmv1r.v v10, v8
4274 ; CHECK-NEXT: vmv1r.v v11, v8
4275 ; CHECK-NEXT: vmv1r.v v12, v8
4276 ; CHECK-NEXT: vmv1r.v v13, v8
4277 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4278 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
4279 ; CHECK-NEXT: ret
4280 entry:
4281 tail call void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4282 ret void
4283 }
4285 define void @test_vsoxseg4_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4286 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_nxv1i64:
4287 ; CHECK: # %bb.0: # %entry
4288 ; CHECK-NEXT: vmv1r.v v10, v8
4289 ; CHECK-NEXT: vmv1r.v v11, v8
4290 ; CHECK-NEXT: vmv1r.v v12, v8
4291 ; CHECK-NEXT: vmv1r.v v13, v8
4292 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4293 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
4294 ; CHECK-NEXT: ret
4295 entry:
4296 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4297 ret void
4298 }
4300 declare void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4301 declare void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4303 define void @test_vsoxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4304 ; CHECK-LABEL: test_vsoxseg4_nxv1i16_nxv1i32:
4305 ; CHECK: # %bb.0: # %entry
4306 ; CHECK-NEXT: vmv1r.v v10, v8
4307 ; CHECK-NEXT: vmv1r.v v11, v8
4308 ; CHECK-NEXT: vmv1r.v v12, v8
4309 ; CHECK-NEXT: vmv1r.v v13, v8
4310 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4311 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
4312 ; CHECK-NEXT: ret
4313 entry:
4314 tail call void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4315 ret void
4316 }
4318 define void @test_vsoxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4319 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_nxv1i32:
4320 ; CHECK: # %bb.0: # %entry
4321 ; CHECK-NEXT: vmv1r.v v10, v8
4322 ; CHECK-NEXT: vmv1r.v v11, v8
4323 ; CHECK-NEXT: vmv1r.v v12, v8
4324 ; CHECK-NEXT: vmv1r.v v13, v8
4325 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4326 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
4327 ; CHECK-NEXT: ret
4328 entry:
4329 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4330 ret void
4331 }
4333 declare void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4334 declare void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4336 define void @test_vsoxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4337 ; CHECK-LABEL: test_vsoxseg4_nxv1i16_nxv1i16:
4338 ; CHECK: # %bb.0: # %entry
4339 ; CHECK-NEXT: vmv1r.v v10, v8
4340 ; CHECK-NEXT: vmv1r.v v11, v8
4341 ; CHECK-NEXT: vmv1r.v v12, v8
4342 ; CHECK-NEXT: vmv1r.v v13, v8
4343 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4344 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
4345 ; CHECK-NEXT: ret
4346 entry:
4347 tail call void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4348 ret void
4349 }
4351 define void @test_vsoxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4352 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_nxv1i16:
4353 ; CHECK: # %bb.0: # %entry
4354 ; CHECK-NEXT: vmv1r.v v10, v8
4355 ; CHECK-NEXT: vmv1r.v v11, v8
4356 ; CHECK-NEXT: vmv1r.v v12, v8
4357 ; CHECK-NEXT: vmv1r.v v13, v8
4358 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4359 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
4360 ; CHECK-NEXT: ret
4361 entry:
4362 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4363 ret void
4364 }
4366 declare void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4367 declare void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4369 define void @test_vsoxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4370 ; CHECK-LABEL: test_vsoxseg4_nxv1i16_nxv1i8:
4371 ; CHECK: # %bb.0: # %entry
4372 ; CHECK-NEXT: vmv1r.v v10, v8
4373 ; CHECK-NEXT: vmv1r.v v11, v8
4374 ; CHECK-NEXT: vmv1r.v v12, v8
4375 ; CHECK-NEXT: vmv1r.v v13, v8
4376 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4377 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
4378 ; CHECK-NEXT: ret
4379 entry:
4380 tail call void @llvm.riscv.vsoxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4381 ret void
4382 }
4384 define void @test_vsoxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4385 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_nxv1i8:
4386 ; CHECK: # %bb.0: # %entry
4387 ; CHECK-NEXT: vmv1r.v v10, v8
4388 ; CHECK-NEXT: vmv1r.v v11, v8
4389 ; CHECK-NEXT: vmv1r.v v12, v8
4390 ; CHECK-NEXT: vmv1r.v v13, v8
4391 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4392 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
4393 ; CHECK-NEXT: ret
4394 entry:
4395 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4396 ret void
4397 }
4399 declare void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4400 declare void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4402 define void @test_vsoxseg5_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4403 ; CHECK-LABEL: test_vsoxseg5_nxv1i16_nxv1i64:
4404 ; CHECK: # %bb.0: # %entry
4405 ; CHECK-NEXT: vmv1r.v v10, v8
4406 ; CHECK-NEXT: vmv1r.v v11, v8
4407 ; CHECK-NEXT: vmv1r.v v12, v8
4408 ; CHECK-NEXT: vmv1r.v v13, v8
4409 ; CHECK-NEXT: vmv1r.v v14, v8
4410 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4411 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
4412 ; CHECK-NEXT: ret
4413 entry:
4414 tail call void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4415 ret void
4416 }
4418 define void @test_vsoxseg5_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4419 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_nxv1i64:
4420 ; CHECK: # %bb.0: # %entry
4421 ; CHECK-NEXT: vmv1r.v v10, v8
4422 ; CHECK-NEXT: vmv1r.v v11, v8
4423 ; CHECK-NEXT: vmv1r.v v12, v8
4424 ; CHECK-NEXT: vmv1r.v v13, v8
4425 ; CHECK-NEXT: vmv1r.v v14, v8
4426 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4427 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
4428 ; CHECK-NEXT: ret
4429 entry:
4430 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4431 ret void
4432 }
4434 declare void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4435 declare void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4437 define void @test_vsoxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4438 ; CHECK-LABEL: test_vsoxseg5_nxv1i16_nxv1i32:
4439 ; CHECK: # %bb.0: # %entry
4440 ; CHECK-NEXT: vmv1r.v v10, v8
4441 ; CHECK-NEXT: vmv1r.v v11, v8
4442 ; CHECK-NEXT: vmv1r.v v12, v8
4443 ; CHECK-NEXT: vmv1r.v v13, v8
4444 ; CHECK-NEXT: vmv1r.v v14, v8
4445 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4446 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
4447 ; CHECK-NEXT: ret
4448 entry:
4449 tail call void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4450 ret void
4451 }
4453 define void @test_vsoxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4454 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_nxv1i32:
4455 ; CHECK: # %bb.0: # %entry
4456 ; CHECK-NEXT: vmv1r.v v10, v8
4457 ; CHECK-NEXT: vmv1r.v v11, v8
4458 ; CHECK-NEXT: vmv1r.v v12, v8
4459 ; CHECK-NEXT: vmv1r.v v13, v8
4460 ; CHECK-NEXT: vmv1r.v v14, v8
4461 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4462 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
4463 ; CHECK-NEXT: ret
4464 entry:
4465 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4466 ret void
4467 }
4469 declare void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4470 declare void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4472 define void @test_vsoxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4473 ; CHECK-LABEL: test_vsoxseg5_nxv1i16_nxv1i16:
4474 ; CHECK: # %bb.0: # %entry
4475 ; CHECK-NEXT: vmv1r.v v10, v8
4476 ; CHECK-NEXT: vmv1r.v v11, v8
4477 ; CHECK-NEXT: vmv1r.v v12, v8
4478 ; CHECK-NEXT: vmv1r.v v13, v8
4479 ; CHECK-NEXT: vmv1r.v v14, v8
4480 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4481 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
4482 ; CHECK-NEXT: ret
4483 entry:
4484 tail call void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4485 ret void
4486 }
4488 define void @test_vsoxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4489 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_nxv1i16:
4490 ; CHECK: # %bb.0: # %entry
4491 ; CHECK-NEXT: vmv1r.v v10, v8
4492 ; CHECK-NEXT: vmv1r.v v11, v8
4493 ; CHECK-NEXT: vmv1r.v v12, v8
4494 ; CHECK-NEXT: vmv1r.v v13, v8
4495 ; CHECK-NEXT: vmv1r.v v14, v8
4496 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4497 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
4498 ; CHECK-NEXT: ret
4499 entry:
4500 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4501 ret void
4502 }
4504 declare void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4505 declare void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4507 define void @test_vsoxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4508 ; CHECK-LABEL: test_vsoxseg5_nxv1i16_nxv1i8:
4509 ; CHECK: # %bb.0: # %entry
4510 ; CHECK-NEXT: vmv1r.v v10, v8
4511 ; CHECK-NEXT: vmv1r.v v11, v8
4512 ; CHECK-NEXT: vmv1r.v v12, v8
4513 ; CHECK-NEXT: vmv1r.v v13, v8
4514 ; CHECK-NEXT: vmv1r.v v14, v8
4515 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4516 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
4517 ; CHECK-NEXT: ret
4518 entry:
4519 tail call void @llvm.riscv.vsoxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4520 ret void
4521 }
4523 define void @test_vsoxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4524 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_nxv1i8:
4525 ; CHECK: # %bb.0: # %entry
4526 ; CHECK-NEXT: vmv1r.v v10, v8
4527 ; CHECK-NEXT: vmv1r.v v11, v8
4528 ; CHECK-NEXT: vmv1r.v v12, v8
4529 ; CHECK-NEXT: vmv1r.v v13, v8
4530 ; CHECK-NEXT: vmv1r.v v14, v8
4531 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4532 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
4533 ; CHECK-NEXT: ret
4534 entry:
4535 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4536 ret void
4537 }
4539 declare void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4540 declare void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4542 define void @test_vsoxseg6_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4543 ; CHECK-LABEL: test_vsoxseg6_nxv1i16_nxv1i64:
4544 ; CHECK: # %bb.0: # %entry
4545 ; CHECK-NEXT: vmv1r.v v10, v8
4546 ; CHECK-NEXT: vmv1r.v v11, v8
4547 ; CHECK-NEXT: vmv1r.v v12, v8
4548 ; CHECK-NEXT: vmv1r.v v13, v8
4549 ; CHECK-NEXT: vmv1r.v v14, v8
4550 ; CHECK-NEXT: vmv1r.v v15, v8
4551 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4552 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
4553 ; CHECK-NEXT: ret
4554 entry:
4555 tail call void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4556 ret void
4557 }
4559 define void @test_vsoxseg6_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4560 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_nxv1i64:
4561 ; CHECK: # %bb.0: # %entry
4562 ; CHECK-NEXT: vmv1r.v v10, v8
4563 ; CHECK-NEXT: vmv1r.v v11, v8
4564 ; CHECK-NEXT: vmv1r.v v12, v8
4565 ; CHECK-NEXT: vmv1r.v v13, v8
4566 ; CHECK-NEXT: vmv1r.v v14, v8
4567 ; CHECK-NEXT: vmv1r.v v15, v8
4568 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4569 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
4570 ; CHECK-NEXT: ret
4571 entry:
4572 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4573 ret void
4574 }
4576 declare void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4577 declare void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4579 define void @test_vsoxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4580 ; CHECK-LABEL: test_vsoxseg6_nxv1i16_nxv1i32:
4581 ; CHECK: # %bb.0: # %entry
4582 ; CHECK-NEXT: vmv1r.v v10, v8
4583 ; CHECK-NEXT: vmv1r.v v11, v8
4584 ; CHECK-NEXT: vmv1r.v v12, v8
4585 ; CHECK-NEXT: vmv1r.v v13, v8
4586 ; CHECK-NEXT: vmv1r.v v14, v8
4587 ; CHECK-NEXT: vmv1r.v v15, v8
4588 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4589 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
4590 ; CHECK-NEXT: ret
4591 entry:
4592 tail call void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4593 ret void
4594 }
4596 define void @test_vsoxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4597 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_nxv1i32:
4598 ; CHECK: # %bb.0: # %entry
4599 ; CHECK-NEXT: vmv1r.v v10, v8
4600 ; CHECK-NEXT: vmv1r.v v11, v8
4601 ; CHECK-NEXT: vmv1r.v v12, v8
4602 ; CHECK-NEXT: vmv1r.v v13, v8
4603 ; CHECK-NEXT: vmv1r.v v14, v8
4604 ; CHECK-NEXT: vmv1r.v v15, v8
4605 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4606 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
4607 ; CHECK-NEXT: ret
4608 entry:
4609 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4610 ret void
4611 }
4613 declare void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4614 declare void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4616 define void @test_vsoxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4617 ; CHECK-LABEL: test_vsoxseg6_nxv1i16_nxv1i16:
4618 ; CHECK: # %bb.0: # %entry
4619 ; CHECK-NEXT: vmv1r.v v10, v8
4620 ; CHECK-NEXT: vmv1r.v v11, v8
4621 ; CHECK-NEXT: vmv1r.v v12, v8
4622 ; CHECK-NEXT: vmv1r.v v13, v8
4623 ; CHECK-NEXT: vmv1r.v v14, v8
4624 ; CHECK-NEXT: vmv1r.v v15, v8
4625 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4626 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
4627 ; CHECK-NEXT: ret
4628 entry:
4629 tail call void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4630 ret void
4631 }
4633 define void @test_vsoxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4634 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_nxv1i16:
4635 ; CHECK: # %bb.0: # %entry
4636 ; CHECK-NEXT: vmv1r.v v10, v8
4637 ; CHECK-NEXT: vmv1r.v v11, v8
4638 ; CHECK-NEXT: vmv1r.v v12, v8
4639 ; CHECK-NEXT: vmv1r.v v13, v8
4640 ; CHECK-NEXT: vmv1r.v v14, v8
4641 ; CHECK-NEXT: vmv1r.v v15, v8
4642 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4643 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
4644 ; CHECK-NEXT: ret
4645 entry:
4646 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4647 ret void
4648 }
4650 declare void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4651 declare void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4653 define void @test_vsoxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4654 ; CHECK-LABEL: test_vsoxseg6_nxv1i16_nxv1i8:
4655 ; CHECK: # %bb.0: # %entry
4656 ; CHECK-NEXT: vmv1r.v v10, v8
4657 ; CHECK-NEXT: vmv1r.v v11, v8
4658 ; CHECK-NEXT: vmv1r.v v12, v8
4659 ; CHECK-NEXT: vmv1r.v v13, v8
4660 ; CHECK-NEXT: vmv1r.v v14, v8
4661 ; CHECK-NEXT: vmv1r.v v15, v8
4662 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4663 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
4664 ; CHECK-NEXT: ret
4665 entry:
4666 tail call void @llvm.riscv.vsoxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4667 ret void
4668 }
4670 define void @test_vsoxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4671 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_nxv1i8:
4672 ; CHECK: # %bb.0: # %entry
4673 ; CHECK-NEXT: vmv1r.v v10, v8
4674 ; CHECK-NEXT: vmv1r.v v11, v8
4675 ; CHECK-NEXT: vmv1r.v v12, v8
4676 ; CHECK-NEXT: vmv1r.v v13, v8
4677 ; CHECK-NEXT: vmv1r.v v14, v8
4678 ; CHECK-NEXT: vmv1r.v v15, v8
4679 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4680 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
4681 ; CHECK-NEXT: ret
4682 entry:
4683 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4684 ret void
4685 }
4687 declare void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4688 declare void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4690 define void @test_vsoxseg7_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4691 ; CHECK-LABEL: test_vsoxseg7_nxv1i16_nxv1i64:
4692 ; CHECK: # %bb.0: # %entry
4693 ; CHECK-NEXT: vmv1r.v v10, v8
4694 ; CHECK-NEXT: vmv1r.v v11, v8
4695 ; CHECK-NEXT: vmv1r.v v12, v8
4696 ; CHECK-NEXT: vmv1r.v v13, v8
4697 ; CHECK-NEXT: vmv1r.v v14, v8
4698 ; CHECK-NEXT: vmv1r.v v15, v8
4699 ; CHECK-NEXT: vmv1r.v v16, v8
4700 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4701 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
4702 ; CHECK-NEXT: ret
4703 entry:
4704 tail call void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4705 ret void
4706 }
4708 define void @test_vsoxseg7_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4709 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_nxv1i64:
4710 ; CHECK: # %bb.0: # %entry
4711 ; CHECK-NEXT: vmv1r.v v10, v8
4712 ; CHECK-NEXT: vmv1r.v v11, v8
4713 ; CHECK-NEXT: vmv1r.v v12, v8
4714 ; CHECK-NEXT: vmv1r.v v13, v8
4715 ; CHECK-NEXT: vmv1r.v v14, v8
4716 ; CHECK-NEXT: vmv1r.v v15, v8
4717 ; CHECK-NEXT: vmv1r.v v16, v8
4718 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4719 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
4720 ; CHECK-NEXT: ret
4721 entry:
4722 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4723 ret void
4724 }
4726 declare void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4727 declare void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4729 define void @test_vsoxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4730 ; CHECK-LABEL: test_vsoxseg7_nxv1i16_nxv1i32:
4731 ; CHECK: # %bb.0: # %entry
4732 ; CHECK-NEXT: vmv1r.v v10, v8
4733 ; CHECK-NEXT: vmv1r.v v11, v8
4734 ; CHECK-NEXT: vmv1r.v v12, v8
4735 ; CHECK-NEXT: vmv1r.v v13, v8
4736 ; CHECK-NEXT: vmv1r.v v14, v8
4737 ; CHECK-NEXT: vmv1r.v v15, v8
4738 ; CHECK-NEXT: vmv1r.v v16, v8
4739 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4740 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
4741 ; CHECK-NEXT: ret
4742 entry:
4743 tail call void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4744 ret void
4745 }
4747 define void @test_vsoxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4748 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_nxv1i32:
4749 ; CHECK: # %bb.0: # %entry
4750 ; CHECK-NEXT: vmv1r.v v10, v8
4751 ; CHECK-NEXT: vmv1r.v v11, v8
4752 ; CHECK-NEXT: vmv1r.v v12, v8
4753 ; CHECK-NEXT: vmv1r.v v13, v8
4754 ; CHECK-NEXT: vmv1r.v v14, v8
4755 ; CHECK-NEXT: vmv1r.v v15, v8
4756 ; CHECK-NEXT: vmv1r.v v16, v8
4757 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4758 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
4759 ; CHECK-NEXT: ret
4760 entry:
4761 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4762 ret void
4763 }
4765 declare void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4766 declare void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4768 define void @test_vsoxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4769 ; CHECK-LABEL: test_vsoxseg7_nxv1i16_nxv1i16:
4770 ; CHECK: # %bb.0: # %entry
4771 ; CHECK-NEXT: vmv1r.v v10, v8
4772 ; CHECK-NEXT: vmv1r.v v11, v8
4773 ; CHECK-NEXT: vmv1r.v v12, v8
4774 ; CHECK-NEXT: vmv1r.v v13, v8
4775 ; CHECK-NEXT: vmv1r.v v14, v8
4776 ; CHECK-NEXT: vmv1r.v v15, v8
4777 ; CHECK-NEXT: vmv1r.v v16, v8
4778 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4779 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
4780 ; CHECK-NEXT: ret
4781 entry:
4782 tail call void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4783 ret void
4784 }
4786 define void @test_vsoxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4787 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_nxv1i16:
4788 ; CHECK: # %bb.0: # %entry
4789 ; CHECK-NEXT: vmv1r.v v10, v8
4790 ; CHECK-NEXT: vmv1r.v v11, v8
4791 ; CHECK-NEXT: vmv1r.v v12, v8
4792 ; CHECK-NEXT: vmv1r.v v13, v8
4793 ; CHECK-NEXT: vmv1r.v v14, v8
4794 ; CHECK-NEXT: vmv1r.v v15, v8
4795 ; CHECK-NEXT: vmv1r.v v16, v8
4796 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4797 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
4798 ; CHECK-NEXT: ret
4799 entry:
4800 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4801 ret void
4802 }
4804 declare void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4805 declare void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4807 define void @test_vsoxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4808 ; CHECK-LABEL: test_vsoxseg7_nxv1i16_nxv1i8:
4809 ; CHECK: # %bb.0: # %entry
4810 ; CHECK-NEXT: vmv1r.v v10, v8
4811 ; CHECK-NEXT: vmv1r.v v11, v8
4812 ; CHECK-NEXT: vmv1r.v v12, v8
4813 ; CHECK-NEXT: vmv1r.v v13, v8
4814 ; CHECK-NEXT: vmv1r.v v14, v8
4815 ; CHECK-NEXT: vmv1r.v v15, v8
4816 ; CHECK-NEXT: vmv1r.v v16, v8
4817 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4818 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
4819 ; CHECK-NEXT: ret
4820 entry:
4821 tail call void @llvm.riscv.vsoxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4822 ret void
4823 }
4825 define void @test_vsoxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4826 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_nxv1i8:
4827 ; CHECK: # %bb.0: # %entry
4828 ; CHECK-NEXT: vmv1r.v v10, v8
4829 ; CHECK-NEXT: vmv1r.v v11, v8
4830 ; CHECK-NEXT: vmv1r.v v12, v8
4831 ; CHECK-NEXT: vmv1r.v v13, v8
4832 ; CHECK-NEXT: vmv1r.v v14, v8
4833 ; CHECK-NEXT: vmv1r.v v15, v8
4834 ; CHECK-NEXT: vmv1r.v v16, v8
4835 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4836 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
4837 ; CHECK-NEXT: ret
4838 entry:
4839 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
4840 ret void
4841 }
4843 declare void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, i64)
4844 declare void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
4846 define void @test_vsoxseg8_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
4847 ; CHECK-LABEL: test_vsoxseg8_nxv1i16_nxv1i64:
4848 ; CHECK: # %bb.0: # %entry
4849 ; CHECK-NEXT: vmv1r.v v10, v8
4850 ; CHECK-NEXT: vmv1r.v v11, v8
4851 ; CHECK-NEXT: vmv1r.v v12, v8
4852 ; CHECK-NEXT: vmv1r.v v13, v8
4853 ; CHECK-NEXT: vmv1r.v v14, v8
4854 ; CHECK-NEXT: vmv1r.v v15, v8
4855 ; CHECK-NEXT: vmv1r.v v16, v8
4856 ; CHECK-NEXT: vmv1r.v v17, v8
4857 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4858 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
4859 ; CHECK-NEXT: ret
4860 entry:
4861 tail call void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
4862 ret void
4863 }
4865 define void @test_vsoxseg8_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4866 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_nxv1i64:
4867 ; CHECK: # %bb.0: # %entry
4868 ; CHECK-NEXT: vmv1r.v v10, v8
4869 ; CHECK-NEXT: vmv1r.v v11, v8
4870 ; CHECK-NEXT: vmv1r.v v12, v8
4871 ; CHECK-NEXT: vmv1r.v v13, v8
4872 ; CHECK-NEXT: vmv1r.v v14, v8
4873 ; CHECK-NEXT: vmv1r.v v15, v8
4874 ; CHECK-NEXT: vmv1r.v v16, v8
4875 ; CHECK-NEXT: vmv1r.v v17, v8
4876 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4877 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
4878 ; CHECK-NEXT: ret
4879 entry:
4880 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
4881 ret void
4882 }
4884 declare void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, i64)
4885 declare void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
4887 define void @test_vsoxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
4888 ; CHECK-LABEL: test_vsoxseg8_nxv1i16_nxv1i32:
4889 ; CHECK: # %bb.0: # %entry
4890 ; CHECK-NEXT: vmv1r.v v10, v8
4891 ; CHECK-NEXT: vmv1r.v v11, v8
4892 ; CHECK-NEXT: vmv1r.v v12, v8
4893 ; CHECK-NEXT: vmv1r.v v13, v8
4894 ; CHECK-NEXT: vmv1r.v v14, v8
4895 ; CHECK-NEXT: vmv1r.v v15, v8
4896 ; CHECK-NEXT: vmv1r.v v16, v8
4897 ; CHECK-NEXT: vmv1r.v v17, v8
4898 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4899 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
4900 ; CHECK-NEXT: ret
4901 entry:
4902 tail call void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
4903 ret void
4904 }
4906 define void @test_vsoxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4907 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_nxv1i32:
4908 ; CHECK: # %bb.0: # %entry
4909 ; CHECK-NEXT: vmv1r.v v10, v8
4910 ; CHECK-NEXT: vmv1r.v v11, v8
4911 ; CHECK-NEXT: vmv1r.v v12, v8
4912 ; CHECK-NEXT: vmv1r.v v13, v8
4913 ; CHECK-NEXT: vmv1r.v v14, v8
4914 ; CHECK-NEXT: vmv1r.v v15, v8
4915 ; CHECK-NEXT: vmv1r.v v16, v8
4916 ; CHECK-NEXT: vmv1r.v v17, v8
4917 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4918 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
4919 ; CHECK-NEXT: ret
4920 entry:
4921 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
4922 ret void
4923 }
4925 declare void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, i64)
4926 declare void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
4928 define void @test_vsoxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
4929 ; CHECK-LABEL: test_vsoxseg8_nxv1i16_nxv1i16:
4930 ; CHECK: # %bb.0: # %entry
4931 ; CHECK-NEXT: vmv1r.v v10, v8
4932 ; CHECK-NEXT: vmv1r.v v11, v8
4933 ; CHECK-NEXT: vmv1r.v v12, v8
4934 ; CHECK-NEXT: vmv1r.v v13, v8
4935 ; CHECK-NEXT: vmv1r.v v14, v8
4936 ; CHECK-NEXT: vmv1r.v v15, v8
4937 ; CHECK-NEXT: vmv1r.v v16, v8
4938 ; CHECK-NEXT: vmv1r.v v17, v8
4939 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4940 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
4941 ; CHECK-NEXT: ret
4942 entry:
4943 tail call void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
4944 ret void
4945 }
4947 define void @test_vsoxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4948 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_nxv1i16:
4949 ; CHECK: # %bb.0: # %entry
4950 ; CHECK-NEXT: vmv1r.v v10, v8
4951 ; CHECK-NEXT: vmv1r.v v11, v8
4952 ; CHECK-NEXT: vmv1r.v v12, v8
4953 ; CHECK-NEXT: vmv1r.v v13, v8
4954 ; CHECK-NEXT: vmv1r.v v14, v8
4955 ; CHECK-NEXT: vmv1r.v v15, v8
4956 ; CHECK-NEXT: vmv1r.v v16, v8
4957 ; CHECK-NEXT: vmv1r.v v17, v8
4958 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4959 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
4960 ; CHECK-NEXT: ret
4961 entry:
4962 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
4963 ret void
4964 }
4966 declare void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, i64)
4967 declare void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
4969 define void @test_vsoxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
4970 ; CHECK-LABEL: test_vsoxseg8_nxv1i16_nxv1i8:
4971 ; CHECK: # %bb.0: # %entry
4972 ; CHECK-NEXT: vmv1r.v v10, v8
4973 ; CHECK-NEXT: vmv1r.v v11, v8
4974 ; CHECK-NEXT: vmv1r.v v12, v8
4975 ; CHECK-NEXT: vmv1r.v v13, v8
4976 ; CHECK-NEXT: vmv1r.v v14, v8
4977 ; CHECK-NEXT: vmv1r.v v15, v8
4978 ; CHECK-NEXT: vmv1r.v v16, v8
4979 ; CHECK-NEXT: vmv1r.v v17, v8
4980 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
4981 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
4982 ; CHECK-NEXT: ret
4983 entry:
4984 tail call void @llvm.riscv.vsoxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
4985 ret void
4986 }
4988 define void @test_vsoxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
4989 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_nxv1i8:
4990 ; CHECK: # %bb.0: # %entry
4991 ; CHECK-NEXT: vmv1r.v v10, v8
4992 ; CHECK-NEXT: vmv1r.v v11, v8
4993 ; CHECK-NEXT: vmv1r.v v12, v8
4994 ; CHECK-NEXT: vmv1r.v v13, v8
4995 ; CHECK-NEXT: vmv1r.v v14, v8
4996 ; CHECK-NEXT: vmv1r.v v15, v8
4997 ; CHECK-NEXT: vmv1r.v v16, v8
4998 ; CHECK-NEXT: vmv1r.v v17, v8
4999 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
5000 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
5001 ; CHECK-NEXT: ret
5002 entry:
5003 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
5004 ret void
5005 }
5007 declare void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5008 declare void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5010 define void @test_vsoxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5011 ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i32:
5012 ; CHECK: # %bb.0: # %entry
5013 ; CHECK-NEXT: vmv1r.v v10, v9
5014 ; CHECK-NEXT: vmv1r.v v9, v8
5015 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5016 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
5017 ; CHECK-NEXT: ret
5018 entry:
5019 tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5020 ret void
5021 }
5023 define void @test_vsoxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5024 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i32:
5025 ; CHECK: # %bb.0: # %entry
5026 ; CHECK-NEXT: vmv1r.v v10, v9
5027 ; CHECK-NEXT: vmv1r.v v9, v8
5028 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5029 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
5030 ; CHECK-NEXT: ret
5031 entry:
5032 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5033 ret void
5034 }
5036 declare void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5037 declare void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5039 define void @test_vsoxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5040 ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i8:
5041 ; CHECK: # %bb.0: # %entry
5042 ; CHECK-NEXT: vmv1r.v v10, v9
5043 ; CHECK-NEXT: vmv1r.v v9, v8
5044 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5045 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
5046 ; CHECK-NEXT: ret
5047 entry:
5048 tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5049 ret void
5050 }
5052 define void @test_vsoxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5053 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i8:
5054 ; CHECK: # %bb.0: # %entry
5055 ; CHECK-NEXT: vmv1r.v v10, v9
5056 ; CHECK-NEXT: vmv1r.v v9, v8
5057 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5058 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
5059 ; CHECK-NEXT: ret
5060 entry:
5061 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5062 ret void
5063 }
5065 declare void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5066 declare void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5068 define void @test_vsoxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5069 ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i16:
5070 ; CHECK: # %bb.0: # %entry
5071 ; CHECK-NEXT: vmv1r.v v10, v9
5072 ; CHECK-NEXT: vmv1r.v v9, v8
5073 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5074 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
5075 ; CHECK-NEXT: ret
5076 entry:
5077 tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5078 ret void
5079 }
5081 define void @test_vsoxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5082 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i16:
5083 ; CHECK: # %bb.0: # %entry
5084 ; CHECK-NEXT: vmv1r.v v10, v9
5085 ; CHECK-NEXT: vmv1r.v v9, v8
5086 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5087 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
5088 ; CHECK-NEXT: ret
5089 entry:
5090 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5091 ret void
5092 }
5094 declare void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5095 declare void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5097 define void @test_vsoxseg2_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5098 ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i64:
5099 ; CHECK: # %bb.0: # %entry
5100 ; CHECK-NEXT: vmv1r.v v9, v8
5101 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5102 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
5103 ; CHECK-NEXT: ret
5104 entry:
5105 tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5106 ret void
5107 }
5109 define void @test_vsoxseg2_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5110 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i64:
5111 ; CHECK: # %bb.0: # %entry
5112 ; CHECK-NEXT: vmv1r.v v9, v8
5113 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5114 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
5115 ; CHECK-NEXT: ret
5116 entry:
5117 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5118 ret void
5119 }
5121 declare void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5122 declare void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5124 define void @test_vsoxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5125 ; CHECK-LABEL: test_vsoxseg3_nxv2i32_nxv2i32:
5126 ; CHECK: # %bb.0: # %entry
5127 ; CHECK-NEXT: vmv1r.v v10, v8
5128 ; CHECK-NEXT: vmv1r.v v11, v8
5129 ; CHECK-NEXT: vmv1r.v v12, v8
5130 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5131 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
5132 ; CHECK-NEXT: ret
5133 entry:
5134 tail call void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5135 ret void
5136 }
5138 define void @test_vsoxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5139 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_nxv2i32:
5140 ; CHECK: # %bb.0: # %entry
5141 ; CHECK-NEXT: vmv1r.v v10, v8
5142 ; CHECK-NEXT: vmv1r.v v11, v8
5143 ; CHECK-NEXT: vmv1r.v v12, v8
5144 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5145 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
5146 ; CHECK-NEXT: ret
5147 entry:
5148 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5149 ret void
5150 }
5152 declare void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5153 declare void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5155 define void @test_vsoxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5156 ; CHECK-LABEL: test_vsoxseg3_nxv2i32_nxv2i8:
5157 ; CHECK: # %bb.0: # %entry
5158 ; CHECK-NEXT: vmv1r.v v10, v8
5159 ; CHECK-NEXT: vmv1r.v v11, v8
5160 ; CHECK-NEXT: vmv1r.v v12, v8
5161 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5162 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
5163 ; CHECK-NEXT: ret
5164 entry:
5165 tail call void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5166 ret void
5167 }
5169 define void @test_vsoxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5170 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_nxv2i8:
5171 ; CHECK: # %bb.0: # %entry
5172 ; CHECK-NEXT: vmv1r.v v10, v8
5173 ; CHECK-NEXT: vmv1r.v v11, v8
5174 ; CHECK-NEXT: vmv1r.v v12, v8
5175 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5176 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
5177 ; CHECK-NEXT: ret
5178 entry:
5179 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5180 ret void
5181 }
5183 declare void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5184 declare void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5186 define void @test_vsoxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5187 ; CHECK-LABEL: test_vsoxseg3_nxv2i32_nxv2i16:
5188 ; CHECK: # %bb.0: # %entry
5189 ; CHECK-NEXT: vmv1r.v v10, v8
5190 ; CHECK-NEXT: vmv1r.v v11, v8
5191 ; CHECK-NEXT: vmv1r.v v12, v8
5192 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5193 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
5194 ; CHECK-NEXT: ret
5195 entry:
5196 tail call void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5197 ret void
5198 }
5200 define void @test_vsoxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5201 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_nxv2i16:
5202 ; CHECK: # %bb.0: # %entry
5203 ; CHECK-NEXT: vmv1r.v v10, v8
5204 ; CHECK-NEXT: vmv1r.v v11, v8
5205 ; CHECK-NEXT: vmv1r.v v12, v8
5206 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5207 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
5208 ; CHECK-NEXT: ret
5209 entry:
5210 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5211 ret void
5212 }
5214 declare void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5215 declare void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5217 define void @test_vsoxseg3_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5218 ; CHECK-LABEL: test_vsoxseg3_nxv2i32_nxv2i64:
5219 ; CHECK: # %bb.0: # %entry
5220 ; CHECK-NEXT: vmv1r.v v9, v8
5221 ; CHECK-NEXT: vmv2r.v v12, v10
5222 ; CHECK-NEXT: vmv1r.v v10, v8
5223 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5224 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
5225 ; CHECK-NEXT: ret
5226 entry:
5227 tail call void @llvm.riscv.vsoxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5228 ret void
5229 }
5231 define void @test_vsoxseg3_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5232 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_nxv2i64:
5233 ; CHECK: # %bb.0: # %entry
5234 ; CHECK-NEXT: vmv1r.v v9, v8
5235 ; CHECK-NEXT: vmv2r.v v12, v10
5236 ; CHECK-NEXT: vmv1r.v v10, v8
5237 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5238 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
5239 ; CHECK-NEXT: ret
5240 entry:
5241 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5242 ret void
5243 }
5245 declare void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5246 declare void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5248 define void @test_vsoxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5249 ; CHECK-LABEL: test_vsoxseg4_nxv2i32_nxv2i32:
5250 ; CHECK: # %bb.0: # %entry
5251 ; CHECK-NEXT: vmv1r.v v10, v8
5252 ; CHECK-NEXT: vmv1r.v v11, v8
5253 ; CHECK-NEXT: vmv1r.v v12, v8
5254 ; CHECK-NEXT: vmv1r.v v13, v8
5255 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5256 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
5257 ; CHECK-NEXT: ret
5258 entry:
5259 tail call void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5260 ret void
5261 }
5263 define void @test_vsoxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5264 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_nxv2i32:
5265 ; CHECK: # %bb.0: # %entry
5266 ; CHECK-NEXT: vmv1r.v v10, v8
5267 ; CHECK-NEXT: vmv1r.v v11, v8
5268 ; CHECK-NEXT: vmv1r.v v12, v8
5269 ; CHECK-NEXT: vmv1r.v v13, v8
5270 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5271 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
5272 ; CHECK-NEXT: ret
5273 entry:
5274 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5275 ret void
5276 }
5278 declare void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5279 declare void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5281 define void @test_vsoxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5282 ; CHECK-LABEL: test_vsoxseg4_nxv2i32_nxv2i8:
5283 ; CHECK: # %bb.0: # %entry
5284 ; CHECK-NEXT: vmv1r.v v10, v8
5285 ; CHECK-NEXT: vmv1r.v v11, v8
5286 ; CHECK-NEXT: vmv1r.v v12, v8
5287 ; CHECK-NEXT: vmv1r.v v13, v8
5288 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5289 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
5290 ; CHECK-NEXT: ret
5291 entry:
5292 tail call void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5293 ret void
5294 }
5296 define void @test_vsoxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5297 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_nxv2i8:
5298 ; CHECK: # %bb.0: # %entry
5299 ; CHECK-NEXT: vmv1r.v v10, v8
5300 ; CHECK-NEXT: vmv1r.v v11, v8
5301 ; CHECK-NEXT: vmv1r.v v12, v8
5302 ; CHECK-NEXT: vmv1r.v v13, v8
5303 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5304 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
5305 ; CHECK-NEXT: ret
5306 entry:
5307 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5308 ret void
5309 }
5311 declare void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5312 declare void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5314 define void @test_vsoxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5315 ; CHECK-LABEL: test_vsoxseg4_nxv2i32_nxv2i16:
5316 ; CHECK: # %bb.0: # %entry
5317 ; CHECK-NEXT: vmv1r.v v10, v8
5318 ; CHECK-NEXT: vmv1r.v v11, v8
5319 ; CHECK-NEXT: vmv1r.v v12, v8
5320 ; CHECK-NEXT: vmv1r.v v13, v8
5321 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5322 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
5323 ; CHECK-NEXT: ret
5324 entry:
5325 tail call void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5326 ret void
5327 }
5329 define void @test_vsoxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5330 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_nxv2i16:
5331 ; CHECK: # %bb.0: # %entry
5332 ; CHECK-NEXT: vmv1r.v v10, v8
5333 ; CHECK-NEXT: vmv1r.v v11, v8
5334 ; CHECK-NEXT: vmv1r.v v12, v8
5335 ; CHECK-NEXT: vmv1r.v v13, v8
5336 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5337 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
5338 ; CHECK-NEXT: ret
5339 entry:
5340 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5341 ret void
5342 }
5344 declare void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5345 declare void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5347 define void @test_vsoxseg4_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5348 ; CHECK-LABEL: test_vsoxseg4_nxv2i32_nxv2i64:
5349 ; CHECK: # %bb.0: # %entry
5350 ; CHECK-NEXT: vmv1r.v v12, v8
5351 ; CHECK-NEXT: vmv1r.v v13, v8
5352 ; CHECK-NEXT: vmv1r.v v14, v8
5353 ; CHECK-NEXT: vmv1r.v v15, v8
5354 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5355 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
5356 ; CHECK-NEXT: ret
5357 entry:
5358 tail call void @llvm.riscv.vsoxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5359 ret void
5360 }
5362 define void @test_vsoxseg4_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5363 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_nxv2i64:
5364 ; CHECK: # %bb.0: # %entry
5365 ; CHECK-NEXT: vmv1r.v v12, v8
5366 ; CHECK-NEXT: vmv1r.v v13, v8
5367 ; CHECK-NEXT: vmv1r.v v14, v8
5368 ; CHECK-NEXT: vmv1r.v v15, v8
5369 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5370 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
5371 ; CHECK-NEXT: ret
5372 entry:
5373 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5374 ret void
5375 }
5377 declare void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5378 declare void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5380 define void @test_vsoxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5381 ; CHECK-LABEL: test_vsoxseg5_nxv2i32_nxv2i32:
5382 ; CHECK: # %bb.0: # %entry
5383 ; CHECK-NEXT: vmv1r.v v10, v8
5384 ; CHECK-NEXT: vmv1r.v v11, v8
5385 ; CHECK-NEXT: vmv1r.v v12, v8
5386 ; CHECK-NEXT: vmv1r.v v13, v8
5387 ; CHECK-NEXT: vmv1r.v v14, v8
5388 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5389 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
5390 ; CHECK-NEXT: ret
5391 entry:
5392 tail call void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5393 ret void
5394 }
5396 define void @test_vsoxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5397 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_nxv2i32:
5398 ; CHECK: # %bb.0: # %entry
5399 ; CHECK-NEXT: vmv1r.v v10, v8
5400 ; CHECK-NEXT: vmv1r.v v11, v8
5401 ; CHECK-NEXT: vmv1r.v v12, v8
5402 ; CHECK-NEXT: vmv1r.v v13, v8
5403 ; CHECK-NEXT: vmv1r.v v14, v8
5404 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5405 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
5406 ; CHECK-NEXT: ret
5407 entry:
5408 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5409 ret void
5410 }
5412 declare void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5413 declare void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5415 define void @test_vsoxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5416 ; CHECK-LABEL: test_vsoxseg5_nxv2i32_nxv2i8:
5417 ; CHECK: # %bb.0: # %entry
5418 ; CHECK-NEXT: vmv1r.v v10, v8
5419 ; CHECK-NEXT: vmv1r.v v11, v8
5420 ; CHECK-NEXT: vmv1r.v v12, v8
5421 ; CHECK-NEXT: vmv1r.v v13, v8
5422 ; CHECK-NEXT: vmv1r.v v14, v8
5423 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5424 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
5425 ; CHECK-NEXT: ret
5426 entry:
5427 tail call void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5428 ret void
5429 }
5431 define void @test_vsoxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5432 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_nxv2i8:
5433 ; CHECK: # %bb.0: # %entry
5434 ; CHECK-NEXT: vmv1r.v v10, v8
5435 ; CHECK-NEXT: vmv1r.v v11, v8
5436 ; CHECK-NEXT: vmv1r.v v12, v8
5437 ; CHECK-NEXT: vmv1r.v v13, v8
5438 ; CHECK-NEXT: vmv1r.v v14, v8
5439 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5440 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
5441 ; CHECK-NEXT: ret
5442 entry:
5443 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5444 ret void
5445 }
5447 declare void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5448 declare void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5450 define void @test_vsoxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5451 ; CHECK-LABEL: test_vsoxseg5_nxv2i32_nxv2i16:
5452 ; CHECK: # %bb.0: # %entry
5453 ; CHECK-NEXT: vmv1r.v v10, v8
5454 ; CHECK-NEXT: vmv1r.v v11, v8
5455 ; CHECK-NEXT: vmv1r.v v12, v8
5456 ; CHECK-NEXT: vmv1r.v v13, v8
5457 ; CHECK-NEXT: vmv1r.v v14, v8
5458 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5459 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
5460 ; CHECK-NEXT: ret
5461 entry:
5462 tail call void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5463 ret void
5464 }
5466 define void @test_vsoxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5467 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_nxv2i16:
5468 ; CHECK: # %bb.0: # %entry
5469 ; CHECK-NEXT: vmv1r.v v10, v8
5470 ; CHECK-NEXT: vmv1r.v v11, v8
5471 ; CHECK-NEXT: vmv1r.v v12, v8
5472 ; CHECK-NEXT: vmv1r.v v13, v8
5473 ; CHECK-NEXT: vmv1r.v v14, v8
5474 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5475 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
5476 ; CHECK-NEXT: ret
5477 entry:
5478 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5479 ret void
5480 }
5482 declare void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5483 declare void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5485 define void @test_vsoxseg5_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5486 ; CHECK-LABEL: test_vsoxseg5_nxv2i32_nxv2i64:
5487 ; CHECK: # %bb.0: # %entry
5488 ; CHECK-NEXT: vmv1r.v v12, v8
5489 ; CHECK-NEXT: vmv1r.v v13, v8
5490 ; CHECK-NEXT: vmv1r.v v14, v8
5491 ; CHECK-NEXT: vmv1r.v v15, v8
5492 ; CHECK-NEXT: vmv1r.v v16, v8
5493 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5494 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10
5495 ; CHECK-NEXT: ret
5496 entry:
5497 tail call void @llvm.riscv.vsoxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5498 ret void
5499 }
5501 define void @test_vsoxseg5_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5502 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_nxv2i64:
5503 ; CHECK: # %bb.0: # %entry
5504 ; CHECK-NEXT: vmv1r.v v12, v8
5505 ; CHECK-NEXT: vmv1r.v v13, v8
5506 ; CHECK-NEXT: vmv1r.v v14, v8
5507 ; CHECK-NEXT: vmv1r.v v15, v8
5508 ; CHECK-NEXT: vmv1r.v v16, v8
5509 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5510 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10, v0.t
5511 ; CHECK-NEXT: ret
5512 entry:
5513 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5514 ret void
5515 }
5517 declare void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5518 declare void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5520 define void @test_vsoxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5521 ; CHECK-LABEL: test_vsoxseg6_nxv2i32_nxv2i32:
5522 ; CHECK: # %bb.0: # %entry
5523 ; CHECK-NEXT: vmv1r.v v10, v8
5524 ; CHECK-NEXT: vmv1r.v v11, v8
5525 ; CHECK-NEXT: vmv1r.v v12, v8
5526 ; CHECK-NEXT: vmv1r.v v13, v8
5527 ; CHECK-NEXT: vmv1r.v v14, v8
5528 ; CHECK-NEXT: vmv1r.v v15, v8
5529 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5530 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
5531 ; CHECK-NEXT: ret
5532 entry:
5533 tail call void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5534 ret void
5535 }
5537 define void @test_vsoxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5538 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_nxv2i32:
5539 ; CHECK: # %bb.0: # %entry
5540 ; CHECK-NEXT: vmv1r.v v10, v8
5541 ; CHECK-NEXT: vmv1r.v v11, v8
5542 ; CHECK-NEXT: vmv1r.v v12, v8
5543 ; CHECK-NEXT: vmv1r.v v13, v8
5544 ; CHECK-NEXT: vmv1r.v v14, v8
5545 ; CHECK-NEXT: vmv1r.v v15, v8
5546 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5547 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
5548 ; CHECK-NEXT: ret
5549 entry:
5550 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5551 ret void
5552 }
5554 declare void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5555 declare void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5557 define void @test_vsoxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5558 ; CHECK-LABEL: test_vsoxseg6_nxv2i32_nxv2i8:
5559 ; CHECK: # %bb.0: # %entry
5560 ; CHECK-NEXT: vmv1r.v v10, v8
5561 ; CHECK-NEXT: vmv1r.v v11, v8
5562 ; CHECK-NEXT: vmv1r.v v12, v8
5563 ; CHECK-NEXT: vmv1r.v v13, v8
5564 ; CHECK-NEXT: vmv1r.v v14, v8
5565 ; CHECK-NEXT: vmv1r.v v15, v8
5566 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5567 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
5568 ; CHECK-NEXT: ret
5569 entry:
5570 tail call void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5571 ret void
5572 }
5574 define void @test_vsoxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5575 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_nxv2i8:
5576 ; CHECK: # %bb.0: # %entry
5577 ; CHECK-NEXT: vmv1r.v v10, v8
5578 ; CHECK-NEXT: vmv1r.v v11, v8
5579 ; CHECK-NEXT: vmv1r.v v12, v8
5580 ; CHECK-NEXT: vmv1r.v v13, v8
5581 ; CHECK-NEXT: vmv1r.v v14, v8
5582 ; CHECK-NEXT: vmv1r.v v15, v8
5583 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5584 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
5585 ; CHECK-NEXT: ret
5586 entry:
5587 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5588 ret void
5589 }
5591 declare void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5592 declare void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5594 define void @test_vsoxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5595 ; CHECK-LABEL: test_vsoxseg6_nxv2i32_nxv2i16:
5596 ; CHECK: # %bb.0: # %entry
5597 ; CHECK-NEXT: vmv1r.v v10, v8
5598 ; CHECK-NEXT: vmv1r.v v11, v8
5599 ; CHECK-NEXT: vmv1r.v v12, v8
5600 ; CHECK-NEXT: vmv1r.v v13, v8
5601 ; CHECK-NEXT: vmv1r.v v14, v8
5602 ; CHECK-NEXT: vmv1r.v v15, v8
5603 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5604 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
5605 ; CHECK-NEXT: ret
5606 entry:
5607 tail call void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5608 ret void
5609 }
5611 define void @test_vsoxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5612 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_nxv2i16:
5613 ; CHECK: # %bb.0: # %entry
5614 ; CHECK-NEXT: vmv1r.v v10, v8
5615 ; CHECK-NEXT: vmv1r.v v11, v8
5616 ; CHECK-NEXT: vmv1r.v v12, v8
5617 ; CHECK-NEXT: vmv1r.v v13, v8
5618 ; CHECK-NEXT: vmv1r.v v14, v8
5619 ; CHECK-NEXT: vmv1r.v v15, v8
5620 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5621 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
5622 ; CHECK-NEXT: ret
5623 entry:
5624 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5625 ret void
5626 }
5628 declare void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5629 declare void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5631 define void @test_vsoxseg6_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5632 ; CHECK-LABEL: test_vsoxseg6_nxv2i32_nxv2i64:
5633 ; CHECK: # %bb.0: # %entry
5634 ; CHECK-NEXT: vmv1r.v v12, v8
5635 ; CHECK-NEXT: vmv1r.v v13, v8
5636 ; CHECK-NEXT: vmv1r.v v14, v8
5637 ; CHECK-NEXT: vmv1r.v v15, v8
5638 ; CHECK-NEXT: vmv1r.v v16, v8
5639 ; CHECK-NEXT: vmv1r.v v17, v8
5640 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5641 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10
5642 ; CHECK-NEXT: ret
5643 entry:
5644 tail call void @llvm.riscv.vsoxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5645 ret void
5646 }
5648 define void @test_vsoxseg6_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5649 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_nxv2i64:
5650 ; CHECK: # %bb.0: # %entry
5651 ; CHECK-NEXT: vmv1r.v v12, v8
5652 ; CHECK-NEXT: vmv1r.v v13, v8
5653 ; CHECK-NEXT: vmv1r.v v14, v8
5654 ; CHECK-NEXT: vmv1r.v v15, v8
5655 ; CHECK-NEXT: vmv1r.v v16, v8
5656 ; CHECK-NEXT: vmv1r.v v17, v8
5657 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5658 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10, v0.t
5659 ; CHECK-NEXT: ret
5660 entry:
5661 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5662 ret void
5663 }
5665 declare void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5666 declare void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5668 define void @test_vsoxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5669 ; CHECK-LABEL: test_vsoxseg7_nxv2i32_nxv2i32:
5670 ; CHECK: # %bb.0: # %entry
5671 ; CHECK-NEXT: vmv1r.v v10, v8
5672 ; CHECK-NEXT: vmv1r.v v11, v8
5673 ; CHECK-NEXT: vmv1r.v v12, v8
5674 ; CHECK-NEXT: vmv1r.v v13, v8
5675 ; CHECK-NEXT: vmv1r.v v14, v8
5676 ; CHECK-NEXT: vmv1r.v v15, v8
5677 ; CHECK-NEXT: vmv1r.v v16, v8
5678 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5679 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
5680 ; CHECK-NEXT: ret
5681 entry:
5682 tail call void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5683 ret void
5684 }
5686 define void @test_vsoxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5687 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_nxv2i32:
5688 ; CHECK: # %bb.0: # %entry
5689 ; CHECK-NEXT: vmv1r.v v10, v8
5690 ; CHECK-NEXT: vmv1r.v v11, v8
5691 ; CHECK-NEXT: vmv1r.v v12, v8
5692 ; CHECK-NEXT: vmv1r.v v13, v8
5693 ; CHECK-NEXT: vmv1r.v v14, v8
5694 ; CHECK-NEXT: vmv1r.v v15, v8
5695 ; CHECK-NEXT: vmv1r.v v16, v8
5696 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5697 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
5698 ; CHECK-NEXT: ret
5699 entry:
5700 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5701 ret void
5702 }
5704 declare void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5705 declare void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5707 define void @test_vsoxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5708 ; CHECK-LABEL: test_vsoxseg7_nxv2i32_nxv2i8:
5709 ; CHECK: # %bb.0: # %entry
5710 ; CHECK-NEXT: vmv1r.v v10, v8
5711 ; CHECK-NEXT: vmv1r.v v11, v8
5712 ; CHECK-NEXT: vmv1r.v v12, v8
5713 ; CHECK-NEXT: vmv1r.v v13, v8
5714 ; CHECK-NEXT: vmv1r.v v14, v8
5715 ; CHECK-NEXT: vmv1r.v v15, v8
5716 ; CHECK-NEXT: vmv1r.v v16, v8
5717 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5718 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
5719 ; CHECK-NEXT: ret
5720 entry:
5721 tail call void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5722 ret void
5723 }
5725 define void @test_vsoxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5726 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_nxv2i8:
5727 ; CHECK: # %bb.0: # %entry
5728 ; CHECK-NEXT: vmv1r.v v10, v8
5729 ; CHECK-NEXT: vmv1r.v v11, v8
5730 ; CHECK-NEXT: vmv1r.v v12, v8
5731 ; CHECK-NEXT: vmv1r.v v13, v8
5732 ; CHECK-NEXT: vmv1r.v v14, v8
5733 ; CHECK-NEXT: vmv1r.v v15, v8
5734 ; CHECK-NEXT: vmv1r.v v16, v8
5735 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5736 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
5737 ; CHECK-NEXT: ret
5738 entry:
5739 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5740 ret void
5741 }
5743 declare void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5744 declare void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5746 define void @test_vsoxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5747 ; CHECK-LABEL: test_vsoxseg7_nxv2i32_nxv2i16:
5748 ; CHECK: # %bb.0: # %entry
5749 ; CHECK-NEXT: vmv1r.v v10, v8
5750 ; CHECK-NEXT: vmv1r.v v11, v8
5751 ; CHECK-NEXT: vmv1r.v v12, v8
5752 ; CHECK-NEXT: vmv1r.v v13, v8
5753 ; CHECK-NEXT: vmv1r.v v14, v8
5754 ; CHECK-NEXT: vmv1r.v v15, v8
5755 ; CHECK-NEXT: vmv1r.v v16, v8
5756 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5757 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
5758 ; CHECK-NEXT: ret
5759 entry:
5760 tail call void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5761 ret void
5762 }
5764 define void @test_vsoxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5765 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_nxv2i16:
5766 ; CHECK: # %bb.0: # %entry
5767 ; CHECK-NEXT: vmv1r.v v10, v8
5768 ; CHECK-NEXT: vmv1r.v v11, v8
5769 ; CHECK-NEXT: vmv1r.v v12, v8
5770 ; CHECK-NEXT: vmv1r.v v13, v8
5771 ; CHECK-NEXT: vmv1r.v v14, v8
5772 ; CHECK-NEXT: vmv1r.v v15, v8
5773 ; CHECK-NEXT: vmv1r.v v16, v8
5774 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5775 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
5776 ; CHECK-NEXT: ret
5777 entry:
5778 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5779 ret void
5780 }
5782 declare void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5783 declare void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5785 define void @test_vsoxseg7_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5786 ; CHECK-LABEL: test_vsoxseg7_nxv2i32_nxv2i64:
5787 ; CHECK: # %bb.0: # %entry
5788 ; CHECK-NEXT: vmv1r.v v12, v8
5789 ; CHECK-NEXT: vmv1r.v v13, v8
5790 ; CHECK-NEXT: vmv1r.v v14, v8
5791 ; CHECK-NEXT: vmv1r.v v15, v8
5792 ; CHECK-NEXT: vmv1r.v v16, v8
5793 ; CHECK-NEXT: vmv1r.v v17, v8
5794 ; CHECK-NEXT: vmv1r.v v18, v8
5795 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5796 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10
5797 ; CHECK-NEXT: ret
5798 entry:
5799 tail call void @llvm.riscv.vsoxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5800 ret void
5801 }
5803 define void @test_vsoxseg7_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5804 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_nxv2i64:
5805 ; CHECK: # %bb.0: # %entry
5806 ; CHECK-NEXT: vmv1r.v v12, v8
5807 ; CHECK-NEXT: vmv1r.v v13, v8
5808 ; CHECK-NEXT: vmv1r.v v14, v8
5809 ; CHECK-NEXT: vmv1r.v v15, v8
5810 ; CHECK-NEXT: vmv1r.v v16, v8
5811 ; CHECK-NEXT: vmv1r.v v17, v8
5812 ; CHECK-NEXT: vmv1r.v v18, v8
5813 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5814 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10, v0.t
5815 ; CHECK-NEXT: ret
5816 entry:
5817 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5818 ret void
5819 }
5821 declare void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, i64)
5822 declare void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
5824 define void @test_vsoxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
5825 ; CHECK-LABEL: test_vsoxseg8_nxv2i32_nxv2i32:
5826 ; CHECK: # %bb.0: # %entry
5827 ; CHECK-NEXT: vmv1r.v v10, v8
5828 ; CHECK-NEXT: vmv1r.v v11, v8
5829 ; CHECK-NEXT: vmv1r.v v12, v8
5830 ; CHECK-NEXT: vmv1r.v v13, v8
5831 ; CHECK-NEXT: vmv1r.v v14, v8
5832 ; CHECK-NEXT: vmv1r.v v15, v8
5833 ; CHECK-NEXT: vmv1r.v v16, v8
5834 ; CHECK-NEXT: vmv1r.v v17, v8
5835 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5836 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
5837 ; CHECK-NEXT: ret
5838 entry:
5839 tail call void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
5840 ret void
5841 }
5843 define void @test_vsoxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5844 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_nxv2i32:
5845 ; CHECK: # %bb.0: # %entry
5846 ; CHECK-NEXT: vmv1r.v v10, v8
5847 ; CHECK-NEXT: vmv1r.v v11, v8
5848 ; CHECK-NEXT: vmv1r.v v12, v8
5849 ; CHECK-NEXT: vmv1r.v v13, v8
5850 ; CHECK-NEXT: vmv1r.v v14, v8
5851 ; CHECK-NEXT: vmv1r.v v15, v8
5852 ; CHECK-NEXT: vmv1r.v v16, v8
5853 ; CHECK-NEXT: vmv1r.v v17, v8
5854 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5855 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
5856 ; CHECK-NEXT: ret
5857 entry:
5858 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
5859 ret void
5860 }
5862 declare void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, i64)
5863 declare void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
5865 define void @test_vsoxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
5866 ; CHECK-LABEL: test_vsoxseg8_nxv2i32_nxv2i8:
5867 ; CHECK: # %bb.0: # %entry
5868 ; CHECK-NEXT: vmv1r.v v10, v8
5869 ; CHECK-NEXT: vmv1r.v v11, v8
5870 ; CHECK-NEXT: vmv1r.v v12, v8
5871 ; CHECK-NEXT: vmv1r.v v13, v8
5872 ; CHECK-NEXT: vmv1r.v v14, v8
5873 ; CHECK-NEXT: vmv1r.v v15, v8
5874 ; CHECK-NEXT: vmv1r.v v16, v8
5875 ; CHECK-NEXT: vmv1r.v v17, v8
5876 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5877 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
5878 ; CHECK-NEXT: ret
5879 entry:
5880 tail call void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
5881 ret void
5882 }
5884 define void @test_vsoxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5885 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_nxv2i8:
5886 ; CHECK: # %bb.0: # %entry
5887 ; CHECK-NEXT: vmv1r.v v10, v8
5888 ; CHECK-NEXT: vmv1r.v v11, v8
5889 ; CHECK-NEXT: vmv1r.v v12, v8
5890 ; CHECK-NEXT: vmv1r.v v13, v8
5891 ; CHECK-NEXT: vmv1r.v v14, v8
5892 ; CHECK-NEXT: vmv1r.v v15, v8
5893 ; CHECK-NEXT: vmv1r.v v16, v8
5894 ; CHECK-NEXT: vmv1r.v v17, v8
5895 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5896 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
5897 ; CHECK-NEXT: ret
5898 entry:
5899 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
5900 ret void
5901 }
5903 declare void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, i64)
5904 declare void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
5906 define void @test_vsoxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
5907 ; CHECK-LABEL: test_vsoxseg8_nxv2i32_nxv2i16:
5908 ; CHECK: # %bb.0: # %entry
5909 ; CHECK-NEXT: vmv1r.v v10, v8
5910 ; CHECK-NEXT: vmv1r.v v11, v8
5911 ; CHECK-NEXT: vmv1r.v v12, v8
5912 ; CHECK-NEXT: vmv1r.v v13, v8
5913 ; CHECK-NEXT: vmv1r.v v14, v8
5914 ; CHECK-NEXT: vmv1r.v v15, v8
5915 ; CHECK-NEXT: vmv1r.v v16, v8
5916 ; CHECK-NEXT: vmv1r.v v17, v8
5917 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5918 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
5919 ; CHECK-NEXT: ret
5920 entry:
5921 tail call void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
5922 ret void
5923 }
5925 define void @test_vsoxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5926 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_nxv2i16:
5927 ; CHECK: # %bb.0: # %entry
5928 ; CHECK-NEXT: vmv1r.v v10, v8
5929 ; CHECK-NEXT: vmv1r.v v11, v8
5930 ; CHECK-NEXT: vmv1r.v v12, v8
5931 ; CHECK-NEXT: vmv1r.v v13, v8
5932 ; CHECK-NEXT: vmv1r.v v14, v8
5933 ; CHECK-NEXT: vmv1r.v v15, v8
5934 ; CHECK-NEXT: vmv1r.v v16, v8
5935 ; CHECK-NEXT: vmv1r.v v17, v8
5936 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5937 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
5938 ; CHECK-NEXT: ret
5939 entry:
5940 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
5941 ret void
5942 }
5944 declare void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, i64)
5945 declare void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
5947 define void @test_vsoxseg8_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
5948 ; CHECK-LABEL: test_vsoxseg8_nxv2i32_nxv2i64:
5949 ; CHECK: # %bb.0: # %entry
5950 ; CHECK-NEXT: vmv1r.v v12, v8
5951 ; CHECK-NEXT: vmv1r.v v13, v8
5952 ; CHECK-NEXT: vmv1r.v v14, v8
5953 ; CHECK-NEXT: vmv1r.v v15, v8
5954 ; CHECK-NEXT: vmv1r.v v16, v8
5955 ; CHECK-NEXT: vmv1r.v v17, v8
5956 ; CHECK-NEXT: vmv1r.v v18, v8
5957 ; CHECK-NEXT: vmv1r.v v19, v8
5958 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5959 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10
5960 ; CHECK-NEXT: ret
5961 entry:
5962 tail call void @llvm.riscv.vsoxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
5963 ret void
5964 }
5966 define void @test_vsoxseg8_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
5967 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_nxv2i64:
5968 ; CHECK: # %bb.0: # %entry
5969 ; CHECK-NEXT: vmv1r.v v12, v8
5970 ; CHECK-NEXT: vmv1r.v v13, v8
5971 ; CHECK-NEXT: vmv1r.v v14, v8
5972 ; CHECK-NEXT: vmv1r.v v15, v8
5973 ; CHECK-NEXT: vmv1r.v v16, v8
5974 ; CHECK-NEXT: vmv1r.v v17, v8
5975 ; CHECK-NEXT: vmv1r.v v18, v8
5976 ; CHECK-NEXT: vmv1r.v v19, v8
5977 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
5978 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10, v0.t
5979 ; CHECK-NEXT: ret
5980 entry:
5981 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
5982 ret void
5983 }
5985 declare void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
5986 declare void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
5988 define void @test_vsoxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
5989 ; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i16:
5990 ; CHECK: # %bb.0: # %entry
5991 ; CHECK-NEXT: vmv1r.v v9, v8
5992 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
5993 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
5994 ; CHECK-NEXT: ret
5995 entry:
5996 tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
5997 ret void
5998 }
6000 define void @test_vsoxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6001 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i16:
6002 ; CHECK: # %bb.0: # %entry
6003 ; CHECK-NEXT: vmv1r.v v9, v8
6004 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6005 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
6006 ; CHECK-NEXT: ret
6007 entry:
6008 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6009 ret void
6010 }
6012 declare void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6013 declare void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6015 define void @test_vsoxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6016 ; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i8:
6017 ; CHECK: # %bb.0: # %entry
6018 ; CHECK-NEXT: vmv1r.v v10, v9
6019 ; CHECK-NEXT: vmv1r.v v9, v8
6020 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6021 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
6022 ; CHECK-NEXT: ret
6023 entry:
6024 tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6025 ret void
6026 }
6028 define void @test_vsoxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6029 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i8:
6030 ; CHECK: # %bb.0: # %entry
6031 ; CHECK-NEXT: vmv1r.v v10, v9
6032 ; CHECK-NEXT: vmv1r.v v9, v8
6033 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6034 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
6035 ; CHECK-NEXT: ret
6036 entry:
6037 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6038 ret void
6039 }
6041 declare void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6042 declare void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6044 define void @test_vsoxseg2_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6045 ; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i64:
6046 ; CHECK: # %bb.0: # %entry
6047 ; CHECK-NEXT: vmv1r.v v9, v8
6048 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6049 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
6050 ; CHECK-NEXT: ret
6051 entry:
6052 tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6053 ret void
6054 }
6056 define void @test_vsoxseg2_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6057 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i64:
6058 ; CHECK: # %bb.0: # %entry
6059 ; CHECK-NEXT: vmv1r.v v9, v8
6060 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6061 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
6062 ; CHECK-NEXT: ret
6063 entry:
6064 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6065 ret void
6066 }
6068 declare void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6069 declare void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6071 define void @test_vsoxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6072 ; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i32:
6073 ; CHECK: # %bb.0: # %entry
6074 ; CHECK-NEXT: vmv1r.v v9, v8
6075 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6076 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
6077 ; CHECK-NEXT: ret
6078 entry:
6079 tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6080 ret void
6081 }
6083 define void @test_vsoxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6084 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i32:
6085 ; CHECK: # %bb.0: # %entry
6086 ; CHECK-NEXT: vmv1r.v v9, v8
6087 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6088 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
6089 ; CHECK-NEXT: ret
6090 entry:
6091 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6092 ret void
6093 }
6095 declare void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6096 declare void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6098 define void @test_vsoxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6099 ; CHECK-LABEL: test_vsoxseg3_nxv8i8_nxv8i16:
6100 ; CHECK: # %bb.0: # %entry
6101 ; CHECK-NEXT: vmv1r.v v9, v8
6102 ; CHECK-NEXT: vmv2r.v v12, v10
6103 ; CHECK-NEXT: vmv1r.v v10, v8
6104 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6105 ; CHECK-NEXT: vsoxseg3ei16.v v8, (a0), v12
6106 ; CHECK-NEXT: ret
6107 entry:
6108 tail call void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6109 ret void
6110 }
6112 define void @test_vsoxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6113 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_nxv8i16:
6114 ; CHECK: # %bb.0: # %entry
6115 ; CHECK-NEXT: vmv1r.v v9, v8
6116 ; CHECK-NEXT: vmv2r.v v12, v10
6117 ; CHECK-NEXT: vmv1r.v v10, v8
6118 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6119 ; CHECK-NEXT: vsoxseg3ei16.v v8, (a0), v12, v0.t
6120 ; CHECK-NEXT: ret
6121 entry:
6122 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6123 ret void
6124 }
6126 declare void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6127 declare void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6129 define void @test_vsoxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6130 ; CHECK-LABEL: test_vsoxseg3_nxv8i8_nxv8i8:
6131 ; CHECK: # %bb.0: # %entry
6132 ; CHECK-NEXT: vmv1r.v v10, v8
6133 ; CHECK-NEXT: vmv1r.v v11, v8
6134 ; CHECK-NEXT: vmv1r.v v12, v8
6135 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6136 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
6137 ; CHECK-NEXT: ret
6138 entry:
6139 tail call void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6140 ret void
6141 }
6143 define void @test_vsoxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6144 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_nxv8i8:
6145 ; CHECK: # %bb.0: # %entry
6146 ; CHECK-NEXT: vmv1r.v v10, v8
6147 ; CHECK-NEXT: vmv1r.v v11, v8
6148 ; CHECK-NEXT: vmv1r.v v12, v8
6149 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6150 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
6151 ; CHECK-NEXT: ret
6152 entry:
6153 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6154 ret void
6155 }
6157 declare void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6158 declare void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6160 define void @test_vsoxseg3_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6161 ; CHECK-LABEL: test_vsoxseg3_nxv8i8_nxv8i64:
6162 ; CHECK: # %bb.0: # %entry
6163 ; CHECK-NEXT: vmv1r.v v9, v8
6164 ; CHECK-NEXT: vmv1r.v v10, v8
6165 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6166 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16
6167 ; CHECK-NEXT: ret
6168 entry:
6169 tail call void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6170 ret void
6171 }
6173 define void @test_vsoxseg3_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6174 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_nxv8i64:
6175 ; CHECK: # %bb.0: # %entry
6176 ; CHECK-NEXT: vmv1r.v v9, v8
6177 ; CHECK-NEXT: vmv1r.v v10, v8
6178 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6179 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16, v0.t
6180 ; CHECK-NEXT: ret
6181 entry:
6182 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6183 ret void
6184 }
6186 declare void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6187 declare void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6189 define void @test_vsoxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6190 ; CHECK-LABEL: test_vsoxseg3_nxv8i8_nxv8i32:
6191 ; CHECK: # %bb.0: # %entry
6192 ; CHECK-NEXT: vmv1r.v v9, v8
6193 ; CHECK-NEXT: vmv1r.v v10, v8
6194 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6195 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12
6196 ; CHECK-NEXT: ret
6197 entry:
6198 tail call void @llvm.riscv.vsoxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6199 ret void
6200 }
6202 define void @test_vsoxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6203 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_nxv8i32:
6204 ; CHECK: # %bb.0: # %entry
6205 ; CHECK-NEXT: vmv1r.v v9, v8
6206 ; CHECK-NEXT: vmv1r.v v10, v8
6207 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6208 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12, v0.t
6209 ; CHECK-NEXT: ret
6210 entry:
6211 tail call void @llvm.riscv.vsoxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6212 ret void
6213 }
6215 declare void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6216 declare void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6218 define void @test_vsoxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6219 ; CHECK-LABEL: test_vsoxseg4_nxv8i8_nxv8i16:
6220 ; CHECK: # %bb.0: # %entry
6221 ; CHECK-NEXT: vmv1r.v v12, v8
6222 ; CHECK-NEXT: vmv1r.v v13, v8
6223 ; CHECK-NEXT: vmv1r.v v14, v8
6224 ; CHECK-NEXT: vmv1r.v v15, v8
6225 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6226 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
6227 ; CHECK-NEXT: ret
6228 entry:
6229 tail call void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6230 ret void
6231 }
6233 define void @test_vsoxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6234 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_nxv8i16:
6235 ; CHECK: # %bb.0: # %entry
6236 ; CHECK-NEXT: vmv1r.v v12, v8
6237 ; CHECK-NEXT: vmv1r.v v13, v8
6238 ; CHECK-NEXT: vmv1r.v v14, v8
6239 ; CHECK-NEXT: vmv1r.v v15, v8
6240 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6241 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
6242 ; CHECK-NEXT: ret
6243 entry:
6244 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6245 ret void
6246 }
6248 declare void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6249 declare void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6251 define void @test_vsoxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6252 ; CHECK-LABEL: test_vsoxseg4_nxv8i8_nxv8i8:
6253 ; CHECK: # %bb.0: # %entry
6254 ; CHECK-NEXT: vmv1r.v v10, v8
6255 ; CHECK-NEXT: vmv1r.v v11, v8
6256 ; CHECK-NEXT: vmv1r.v v12, v8
6257 ; CHECK-NEXT: vmv1r.v v13, v8
6258 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6259 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
6260 ; CHECK-NEXT: ret
6261 entry:
6262 tail call void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6263 ret void
6264 }
6266 define void @test_vsoxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6267 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_nxv8i8:
6268 ; CHECK: # %bb.0: # %entry
6269 ; CHECK-NEXT: vmv1r.v v10, v8
6270 ; CHECK-NEXT: vmv1r.v v11, v8
6271 ; CHECK-NEXT: vmv1r.v v12, v8
6272 ; CHECK-NEXT: vmv1r.v v13, v8
6273 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6274 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
6275 ; CHECK-NEXT: ret
6276 entry:
6277 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6278 ret void
6279 }
6281 declare void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6282 declare void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6284 define void @test_vsoxseg4_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6285 ; CHECK-LABEL: test_vsoxseg4_nxv8i8_nxv8i64:
6286 ; CHECK: # %bb.0: # %entry
6287 ; CHECK-NEXT: vmv1r.v v9, v8
6288 ; CHECK-NEXT: vmv1r.v v10, v8
6289 ; CHECK-NEXT: vmv1r.v v11, v8
6290 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6291 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16
6292 ; CHECK-NEXT: ret
6293 entry:
6294 tail call void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6295 ret void
6296 }
6298 define void @test_vsoxseg4_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6299 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_nxv8i64:
6300 ; CHECK: # %bb.0: # %entry
6301 ; CHECK-NEXT: vmv1r.v v9, v8
6302 ; CHECK-NEXT: vmv1r.v v10, v8
6303 ; CHECK-NEXT: vmv1r.v v11, v8
6304 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6305 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16, v0.t
6306 ; CHECK-NEXT: ret
6307 entry:
6308 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6309 ret void
6310 }
6312 declare void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6313 declare void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6315 define void @test_vsoxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6316 ; CHECK-LABEL: test_vsoxseg4_nxv8i8_nxv8i32:
6317 ; CHECK: # %bb.0: # %entry
6318 ; CHECK-NEXT: vmv1r.v v9, v8
6319 ; CHECK-NEXT: vmv1r.v v10, v8
6320 ; CHECK-NEXT: vmv1r.v v11, v8
6321 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6322 ; CHECK-NEXT: vsoxseg4ei32.v v8, (a0), v12
6323 ; CHECK-NEXT: ret
6324 entry:
6325 tail call void @llvm.riscv.vsoxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6326 ret void
6327 }
6329 define void @test_vsoxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6330 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_nxv8i32:
6331 ; CHECK: # %bb.0: # %entry
6332 ; CHECK-NEXT: vmv1r.v v9, v8
6333 ; CHECK-NEXT: vmv1r.v v10, v8
6334 ; CHECK-NEXT: vmv1r.v v11, v8
6335 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6336 ; CHECK-NEXT: vsoxseg4ei32.v v8, (a0), v12, v0.t
6337 ; CHECK-NEXT: ret
6338 entry:
6339 tail call void @llvm.riscv.vsoxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6340 ret void
6341 }
6343 declare void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6344 declare void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6346 define void @test_vsoxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6347 ; CHECK-LABEL: test_vsoxseg5_nxv8i8_nxv8i16:
6348 ; CHECK: # %bb.0: # %entry
6349 ; CHECK-NEXT: vmv1r.v v12, v8
6350 ; CHECK-NEXT: vmv1r.v v13, v8
6351 ; CHECK-NEXT: vmv1r.v v14, v8
6352 ; CHECK-NEXT: vmv1r.v v15, v8
6353 ; CHECK-NEXT: vmv1r.v v16, v8
6354 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6355 ; CHECK-NEXT: vsoxseg5ei16.v v12, (a0), v10
6356 ; CHECK-NEXT: ret
6357 entry:
6358 tail call void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6359 ret void
6360 }
6362 define void @test_vsoxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6363 ; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_nxv8i16:
6364 ; CHECK: # %bb.0: # %entry
6365 ; CHECK-NEXT: vmv1r.v v12, v8
6366 ; CHECK-NEXT: vmv1r.v v13, v8
6367 ; CHECK-NEXT: vmv1r.v v14, v8
6368 ; CHECK-NEXT: vmv1r.v v15, v8
6369 ; CHECK-NEXT: vmv1r.v v16, v8
6370 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6371 ; CHECK-NEXT: vsoxseg5ei16.v v12, (a0), v10, v0.t
6372 ; CHECK-NEXT: ret
6373 entry:
6374 tail call void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6375 ret void
6376 }
6378 declare void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6379 declare void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6381 define void @test_vsoxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6382 ; CHECK-LABEL: test_vsoxseg5_nxv8i8_nxv8i8:
6383 ; CHECK: # %bb.0: # %entry
6384 ; CHECK-NEXT: vmv1r.v v10, v8
6385 ; CHECK-NEXT: vmv1r.v v11, v8
6386 ; CHECK-NEXT: vmv1r.v v12, v8
6387 ; CHECK-NEXT: vmv1r.v v13, v8
6388 ; CHECK-NEXT: vmv1r.v v14, v8
6389 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6390 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
6391 ; CHECK-NEXT: ret
6392 entry:
6393 tail call void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6394 ret void
6395 }
6397 define void @test_vsoxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6398 ; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_nxv8i8:
6399 ; CHECK: # %bb.0: # %entry
6400 ; CHECK-NEXT: vmv1r.v v10, v8
6401 ; CHECK-NEXT: vmv1r.v v11, v8
6402 ; CHECK-NEXT: vmv1r.v v12, v8
6403 ; CHECK-NEXT: vmv1r.v v13, v8
6404 ; CHECK-NEXT: vmv1r.v v14, v8
6405 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6406 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
6407 ; CHECK-NEXT: ret
6408 entry:
6409 tail call void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6410 ret void
6411 }
6413 declare void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6414 declare void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6416 define void @test_vsoxseg5_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6417 ; CHECK-LABEL: test_vsoxseg5_nxv8i8_nxv8i64:
6418 ; CHECK: # %bb.0: # %entry
6419 ; CHECK-NEXT: vmv1r.v v9, v8
6420 ; CHECK-NEXT: vmv1r.v v10, v8
6421 ; CHECK-NEXT: vmv1r.v v11, v8
6422 ; CHECK-NEXT: vmv1r.v v12, v8
6423 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6424 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16
6425 ; CHECK-NEXT: ret
6426 entry:
6427 tail call void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6428 ret void
6429 }
6431 define void @test_vsoxseg5_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6432 ; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_nxv8i64:
6433 ; CHECK: # %bb.0: # %entry
6434 ; CHECK-NEXT: vmv1r.v v9, v8
6435 ; CHECK-NEXT: vmv1r.v v10, v8
6436 ; CHECK-NEXT: vmv1r.v v11, v8
6437 ; CHECK-NEXT: vmv1r.v v12, v8
6438 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6439 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16, v0.t
6440 ; CHECK-NEXT: ret
6441 entry:
6442 tail call void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6443 ret void
6444 }
6446 declare void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6447 declare void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6449 define void @test_vsoxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6450 ; CHECK-LABEL: test_vsoxseg5_nxv8i8_nxv8i32:
6451 ; CHECK: # %bb.0: # %entry
6452 ; CHECK-NEXT: vmv1r.v v9, v8
6453 ; CHECK-NEXT: vmv1r.v v10, v8
6454 ; CHECK-NEXT: vmv1r.v v11, v8
6455 ; CHECK-NEXT: vmv4r.v v16, v12
6456 ; CHECK-NEXT: vmv1r.v v12, v8
6457 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6458 ; CHECK-NEXT: vsoxseg5ei32.v v8, (a0), v16
6459 ; CHECK-NEXT: ret
6460 entry:
6461 tail call void @llvm.riscv.vsoxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6462 ret void
6463 }
6465 define void @test_vsoxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6466 ; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_nxv8i32:
6467 ; CHECK: # %bb.0: # %entry
6468 ; CHECK-NEXT: vmv1r.v v9, v8
6469 ; CHECK-NEXT: vmv1r.v v10, v8
6470 ; CHECK-NEXT: vmv1r.v v11, v8
6471 ; CHECK-NEXT: vmv4r.v v16, v12
6472 ; CHECK-NEXT: vmv1r.v v12, v8
6473 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6474 ; CHECK-NEXT: vsoxseg5ei32.v v8, (a0), v16, v0.t
6475 ; CHECK-NEXT: ret
6476 entry:
6477 tail call void @llvm.riscv.vsoxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6478 ret void
6479 }
6481 declare void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6482 declare void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6484 define void @test_vsoxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6485 ; CHECK-LABEL: test_vsoxseg6_nxv8i8_nxv8i16:
6486 ; CHECK: # %bb.0: # %entry
6487 ; CHECK-NEXT: vmv1r.v v12, v8
6488 ; CHECK-NEXT: vmv1r.v v13, v8
6489 ; CHECK-NEXT: vmv1r.v v14, v8
6490 ; CHECK-NEXT: vmv1r.v v15, v8
6491 ; CHECK-NEXT: vmv1r.v v16, v8
6492 ; CHECK-NEXT: vmv1r.v v17, v8
6493 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6494 ; CHECK-NEXT: vsoxseg6ei16.v v12, (a0), v10
6495 ; CHECK-NEXT: ret
6496 entry:
6497 tail call void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6498 ret void
6499 }
6501 define void @test_vsoxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6502 ; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_nxv8i16:
6503 ; CHECK: # %bb.0: # %entry
6504 ; CHECK-NEXT: vmv1r.v v12, v8
6505 ; CHECK-NEXT: vmv1r.v v13, v8
6506 ; CHECK-NEXT: vmv1r.v v14, v8
6507 ; CHECK-NEXT: vmv1r.v v15, v8
6508 ; CHECK-NEXT: vmv1r.v v16, v8
6509 ; CHECK-NEXT: vmv1r.v v17, v8
6510 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6511 ; CHECK-NEXT: vsoxseg6ei16.v v12, (a0), v10, v0.t
6512 ; CHECK-NEXT: ret
6513 entry:
6514 tail call void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6515 ret void
6516 }
6518 declare void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6519 declare void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6521 define void @test_vsoxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6522 ; CHECK-LABEL: test_vsoxseg6_nxv8i8_nxv8i8:
6523 ; CHECK: # %bb.0: # %entry
6524 ; CHECK-NEXT: vmv1r.v v10, v8
6525 ; CHECK-NEXT: vmv1r.v v11, v8
6526 ; CHECK-NEXT: vmv1r.v v12, v8
6527 ; CHECK-NEXT: vmv1r.v v13, v8
6528 ; CHECK-NEXT: vmv1r.v v14, v8
6529 ; CHECK-NEXT: vmv1r.v v15, v8
6530 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6531 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
6532 ; CHECK-NEXT: ret
6533 entry:
6534 tail call void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6535 ret void
6536 }
6538 define void @test_vsoxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6539 ; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_nxv8i8:
6540 ; CHECK: # %bb.0: # %entry
6541 ; CHECK-NEXT: vmv1r.v v10, v8
6542 ; CHECK-NEXT: vmv1r.v v11, v8
6543 ; CHECK-NEXT: vmv1r.v v12, v8
6544 ; CHECK-NEXT: vmv1r.v v13, v8
6545 ; CHECK-NEXT: vmv1r.v v14, v8
6546 ; CHECK-NEXT: vmv1r.v v15, v8
6547 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6548 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
6549 ; CHECK-NEXT: ret
6550 entry:
6551 tail call void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6552 ret void
6553 }
6555 declare void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6556 declare void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6558 define void @test_vsoxseg6_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6559 ; CHECK-LABEL: test_vsoxseg6_nxv8i8_nxv8i64:
6560 ; CHECK: # %bb.0: # %entry
6561 ; CHECK-NEXT: vmv1r.v v9, v8
6562 ; CHECK-NEXT: vmv1r.v v10, v8
6563 ; CHECK-NEXT: vmv1r.v v11, v8
6564 ; CHECK-NEXT: vmv1r.v v12, v8
6565 ; CHECK-NEXT: vmv1r.v v13, v8
6566 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6567 ; CHECK-NEXT: vsoxseg6ei64.v v8, (a0), v16
6568 ; CHECK-NEXT: ret
6569 entry:
6570 tail call void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6571 ret void
6572 }
6574 define void @test_vsoxseg6_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6575 ; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_nxv8i64:
6576 ; CHECK: # %bb.0: # %entry
6577 ; CHECK-NEXT: vmv1r.v v9, v8
6578 ; CHECK-NEXT: vmv1r.v v10, v8
6579 ; CHECK-NEXT: vmv1r.v v11, v8
6580 ; CHECK-NEXT: vmv1r.v v12, v8
6581 ; CHECK-NEXT: vmv1r.v v13, v8
6582 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6583 ; CHECK-NEXT: vsoxseg6ei64.v v8, (a0), v16, v0.t
6584 ; CHECK-NEXT: ret
6585 entry:
6586 tail call void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6587 ret void
6588 }
6590 declare void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6591 declare void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6593 define void @test_vsoxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6594 ; CHECK-LABEL: test_vsoxseg6_nxv8i8_nxv8i32:
6595 ; CHECK: # %bb.0: # %entry
6596 ; CHECK-NEXT: vmv1r.v v16, v8
6597 ; CHECK-NEXT: vmv1r.v v17, v8
6598 ; CHECK-NEXT: vmv1r.v v18, v8
6599 ; CHECK-NEXT: vmv1r.v v19, v8
6600 ; CHECK-NEXT: vmv1r.v v20, v8
6601 ; CHECK-NEXT: vmv1r.v v21, v8
6602 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6603 ; CHECK-NEXT: vsoxseg6ei32.v v16, (a0), v12
6604 ; CHECK-NEXT: ret
6605 entry:
6606 tail call void @llvm.riscv.vsoxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6607 ret void
6608 }
6610 define void @test_vsoxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6611 ; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_nxv8i32:
6612 ; CHECK: # %bb.0: # %entry
6613 ; CHECK-NEXT: vmv1r.v v16, v8
6614 ; CHECK-NEXT: vmv1r.v v17, v8
6615 ; CHECK-NEXT: vmv1r.v v18, v8
6616 ; CHECK-NEXT: vmv1r.v v19, v8
6617 ; CHECK-NEXT: vmv1r.v v20, v8
6618 ; CHECK-NEXT: vmv1r.v v21, v8
6619 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6620 ; CHECK-NEXT: vsoxseg6ei32.v v16, (a0), v12, v0.t
6621 ; CHECK-NEXT: ret
6622 entry:
6623 tail call void @llvm.riscv.vsoxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6624 ret void
6625 }
6627 declare void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6628 declare void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6630 define void @test_vsoxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6631 ; CHECK-LABEL: test_vsoxseg7_nxv8i8_nxv8i16:
6632 ; CHECK: # %bb.0: # %entry
6633 ; CHECK-NEXT: vmv1r.v v12, v8
6634 ; CHECK-NEXT: vmv1r.v v13, v8
6635 ; CHECK-NEXT: vmv1r.v v14, v8
6636 ; CHECK-NEXT: vmv1r.v v15, v8
6637 ; CHECK-NEXT: vmv1r.v v16, v8
6638 ; CHECK-NEXT: vmv1r.v v17, v8
6639 ; CHECK-NEXT: vmv1r.v v18, v8
6640 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6641 ; CHECK-NEXT: vsoxseg7ei16.v v12, (a0), v10
6642 ; CHECK-NEXT: ret
6643 entry:
6644 tail call void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6645 ret void
6646 }
6648 define void @test_vsoxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6649 ; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_nxv8i16:
6650 ; CHECK: # %bb.0: # %entry
6651 ; CHECK-NEXT: vmv1r.v v12, v8
6652 ; CHECK-NEXT: vmv1r.v v13, v8
6653 ; CHECK-NEXT: vmv1r.v v14, v8
6654 ; CHECK-NEXT: vmv1r.v v15, v8
6655 ; CHECK-NEXT: vmv1r.v v16, v8
6656 ; CHECK-NEXT: vmv1r.v v17, v8
6657 ; CHECK-NEXT: vmv1r.v v18, v8
6658 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6659 ; CHECK-NEXT: vsoxseg7ei16.v v12, (a0), v10, v0.t
6660 ; CHECK-NEXT: ret
6661 entry:
6662 tail call void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6663 ret void
6664 }
6666 declare void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6667 declare void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6669 define void @test_vsoxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6670 ; CHECK-LABEL: test_vsoxseg7_nxv8i8_nxv8i8:
6671 ; CHECK: # %bb.0: # %entry
6672 ; CHECK-NEXT: vmv1r.v v10, v8
6673 ; CHECK-NEXT: vmv1r.v v11, v8
6674 ; CHECK-NEXT: vmv1r.v v12, v8
6675 ; CHECK-NEXT: vmv1r.v v13, v8
6676 ; CHECK-NEXT: vmv1r.v v14, v8
6677 ; CHECK-NEXT: vmv1r.v v15, v8
6678 ; CHECK-NEXT: vmv1r.v v16, v8
6679 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6680 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
6681 ; CHECK-NEXT: ret
6682 entry:
6683 tail call void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6684 ret void
6685 }
6687 define void @test_vsoxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6688 ; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_nxv8i8:
6689 ; CHECK: # %bb.0: # %entry
6690 ; CHECK-NEXT: vmv1r.v v10, v8
6691 ; CHECK-NEXT: vmv1r.v v11, v8
6692 ; CHECK-NEXT: vmv1r.v v12, v8
6693 ; CHECK-NEXT: vmv1r.v v13, v8
6694 ; CHECK-NEXT: vmv1r.v v14, v8
6695 ; CHECK-NEXT: vmv1r.v v15, v8
6696 ; CHECK-NEXT: vmv1r.v v16, v8
6697 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6698 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
6699 ; CHECK-NEXT: ret
6700 entry:
6701 tail call void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6702 ret void
6703 }
6705 declare void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6706 declare void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6708 define void @test_vsoxseg7_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6709 ; CHECK-LABEL: test_vsoxseg7_nxv8i8_nxv8i64:
6710 ; CHECK: # %bb.0: # %entry
6711 ; CHECK-NEXT: vmv1r.v v9, v8
6712 ; CHECK-NEXT: vmv1r.v v10, v8
6713 ; CHECK-NEXT: vmv1r.v v11, v8
6714 ; CHECK-NEXT: vmv1r.v v12, v8
6715 ; CHECK-NEXT: vmv1r.v v13, v8
6716 ; CHECK-NEXT: vmv1r.v v14, v8
6717 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6718 ; CHECK-NEXT: vsoxseg7ei64.v v8, (a0), v16
6719 ; CHECK-NEXT: ret
6720 entry:
6721 tail call void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6722 ret void
6723 }
6725 define void @test_vsoxseg7_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6726 ; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_nxv8i64:
6727 ; CHECK: # %bb.0: # %entry
6728 ; CHECK-NEXT: vmv1r.v v9, v8
6729 ; CHECK-NEXT: vmv1r.v v10, v8
6730 ; CHECK-NEXT: vmv1r.v v11, v8
6731 ; CHECK-NEXT: vmv1r.v v12, v8
6732 ; CHECK-NEXT: vmv1r.v v13, v8
6733 ; CHECK-NEXT: vmv1r.v v14, v8
6734 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6735 ; CHECK-NEXT: vsoxseg7ei64.v v8, (a0), v16, v0.t
6736 ; CHECK-NEXT: ret
6737 entry:
6738 tail call void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6739 ret void
6740 }
6742 declare void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6743 declare void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6745 define void @test_vsoxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6746 ; CHECK-LABEL: test_vsoxseg7_nxv8i8_nxv8i32:
6747 ; CHECK: # %bb.0: # %entry
6748 ; CHECK-NEXT: vmv1r.v v16, v8
6749 ; CHECK-NEXT: vmv1r.v v17, v8
6750 ; CHECK-NEXT: vmv1r.v v18, v8
6751 ; CHECK-NEXT: vmv1r.v v19, v8
6752 ; CHECK-NEXT: vmv1r.v v20, v8
6753 ; CHECK-NEXT: vmv1r.v v21, v8
6754 ; CHECK-NEXT: vmv1r.v v22, v8
6755 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6756 ; CHECK-NEXT: vsoxseg7ei32.v v16, (a0), v12
6757 ; CHECK-NEXT: ret
6758 entry:
6759 tail call void @llvm.riscv.vsoxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6760 ret void
6761 }
6763 define void @test_vsoxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6764 ; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_nxv8i32:
6765 ; CHECK: # %bb.0: # %entry
6766 ; CHECK-NEXT: vmv1r.v v16, v8
6767 ; CHECK-NEXT: vmv1r.v v17, v8
6768 ; CHECK-NEXT: vmv1r.v v18, v8
6769 ; CHECK-NEXT: vmv1r.v v19, v8
6770 ; CHECK-NEXT: vmv1r.v v20, v8
6771 ; CHECK-NEXT: vmv1r.v v21, v8
6772 ; CHECK-NEXT: vmv1r.v v22, v8
6773 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6774 ; CHECK-NEXT: vsoxseg7ei32.v v16, (a0), v12, v0.t
6775 ; CHECK-NEXT: ret
6776 entry:
6777 tail call void @llvm.riscv.vsoxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6778 ret void
6779 }
6781 declare void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, i64)
6782 declare void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
6784 define void @test_vsoxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
6785 ; CHECK-LABEL: test_vsoxseg8_nxv8i8_nxv8i16:
6786 ; CHECK: # %bb.0: # %entry
6787 ; CHECK-NEXT: vmv1r.v v12, v8
6788 ; CHECK-NEXT: vmv1r.v v13, v8
6789 ; CHECK-NEXT: vmv1r.v v14, v8
6790 ; CHECK-NEXT: vmv1r.v v15, v8
6791 ; CHECK-NEXT: vmv1r.v v16, v8
6792 ; CHECK-NEXT: vmv1r.v v17, v8
6793 ; CHECK-NEXT: vmv1r.v v18, v8
6794 ; CHECK-NEXT: vmv1r.v v19, v8
6795 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6796 ; CHECK-NEXT: vsoxseg8ei16.v v12, (a0), v10
6797 ; CHECK-NEXT: ret
6798 entry:
6799 tail call void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
6800 ret void
6801 }
6803 define void @test_vsoxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6804 ; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_nxv8i16:
6805 ; CHECK: # %bb.0: # %entry
6806 ; CHECK-NEXT: vmv1r.v v12, v8
6807 ; CHECK-NEXT: vmv1r.v v13, v8
6808 ; CHECK-NEXT: vmv1r.v v14, v8
6809 ; CHECK-NEXT: vmv1r.v v15, v8
6810 ; CHECK-NEXT: vmv1r.v v16, v8
6811 ; CHECK-NEXT: vmv1r.v v17, v8
6812 ; CHECK-NEXT: vmv1r.v v18, v8
6813 ; CHECK-NEXT: vmv1r.v v19, v8
6814 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6815 ; CHECK-NEXT: vsoxseg8ei16.v v12, (a0), v10, v0.t
6816 ; CHECK-NEXT: ret
6817 entry:
6818 tail call void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
6819 ret void
6820 }
6822 declare void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, i64)
6823 declare void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
6825 define void @test_vsoxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
6826 ; CHECK-LABEL: test_vsoxseg8_nxv8i8_nxv8i8:
6827 ; CHECK: # %bb.0: # %entry
6828 ; CHECK-NEXT: vmv1r.v v10, v8
6829 ; CHECK-NEXT: vmv1r.v v11, v8
6830 ; CHECK-NEXT: vmv1r.v v12, v8
6831 ; CHECK-NEXT: vmv1r.v v13, v8
6832 ; CHECK-NEXT: vmv1r.v v14, v8
6833 ; CHECK-NEXT: vmv1r.v v15, v8
6834 ; CHECK-NEXT: vmv1r.v v16, v8
6835 ; CHECK-NEXT: vmv1r.v v17, v8
6836 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6837 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
6838 ; CHECK-NEXT: ret
6839 entry:
6840 tail call void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
6841 ret void
6842 }
6844 define void @test_vsoxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6845 ; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_nxv8i8:
6846 ; CHECK: # %bb.0: # %entry
6847 ; CHECK-NEXT: vmv1r.v v10, v8
6848 ; CHECK-NEXT: vmv1r.v v11, v8
6849 ; CHECK-NEXT: vmv1r.v v12, v8
6850 ; CHECK-NEXT: vmv1r.v v13, v8
6851 ; CHECK-NEXT: vmv1r.v v14, v8
6852 ; CHECK-NEXT: vmv1r.v v15, v8
6853 ; CHECK-NEXT: vmv1r.v v16, v8
6854 ; CHECK-NEXT: vmv1r.v v17, v8
6855 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6856 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
6857 ; CHECK-NEXT: ret
6858 entry:
6859 tail call void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
6860 ret void
6861 }
6863 declare void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, i64)
6864 declare void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
6866 define void @test_vsoxseg8_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
6867 ; CHECK-LABEL: test_vsoxseg8_nxv8i8_nxv8i64:
6868 ; CHECK: # %bb.0: # %entry
6869 ; CHECK-NEXT: vmv1r.v v9, v8
6870 ; CHECK-NEXT: vmv1r.v v10, v8
6871 ; CHECK-NEXT: vmv1r.v v11, v8
6872 ; CHECK-NEXT: vmv1r.v v12, v8
6873 ; CHECK-NEXT: vmv1r.v v13, v8
6874 ; CHECK-NEXT: vmv1r.v v14, v8
6875 ; CHECK-NEXT: vmv1r.v v15, v8
6876 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6877 ; CHECK-NEXT: vsoxseg8ei64.v v8, (a0), v16
6878 ; CHECK-NEXT: ret
6879 entry:
6880 tail call void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
6881 ret void
6882 }
6884 define void @test_vsoxseg8_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6885 ; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_nxv8i64:
6886 ; CHECK: # %bb.0: # %entry
6887 ; CHECK-NEXT: vmv1r.v v9, v8
6888 ; CHECK-NEXT: vmv1r.v v10, v8
6889 ; CHECK-NEXT: vmv1r.v v11, v8
6890 ; CHECK-NEXT: vmv1r.v v12, v8
6891 ; CHECK-NEXT: vmv1r.v v13, v8
6892 ; CHECK-NEXT: vmv1r.v v14, v8
6893 ; CHECK-NEXT: vmv1r.v v15, v8
6894 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6895 ; CHECK-NEXT: vsoxseg8ei64.v v8, (a0), v16, v0.t
6896 ; CHECK-NEXT: ret
6897 entry:
6898 tail call void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
6899 ret void
6900 }
6902 declare void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, i64)
6903 declare void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
6905 define void @test_vsoxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
6906 ; CHECK-LABEL: test_vsoxseg8_nxv8i8_nxv8i32:
6907 ; CHECK: # %bb.0: # %entry
6908 ; CHECK-NEXT: vmv1r.v v16, v8
6909 ; CHECK-NEXT: vmv1r.v v17, v8
6910 ; CHECK-NEXT: vmv1r.v v18, v8
6911 ; CHECK-NEXT: vmv1r.v v19, v8
6912 ; CHECK-NEXT: vmv1r.v v20, v8
6913 ; CHECK-NEXT: vmv1r.v v21, v8
6914 ; CHECK-NEXT: vmv1r.v v22, v8
6915 ; CHECK-NEXT: vmv1r.v v23, v8
6916 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6917 ; CHECK-NEXT: vsoxseg8ei32.v v16, (a0), v12
6918 ; CHECK-NEXT: ret
6919 entry:
6920 tail call void @llvm.riscv.vsoxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
6921 ret void
6922 }
6924 define void @test_vsoxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
6925 ; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_nxv8i32:
6926 ; CHECK: # %bb.0: # %entry
6927 ; CHECK-NEXT: vmv1r.v v16, v8
6928 ; CHECK-NEXT: vmv1r.v v17, v8
6929 ; CHECK-NEXT: vmv1r.v v18, v8
6930 ; CHECK-NEXT: vmv1r.v v19, v8
6931 ; CHECK-NEXT: vmv1r.v v20, v8
6932 ; CHECK-NEXT: vmv1r.v v21, v8
6933 ; CHECK-NEXT: vmv1r.v v22, v8
6934 ; CHECK-NEXT: vmv1r.v v23, v8
6935 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
6936 ; CHECK-NEXT: vsoxseg8ei32.v v16, (a0), v12, v0.t
6937 ; CHECK-NEXT: ret
6938 entry:
6939 tail call void @llvm.riscv.vsoxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
6940 ret void
6941 }
6943 declare void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i32>, i64)
6944 declare void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
6946 define void @test_vsoxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
6947 ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i32:
6948 ; CHECK: # %bb.0: # %entry
6949 ; CHECK-NEXT: vmv2r.v v16, v12
6950 ; CHECK-NEXT: vmv4r.v v12, v8
6951 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
6952 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
6953 ; CHECK-NEXT: ret
6954 entry:
6955 tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
6956 ret void
6957 }
6959 define void @test_vsoxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
6960 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i32:
6961 ; CHECK: # %bb.0: # %entry
6962 ; CHECK-NEXT: vmv2r.v v16, v12
6963 ; CHECK-NEXT: vmv4r.v v12, v8
6964 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
6965 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
6966 ; CHECK-NEXT: ret
6967 entry:
6968 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
6969 ret void
6970 }
6972 declare void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i8>, i64)
6973 declare void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
6975 define void @test_vsoxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
6976 ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i8:
6977 ; CHECK: # %bb.0: # %entry
6978 ; CHECK-NEXT: vmv1r.v v16, v12
6979 ; CHECK-NEXT: vmv4r.v v12, v8
6980 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
6981 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
6982 ; CHECK-NEXT: ret
6983 entry:
6984 tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
6985 ret void
6986 }
6988 define void @test_vsoxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
6989 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i8:
6990 ; CHECK: # %bb.0: # %entry
6991 ; CHECK-NEXT: vmv1r.v v16, v12
6992 ; CHECK-NEXT: vmv4r.v v12, v8
6993 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
6994 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
6995 ; CHECK-NEXT: ret
6996 entry:
6997 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
6998 ret void
6999 }
7001 declare void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i64>, i64)
7002 declare void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7004 define void @test_vsoxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7005 ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i64:
7006 ; CHECK: # %bb.0: # %entry
7007 ; CHECK-NEXT: vmv4r.v v16, v12
7008 ; CHECK-NEXT: vmv4r.v v12, v8
7009 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
7010 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
7011 ; CHECK-NEXT: ret
7012 entry:
7013 tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7014 ret void
7015 }
7017 define void @test_vsoxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7018 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i64:
7019 ; CHECK: # %bb.0: # %entry
7020 ; CHECK-NEXT: vmv4r.v v16, v12
7021 ; CHECK-NEXT: vmv4r.v v12, v8
7022 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
7023 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
7024 ; CHECK-NEXT: ret
7025 entry:
7026 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7027 ret void
7028 }
7030 declare void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i16>, i64)
7031 declare void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7033 define void @test_vsoxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7034 ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i16:
7035 ; CHECK: # %bb.0: # %entry
7036 ; CHECK-NEXT: vmv1r.v v16, v12
7037 ; CHECK-NEXT: vmv4r.v v12, v8
7038 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
7039 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
7040 ; CHECK-NEXT: ret
7041 entry:
7042 tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7043 ret void
7044 }
7046 define void @test_vsoxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7047 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i16:
7048 ; CHECK: # %bb.0: # %entry
7049 ; CHECK-NEXT: vmv1r.v v16, v12
7050 ; CHECK-NEXT: vmv4r.v v12, v8
7051 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
7052 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
7053 ; CHECK-NEXT: ret
7054 entry:
7055 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7056 ret void
7057 }
7059 declare void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7060 declare void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7062 define void @test_vsoxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7063 ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i32:
7064 ; CHECK: # %bb.0: # %entry
7065 ; CHECK-NEXT: vmv1r.v v9, v8
7066 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7067 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
7068 ; CHECK-NEXT: ret
7069 entry:
7070 tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7071 ret void
7072 }
7074 define void @test_vsoxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7075 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i32:
7076 ; CHECK: # %bb.0: # %entry
7077 ; CHECK-NEXT: vmv1r.v v9, v8
7078 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7079 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
7080 ; CHECK-NEXT: ret
7081 entry:
7082 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7083 ret void
7084 }
7086 declare void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7087 declare void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7089 define void @test_vsoxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7090 ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i8:
7091 ; CHECK: # %bb.0: # %entry
7092 ; CHECK-NEXT: vmv1r.v v10, v9
7093 ; CHECK-NEXT: vmv1r.v v9, v8
7094 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7095 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
7096 ; CHECK-NEXT: ret
7097 entry:
7098 tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7099 ret void
7100 }
7102 define void @test_vsoxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7103 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i8:
7104 ; CHECK: # %bb.0: # %entry
7105 ; CHECK-NEXT: vmv1r.v v10, v9
7106 ; CHECK-NEXT: vmv1r.v v9, v8
7107 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7108 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
7109 ; CHECK-NEXT: ret
7110 entry:
7111 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7112 ret void
7113 }
7115 declare void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7116 declare void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7118 define void @test_vsoxseg2_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7119 ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i64:
7120 ; CHECK: # %bb.0: # %entry
7121 ; CHECK-NEXT: vmv1r.v v9, v8
7122 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7123 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
7124 ; CHECK-NEXT: ret
7125 entry:
7126 tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7127 ret void
7128 }
7130 define void @test_vsoxseg2_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7131 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i64:
7132 ; CHECK: # %bb.0: # %entry
7133 ; CHECK-NEXT: vmv1r.v v9, v8
7134 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7135 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
7136 ; CHECK-NEXT: ret
7137 entry:
7138 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7139 ret void
7140 }
7142 declare void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7143 declare void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7145 define void @test_vsoxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7146 ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i16:
7147 ; CHECK: # %bb.0: # %entry
7148 ; CHECK-NEXT: vmv1r.v v10, v9
7149 ; CHECK-NEXT: vmv1r.v v9, v8
7150 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7151 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
7152 ; CHECK-NEXT: ret
7153 entry:
7154 tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7155 ret void
7156 }
7158 define void @test_vsoxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7159 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i16:
7160 ; CHECK: # %bb.0: # %entry
7161 ; CHECK-NEXT: vmv1r.v v10, v9
7162 ; CHECK-NEXT: vmv1r.v v9, v8
7163 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7164 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
7165 ; CHECK-NEXT: ret
7166 entry:
7167 tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7168 ret void
7169 }
7171 declare void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7172 declare void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7174 define void @test_vsoxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7175 ; CHECK-LABEL: test_vsoxseg3_nxv4i16_nxv4i32:
7176 ; CHECK: # %bb.0: # %entry
7177 ; CHECK-NEXT: vmv1r.v v9, v8
7178 ; CHECK-NEXT: vmv2r.v v12, v10
7179 ; CHECK-NEXT: vmv1r.v v10, v8
7180 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7181 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12
7182 ; CHECK-NEXT: ret
7183 entry:
7184 tail call void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7185 ret void
7186 }
7188 define void @test_vsoxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7189 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_nxv4i32:
7190 ; CHECK: # %bb.0: # %entry
7191 ; CHECK-NEXT: vmv1r.v v9, v8
7192 ; CHECK-NEXT: vmv2r.v v12, v10
7193 ; CHECK-NEXT: vmv1r.v v10, v8
7194 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7195 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12, v0.t
7196 ; CHECK-NEXT: ret
7197 entry:
7198 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7199 ret void
7200 }
7202 declare void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7203 declare void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7205 define void @test_vsoxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7206 ; CHECK-LABEL: test_vsoxseg3_nxv4i16_nxv4i8:
7207 ; CHECK: # %bb.0: # %entry
7208 ; CHECK-NEXT: vmv1r.v v10, v8
7209 ; CHECK-NEXT: vmv1r.v v11, v8
7210 ; CHECK-NEXT: vmv1r.v v12, v8
7211 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7212 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
7213 ; CHECK-NEXT: ret
7214 entry:
7215 tail call void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7216 ret void
7217 }
7219 define void @test_vsoxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7220 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_nxv4i8:
7221 ; CHECK: # %bb.0: # %entry
7222 ; CHECK-NEXT: vmv1r.v v10, v8
7223 ; CHECK-NEXT: vmv1r.v v11, v8
7224 ; CHECK-NEXT: vmv1r.v v12, v8
7225 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7226 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
7227 ; CHECK-NEXT: ret
7228 entry:
7229 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7230 ret void
7231 }
7233 declare void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7234 declare void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7236 define void @test_vsoxseg3_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7237 ; CHECK-LABEL: test_vsoxseg3_nxv4i16_nxv4i64:
7238 ; CHECK: # %bb.0: # %entry
7239 ; CHECK-NEXT: vmv1r.v v9, v8
7240 ; CHECK-NEXT: vmv1r.v v10, v8
7241 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7242 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
7243 ; CHECK-NEXT: ret
7244 entry:
7245 tail call void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7246 ret void
7247 }
7249 define void @test_vsoxseg3_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7250 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_nxv4i64:
7251 ; CHECK: # %bb.0: # %entry
7252 ; CHECK-NEXT: vmv1r.v v9, v8
7253 ; CHECK-NEXT: vmv1r.v v10, v8
7254 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7255 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
7256 ; CHECK-NEXT: ret
7257 entry:
7258 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7259 ret void
7260 }
7262 declare void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7263 declare void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7265 define void @test_vsoxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7266 ; CHECK-LABEL: test_vsoxseg3_nxv4i16_nxv4i16:
7267 ; CHECK: # %bb.0: # %entry
7268 ; CHECK-NEXT: vmv1r.v v10, v8
7269 ; CHECK-NEXT: vmv1r.v v11, v8
7270 ; CHECK-NEXT: vmv1r.v v12, v8
7271 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7272 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
7273 ; CHECK-NEXT: ret
7274 entry:
7275 tail call void @llvm.riscv.vsoxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7276 ret void
7277 }
7279 define void @test_vsoxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7280 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_nxv4i16:
7281 ; CHECK: # %bb.0: # %entry
7282 ; CHECK-NEXT: vmv1r.v v10, v8
7283 ; CHECK-NEXT: vmv1r.v v11, v8
7284 ; CHECK-NEXT: vmv1r.v v12, v8
7285 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7286 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
7287 ; CHECK-NEXT: ret
7288 entry:
7289 tail call void @llvm.riscv.vsoxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7290 ret void
7291 }
7293 declare void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7294 declare void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7296 define void @test_vsoxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7297 ; CHECK-LABEL: test_vsoxseg4_nxv4i16_nxv4i32:
7298 ; CHECK: # %bb.0: # %entry
7299 ; CHECK-NEXT: vmv1r.v v12, v8
7300 ; CHECK-NEXT: vmv1r.v v13, v8
7301 ; CHECK-NEXT: vmv1r.v v14, v8
7302 ; CHECK-NEXT: vmv1r.v v15, v8
7303 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7304 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
7305 ; CHECK-NEXT: ret
7306 entry:
7307 tail call void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7308 ret void
7309 }
7311 define void @test_vsoxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7312 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_nxv4i32:
7313 ; CHECK: # %bb.0: # %entry
7314 ; CHECK-NEXT: vmv1r.v v12, v8
7315 ; CHECK-NEXT: vmv1r.v v13, v8
7316 ; CHECK-NEXT: vmv1r.v v14, v8
7317 ; CHECK-NEXT: vmv1r.v v15, v8
7318 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7319 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
7320 ; CHECK-NEXT: ret
7321 entry:
7322 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7323 ret void
7324 }
7326 declare void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7327 declare void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7329 define void @test_vsoxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7330 ; CHECK-LABEL: test_vsoxseg4_nxv4i16_nxv4i8:
7331 ; CHECK: # %bb.0: # %entry
7332 ; CHECK-NEXT: vmv1r.v v10, v8
7333 ; CHECK-NEXT: vmv1r.v v11, v8
7334 ; CHECK-NEXT: vmv1r.v v12, v8
7335 ; CHECK-NEXT: vmv1r.v v13, v8
7336 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7337 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
7338 ; CHECK-NEXT: ret
7339 entry:
7340 tail call void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7341 ret void
7342 }
7344 define void @test_vsoxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7345 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_nxv4i8:
7346 ; CHECK: # %bb.0: # %entry
7347 ; CHECK-NEXT: vmv1r.v v10, v8
7348 ; CHECK-NEXT: vmv1r.v v11, v8
7349 ; CHECK-NEXT: vmv1r.v v12, v8
7350 ; CHECK-NEXT: vmv1r.v v13, v8
7351 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7352 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
7353 ; CHECK-NEXT: ret
7354 entry:
7355 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7356 ret void
7357 }
7359 declare void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7360 declare void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7362 define void @test_vsoxseg4_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7363 ; CHECK-LABEL: test_vsoxseg4_nxv4i16_nxv4i64:
7364 ; CHECK: # %bb.0: # %entry
7365 ; CHECK-NEXT: vmv1r.v v9, v8
7366 ; CHECK-NEXT: vmv1r.v v10, v8
7367 ; CHECK-NEXT: vmv1r.v v11, v8
7368 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7369 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12
7370 ; CHECK-NEXT: ret
7371 entry:
7372 tail call void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7373 ret void
7374 }
7376 define void @test_vsoxseg4_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7377 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_nxv4i64:
7378 ; CHECK: # %bb.0: # %entry
7379 ; CHECK-NEXT: vmv1r.v v9, v8
7380 ; CHECK-NEXT: vmv1r.v v10, v8
7381 ; CHECK-NEXT: vmv1r.v v11, v8
7382 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7383 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12, v0.t
7384 ; CHECK-NEXT: ret
7385 entry:
7386 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7387 ret void
7388 }
7390 declare void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7391 declare void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7393 define void @test_vsoxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7394 ; CHECK-LABEL: test_vsoxseg4_nxv4i16_nxv4i16:
7395 ; CHECK: # %bb.0: # %entry
7396 ; CHECK-NEXT: vmv1r.v v10, v8
7397 ; CHECK-NEXT: vmv1r.v v11, v8
7398 ; CHECK-NEXT: vmv1r.v v12, v8
7399 ; CHECK-NEXT: vmv1r.v v13, v8
7400 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7401 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
7402 ; CHECK-NEXT: ret
7403 entry:
7404 tail call void @llvm.riscv.vsoxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7405 ret void
7406 }
7408 define void @test_vsoxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7409 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_nxv4i16:
7410 ; CHECK: # %bb.0: # %entry
7411 ; CHECK-NEXT: vmv1r.v v10, v8
7412 ; CHECK-NEXT: vmv1r.v v11, v8
7413 ; CHECK-NEXT: vmv1r.v v12, v8
7414 ; CHECK-NEXT: vmv1r.v v13, v8
7415 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7416 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
7417 ; CHECK-NEXT: ret
7418 entry:
7419 tail call void @llvm.riscv.vsoxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7420 ret void
7421 }
7423 declare void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7424 declare void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7426 define void @test_vsoxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7427 ; CHECK-LABEL: test_vsoxseg5_nxv4i16_nxv4i32:
7428 ; CHECK: # %bb.0: # %entry
7429 ; CHECK-NEXT: vmv1r.v v12, v8
7430 ; CHECK-NEXT: vmv1r.v v13, v8
7431 ; CHECK-NEXT: vmv1r.v v14, v8
7432 ; CHECK-NEXT: vmv1r.v v15, v8
7433 ; CHECK-NEXT: vmv1r.v v16, v8
7434 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7435 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10
7436 ; CHECK-NEXT: ret
7437 entry:
7438 tail call void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7439 ret void
7440 }
7442 define void @test_vsoxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7443 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_nxv4i32:
7444 ; CHECK: # %bb.0: # %entry
7445 ; CHECK-NEXT: vmv1r.v v12, v8
7446 ; CHECK-NEXT: vmv1r.v v13, v8
7447 ; CHECK-NEXT: vmv1r.v v14, v8
7448 ; CHECK-NEXT: vmv1r.v v15, v8
7449 ; CHECK-NEXT: vmv1r.v v16, v8
7450 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7451 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10, v0.t
7452 ; CHECK-NEXT: ret
7453 entry:
7454 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7455 ret void
7456 }
7458 declare void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7459 declare void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7461 define void @test_vsoxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7462 ; CHECK-LABEL: test_vsoxseg5_nxv4i16_nxv4i8:
7463 ; CHECK: # %bb.0: # %entry
7464 ; CHECK-NEXT: vmv1r.v v10, v8
7465 ; CHECK-NEXT: vmv1r.v v11, v8
7466 ; CHECK-NEXT: vmv1r.v v12, v8
7467 ; CHECK-NEXT: vmv1r.v v13, v8
7468 ; CHECK-NEXT: vmv1r.v v14, v8
7469 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7470 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
7471 ; CHECK-NEXT: ret
7472 entry:
7473 tail call void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7474 ret void
7475 }
7477 define void @test_vsoxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7478 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_nxv4i8:
7479 ; CHECK: # %bb.0: # %entry
7480 ; CHECK-NEXT: vmv1r.v v10, v8
7481 ; CHECK-NEXT: vmv1r.v v11, v8
7482 ; CHECK-NEXT: vmv1r.v v12, v8
7483 ; CHECK-NEXT: vmv1r.v v13, v8
7484 ; CHECK-NEXT: vmv1r.v v14, v8
7485 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7486 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
7487 ; CHECK-NEXT: ret
7488 entry:
7489 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7490 ret void
7491 }
7493 declare void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7494 declare void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7496 define void @test_vsoxseg5_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7497 ; CHECK-LABEL: test_vsoxseg5_nxv4i16_nxv4i64:
7498 ; CHECK: # %bb.0: # %entry
7499 ; CHECK-NEXT: vmv1r.v v9, v8
7500 ; CHECK-NEXT: vmv1r.v v10, v8
7501 ; CHECK-NEXT: vmv1r.v v11, v8
7502 ; CHECK-NEXT: vmv4r.v v16, v12
7503 ; CHECK-NEXT: vmv1r.v v12, v8
7504 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7505 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16
7506 ; CHECK-NEXT: ret
7507 entry:
7508 tail call void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7509 ret void
7510 }
7512 define void @test_vsoxseg5_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7513 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_nxv4i64:
7514 ; CHECK: # %bb.0: # %entry
7515 ; CHECK-NEXT: vmv1r.v v9, v8
7516 ; CHECK-NEXT: vmv1r.v v10, v8
7517 ; CHECK-NEXT: vmv1r.v v11, v8
7518 ; CHECK-NEXT: vmv4r.v v16, v12
7519 ; CHECK-NEXT: vmv1r.v v12, v8
7520 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7521 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16, v0.t
7522 ; CHECK-NEXT: ret
7523 entry:
7524 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7525 ret void
7526 }
7528 declare void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7529 declare void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7531 define void @test_vsoxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7532 ; CHECK-LABEL: test_vsoxseg5_nxv4i16_nxv4i16:
7533 ; CHECK: # %bb.0: # %entry
7534 ; CHECK-NEXT: vmv1r.v v10, v8
7535 ; CHECK-NEXT: vmv1r.v v11, v8
7536 ; CHECK-NEXT: vmv1r.v v12, v8
7537 ; CHECK-NEXT: vmv1r.v v13, v8
7538 ; CHECK-NEXT: vmv1r.v v14, v8
7539 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7540 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
7541 ; CHECK-NEXT: ret
7542 entry:
7543 tail call void @llvm.riscv.vsoxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7544 ret void
7545 }
7547 define void @test_vsoxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7548 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_nxv4i16:
7549 ; CHECK: # %bb.0: # %entry
7550 ; CHECK-NEXT: vmv1r.v v10, v8
7551 ; CHECK-NEXT: vmv1r.v v11, v8
7552 ; CHECK-NEXT: vmv1r.v v12, v8
7553 ; CHECK-NEXT: vmv1r.v v13, v8
7554 ; CHECK-NEXT: vmv1r.v v14, v8
7555 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7556 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
7557 ; CHECK-NEXT: ret
7558 entry:
7559 tail call void @llvm.riscv.vsoxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7560 ret void
7561 }
7563 declare void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7564 declare void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7566 define void @test_vsoxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7567 ; CHECK-LABEL: test_vsoxseg6_nxv4i16_nxv4i32:
7568 ; CHECK: # %bb.0: # %entry
7569 ; CHECK-NEXT: vmv1r.v v12, v8
7570 ; CHECK-NEXT: vmv1r.v v13, v8
7571 ; CHECK-NEXT: vmv1r.v v14, v8
7572 ; CHECK-NEXT: vmv1r.v v15, v8
7573 ; CHECK-NEXT: vmv1r.v v16, v8
7574 ; CHECK-NEXT: vmv1r.v v17, v8
7575 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7576 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10
7577 ; CHECK-NEXT: ret
7578 entry:
7579 tail call void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7580 ret void
7581 }
7583 define void @test_vsoxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7584 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_nxv4i32:
7585 ; CHECK: # %bb.0: # %entry
7586 ; CHECK-NEXT: vmv1r.v v12, v8
7587 ; CHECK-NEXT: vmv1r.v v13, v8
7588 ; CHECK-NEXT: vmv1r.v v14, v8
7589 ; CHECK-NEXT: vmv1r.v v15, v8
7590 ; CHECK-NEXT: vmv1r.v v16, v8
7591 ; CHECK-NEXT: vmv1r.v v17, v8
7592 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7593 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10, v0.t
7594 ; CHECK-NEXT: ret
7595 entry:
7596 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7597 ret void
7598 }
7600 declare void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7601 declare void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7603 define void @test_vsoxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7604 ; CHECK-LABEL: test_vsoxseg6_nxv4i16_nxv4i8:
7605 ; CHECK: # %bb.0: # %entry
7606 ; CHECK-NEXT: vmv1r.v v10, v8
7607 ; CHECK-NEXT: vmv1r.v v11, v8
7608 ; CHECK-NEXT: vmv1r.v v12, v8
7609 ; CHECK-NEXT: vmv1r.v v13, v8
7610 ; CHECK-NEXT: vmv1r.v v14, v8
7611 ; CHECK-NEXT: vmv1r.v v15, v8
7612 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7613 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
7614 ; CHECK-NEXT: ret
7615 entry:
7616 tail call void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7617 ret void
7618 }
7620 define void @test_vsoxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7621 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_nxv4i8:
7622 ; CHECK: # %bb.0: # %entry
7623 ; CHECK-NEXT: vmv1r.v v10, v8
7624 ; CHECK-NEXT: vmv1r.v v11, v8
7625 ; CHECK-NEXT: vmv1r.v v12, v8
7626 ; CHECK-NEXT: vmv1r.v v13, v8
7627 ; CHECK-NEXT: vmv1r.v v14, v8
7628 ; CHECK-NEXT: vmv1r.v v15, v8
7629 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7630 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
7631 ; CHECK-NEXT: ret
7632 entry:
7633 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7634 ret void
7635 }
7637 declare void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7638 declare void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7640 define void @test_vsoxseg6_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7641 ; CHECK-LABEL: test_vsoxseg6_nxv4i16_nxv4i64:
7642 ; CHECK: # %bb.0: # %entry
7643 ; CHECK-NEXT: vmv1r.v v16, v8
7644 ; CHECK-NEXT: vmv1r.v v17, v8
7645 ; CHECK-NEXT: vmv1r.v v18, v8
7646 ; CHECK-NEXT: vmv1r.v v19, v8
7647 ; CHECK-NEXT: vmv1r.v v20, v8
7648 ; CHECK-NEXT: vmv1r.v v21, v8
7649 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7650 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12
7651 ; CHECK-NEXT: ret
7652 entry:
7653 tail call void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7654 ret void
7655 }
7657 define void @test_vsoxseg6_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7658 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_nxv4i64:
7659 ; CHECK: # %bb.0: # %entry
7660 ; CHECK-NEXT: vmv1r.v v16, v8
7661 ; CHECK-NEXT: vmv1r.v v17, v8
7662 ; CHECK-NEXT: vmv1r.v v18, v8
7663 ; CHECK-NEXT: vmv1r.v v19, v8
7664 ; CHECK-NEXT: vmv1r.v v20, v8
7665 ; CHECK-NEXT: vmv1r.v v21, v8
7666 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7667 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12, v0.t
7668 ; CHECK-NEXT: ret
7669 entry:
7670 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7671 ret void
7672 }
7674 declare void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7675 declare void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7677 define void @test_vsoxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7678 ; CHECK-LABEL: test_vsoxseg6_nxv4i16_nxv4i16:
7679 ; CHECK: # %bb.0: # %entry
7680 ; CHECK-NEXT: vmv1r.v v10, v8
7681 ; CHECK-NEXT: vmv1r.v v11, v8
7682 ; CHECK-NEXT: vmv1r.v v12, v8
7683 ; CHECK-NEXT: vmv1r.v v13, v8
7684 ; CHECK-NEXT: vmv1r.v v14, v8
7685 ; CHECK-NEXT: vmv1r.v v15, v8
7686 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7687 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
7688 ; CHECK-NEXT: ret
7689 entry:
7690 tail call void @llvm.riscv.vsoxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7691 ret void
7692 }
7694 define void @test_vsoxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7695 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_nxv4i16:
7696 ; CHECK: # %bb.0: # %entry
7697 ; CHECK-NEXT: vmv1r.v v10, v8
7698 ; CHECK-NEXT: vmv1r.v v11, v8
7699 ; CHECK-NEXT: vmv1r.v v12, v8
7700 ; CHECK-NEXT: vmv1r.v v13, v8
7701 ; CHECK-NEXT: vmv1r.v v14, v8
7702 ; CHECK-NEXT: vmv1r.v v15, v8
7703 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7704 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
7705 ; CHECK-NEXT: ret
7706 entry:
7707 tail call void @llvm.riscv.vsoxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7708 ret void
7709 }
7711 declare void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7712 declare void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7714 define void @test_vsoxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7715 ; CHECK-LABEL: test_vsoxseg7_nxv4i16_nxv4i32:
7716 ; CHECK: # %bb.0: # %entry
7717 ; CHECK-NEXT: vmv1r.v v12, v8
7718 ; CHECK-NEXT: vmv1r.v v13, v8
7719 ; CHECK-NEXT: vmv1r.v v14, v8
7720 ; CHECK-NEXT: vmv1r.v v15, v8
7721 ; CHECK-NEXT: vmv1r.v v16, v8
7722 ; CHECK-NEXT: vmv1r.v v17, v8
7723 ; CHECK-NEXT: vmv1r.v v18, v8
7724 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7725 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10
7726 ; CHECK-NEXT: ret
7727 entry:
7728 tail call void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7729 ret void
7730 }
7732 define void @test_vsoxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7733 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_nxv4i32:
7734 ; CHECK: # %bb.0: # %entry
7735 ; CHECK-NEXT: vmv1r.v v12, v8
7736 ; CHECK-NEXT: vmv1r.v v13, v8
7737 ; CHECK-NEXT: vmv1r.v v14, v8
7738 ; CHECK-NEXT: vmv1r.v v15, v8
7739 ; CHECK-NEXT: vmv1r.v v16, v8
7740 ; CHECK-NEXT: vmv1r.v v17, v8
7741 ; CHECK-NEXT: vmv1r.v v18, v8
7742 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7743 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10, v0.t
7744 ; CHECK-NEXT: ret
7745 entry:
7746 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7747 ret void
7748 }
7750 declare void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7751 declare void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7753 define void @test_vsoxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7754 ; CHECK-LABEL: test_vsoxseg7_nxv4i16_nxv4i8:
7755 ; CHECK: # %bb.0: # %entry
7756 ; CHECK-NEXT: vmv1r.v v10, v8
7757 ; CHECK-NEXT: vmv1r.v v11, v8
7758 ; CHECK-NEXT: vmv1r.v v12, v8
7759 ; CHECK-NEXT: vmv1r.v v13, v8
7760 ; CHECK-NEXT: vmv1r.v v14, v8
7761 ; CHECK-NEXT: vmv1r.v v15, v8
7762 ; CHECK-NEXT: vmv1r.v v16, v8
7763 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7764 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
7765 ; CHECK-NEXT: ret
7766 entry:
7767 tail call void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7768 ret void
7769 }
7771 define void @test_vsoxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7772 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_nxv4i8:
7773 ; CHECK: # %bb.0: # %entry
7774 ; CHECK-NEXT: vmv1r.v v10, v8
7775 ; CHECK-NEXT: vmv1r.v v11, v8
7776 ; CHECK-NEXT: vmv1r.v v12, v8
7777 ; CHECK-NEXT: vmv1r.v v13, v8
7778 ; CHECK-NEXT: vmv1r.v v14, v8
7779 ; CHECK-NEXT: vmv1r.v v15, v8
7780 ; CHECK-NEXT: vmv1r.v v16, v8
7781 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7782 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
7783 ; CHECK-NEXT: ret
7784 entry:
7785 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7786 ret void
7787 }
7789 declare void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7790 declare void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7792 define void @test_vsoxseg7_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7793 ; CHECK-LABEL: test_vsoxseg7_nxv4i16_nxv4i64:
7794 ; CHECK: # %bb.0: # %entry
7795 ; CHECK-NEXT: vmv1r.v v16, v8
7796 ; CHECK-NEXT: vmv1r.v v17, v8
7797 ; CHECK-NEXT: vmv1r.v v18, v8
7798 ; CHECK-NEXT: vmv1r.v v19, v8
7799 ; CHECK-NEXT: vmv1r.v v20, v8
7800 ; CHECK-NEXT: vmv1r.v v21, v8
7801 ; CHECK-NEXT: vmv1r.v v22, v8
7802 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7803 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12
7804 ; CHECK-NEXT: ret
7805 entry:
7806 tail call void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7807 ret void
7808 }
7810 define void @test_vsoxseg7_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7811 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_nxv4i64:
7812 ; CHECK: # %bb.0: # %entry
7813 ; CHECK-NEXT: vmv1r.v v16, v8
7814 ; CHECK-NEXT: vmv1r.v v17, v8
7815 ; CHECK-NEXT: vmv1r.v v18, v8
7816 ; CHECK-NEXT: vmv1r.v v19, v8
7817 ; CHECK-NEXT: vmv1r.v v20, v8
7818 ; CHECK-NEXT: vmv1r.v v21, v8
7819 ; CHECK-NEXT: vmv1r.v v22, v8
7820 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7821 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12, v0.t
7822 ; CHECK-NEXT: ret
7823 entry:
7824 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7825 ret void
7826 }
7828 declare void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7829 declare void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7831 define void @test_vsoxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7832 ; CHECK-LABEL: test_vsoxseg7_nxv4i16_nxv4i16:
7833 ; CHECK: # %bb.0: # %entry
7834 ; CHECK-NEXT: vmv1r.v v10, v8
7835 ; CHECK-NEXT: vmv1r.v v11, v8
7836 ; CHECK-NEXT: vmv1r.v v12, v8
7837 ; CHECK-NEXT: vmv1r.v v13, v8
7838 ; CHECK-NEXT: vmv1r.v v14, v8
7839 ; CHECK-NEXT: vmv1r.v v15, v8
7840 ; CHECK-NEXT: vmv1r.v v16, v8
7841 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7842 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
7843 ; CHECK-NEXT: ret
7844 entry:
7845 tail call void @llvm.riscv.vsoxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
7846 ret void
7847 }
7849 define void @test_vsoxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7850 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_nxv4i16:
7851 ; CHECK: # %bb.0: # %entry
7852 ; CHECK-NEXT: vmv1r.v v10, v8
7853 ; CHECK-NEXT: vmv1r.v v11, v8
7854 ; CHECK-NEXT: vmv1r.v v12, v8
7855 ; CHECK-NEXT: vmv1r.v v13, v8
7856 ; CHECK-NEXT: vmv1r.v v14, v8
7857 ; CHECK-NEXT: vmv1r.v v15, v8
7858 ; CHECK-NEXT: vmv1r.v v16, v8
7859 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7860 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
7861 ; CHECK-NEXT: ret
7862 entry:
7863 tail call void @llvm.riscv.vsoxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
7864 ret void
7865 }
7867 declare void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, i64)
7868 declare void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
7870 define void @test_vsoxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
7871 ; CHECK-LABEL: test_vsoxseg8_nxv4i16_nxv4i32:
7872 ; CHECK: # %bb.0: # %entry
7873 ; CHECK-NEXT: vmv1r.v v12, v8
7874 ; CHECK-NEXT: vmv1r.v v13, v8
7875 ; CHECK-NEXT: vmv1r.v v14, v8
7876 ; CHECK-NEXT: vmv1r.v v15, v8
7877 ; CHECK-NEXT: vmv1r.v v16, v8
7878 ; CHECK-NEXT: vmv1r.v v17, v8
7879 ; CHECK-NEXT: vmv1r.v v18, v8
7880 ; CHECK-NEXT: vmv1r.v v19, v8
7881 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7882 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10
7883 ; CHECK-NEXT: ret
7884 entry:
7885 tail call void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
7886 ret void
7887 }
7889 define void @test_vsoxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7890 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_nxv4i32:
7891 ; CHECK: # %bb.0: # %entry
7892 ; CHECK-NEXT: vmv1r.v v12, v8
7893 ; CHECK-NEXT: vmv1r.v v13, v8
7894 ; CHECK-NEXT: vmv1r.v v14, v8
7895 ; CHECK-NEXT: vmv1r.v v15, v8
7896 ; CHECK-NEXT: vmv1r.v v16, v8
7897 ; CHECK-NEXT: vmv1r.v v17, v8
7898 ; CHECK-NEXT: vmv1r.v v18, v8
7899 ; CHECK-NEXT: vmv1r.v v19, v8
7900 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7901 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10, v0.t
7902 ; CHECK-NEXT: ret
7903 entry:
7904 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
7905 ret void
7906 }
7908 declare void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, i64)
7909 declare void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
7911 define void @test_vsoxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
7912 ; CHECK-LABEL: test_vsoxseg8_nxv4i16_nxv4i8:
7913 ; CHECK: # %bb.0: # %entry
7914 ; CHECK-NEXT: vmv1r.v v10, v8
7915 ; CHECK-NEXT: vmv1r.v v11, v8
7916 ; CHECK-NEXT: vmv1r.v v12, v8
7917 ; CHECK-NEXT: vmv1r.v v13, v8
7918 ; CHECK-NEXT: vmv1r.v v14, v8
7919 ; CHECK-NEXT: vmv1r.v v15, v8
7920 ; CHECK-NEXT: vmv1r.v v16, v8
7921 ; CHECK-NEXT: vmv1r.v v17, v8
7922 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7923 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
7924 ; CHECK-NEXT: ret
7925 entry:
7926 tail call void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
7927 ret void
7928 }
7930 define void @test_vsoxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7931 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_nxv4i8:
7932 ; CHECK: # %bb.0: # %entry
7933 ; CHECK-NEXT: vmv1r.v v10, v8
7934 ; CHECK-NEXT: vmv1r.v v11, v8
7935 ; CHECK-NEXT: vmv1r.v v12, v8
7936 ; CHECK-NEXT: vmv1r.v v13, v8
7937 ; CHECK-NEXT: vmv1r.v v14, v8
7938 ; CHECK-NEXT: vmv1r.v v15, v8
7939 ; CHECK-NEXT: vmv1r.v v16, v8
7940 ; CHECK-NEXT: vmv1r.v v17, v8
7941 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7942 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
7943 ; CHECK-NEXT: ret
7944 entry:
7945 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
7946 ret void
7947 }
7949 declare void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, i64)
7950 declare void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
7952 define void @test_vsoxseg8_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
7953 ; CHECK-LABEL: test_vsoxseg8_nxv4i16_nxv4i64:
7954 ; CHECK: # %bb.0: # %entry
7955 ; CHECK-NEXT: vmv1r.v v16, v8
7956 ; CHECK-NEXT: vmv1r.v v17, v8
7957 ; CHECK-NEXT: vmv1r.v v18, v8
7958 ; CHECK-NEXT: vmv1r.v v19, v8
7959 ; CHECK-NEXT: vmv1r.v v20, v8
7960 ; CHECK-NEXT: vmv1r.v v21, v8
7961 ; CHECK-NEXT: vmv1r.v v22, v8
7962 ; CHECK-NEXT: vmv1r.v v23, v8
7963 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7964 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12
7965 ; CHECK-NEXT: ret
7966 entry:
7967 tail call void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
7968 ret void
7969 }
7971 define void @test_vsoxseg8_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
7972 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_nxv4i64:
7973 ; CHECK: # %bb.0: # %entry
7974 ; CHECK-NEXT: vmv1r.v v16, v8
7975 ; CHECK-NEXT: vmv1r.v v17, v8
7976 ; CHECK-NEXT: vmv1r.v v18, v8
7977 ; CHECK-NEXT: vmv1r.v v19, v8
7978 ; CHECK-NEXT: vmv1r.v v20, v8
7979 ; CHECK-NEXT: vmv1r.v v21, v8
7980 ; CHECK-NEXT: vmv1r.v v22, v8
7981 ; CHECK-NEXT: vmv1r.v v23, v8
7982 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
7983 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12, v0.t
7984 ; CHECK-NEXT: ret
7985 entry:
7986 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
7987 ret void
7988 }
7990 declare void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, i64)
7991 declare void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
7993 define void @test_vsoxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
7994 ; CHECK-LABEL: test_vsoxseg8_nxv4i16_nxv4i16:
7995 ; CHECK: # %bb.0: # %entry
7996 ; CHECK-NEXT: vmv1r.v v10, v8
7997 ; CHECK-NEXT: vmv1r.v v11, v8
7998 ; CHECK-NEXT: vmv1r.v v12, v8
7999 ; CHECK-NEXT: vmv1r.v v13, v8
8000 ; CHECK-NEXT: vmv1r.v v14, v8
8001 ; CHECK-NEXT: vmv1r.v v15, v8
8002 ; CHECK-NEXT: vmv1r.v v16, v8
8003 ; CHECK-NEXT: vmv1r.v v17, v8
8004 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
8005 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
8006 ; CHECK-NEXT: ret
8007 entry:
8008 tail call void @llvm.riscv.vsoxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
8009 ret void
8010 }
8012 define void @test_vsoxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
8013 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_nxv4i16:
8014 ; CHECK: # %bb.0: # %entry
8015 ; CHECK-NEXT: vmv1r.v v10, v8
8016 ; CHECK-NEXT: vmv1r.v v11, v8
8017 ; CHECK-NEXT: vmv1r.v v12, v8
8018 ; CHECK-NEXT: vmv1r.v v13, v8
8019 ; CHECK-NEXT: vmv1r.v v14, v8
8020 ; CHECK-NEXT: vmv1r.v v15, v8
8021 ; CHECK-NEXT: vmv1r.v v16, v8
8022 ; CHECK-NEXT: vmv1r.v v17, v8
8023 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
8024 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
8025 ; CHECK-NEXT: ret
8026 entry:
8027 tail call void @llvm.riscv.vsoxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
8028 ret void
8029 }
8031 declare void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8032 declare void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8034 define void @test_vsoxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8035 ; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i64:
8036 ; CHECK: # %bb.0: # %entry
8037 ; CHECK-NEXT: vmv1r.v v10, v9
8038 ; CHECK-NEXT: vmv1r.v v9, v8
8039 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8040 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
8041 ; CHECK-NEXT: ret
8042 entry:
8043 tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8044 ret void
8045 }
8047 define void @test_vsoxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8048 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i64:
8049 ; CHECK: # %bb.0: # %entry
8050 ; CHECK-NEXT: vmv1r.v v10, v9
8051 ; CHECK-NEXT: vmv1r.v v9, v8
8052 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8053 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
8054 ; CHECK-NEXT: ret
8055 entry:
8056 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8057 ret void
8058 }
8060 declare void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8061 declare void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8063 define void @test_vsoxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8064 ; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i32:
8065 ; CHECK: # %bb.0: # %entry
8066 ; CHECK-NEXT: vmv1r.v v10, v9
8067 ; CHECK-NEXT: vmv1r.v v9, v8
8068 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8069 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
8070 ; CHECK-NEXT: ret
8071 entry:
8072 tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8073 ret void
8074 }
8076 define void @test_vsoxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8077 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i32:
8078 ; CHECK: # %bb.0: # %entry
8079 ; CHECK-NEXT: vmv1r.v v10, v9
8080 ; CHECK-NEXT: vmv1r.v v9, v8
8081 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8082 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
8083 ; CHECK-NEXT: ret
8084 entry:
8085 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8086 ret void
8087 }
8089 declare void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8090 declare void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8092 define void @test_vsoxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8093 ; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i16:
8094 ; CHECK: # %bb.0: # %entry
8095 ; CHECK-NEXT: vmv1r.v v10, v9
8096 ; CHECK-NEXT: vmv1r.v v9, v8
8097 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8098 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
8099 ; CHECK-NEXT: ret
8100 entry:
8101 tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8102 ret void
8103 }
8105 define void @test_vsoxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8106 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i16:
8107 ; CHECK: # %bb.0: # %entry
8108 ; CHECK-NEXT: vmv1r.v v10, v9
8109 ; CHECK-NEXT: vmv1r.v v9, v8
8110 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8111 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
8112 ; CHECK-NEXT: ret
8113 entry:
8114 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8115 ret void
8116 }
8118 declare void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8119 declare void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8121 define void @test_vsoxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8122 ; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i8:
8123 ; CHECK: # %bb.0: # %entry
8124 ; CHECK-NEXT: vmv1r.v v10, v9
8125 ; CHECK-NEXT: vmv1r.v v9, v8
8126 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8127 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
8128 ; CHECK-NEXT: ret
8129 entry:
8130 tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8131 ret void
8132 }
8134 define void @test_vsoxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8135 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i8:
8136 ; CHECK: # %bb.0: # %entry
8137 ; CHECK-NEXT: vmv1r.v v10, v9
8138 ; CHECK-NEXT: vmv1r.v v9, v8
8139 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8140 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
8141 ; CHECK-NEXT: ret
8142 entry:
8143 tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8144 ret void
8145 }
8147 declare void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8148 declare void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8150 define void @test_vsoxseg3_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8151 ; CHECK-LABEL: test_vsoxseg3_nxv1i8_nxv1i64:
8152 ; CHECK: # %bb.0: # %entry
8153 ; CHECK-NEXT: vmv1r.v v10, v8
8154 ; CHECK-NEXT: vmv1r.v v11, v8
8155 ; CHECK-NEXT: vmv1r.v v12, v8
8156 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8157 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
8158 ; CHECK-NEXT: ret
8159 entry:
8160 tail call void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8161 ret void
8162 }
8164 define void @test_vsoxseg3_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8165 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_nxv1i64:
8166 ; CHECK: # %bb.0: # %entry
8167 ; CHECK-NEXT: vmv1r.v v10, v8
8168 ; CHECK-NEXT: vmv1r.v v11, v8
8169 ; CHECK-NEXT: vmv1r.v v12, v8
8170 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8171 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
8172 ; CHECK-NEXT: ret
8173 entry:
8174 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8175 ret void
8176 }
8178 declare void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8179 declare void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8181 define void @test_vsoxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8182 ; CHECK-LABEL: test_vsoxseg3_nxv1i8_nxv1i32:
8183 ; CHECK: # %bb.0: # %entry
8184 ; CHECK-NEXT: vmv1r.v v10, v8
8185 ; CHECK-NEXT: vmv1r.v v11, v8
8186 ; CHECK-NEXT: vmv1r.v v12, v8
8187 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8188 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
8189 ; CHECK-NEXT: ret
8190 entry:
8191 tail call void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8192 ret void
8193 }
8195 define void @test_vsoxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8196 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_nxv1i32:
8197 ; CHECK: # %bb.0: # %entry
8198 ; CHECK-NEXT: vmv1r.v v10, v8
8199 ; CHECK-NEXT: vmv1r.v v11, v8
8200 ; CHECK-NEXT: vmv1r.v v12, v8
8201 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8202 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
8203 ; CHECK-NEXT: ret
8204 entry:
8205 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8206 ret void
8207 }
8209 declare void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8210 declare void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8212 define void @test_vsoxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8213 ; CHECK-LABEL: test_vsoxseg3_nxv1i8_nxv1i16:
8214 ; CHECK: # %bb.0: # %entry
8215 ; CHECK-NEXT: vmv1r.v v10, v8
8216 ; CHECK-NEXT: vmv1r.v v11, v8
8217 ; CHECK-NEXT: vmv1r.v v12, v8
8218 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8219 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
8220 ; CHECK-NEXT: ret
8221 entry:
8222 tail call void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8223 ret void
8224 }
8226 define void @test_vsoxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8227 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_nxv1i16:
8228 ; CHECK: # %bb.0: # %entry
8229 ; CHECK-NEXT: vmv1r.v v10, v8
8230 ; CHECK-NEXT: vmv1r.v v11, v8
8231 ; CHECK-NEXT: vmv1r.v v12, v8
8232 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8233 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
8234 ; CHECK-NEXT: ret
8235 entry:
8236 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8237 ret void
8238 }
8240 declare void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8241 declare void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8243 define void @test_vsoxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8244 ; CHECK-LABEL: test_vsoxseg3_nxv1i8_nxv1i8:
8245 ; CHECK: # %bb.0: # %entry
8246 ; CHECK-NEXT: vmv1r.v v10, v8
8247 ; CHECK-NEXT: vmv1r.v v11, v8
8248 ; CHECK-NEXT: vmv1r.v v12, v8
8249 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8250 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
8251 ; CHECK-NEXT: ret
8252 entry:
8253 tail call void @llvm.riscv.vsoxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8254 ret void
8255 }
8257 define void @test_vsoxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8258 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_nxv1i8:
8259 ; CHECK: # %bb.0: # %entry
8260 ; CHECK-NEXT: vmv1r.v v10, v8
8261 ; CHECK-NEXT: vmv1r.v v11, v8
8262 ; CHECK-NEXT: vmv1r.v v12, v8
8263 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8264 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
8265 ; CHECK-NEXT: ret
8266 entry:
8267 tail call void @llvm.riscv.vsoxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8268 ret void
8269 }
8271 declare void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8272 declare void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8274 define void @test_vsoxseg4_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8275 ; CHECK-LABEL: test_vsoxseg4_nxv1i8_nxv1i64:
8276 ; CHECK: # %bb.0: # %entry
8277 ; CHECK-NEXT: vmv1r.v v10, v8
8278 ; CHECK-NEXT: vmv1r.v v11, v8
8279 ; CHECK-NEXT: vmv1r.v v12, v8
8280 ; CHECK-NEXT: vmv1r.v v13, v8
8281 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8282 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
8283 ; CHECK-NEXT: ret
8284 entry:
8285 tail call void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8286 ret void
8287 }
8289 define void @test_vsoxseg4_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8290 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_nxv1i64:
8291 ; CHECK: # %bb.0: # %entry
8292 ; CHECK-NEXT: vmv1r.v v10, v8
8293 ; CHECK-NEXT: vmv1r.v v11, v8
8294 ; CHECK-NEXT: vmv1r.v v12, v8
8295 ; CHECK-NEXT: vmv1r.v v13, v8
8296 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8297 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
8298 ; CHECK-NEXT: ret
8299 entry:
8300 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8301 ret void
8302 }
8304 declare void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8305 declare void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8307 define void @test_vsoxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8308 ; CHECK-LABEL: test_vsoxseg4_nxv1i8_nxv1i32:
8309 ; CHECK: # %bb.0: # %entry
8310 ; CHECK-NEXT: vmv1r.v v10, v8
8311 ; CHECK-NEXT: vmv1r.v v11, v8
8312 ; CHECK-NEXT: vmv1r.v v12, v8
8313 ; CHECK-NEXT: vmv1r.v v13, v8
8314 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8315 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
8316 ; CHECK-NEXT: ret
8317 entry:
8318 tail call void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8319 ret void
8320 }
8322 define void @test_vsoxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8323 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_nxv1i32:
8324 ; CHECK: # %bb.0: # %entry
8325 ; CHECK-NEXT: vmv1r.v v10, v8
8326 ; CHECK-NEXT: vmv1r.v v11, v8
8327 ; CHECK-NEXT: vmv1r.v v12, v8
8328 ; CHECK-NEXT: vmv1r.v v13, v8
8329 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8330 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
8331 ; CHECK-NEXT: ret
8332 entry:
8333 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8334 ret void
8335 }
8337 declare void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8338 declare void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8340 define void @test_vsoxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8341 ; CHECK-LABEL: test_vsoxseg4_nxv1i8_nxv1i16:
8342 ; CHECK: # %bb.0: # %entry
8343 ; CHECK-NEXT: vmv1r.v v10, v8
8344 ; CHECK-NEXT: vmv1r.v v11, v8
8345 ; CHECK-NEXT: vmv1r.v v12, v8
8346 ; CHECK-NEXT: vmv1r.v v13, v8
8347 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8348 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
8349 ; CHECK-NEXT: ret
8350 entry:
8351 tail call void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8352 ret void
8353 }
8355 define void @test_vsoxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8356 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_nxv1i16:
8357 ; CHECK: # %bb.0: # %entry
8358 ; CHECK-NEXT: vmv1r.v v10, v8
8359 ; CHECK-NEXT: vmv1r.v v11, v8
8360 ; CHECK-NEXT: vmv1r.v v12, v8
8361 ; CHECK-NEXT: vmv1r.v v13, v8
8362 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8363 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
8364 ; CHECK-NEXT: ret
8365 entry:
8366 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8367 ret void
8368 }
8370 declare void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8371 declare void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8373 define void @test_vsoxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8374 ; CHECK-LABEL: test_vsoxseg4_nxv1i8_nxv1i8:
8375 ; CHECK: # %bb.0: # %entry
8376 ; CHECK-NEXT: vmv1r.v v10, v8
8377 ; CHECK-NEXT: vmv1r.v v11, v8
8378 ; CHECK-NEXT: vmv1r.v v12, v8
8379 ; CHECK-NEXT: vmv1r.v v13, v8
8380 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8381 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
8382 ; CHECK-NEXT: ret
8383 entry:
8384 tail call void @llvm.riscv.vsoxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8385 ret void
8386 }
8388 define void @test_vsoxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8389 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_nxv1i8:
8390 ; CHECK: # %bb.0: # %entry
8391 ; CHECK-NEXT: vmv1r.v v10, v8
8392 ; CHECK-NEXT: vmv1r.v v11, v8
8393 ; CHECK-NEXT: vmv1r.v v12, v8
8394 ; CHECK-NEXT: vmv1r.v v13, v8
8395 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8396 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
8397 ; CHECK-NEXT: ret
8398 entry:
8399 tail call void @llvm.riscv.vsoxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8400 ret void
8401 }
8403 declare void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8404 declare void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8406 define void @test_vsoxseg5_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8407 ; CHECK-LABEL: test_vsoxseg5_nxv1i8_nxv1i64:
8408 ; CHECK: # %bb.0: # %entry
8409 ; CHECK-NEXT: vmv1r.v v10, v8
8410 ; CHECK-NEXT: vmv1r.v v11, v8
8411 ; CHECK-NEXT: vmv1r.v v12, v8
8412 ; CHECK-NEXT: vmv1r.v v13, v8
8413 ; CHECK-NEXT: vmv1r.v v14, v8
8414 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8415 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
8416 ; CHECK-NEXT: ret
8417 entry:
8418 tail call void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8419 ret void
8420 }
8422 define void @test_vsoxseg5_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8423 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_nxv1i64:
8424 ; CHECK: # %bb.0: # %entry
8425 ; CHECK-NEXT: vmv1r.v v10, v8
8426 ; CHECK-NEXT: vmv1r.v v11, v8
8427 ; CHECK-NEXT: vmv1r.v v12, v8
8428 ; CHECK-NEXT: vmv1r.v v13, v8
8429 ; CHECK-NEXT: vmv1r.v v14, v8
8430 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8431 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
8432 ; CHECK-NEXT: ret
8433 entry:
8434 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8435 ret void
8436 }
8438 declare void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8439 declare void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8441 define void @test_vsoxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8442 ; CHECK-LABEL: test_vsoxseg5_nxv1i8_nxv1i32:
8443 ; CHECK: # %bb.0: # %entry
8444 ; CHECK-NEXT: vmv1r.v v10, v8
8445 ; CHECK-NEXT: vmv1r.v v11, v8
8446 ; CHECK-NEXT: vmv1r.v v12, v8
8447 ; CHECK-NEXT: vmv1r.v v13, v8
8448 ; CHECK-NEXT: vmv1r.v v14, v8
8449 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8450 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
8451 ; CHECK-NEXT: ret
8452 entry:
8453 tail call void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8454 ret void
8455 }
8457 define void @test_vsoxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8458 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_nxv1i32:
8459 ; CHECK: # %bb.0: # %entry
8460 ; CHECK-NEXT: vmv1r.v v10, v8
8461 ; CHECK-NEXT: vmv1r.v v11, v8
8462 ; CHECK-NEXT: vmv1r.v v12, v8
8463 ; CHECK-NEXT: vmv1r.v v13, v8
8464 ; CHECK-NEXT: vmv1r.v v14, v8
8465 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8466 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
8467 ; CHECK-NEXT: ret
8468 entry:
8469 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8470 ret void
8471 }
8473 declare void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8474 declare void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8476 define void @test_vsoxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8477 ; CHECK-LABEL: test_vsoxseg5_nxv1i8_nxv1i16:
8478 ; CHECK: # %bb.0: # %entry
8479 ; CHECK-NEXT: vmv1r.v v10, v8
8480 ; CHECK-NEXT: vmv1r.v v11, v8
8481 ; CHECK-NEXT: vmv1r.v v12, v8
8482 ; CHECK-NEXT: vmv1r.v v13, v8
8483 ; CHECK-NEXT: vmv1r.v v14, v8
8484 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8485 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
8486 ; CHECK-NEXT: ret
8487 entry:
8488 tail call void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8489 ret void
8490 }
8492 define void @test_vsoxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8493 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_nxv1i16:
8494 ; CHECK: # %bb.0: # %entry
8495 ; CHECK-NEXT: vmv1r.v v10, v8
8496 ; CHECK-NEXT: vmv1r.v v11, v8
8497 ; CHECK-NEXT: vmv1r.v v12, v8
8498 ; CHECK-NEXT: vmv1r.v v13, v8
8499 ; CHECK-NEXT: vmv1r.v v14, v8
8500 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8501 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
8502 ; CHECK-NEXT: ret
8503 entry:
8504 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8505 ret void
8506 }
8508 declare void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8509 declare void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8511 define void @test_vsoxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8512 ; CHECK-LABEL: test_vsoxseg5_nxv1i8_nxv1i8:
8513 ; CHECK: # %bb.0: # %entry
8514 ; CHECK-NEXT: vmv1r.v v10, v8
8515 ; CHECK-NEXT: vmv1r.v v11, v8
8516 ; CHECK-NEXT: vmv1r.v v12, v8
8517 ; CHECK-NEXT: vmv1r.v v13, v8
8518 ; CHECK-NEXT: vmv1r.v v14, v8
8519 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8520 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
8521 ; CHECK-NEXT: ret
8522 entry:
8523 tail call void @llvm.riscv.vsoxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8524 ret void
8525 }
8527 define void @test_vsoxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8528 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_nxv1i8:
8529 ; CHECK: # %bb.0: # %entry
8530 ; CHECK-NEXT: vmv1r.v v10, v8
8531 ; CHECK-NEXT: vmv1r.v v11, v8
8532 ; CHECK-NEXT: vmv1r.v v12, v8
8533 ; CHECK-NEXT: vmv1r.v v13, v8
8534 ; CHECK-NEXT: vmv1r.v v14, v8
8535 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8536 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
8537 ; CHECK-NEXT: ret
8538 entry:
8539 tail call void @llvm.riscv.vsoxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8540 ret void
8541 }
8543 declare void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8544 declare void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8546 define void @test_vsoxseg6_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8547 ; CHECK-LABEL: test_vsoxseg6_nxv1i8_nxv1i64:
8548 ; CHECK: # %bb.0: # %entry
8549 ; CHECK-NEXT: vmv1r.v v10, v8
8550 ; CHECK-NEXT: vmv1r.v v11, v8
8551 ; CHECK-NEXT: vmv1r.v v12, v8
8552 ; CHECK-NEXT: vmv1r.v v13, v8
8553 ; CHECK-NEXT: vmv1r.v v14, v8
8554 ; CHECK-NEXT: vmv1r.v v15, v8
8555 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8556 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
8557 ; CHECK-NEXT: ret
8558 entry:
8559 tail call void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8560 ret void
8561 }
8563 define void @test_vsoxseg6_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8564 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_nxv1i64:
8565 ; CHECK: # %bb.0: # %entry
8566 ; CHECK-NEXT: vmv1r.v v10, v8
8567 ; CHECK-NEXT: vmv1r.v v11, v8
8568 ; CHECK-NEXT: vmv1r.v v12, v8
8569 ; CHECK-NEXT: vmv1r.v v13, v8
8570 ; CHECK-NEXT: vmv1r.v v14, v8
8571 ; CHECK-NEXT: vmv1r.v v15, v8
8572 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8573 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
8574 ; CHECK-NEXT: ret
8575 entry:
8576 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8577 ret void
8578 }
8580 declare void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8581 declare void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8583 define void @test_vsoxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8584 ; CHECK-LABEL: test_vsoxseg6_nxv1i8_nxv1i32:
8585 ; CHECK: # %bb.0: # %entry
8586 ; CHECK-NEXT: vmv1r.v v10, v8
8587 ; CHECK-NEXT: vmv1r.v v11, v8
8588 ; CHECK-NEXT: vmv1r.v v12, v8
8589 ; CHECK-NEXT: vmv1r.v v13, v8
8590 ; CHECK-NEXT: vmv1r.v v14, v8
8591 ; CHECK-NEXT: vmv1r.v v15, v8
8592 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8593 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
8594 ; CHECK-NEXT: ret
8595 entry:
8596 tail call void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8597 ret void
8598 }
8600 define void @test_vsoxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8601 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_nxv1i32:
8602 ; CHECK: # %bb.0: # %entry
8603 ; CHECK-NEXT: vmv1r.v v10, v8
8604 ; CHECK-NEXT: vmv1r.v v11, v8
8605 ; CHECK-NEXT: vmv1r.v v12, v8
8606 ; CHECK-NEXT: vmv1r.v v13, v8
8607 ; CHECK-NEXT: vmv1r.v v14, v8
8608 ; CHECK-NEXT: vmv1r.v v15, v8
8609 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8610 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
8611 ; CHECK-NEXT: ret
8612 entry:
8613 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8614 ret void
8615 }
8617 declare void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8618 declare void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8620 define void @test_vsoxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8621 ; CHECK-LABEL: test_vsoxseg6_nxv1i8_nxv1i16:
8622 ; CHECK: # %bb.0: # %entry
8623 ; CHECK-NEXT: vmv1r.v v10, v8
8624 ; CHECK-NEXT: vmv1r.v v11, v8
8625 ; CHECK-NEXT: vmv1r.v v12, v8
8626 ; CHECK-NEXT: vmv1r.v v13, v8
8627 ; CHECK-NEXT: vmv1r.v v14, v8
8628 ; CHECK-NEXT: vmv1r.v v15, v8
8629 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8630 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
8631 ; CHECK-NEXT: ret
8632 entry:
8633 tail call void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8634 ret void
8635 }
8637 define void @test_vsoxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8638 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_nxv1i16:
8639 ; CHECK: # %bb.0: # %entry
8640 ; CHECK-NEXT: vmv1r.v v10, v8
8641 ; CHECK-NEXT: vmv1r.v v11, v8
8642 ; CHECK-NEXT: vmv1r.v v12, v8
8643 ; CHECK-NEXT: vmv1r.v v13, v8
8644 ; CHECK-NEXT: vmv1r.v v14, v8
8645 ; CHECK-NEXT: vmv1r.v v15, v8
8646 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8647 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
8648 ; CHECK-NEXT: ret
8649 entry:
8650 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8651 ret void
8652 }
8654 declare void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8655 declare void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8657 define void @test_vsoxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8658 ; CHECK-LABEL: test_vsoxseg6_nxv1i8_nxv1i8:
8659 ; CHECK: # %bb.0: # %entry
8660 ; CHECK-NEXT: vmv1r.v v10, v8
8661 ; CHECK-NEXT: vmv1r.v v11, v8
8662 ; CHECK-NEXT: vmv1r.v v12, v8
8663 ; CHECK-NEXT: vmv1r.v v13, v8
8664 ; CHECK-NEXT: vmv1r.v v14, v8
8665 ; CHECK-NEXT: vmv1r.v v15, v8
8666 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8667 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
8668 ; CHECK-NEXT: ret
8669 entry:
8670 tail call void @llvm.riscv.vsoxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8671 ret void
8672 }
8674 define void @test_vsoxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8675 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_nxv1i8:
8676 ; CHECK: # %bb.0: # %entry
8677 ; CHECK-NEXT: vmv1r.v v10, v8
8678 ; CHECK-NEXT: vmv1r.v v11, v8
8679 ; CHECK-NEXT: vmv1r.v v12, v8
8680 ; CHECK-NEXT: vmv1r.v v13, v8
8681 ; CHECK-NEXT: vmv1r.v v14, v8
8682 ; CHECK-NEXT: vmv1r.v v15, v8
8683 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8684 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
8685 ; CHECK-NEXT: ret
8686 entry:
8687 tail call void @llvm.riscv.vsoxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8688 ret void
8689 }
8691 declare void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8692 declare void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8694 define void @test_vsoxseg7_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8695 ; CHECK-LABEL: test_vsoxseg7_nxv1i8_nxv1i64:
8696 ; CHECK: # %bb.0: # %entry
8697 ; CHECK-NEXT: vmv1r.v v10, v8
8698 ; CHECK-NEXT: vmv1r.v v11, v8
8699 ; CHECK-NEXT: vmv1r.v v12, v8
8700 ; CHECK-NEXT: vmv1r.v v13, v8
8701 ; CHECK-NEXT: vmv1r.v v14, v8
8702 ; CHECK-NEXT: vmv1r.v v15, v8
8703 ; CHECK-NEXT: vmv1r.v v16, v8
8704 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8705 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
8706 ; CHECK-NEXT: ret
8707 entry:
8708 tail call void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8709 ret void
8710 }
8712 define void @test_vsoxseg7_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8713 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_nxv1i64:
8714 ; CHECK: # %bb.0: # %entry
8715 ; CHECK-NEXT: vmv1r.v v10, v8
8716 ; CHECK-NEXT: vmv1r.v v11, v8
8717 ; CHECK-NEXT: vmv1r.v v12, v8
8718 ; CHECK-NEXT: vmv1r.v v13, v8
8719 ; CHECK-NEXT: vmv1r.v v14, v8
8720 ; CHECK-NEXT: vmv1r.v v15, v8
8721 ; CHECK-NEXT: vmv1r.v v16, v8
8722 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8723 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
8724 ; CHECK-NEXT: ret
8725 entry:
8726 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8727 ret void
8728 }
8730 declare void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8731 declare void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8733 define void @test_vsoxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8734 ; CHECK-LABEL: test_vsoxseg7_nxv1i8_nxv1i32:
8735 ; CHECK: # %bb.0: # %entry
8736 ; CHECK-NEXT: vmv1r.v v10, v8
8737 ; CHECK-NEXT: vmv1r.v v11, v8
8738 ; CHECK-NEXT: vmv1r.v v12, v8
8739 ; CHECK-NEXT: vmv1r.v v13, v8
8740 ; CHECK-NEXT: vmv1r.v v14, v8
8741 ; CHECK-NEXT: vmv1r.v v15, v8
8742 ; CHECK-NEXT: vmv1r.v v16, v8
8743 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8744 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
8745 ; CHECK-NEXT: ret
8746 entry:
8747 tail call void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8748 ret void
8749 }
8751 define void @test_vsoxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8752 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_nxv1i32:
8753 ; CHECK: # %bb.0: # %entry
8754 ; CHECK-NEXT: vmv1r.v v10, v8
8755 ; CHECK-NEXT: vmv1r.v v11, v8
8756 ; CHECK-NEXT: vmv1r.v v12, v8
8757 ; CHECK-NEXT: vmv1r.v v13, v8
8758 ; CHECK-NEXT: vmv1r.v v14, v8
8759 ; CHECK-NEXT: vmv1r.v v15, v8
8760 ; CHECK-NEXT: vmv1r.v v16, v8
8761 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8762 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
8763 ; CHECK-NEXT: ret
8764 entry:
8765 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8766 ret void
8767 }
8769 declare void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8770 declare void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8772 define void @test_vsoxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8773 ; CHECK-LABEL: test_vsoxseg7_nxv1i8_nxv1i16:
8774 ; CHECK: # %bb.0: # %entry
8775 ; CHECK-NEXT: vmv1r.v v10, v8
8776 ; CHECK-NEXT: vmv1r.v v11, v8
8777 ; CHECK-NEXT: vmv1r.v v12, v8
8778 ; CHECK-NEXT: vmv1r.v v13, v8
8779 ; CHECK-NEXT: vmv1r.v v14, v8
8780 ; CHECK-NEXT: vmv1r.v v15, v8
8781 ; CHECK-NEXT: vmv1r.v v16, v8
8782 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8783 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
8784 ; CHECK-NEXT: ret
8785 entry:
8786 tail call void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8787 ret void
8788 }
8790 define void @test_vsoxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8791 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_nxv1i16:
8792 ; CHECK: # %bb.0: # %entry
8793 ; CHECK-NEXT: vmv1r.v v10, v8
8794 ; CHECK-NEXT: vmv1r.v v11, v8
8795 ; CHECK-NEXT: vmv1r.v v12, v8
8796 ; CHECK-NEXT: vmv1r.v v13, v8
8797 ; CHECK-NEXT: vmv1r.v v14, v8
8798 ; CHECK-NEXT: vmv1r.v v15, v8
8799 ; CHECK-NEXT: vmv1r.v v16, v8
8800 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8801 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
8802 ; CHECK-NEXT: ret
8803 entry:
8804 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8805 ret void
8806 }
8808 declare void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8809 declare void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8811 define void @test_vsoxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8812 ; CHECK-LABEL: test_vsoxseg7_nxv1i8_nxv1i8:
8813 ; CHECK: # %bb.0: # %entry
8814 ; CHECK-NEXT: vmv1r.v v10, v8
8815 ; CHECK-NEXT: vmv1r.v v11, v8
8816 ; CHECK-NEXT: vmv1r.v v12, v8
8817 ; CHECK-NEXT: vmv1r.v v13, v8
8818 ; CHECK-NEXT: vmv1r.v v14, v8
8819 ; CHECK-NEXT: vmv1r.v v15, v8
8820 ; CHECK-NEXT: vmv1r.v v16, v8
8821 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8822 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
8823 ; CHECK-NEXT: ret
8824 entry:
8825 tail call void @llvm.riscv.vsoxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8826 ret void
8827 }
8829 define void @test_vsoxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8830 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_nxv1i8:
8831 ; CHECK: # %bb.0: # %entry
8832 ; CHECK-NEXT: vmv1r.v v10, v8
8833 ; CHECK-NEXT: vmv1r.v v11, v8
8834 ; CHECK-NEXT: vmv1r.v v12, v8
8835 ; CHECK-NEXT: vmv1r.v v13, v8
8836 ; CHECK-NEXT: vmv1r.v v14, v8
8837 ; CHECK-NEXT: vmv1r.v v15, v8
8838 ; CHECK-NEXT: vmv1r.v v16, v8
8839 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8840 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
8841 ; CHECK-NEXT: ret
8842 entry:
8843 tail call void @llvm.riscv.vsoxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
8844 ret void
8845 }
8847 declare void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, i64)
8848 declare void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
8850 define void @test_vsoxseg8_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
8851 ; CHECK-LABEL: test_vsoxseg8_nxv1i8_nxv1i64:
8852 ; CHECK: # %bb.0: # %entry
8853 ; CHECK-NEXT: vmv1r.v v10, v8
8854 ; CHECK-NEXT: vmv1r.v v11, v8
8855 ; CHECK-NEXT: vmv1r.v v12, v8
8856 ; CHECK-NEXT: vmv1r.v v13, v8
8857 ; CHECK-NEXT: vmv1r.v v14, v8
8858 ; CHECK-NEXT: vmv1r.v v15, v8
8859 ; CHECK-NEXT: vmv1r.v v16, v8
8860 ; CHECK-NEXT: vmv1r.v v17, v8
8861 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8862 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
8863 ; CHECK-NEXT: ret
8864 entry:
8865 tail call void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
8866 ret void
8867 }
8869 define void @test_vsoxseg8_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8870 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_nxv1i64:
8871 ; CHECK: # %bb.0: # %entry
8872 ; CHECK-NEXT: vmv1r.v v10, v8
8873 ; CHECK-NEXT: vmv1r.v v11, v8
8874 ; CHECK-NEXT: vmv1r.v v12, v8
8875 ; CHECK-NEXT: vmv1r.v v13, v8
8876 ; CHECK-NEXT: vmv1r.v v14, v8
8877 ; CHECK-NEXT: vmv1r.v v15, v8
8878 ; CHECK-NEXT: vmv1r.v v16, v8
8879 ; CHECK-NEXT: vmv1r.v v17, v8
8880 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8881 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
8882 ; CHECK-NEXT: ret
8883 entry:
8884 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
8885 ret void
8886 }
8888 declare void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, i64)
8889 declare void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
8891 define void @test_vsoxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
8892 ; CHECK-LABEL: test_vsoxseg8_nxv1i8_nxv1i32:
8893 ; CHECK: # %bb.0: # %entry
8894 ; CHECK-NEXT: vmv1r.v v10, v8
8895 ; CHECK-NEXT: vmv1r.v v11, v8
8896 ; CHECK-NEXT: vmv1r.v v12, v8
8897 ; CHECK-NEXT: vmv1r.v v13, v8
8898 ; CHECK-NEXT: vmv1r.v v14, v8
8899 ; CHECK-NEXT: vmv1r.v v15, v8
8900 ; CHECK-NEXT: vmv1r.v v16, v8
8901 ; CHECK-NEXT: vmv1r.v v17, v8
8902 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8903 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
8904 ; CHECK-NEXT: ret
8905 entry:
8906 tail call void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
8907 ret void
8908 }
8910 define void @test_vsoxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8911 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_nxv1i32:
8912 ; CHECK: # %bb.0: # %entry
8913 ; CHECK-NEXT: vmv1r.v v10, v8
8914 ; CHECK-NEXT: vmv1r.v v11, v8
8915 ; CHECK-NEXT: vmv1r.v v12, v8
8916 ; CHECK-NEXT: vmv1r.v v13, v8
8917 ; CHECK-NEXT: vmv1r.v v14, v8
8918 ; CHECK-NEXT: vmv1r.v v15, v8
8919 ; CHECK-NEXT: vmv1r.v v16, v8
8920 ; CHECK-NEXT: vmv1r.v v17, v8
8921 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8922 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
8923 ; CHECK-NEXT: ret
8924 entry:
8925 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
8926 ret void
8927 }
8929 declare void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, i64)
8930 declare void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
8932 define void @test_vsoxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
8933 ; CHECK-LABEL: test_vsoxseg8_nxv1i8_nxv1i16:
8934 ; CHECK: # %bb.0: # %entry
8935 ; CHECK-NEXT: vmv1r.v v10, v8
8936 ; CHECK-NEXT: vmv1r.v v11, v8
8937 ; CHECK-NEXT: vmv1r.v v12, v8
8938 ; CHECK-NEXT: vmv1r.v v13, v8
8939 ; CHECK-NEXT: vmv1r.v v14, v8
8940 ; CHECK-NEXT: vmv1r.v v15, v8
8941 ; CHECK-NEXT: vmv1r.v v16, v8
8942 ; CHECK-NEXT: vmv1r.v v17, v8
8943 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8944 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
8945 ; CHECK-NEXT: ret
8946 entry:
8947 tail call void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
8948 ret void
8949 }
8951 define void @test_vsoxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8952 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_nxv1i16:
8953 ; CHECK: # %bb.0: # %entry
8954 ; CHECK-NEXT: vmv1r.v v10, v8
8955 ; CHECK-NEXT: vmv1r.v v11, v8
8956 ; CHECK-NEXT: vmv1r.v v12, v8
8957 ; CHECK-NEXT: vmv1r.v v13, v8
8958 ; CHECK-NEXT: vmv1r.v v14, v8
8959 ; CHECK-NEXT: vmv1r.v v15, v8
8960 ; CHECK-NEXT: vmv1r.v v16, v8
8961 ; CHECK-NEXT: vmv1r.v v17, v8
8962 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8963 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
8964 ; CHECK-NEXT: ret
8965 entry:
8966 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
8967 ret void
8968 }
8970 declare void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, i64)
8971 declare void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
8973 define void @test_vsoxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
8974 ; CHECK-LABEL: test_vsoxseg8_nxv1i8_nxv1i8:
8975 ; CHECK: # %bb.0: # %entry
8976 ; CHECK-NEXT: vmv1r.v v10, v8
8977 ; CHECK-NEXT: vmv1r.v v11, v8
8978 ; CHECK-NEXT: vmv1r.v v12, v8
8979 ; CHECK-NEXT: vmv1r.v v13, v8
8980 ; CHECK-NEXT: vmv1r.v v14, v8
8981 ; CHECK-NEXT: vmv1r.v v15, v8
8982 ; CHECK-NEXT: vmv1r.v v16, v8
8983 ; CHECK-NEXT: vmv1r.v v17, v8
8984 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
8985 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
8986 ; CHECK-NEXT: ret
8987 entry:
8988 tail call void @llvm.riscv.vsoxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
8989 ret void
8990 }
8992 define void @test_vsoxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
8993 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_nxv1i8:
8994 ; CHECK: # %bb.0: # %entry
8995 ; CHECK-NEXT: vmv1r.v v10, v8
8996 ; CHECK-NEXT: vmv1r.v v11, v8
8997 ; CHECK-NEXT: vmv1r.v v12, v8
8998 ; CHECK-NEXT: vmv1r.v v13, v8
8999 ; CHECK-NEXT: vmv1r.v v14, v8
9000 ; CHECK-NEXT: vmv1r.v v15, v8
9001 ; CHECK-NEXT: vmv1r.v v16, v8
9002 ; CHECK-NEXT: vmv1r.v v17, v8
9003 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
9004 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
9005 ; CHECK-NEXT: ret
9006 entry:
9007 tail call void @llvm.riscv.vsoxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
9008 ret void
9009 }
9011 declare void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9012 declare void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9014 define void @test_vsoxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9015 ; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i32:
9016 ; CHECK: # %bb.0: # %entry
9017 ; CHECK-NEXT: vmv1r.v v10, v9
9018 ; CHECK-NEXT: vmv1r.v v9, v8
9019 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9020 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
9021 ; CHECK-NEXT: ret
9022 entry:
9023 tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9024 ret void
9025 }
9027 define void @test_vsoxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9028 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i32:
9029 ; CHECK: # %bb.0: # %entry
9030 ; CHECK-NEXT: vmv1r.v v10, v9
9031 ; CHECK-NEXT: vmv1r.v v9, v8
9032 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9033 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
9034 ; CHECK-NEXT: ret
9035 entry:
9036 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9037 ret void
9038 }
9040 declare void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9041 declare void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9043 define void @test_vsoxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9044 ; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i8:
9045 ; CHECK: # %bb.0: # %entry
9046 ; CHECK-NEXT: vmv1r.v v10, v9
9047 ; CHECK-NEXT: vmv1r.v v9, v8
9048 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9049 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
9050 ; CHECK-NEXT: ret
9051 entry:
9052 tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9053 ret void
9054 }
9056 define void @test_vsoxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9057 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i8:
9058 ; CHECK: # %bb.0: # %entry
9059 ; CHECK-NEXT: vmv1r.v v10, v9
9060 ; CHECK-NEXT: vmv1r.v v9, v8
9061 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9062 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
9063 ; CHECK-NEXT: ret
9064 entry:
9065 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9066 ret void
9067 }
9069 declare void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9070 declare void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9072 define void @test_vsoxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9073 ; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i16:
9074 ; CHECK: # %bb.0: # %entry
9075 ; CHECK-NEXT: vmv1r.v v10, v9
9076 ; CHECK-NEXT: vmv1r.v v9, v8
9077 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9078 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
9079 ; CHECK-NEXT: ret
9080 entry:
9081 tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9082 ret void
9083 }
9085 define void @test_vsoxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9086 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i16:
9087 ; CHECK: # %bb.0: # %entry
9088 ; CHECK-NEXT: vmv1r.v v10, v9
9089 ; CHECK-NEXT: vmv1r.v v9, v8
9090 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9091 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
9092 ; CHECK-NEXT: ret
9093 entry:
9094 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9095 ret void
9096 }
9098 declare void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9099 declare void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9101 define void @test_vsoxseg2_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9102 ; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i64:
9103 ; CHECK: # %bb.0: # %entry
9104 ; CHECK-NEXT: vmv1r.v v9, v8
9105 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9106 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
9107 ; CHECK-NEXT: ret
9108 entry:
9109 tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9110 ret void
9111 }
9113 define void @test_vsoxseg2_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9114 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i64:
9115 ; CHECK: # %bb.0: # %entry
9116 ; CHECK-NEXT: vmv1r.v v9, v8
9117 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9118 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
9119 ; CHECK-NEXT: ret
9120 entry:
9121 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9122 ret void
9123 }
9125 declare void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9126 declare void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9128 define void @test_vsoxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9129 ; CHECK-LABEL: test_vsoxseg3_nxv2i8_nxv2i32:
9130 ; CHECK: # %bb.0: # %entry
9131 ; CHECK-NEXT: vmv1r.v v10, v8
9132 ; CHECK-NEXT: vmv1r.v v11, v8
9133 ; CHECK-NEXT: vmv1r.v v12, v8
9134 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9135 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
9136 ; CHECK-NEXT: ret
9137 entry:
9138 tail call void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9139 ret void
9140 }
9142 define void @test_vsoxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9143 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_nxv2i32:
9144 ; CHECK: # %bb.0: # %entry
9145 ; CHECK-NEXT: vmv1r.v v10, v8
9146 ; CHECK-NEXT: vmv1r.v v11, v8
9147 ; CHECK-NEXT: vmv1r.v v12, v8
9148 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9149 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
9150 ; CHECK-NEXT: ret
9151 entry:
9152 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9153 ret void
9154 }
9156 declare void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9157 declare void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9159 define void @test_vsoxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9160 ; CHECK-LABEL: test_vsoxseg3_nxv2i8_nxv2i8:
9161 ; CHECK: # %bb.0: # %entry
9162 ; CHECK-NEXT: vmv1r.v v10, v8
9163 ; CHECK-NEXT: vmv1r.v v11, v8
9164 ; CHECK-NEXT: vmv1r.v v12, v8
9165 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9166 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
9167 ; CHECK-NEXT: ret
9168 entry:
9169 tail call void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9170 ret void
9171 }
9173 define void @test_vsoxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9174 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_nxv2i8:
9175 ; CHECK: # %bb.0: # %entry
9176 ; CHECK-NEXT: vmv1r.v v10, v8
9177 ; CHECK-NEXT: vmv1r.v v11, v8
9178 ; CHECK-NEXT: vmv1r.v v12, v8
9179 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9180 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
9181 ; CHECK-NEXT: ret
9182 entry:
9183 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9184 ret void
9185 }
9187 declare void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9188 declare void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9190 define void @test_vsoxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9191 ; CHECK-LABEL: test_vsoxseg3_nxv2i8_nxv2i16:
9192 ; CHECK: # %bb.0: # %entry
9193 ; CHECK-NEXT: vmv1r.v v10, v8
9194 ; CHECK-NEXT: vmv1r.v v11, v8
9195 ; CHECK-NEXT: vmv1r.v v12, v8
9196 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9197 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
9198 ; CHECK-NEXT: ret
9199 entry:
9200 tail call void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9201 ret void
9202 }
9204 define void @test_vsoxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9205 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_nxv2i16:
9206 ; CHECK: # %bb.0: # %entry
9207 ; CHECK-NEXT: vmv1r.v v10, v8
9208 ; CHECK-NEXT: vmv1r.v v11, v8
9209 ; CHECK-NEXT: vmv1r.v v12, v8
9210 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9211 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
9212 ; CHECK-NEXT: ret
9213 entry:
9214 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9215 ret void
9216 }
9218 declare void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9219 declare void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9221 define void @test_vsoxseg3_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9222 ; CHECK-LABEL: test_vsoxseg3_nxv2i8_nxv2i64:
9223 ; CHECK: # %bb.0: # %entry
9224 ; CHECK-NEXT: vmv1r.v v9, v8
9225 ; CHECK-NEXT: vmv2r.v v12, v10
9226 ; CHECK-NEXT: vmv1r.v v10, v8
9227 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9228 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
9229 ; CHECK-NEXT: ret
9230 entry:
9231 tail call void @llvm.riscv.vsoxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9232 ret void
9233 }
9235 define void @test_vsoxseg3_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9236 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_nxv2i64:
9237 ; CHECK: # %bb.0: # %entry
9238 ; CHECK-NEXT: vmv1r.v v9, v8
9239 ; CHECK-NEXT: vmv2r.v v12, v10
9240 ; CHECK-NEXT: vmv1r.v v10, v8
9241 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9242 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
9243 ; CHECK-NEXT: ret
9244 entry:
9245 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9246 ret void
9247 }
9249 declare void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9250 declare void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9252 define void @test_vsoxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9253 ; CHECK-LABEL: test_vsoxseg4_nxv2i8_nxv2i32:
9254 ; CHECK: # %bb.0: # %entry
9255 ; CHECK-NEXT: vmv1r.v v10, v8
9256 ; CHECK-NEXT: vmv1r.v v11, v8
9257 ; CHECK-NEXT: vmv1r.v v12, v8
9258 ; CHECK-NEXT: vmv1r.v v13, v8
9259 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9260 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
9261 ; CHECK-NEXT: ret
9262 entry:
9263 tail call void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9264 ret void
9265 }
9267 define void @test_vsoxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9268 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_nxv2i32:
9269 ; CHECK: # %bb.0: # %entry
9270 ; CHECK-NEXT: vmv1r.v v10, v8
9271 ; CHECK-NEXT: vmv1r.v v11, v8
9272 ; CHECK-NEXT: vmv1r.v v12, v8
9273 ; CHECK-NEXT: vmv1r.v v13, v8
9274 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9275 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
9276 ; CHECK-NEXT: ret
9277 entry:
9278 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9279 ret void
9280 }
9282 declare void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9283 declare void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9285 define void @test_vsoxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9286 ; CHECK-LABEL: test_vsoxseg4_nxv2i8_nxv2i8:
9287 ; CHECK: # %bb.0: # %entry
9288 ; CHECK-NEXT: vmv1r.v v10, v8
9289 ; CHECK-NEXT: vmv1r.v v11, v8
9290 ; CHECK-NEXT: vmv1r.v v12, v8
9291 ; CHECK-NEXT: vmv1r.v v13, v8
9292 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9293 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
9294 ; CHECK-NEXT: ret
9295 entry:
9296 tail call void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9297 ret void
9298 }
9300 define void @test_vsoxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9301 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_nxv2i8:
9302 ; CHECK: # %bb.0: # %entry
9303 ; CHECK-NEXT: vmv1r.v v10, v8
9304 ; CHECK-NEXT: vmv1r.v v11, v8
9305 ; CHECK-NEXT: vmv1r.v v12, v8
9306 ; CHECK-NEXT: vmv1r.v v13, v8
9307 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9308 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
9309 ; CHECK-NEXT: ret
9310 entry:
9311 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9312 ret void
9313 }
9315 declare void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9316 declare void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9318 define void @test_vsoxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9319 ; CHECK-LABEL: test_vsoxseg4_nxv2i8_nxv2i16:
9320 ; CHECK: # %bb.0: # %entry
9321 ; CHECK-NEXT: vmv1r.v v10, v8
9322 ; CHECK-NEXT: vmv1r.v v11, v8
9323 ; CHECK-NEXT: vmv1r.v v12, v8
9324 ; CHECK-NEXT: vmv1r.v v13, v8
9325 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9326 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
9327 ; CHECK-NEXT: ret
9328 entry:
9329 tail call void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9330 ret void
9331 }
9333 define void @test_vsoxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9334 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_nxv2i16:
9335 ; CHECK: # %bb.0: # %entry
9336 ; CHECK-NEXT: vmv1r.v v10, v8
9337 ; CHECK-NEXT: vmv1r.v v11, v8
9338 ; CHECK-NEXT: vmv1r.v v12, v8
9339 ; CHECK-NEXT: vmv1r.v v13, v8
9340 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9341 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
9342 ; CHECK-NEXT: ret
9343 entry:
9344 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9345 ret void
9346 }
9348 declare void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9349 declare void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9351 define void @test_vsoxseg4_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9352 ; CHECK-LABEL: test_vsoxseg4_nxv2i8_nxv2i64:
9353 ; CHECK: # %bb.0: # %entry
9354 ; CHECK-NEXT: vmv1r.v v12, v8
9355 ; CHECK-NEXT: vmv1r.v v13, v8
9356 ; CHECK-NEXT: vmv1r.v v14, v8
9357 ; CHECK-NEXT: vmv1r.v v15, v8
9358 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9359 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
9360 ; CHECK-NEXT: ret
9361 entry:
9362 tail call void @llvm.riscv.vsoxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9363 ret void
9364 }
9366 define void @test_vsoxseg4_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9367 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_nxv2i64:
9368 ; CHECK: # %bb.0: # %entry
9369 ; CHECK-NEXT: vmv1r.v v12, v8
9370 ; CHECK-NEXT: vmv1r.v v13, v8
9371 ; CHECK-NEXT: vmv1r.v v14, v8
9372 ; CHECK-NEXT: vmv1r.v v15, v8
9373 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9374 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
9375 ; CHECK-NEXT: ret
9376 entry:
9377 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9378 ret void
9379 }
9381 declare void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9382 declare void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9384 define void @test_vsoxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9385 ; CHECK-LABEL: test_vsoxseg5_nxv2i8_nxv2i32:
9386 ; CHECK: # %bb.0: # %entry
9387 ; CHECK-NEXT: vmv1r.v v10, v8
9388 ; CHECK-NEXT: vmv1r.v v11, v8
9389 ; CHECK-NEXT: vmv1r.v v12, v8
9390 ; CHECK-NEXT: vmv1r.v v13, v8
9391 ; CHECK-NEXT: vmv1r.v v14, v8
9392 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9393 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
9394 ; CHECK-NEXT: ret
9395 entry:
9396 tail call void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9397 ret void
9398 }
9400 define void @test_vsoxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9401 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_nxv2i32:
9402 ; CHECK: # %bb.0: # %entry
9403 ; CHECK-NEXT: vmv1r.v v10, v8
9404 ; CHECK-NEXT: vmv1r.v v11, v8
9405 ; CHECK-NEXT: vmv1r.v v12, v8
9406 ; CHECK-NEXT: vmv1r.v v13, v8
9407 ; CHECK-NEXT: vmv1r.v v14, v8
9408 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9409 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
9410 ; CHECK-NEXT: ret
9411 entry:
9412 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9413 ret void
9414 }
9416 declare void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9417 declare void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9419 define void @test_vsoxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9420 ; CHECK-LABEL: test_vsoxseg5_nxv2i8_nxv2i8:
9421 ; CHECK: # %bb.0: # %entry
9422 ; CHECK-NEXT: vmv1r.v v10, v8
9423 ; CHECK-NEXT: vmv1r.v v11, v8
9424 ; CHECK-NEXT: vmv1r.v v12, v8
9425 ; CHECK-NEXT: vmv1r.v v13, v8
9426 ; CHECK-NEXT: vmv1r.v v14, v8
9427 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9428 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
9429 ; CHECK-NEXT: ret
9430 entry:
9431 tail call void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9432 ret void
9433 }
9435 define void @test_vsoxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9436 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_nxv2i8:
9437 ; CHECK: # %bb.0: # %entry
9438 ; CHECK-NEXT: vmv1r.v v10, v8
9439 ; CHECK-NEXT: vmv1r.v v11, v8
9440 ; CHECK-NEXT: vmv1r.v v12, v8
9441 ; CHECK-NEXT: vmv1r.v v13, v8
9442 ; CHECK-NEXT: vmv1r.v v14, v8
9443 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9444 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
9445 ; CHECK-NEXT: ret
9446 entry:
9447 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9448 ret void
9449 }
9451 declare void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9452 declare void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9454 define void @test_vsoxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9455 ; CHECK-LABEL: test_vsoxseg5_nxv2i8_nxv2i16:
9456 ; CHECK: # %bb.0: # %entry
9457 ; CHECK-NEXT: vmv1r.v v10, v8
9458 ; CHECK-NEXT: vmv1r.v v11, v8
9459 ; CHECK-NEXT: vmv1r.v v12, v8
9460 ; CHECK-NEXT: vmv1r.v v13, v8
9461 ; CHECK-NEXT: vmv1r.v v14, v8
9462 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9463 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
9464 ; CHECK-NEXT: ret
9465 entry:
9466 tail call void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9467 ret void
9468 }
9470 define void @test_vsoxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9471 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_nxv2i16:
9472 ; CHECK: # %bb.0: # %entry
9473 ; CHECK-NEXT: vmv1r.v v10, v8
9474 ; CHECK-NEXT: vmv1r.v v11, v8
9475 ; CHECK-NEXT: vmv1r.v v12, v8
9476 ; CHECK-NEXT: vmv1r.v v13, v8
9477 ; CHECK-NEXT: vmv1r.v v14, v8
9478 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9479 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
9480 ; CHECK-NEXT: ret
9481 entry:
9482 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9483 ret void
9484 }
9486 declare void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9487 declare void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9489 define void @test_vsoxseg5_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9490 ; CHECK-LABEL: test_vsoxseg5_nxv2i8_nxv2i64:
9491 ; CHECK: # %bb.0: # %entry
9492 ; CHECK-NEXT: vmv1r.v v12, v8
9493 ; CHECK-NEXT: vmv1r.v v13, v8
9494 ; CHECK-NEXT: vmv1r.v v14, v8
9495 ; CHECK-NEXT: vmv1r.v v15, v8
9496 ; CHECK-NEXT: vmv1r.v v16, v8
9497 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9498 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10
9499 ; CHECK-NEXT: ret
9500 entry:
9501 tail call void @llvm.riscv.vsoxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9502 ret void
9503 }
9505 define void @test_vsoxseg5_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9506 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_nxv2i64:
9507 ; CHECK: # %bb.0: # %entry
9508 ; CHECK-NEXT: vmv1r.v v12, v8
9509 ; CHECK-NEXT: vmv1r.v v13, v8
9510 ; CHECK-NEXT: vmv1r.v v14, v8
9511 ; CHECK-NEXT: vmv1r.v v15, v8
9512 ; CHECK-NEXT: vmv1r.v v16, v8
9513 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9514 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10, v0.t
9515 ; CHECK-NEXT: ret
9516 entry:
9517 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9518 ret void
9519 }
9521 declare void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9522 declare void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9524 define void @test_vsoxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9525 ; CHECK-LABEL: test_vsoxseg6_nxv2i8_nxv2i32:
9526 ; CHECK: # %bb.0: # %entry
9527 ; CHECK-NEXT: vmv1r.v v10, v8
9528 ; CHECK-NEXT: vmv1r.v v11, v8
9529 ; CHECK-NEXT: vmv1r.v v12, v8
9530 ; CHECK-NEXT: vmv1r.v v13, v8
9531 ; CHECK-NEXT: vmv1r.v v14, v8
9532 ; CHECK-NEXT: vmv1r.v v15, v8
9533 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9534 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
9535 ; CHECK-NEXT: ret
9536 entry:
9537 tail call void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9538 ret void
9539 }
9541 define void @test_vsoxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9542 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_nxv2i32:
9543 ; CHECK: # %bb.0: # %entry
9544 ; CHECK-NEXT: vmv1r.v v10, v8
9545 ; CHECK-NEXT: vmv1r.v v11, v8
9546 ; CHECK-NEXT: vmv1r.v v12, v8
9547 ; CHECK-NEXT: vmv1r.v v13, v8
9548 ; CHECK-NEXT: vmv1r.v v14, v8
9549 ; CHECK-NEXT: vmv1r.v v15, v8
9550 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9551 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
9552 ; CHECK-NEXT: ret
9553 entry:
9554 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9555 ret void
9556 }
9558 declare void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9559 declare void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9561 define void @test_vsoxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9562 ; CHECK-LABEL: test_vsoxseg6_nxv2i8_nxv2i8:
9563 ; CHECK: # %bb.0: # %entry
9564 ; CHECK-NEXT: vmv1r.v v10, v8
9565 ; CHECK-NEXT: vmv1r.v v11, v8
9566 ; CHECK-NEXT: vmv1r.v v12, v8
9567 ; CHECK-NEXT: vmv1r.v v13, v8
9568 ; CHECK-NEXT: vmv1r.v v14, v8
9569 ; CHECK-NEXT: vmv1r.v v15, v8
9570 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9571 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
9572 ; CHECK-NEXT: ret
9573 entry:
9574 tail call void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9575 ret void
9576 }
9578 define void @test_vsoxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9579 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_nxv2i8:
9580 ; CHECK: # %bb.0: # %entry
9581 ; CHECK-NEXT: vmv1r.v v10, v8
9582 ; CHECK-NEXT: vmv1r.v v11, v8
9583 ; CHECK-NEXT: vmv1r.v v12, v8
9584 ; CHECK-NEXT: vmv1r.v v13, v8
9585 ; CHECK-NEXT: vmv1r.v v14, v8
9586 ; CHECK-NEXT: vmv1r.v v15, v8
9587 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9588 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
9589 ; CHECK-NEXT: ret
9590 entry:
9591 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9592 ret void
9593 }
9595 declare void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9596 declare void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9598 define void @test_vsoxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9599 ; CHECK-LABEL: test_vsoxseg6_nxv2i8_nxv2i16:
9600 ; CHECK: # %bb.0: # %entry
9601 ; CHECK-NEXT: vmv1r.v v10, v8
9602 ; CHECK-NEXT: vmv1r.v v11, v8
9603 ; CHECK-NEXT: vmv1r.v v12, v8
9604 ; CHECK-NEXT: vmv1r.v v13, v8
9605 ; CHECK-NEXT: vmv1r.v v14, v8
9606 ; CHECK-NEXT: vmv1r.v v15, v8
9607 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9608 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
9609 ; CHECK-NEXT: ret
9610 entry:
9611 tail call void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9612 ret void
9613 }
9615 define void @test_vsoxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9616 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_nxv2i16:
9617 ; CHECK: # %bb.0: # %entry
9618 ; CHECK-NEXT: vmv1r.v v10, v8
9619 ; CHECK-NEXT: vmv1r.v v11, v8
9620 ; CHECK-NEXT: vmv1r.v v12, v8
9621 ; CHECK-NEXT: vmv1r.v v13, v8
9622 ; CHECK-NEXT: vmv1r.v v14, v8
9623 ; CHECK-NEXT: vmv1r.v v15, v8
9624 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9625 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
9626 ; CHECK-NEXT: ret
9627 entry:
9628 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9629 ret void
9630 }
9632 declare void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9633 declare void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9635 define void @test_vsoxseg6_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9636 ; CHECK-LABEL: test_vsoxseg6_nxv2i8_nxv2i64:
9637 ; CHECK: # %bb.0: # %entry
9638 ; CHECK-NEXT: vmv1r.v v12, v8
9639 ; CHECK-NEXT: vmv1r.v v13, v8
9640 ; CHECK-NEXT: vmv1r.v v14, v8
9641 ; CHECK-NEXT: vmv1r.v v15, v8
9642 ; CHECK-NEXT: vmv1r.v v16, v8
9643 ; CHECK-NEXT: vmv1r.v v17, v8
9644 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9645 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10
9646 ; CHECK-NEXT: ret
9647 entry:
9648 tail call void @llvm.riscv.vsoxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9649 ret void
9650 }
9652 define void @test_vsoxseg6_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9653 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_nxv2i64:
9654 ; CHECK: # %bb.0: # %entry
9655 ; CHECK-NEXT: vmv1r.v v12, v8
9656 ; CHECK-NEXT: vmv1r.v v13, v8
9657 ; CHECK-NEXT: vmv1r.v v14, v8
9658 ; CHECK-NEXT: vmv1r.v v15, v8
9659 ; CHECK-NEXT: vmv1r.v v16, v8
9660 ; CHECK-NEXT: vmv1r.v v17, v8
9661 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9662 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10, v0.t
9663 ; CHECK-NEXT: ret
9664 entry:
9665 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9666 ret void
9667 }
9669 declare void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9670 declare void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9672 define void @test_vsoxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9673 ; CHECK-LABEL: test_vsoxseg7_nxv2i8_nxv2i32:
9674 ; CHECK: # %bb.0: # %entry
9675 ; CHECK-NEXT: vmv1r.v v10, v8
9676 ; CHECK-NEXT: vmv1r.v v11, v8
9677 ; CHECK-NEXT: vmv1r.v v12, v8
9678 ; CHECK-NEXT: vmv1r.v v13, v8
9679 ; CHECK-NEXT: vmv1r.v v14, v8
9680 ; CHECK-NEXT: vmv1r.v v15, v8
9681 ; CHECK-NEXT: vmv1r.v v16, v8
9682 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9683 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
9684 ; CHECK-NEXT: ret
9685 entry:
9686 tail call void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9687 ret void
9688 }
9690 define void @test_vsoxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9691 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_nxv2i32:
9692 ; CHECK: # %bb.0: # %entry
9693 ; CHECK-NEXT: vmv1r.v v10, v8
9694 ; CHECK-NEXT: vmv1r.v v11, v8
9695 ; CHECK-NEXT: vmv1r.v v12, v8
9696 ; CHECK-NEXT: vmv1r.v v13, v8
9697 ; CHECK-NEXT: vmv1r.v v14, v8
9698 ; CHECK-NEXT: vmv1r.v v15, v8
9699 ; CHECK-NEXT: vmv1r.v v16, v8
9700 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9701 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
9702 ; CHECK-NEXT: ret
9703 entry:
9704 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9705 ret void
9706 }
9708 declare void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9709 declare void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9711 define void @test_vsoxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9712 ; CHECK-LABEL: test_vsoxseg7_nxv2i8_nxv2i8:
9713 ; CHECK: # %bb.0: # %entry
9714 ; CHECK-NEXT: vmv1r.v v10, v8
9715 ; CHECK-NEXT: vmv1r.v v11, v8
9716 ; CHECK-NEXT: vmv1r.v v12, v8
9717 ; CHECK-NEXT: vmv1r.v v13, v8
9718 ; CHECK-NEXT: vmv1r.v v14, v8
9719 ; CHECK-NEXT: vmv1r.v v15, v8
9720 ; CHECK-NEXT: vmv1r.v v16, v8
9721 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9722 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
9723 ; CHECK-NEXT: ret
9724 entry:
9725 tail call void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9726 ret void
9727 }
9729 define void @test_vsoxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9730 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_nxv2i8:
9731 ; CHECK: # %bb.0: # %entry
9732 ; CHECK-NEXT: vmv1r.v v10, v8
9733 ; CHECK-NEXT: vmv1r.v v11, v8
9734 ; CHECK-NEXT: vmv1r.v v12, v8
9735 ; CHECK-NEXT: vmv1r.v v13, v8
9736 ; CHECK-NEXT: vmv1r.v v14, v8
9737 ; CHECK-NEXT: vmv1r.v v15, v8
9738 ; CHECK-NEXT: vmv1r.v v16, v8
9739 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9740 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
9741 ; CHECK-NEXT: ret
9742 entry:
9743 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9744 ret void
9745 }
9747 declare void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9748 declare void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9750 define void @test_vsoxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9751 ; CHECK-LABEL: test_vsoxseg7_nxv2i8_nxv2i16:
9752 ; CHECK: # %bb.0: # %entry
9753 ; CHECK-NEXT: vmv1r.v v10, v8
9754 ; CHECK-NEXT: vmv1r.v v11, v8
9755 ; CHECK-NEXT: vmv1r.v v12, v8
9756 ; CHECK-NEXT: vmv1r.v v13, v8
9757 ; CHECK-NEXT: vmv1r.v v14, v8
9758 ; CHECK-NEXT: vmv1r.v v15, v8
9759 ; CHECK-NEXT: vmv1r.v v16, v8
9760 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9761 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
9762 ; CHECK-NEXT: ret
9763 entry:
9764 tail call void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9765 ret void
9766 }
9768 define void @test_vsoxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9769 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_nxv2i16:
9770 ; CHECK: # %bb.0: # %entry
9771 ; CHECK-NEXT: vmv1r.v v10, v8
9772 ; CHECK-NEXT: vmv1r.v v11, v8
9773 ; CHECK-NEXT: vmv1r.v v12, v8
9774 ; CHECK-NEXT: vmv1r.v v13, v8
9775 ; CHECK-NEXT: vmv1r.v v14, v8
9776 ; CHECK-NEXT: vmv1r.v v15, v8
9777 ; CHECK-NEXT: vmv1r.v v16, v8
9778 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9779 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
9780 ; CHECK-NEXT: ret
9781 entry:
9782 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9783 ret void
9784 }
9786 declare void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9787 declare void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9789 define void @test_vsoxseg7_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9790 ; CHECK-LABEL: test_vsoxseg7_nxv2i8_nxv2i64:
9791 ; CHECK: # %bb.0: # %entry
9792 ; CHECK-NEXT: vmv1r.v v12, v8
9793 ; CHECK-NEXT: vmv1r.v v13, v8
9794 ; CHECK-NEXT: vmv1r.v v14, v8
9795 ; CHECK-NEXT: vmv1r.v v15, v8
9796 ; CHECK-NEXT: vmv1r.v v16, v8
9797 ; CHECK-NEXT: vmv1r.v v17, v8
9798 ; CHECK-NEXT: vmv1r.v v18, v8
9799 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9800 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10
9801 ; CHECK-NEXT: ret
9802 entry:
9803 tail call void @llvm.riscv.vsoxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9804 ret void
9805 }
9807 define void @test_vsoxseg7_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9808 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_nxv2i64:
9809 ; CHECK: # %bb.0: # %entry
9810 ; CHECK-NEXT: vmv1r.v v12, v8
9811 ; CHECK-NEXT: vmv1r.v v13, v8
9812 ; CHECK-NEXT: vmv1r.v v14, v8
9813 ; CHECK-NEXT: vmv1r.v v15, v8
9814 ; CHECK-NEXT: vmv1r.v v16, v8
9815 ; CHECK-NEXT: vmv1r.v v17, v8
9816 ; CHECK-NEXT: vmv1r.v v18, v8
9817 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9818 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10, v0.t
9819 ; CHECK-NEXT: ret
9820 entry:
9821 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9822 ret void
9823 }
9825 declare void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, i64)
9826 declare void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
9828 define void @test_vsoxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
9829 ; CHECK-LABEL: test_vsoxseg8_nxv2i8_nxv2i32:
9830 ; CHECK: # %bb.0: # %entry
9831 ; CHECK-NEXT: vmv1r.v v10, v8
9832 ; CHECK-NEXT: vmv1r.v v11, v8
9833 ; CHECK-NEXT: vmv1r.v v12, v8
9834 ; CHECK-NEXT: vmv1r.v v13, v8
9835 ; CHECK-NEXT: vmv1r.v v14, v8
9836 ; CHECK-NEXT: vmv1r.v v15, v8
9837 ; CHECK-NEXT: vmv1r.v v16, v8
9838 ; CHECK-NEXT: vmv1r.v v17, v8
9839 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9840 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
9841 ; CHECK-NEXT: ret
9842 entry:
9843 tail call void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
9844 ret void
9845 }
9847 define void @test_vsoxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9848 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_nxv2i32:
9849 ; CHECK: # %bb.0: # %entry
9850 ; CHECK-NEXT: vmv1r.v v10, v8
9851 ; CHECK-NEXT: vmv1r.v v11, v8
9852 ; CHECK-NEXT: vmv1r.v v12, v8
9853 ; CHECK-NEXT: vmv1r.v v13, v8
9854 ; CHECK-NEXT: vmv1r.v v14, v8
9855 ; CHECK-NEXT: vmv1r.v v15, v8
9856 ; CHECK-NEXT: vmv1r.v v16, v8
9857 ; CHECK-NEXT: vmv1r.v v17, v8
9858 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9859 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
9860 ; CHECK-NEXT: ret
9861 entry:
9862 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
9863 ret void
9864 }
9866 declare void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, i64)
9867 declare void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
9869 define void @test_vsoxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
9870 ; CHECK-LABEL: test_vsoxseg8_nxv2i8_nxv2i8:
9871 ; CHECK: # %bb.0: # %entry
9872 ; CHECK-NEXT: vmv1r.v v10, v8
9873 ; CHECK-NEXT: vmv1r.v v11, v8
9874 ; CHECK-NEXT: vmv1r.v v12, v8
9875 ; CHECK-NEXT: vmv1r.v v13, v8
9876 ; CHECK-NEXT: vmv1r.v v14, v8
9877 ; CHECK-NEXT: vmv1r.v v15, v8
9878 ; CHECK-NEXT: vmv1r.v v16, v8
9879 ; CHECK-NEXT: vmv1r.v v17, v8
9880 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9881 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
9882 ; CHECK-NEXT: ret
9883 entry:
9884 tail call void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
9885 ret void
9886 }
9888 define void @test_vsoxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9889 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_nxv2i8:
9890 ; CHECK: # %bb.0: # %entry
9891 ; CHECK-NEXT: vmv1r.v v10, v8
9892 ; CHECK-NEXT: vmv1r.v v11, v8
9893 ; CHECK-NEXT: vmv1r.v v12, v8
9894 ; CHECK-NEXT: vmv1r.v v13, v8
9895 ; CHECK-NEXT: vmv1r.v v14, v8
9896 ; CHECK-NEXT: vmv1r.v v15, v8
9897 ; CHECK-NEXT: vmv1r.v v16, v8
9898 ; CHECK-NEXT: vmv1r.v v17, v8
9899 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9900 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
9901 ; CHECK-NEXT: ret
9902 entry:
9903 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
9904 ret void
9905 }
9907 declare void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, i64)
9908 declare void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
9910 define void @test_vsoxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
9911 ; CHECK-LABEL: test_vsoxseg8_nxv2i8_nxv2i16:
9912 ; CHECK: # %bb.0: # %entry
9913 ; CHECK-NEXT: vmv1r.v v10, v8
9914 ; CHECK-NEXT: vmv1r.v v11, v8
9915 ; CHECK-NEXT: vmv1r.v v12, v8
9916 ; CHECK-NEXT: vmv1r.v v13, v8
9917 ; CHECK-NEXT: vmv1r.v v14, v8
9918 ; CHECK-NEXT: vmv1r.v v15, v8
9919 ; CHECK-NEXT: vmv1r.v v16, v8
9920 ; CHECK-NEXT: vmv1r.v v17, v8
9921 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9922 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
9923 ; CHECK-NEXT: ret
9924 entry:
9925 tail call void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
9926 ret void
9927 }
9929 define void @test_vsoxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9930 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_nxv2i16:
9931 ; CHECK: # %bb.0: # %entry
9932 ; CHECK-NEXT: vmv1r.v v10, v8
9933 ; CHECK-NEXT: vmv1r.v v11, v8
9934 ; CHECK-NEXT: vmv1r.v v12, v8
9935 ; CHECK-NEXT: vmv1r.v v13, v8
9936 ; CHECK-NEXT: vmv1r.v v14, v8
9937 ; CHECK-NEXT: vmv1r.v v15, v8
9938 ; CHECK-NEXT: vmv1r.v v16, v8
9939 ; CHECK-NEXT: vmv1r.v v17, v8
9940 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9941 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
9942 ; CHECK-NEXT: ret
9943 entry:
9944 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
9945 ret void
9946 }
9948 declare void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, i64)
9949 declare void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
9951 define void @test_vsoxseg8_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
9952 ; CHECK-LABEL: test_vsoxseg8_nxv2i8_nxv2i64:
9953 ; CHECK: # %bb.0: # %entry
9954 ; CHECK-NEXT: vmv1r.v v12, v8
9955 ; CHECK-NEXT: vmv1r.v v13, v8
9956 ; CHECK-NEXT: vmv1r.v v14, v8
9957 ; CHECK-NEXT: vmv1r.v v15, v8
9958 ; CHECK-NEXT: vmv1r.v v16, v8
9959 ; CHECK-NEXT: vmv1r.v v17, v8
9960 ; CHECK-NEXT: vmv1r.v v18, v8
9961 ; CHECK-NEXT: vmv1r.v v19, v8
9962 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9963 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10
9964 ; CHECK-NEXT: ret
9965 entry:
9966 tail call void @llvm.riscv.vsoxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
9967 ret void
9968 }
9970 define void @test_vsoxseg8_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
9971 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_nxv2i64:
9972 ; CHECK: # %bb.0: # %entry
9973 ; CHECK-NEXT: vmv1r.v v12, v8
9974 ; CHECK-NEXT: vmv1r.v v13, v8
9975 ; CHECK-NEXT: vmv1r.v v14, v8
9976 ; CHECK-NEXT: vmv1r.v v15, v8
9977 ; CHECK-NEXT: vmv1r.v v16, v8
9978 ; CHECK-NEXT: vmv1r.v v17, v8
9979 ; CHECK-NEXT: vmv1r.v v18, v8
9980 ; CHECK-NEXT: vmv1r.v v19, v8
9981 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
9982 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10, v0.t
9983 ; CHECK-NEXT: ret
9984 entry:
9985 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
9986 ret void
9987 }
9989 declare void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i16>, i64)
9990 declare void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
9992 define void @test_vsoxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
9993 ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i16:
9994 ; CHECK: # %bb.0: # %entry
9995 ; CHECK-NEXT: vmv2r.v v16, v12
9996 ; CHECK-NEXT: vmv4r.v v12, v8
9997 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
9998 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
9999 ; CHECK-NEXT: ret
10000 entry:
10001 tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
10002 ret void
10003 }
10005 define void @test_vsoxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
10006 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i16:
10007 ; CHECK: # %bb.0: # %entry
10008 ; CHECK-NEXT: vmv2r.v v16, v12
10009 ; CHECK-NEXT: vmv4r.v v12, v8
10010 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10011 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
10012 ; CHECK-NEXT: ret
10013 entry:
10014 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
10015 ret void
10016 }
10018 declare void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i8>, i64)
10019 declare void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
10021 define void @test_vsoxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
10022 ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i8:
10023 ; CHECK: # %bb.0: # %entry
10024 ; CHECK-NEXT: vmv1r.v v16, v12
10025 ; CHECK-NEXT: vmv4r.v v12, v8
10026 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10027 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
10028 ; CHECK-NEXT: ret
10029 entry:
10030 tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
10031 ret void
10032 }
10034 define void @test_vsoxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
10035 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i8:
10036 ; CHECK: # %bb.0: # %entry
10037 ; CHECK-NEXT: vmv1r.v v16, v12
10038 ; CHECK-NEXT: vmv4r.v v12, v8
10039 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10040 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
10041 ; CHECK-NEXT: ret
10042 entry:
10043 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
10044 ret void
10045 }
10047 declare void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i64>, i64)
10048 declare void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
10050 define void @test_vsoxseg2_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
10051 ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i64:
10052 ; CHECK: # %bb.0: # %entry
10053 ; CHECK-NEXT: vmv4r.v v12, v8
10054 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10055 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
10056 ; CHECK-NEXT: ret
10057 entry:
10058 tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
10059 ret void
10060 }
10062 define void @test_vsoxseg2_mask_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
10063 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i64:
10064 ; CHECK: # %bb.0: # %entry
10065 ; CHECK-NEXT: vmv4r.v v12, v8
10066 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10067 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
10068 ; CHECK-NEXT: ret
10069 entry:
10070 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
10071 ret void
10072 }
10074 declare void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i32>, i64)
10075 declare void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
10077 define void @test_vsoxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
10078 ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i32:
10079 ; CHECK: # %bb.0: # %entry
10080 ; CHECK-NEXT: vmv4r.v v16, v12
10081 ; CHECK-NEXT: vmv4r.v v12, v8
10082 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10083 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
10084 ; CHECK-NEXT: ret
10085 entry:
10086 tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
10087 ret void
10088 }
10090 define void @test_vsoxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
10091 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i32:
10092 ; CHECK: # %bb.0: # %entry
10093 ; CHECK-NEXT: vmv4r.v v16, v12
10094 ; CHECK-NEXT: vmv4r.v v12, v8
10095 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
10096 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
10097 ; CHECK-NEXT: ret
10098 entry:
10099 tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
10100 ret void
10101 }
10103 declare void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, ptr, <vscale x 32 x i16>, i64)
10104 declare void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, ptr, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
10106 define void @test_vsoxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i16> %index, i64 %vl) {
10107 ; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i16:
10108 ; CHECK: # %bb.0: # %entry
10109 ; CHECK-NEXT: vmv4r.v v12, v8
10110 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
10111 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
10112 ; CHECK-NEXT: ret
10113 entry:
10114 tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i16> %index, i64 %vl)
10115 ret void
10116 }
10118 define void @test_vsoxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
10119 ; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i16:
10120 ; CHECK: # %bb.0: # %entry
10121 ; CHECK-NEXT: vmv4r.v v12, v8
10122 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
10123 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
10124 ; CHECK-NEXT: ret
10125 entry:
10126 tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
10127 ret void
10128 }
10130 declare void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, ptr, <vscale x 32 x i8>, i64)
10131 declare void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, ptr, <vscale x 32 x i8>, <vscale x 32 x i1>, i64)
10133 define void @test_vsoxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i8> %index, i64 %vl) {
10134 ; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i8:
10135 ; CHECK: # %bb.0: # %entry
10136 ; CHECK-NEXT: vmv4r.v v16, v12
10137 ; CHECK-NEXT: vmv4r.v v12, v8
10138 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
10139 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
10140 ; CHECK-NEXT: ret
10141 entry:
10142 tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i8> %index, i64 %vl)
10143 ret void
10144 }
10146 define void @test_vsoxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
10147 ; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i8:
10148 ; CHECK: # %bb.0: # %entry
10149 ; CHECK-NEXT: vmv4r.v v16, v12
10150 ; CHECK-NEXT: vmv4r.v v12, v8
10151 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
10152 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
10153 ; CHECK-NEXT: ret
10154 entry:
10155 tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, ptr %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
10156 ret void
10157 }
10159 declare void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10160 declare void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10162 define void @test_vsoxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10163 ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i32:
10164 ; CHECK: # %bb.0: # %entry
10165 ; CHECK-NEXT: vmv1r.v v10, v9
10166 ; CHECK-NEXT: vmv1r.v v9, v8
10167 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10168 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
10169 ; CHECK-NEXT: ret
10170 entry:
10171 tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10172 ret void
10173 }
10175 define void @test_vsoxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10176 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i32:
10177 ; CHECK: # %bb.0: # %entry
10178 ; CHECK-NEXT: vmv1r.v v10, v9
10179 ; CHECK-NEXT: vmv1r.v v9, v8
10180 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10181 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
10182 ; CHECK-NEXT: ret
10183 entry:
10184 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10185 ret void
10186 }
10188 declare void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10189 declare void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10191 define void @test_vsoxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10192 ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i8:
10193 ; CHECK: # %bb.0: # %entry
10194 ; CHECK-NEXT: vmv1r.v v10, v9
10195 ; CHECK-NEXT: vmv1r.v v9, v8
10196 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10197 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
10198 ; CHECK-NEXT: ret
10199 entry:
10200 tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10201 ret void
10202 }
10204 define void @test_vsoxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10205 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i8:
10206 ; CHECK: # %bb.0: # %entry
10207 ; CHECK-NEXT: vmv1r.v v10, v9
10208 ; CHECK-NEXT: vmv1r.v v9, v8
10209 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10210 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
10211 ; CHECK-NEXT: ret
10212 entry:
10213 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10214 ret void
10215 }
10217 declare void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10218 declare void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10220 define void @test_vsoxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10221 ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i16:
10222 ; CHECK: # %bb.0: # %entry
10223 ; CHECK-NEXT: vmv1r.v v10, v9
10224 ; CHECK-NEXT: vmv1r.v v9, v8
10225 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10226 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
10227 ; CHECK-NEXT: ret
10228 entry:
10229 tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10230 ret void
10231 }
10233 define void @test_vsoxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10234 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i16:
10235 ; CHECK: # %bb.0: # %entry
10236 ; CHECK-NEXT: vmv1r.v v10, v9
10237 ; CHECK-NEXT: vmv1r.v v9, v8
10238 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10239 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
10240 ; CHECK-NEXT: ret
10241 entry:
10242 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10243 ret void
10244 }
10246 declare void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10247 declare void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10249 define void @test_vsoxseg2_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10250 ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i64:
10251 ; CHECK: # %bb.0: # %entry
10252 ; CHECK-NEXT: vmv1r.v v9, v8
10253 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10254 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
10255 ; CHECK-NEXT: ret
10256 entry:
10257 tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10258 ret void
10259 }
10261 define void @test_vsoxseg2_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10262 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i64:
10263 ; CHECK: # %bb.0: # %entry
10264 ; CHECK-NEXT: vmv1r.v v9, v8
10265 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10266 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
10267 ; CHECK-NEXT: ret
10268 entry:
10269 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10270 ret void
10271 }
10273 declare void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10274 declare void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10276 define void @test_vsoxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10277 ; CHECK-LABEL: test_vsoxseg3_nxv2i16_nxv2i32:
10278 ; CHECK: # %bb.0: # %entry
10279 ; CHECK-NEXT: vmv1r.v v10, v8
10280 ; CHECK-NEXT: vmv1r.v v11, v8
10281 ; CHECK-NEXT: vmv1r.v v12, v8
10282 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10283 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
10284 ; CHECK-NEXT: ret
10285 entry:
10286 tail call void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10287 ret void
10288 }
10290 define void @test_vsoxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10291 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_nxv2i32:
10292 ; CHECK: # %bb.0: # %entry
10293 ; CHECK-NEXT: vmv1r.v v10, v8
10294 ; CHECK-NEXT: vmv1r.v v11, v8
10295 ; CHECK-NEXT: vmv1r.v v12, v8
10296 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10297 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
10298 ; CHECK-NEXT: ret
10299 entry:
10300 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10301 ret void
10302 }
10304 declare void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10305 declare void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10307 define void @test_vsoxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10308 ; CHECK-LABEL: test_vsoxseg3_nxv2i16_nxv2i8:
10309 ; CHECK: # %bb.0: # %entry
10310 ; CHECK-NEXT: vmv1r.v v10, v8
10311 ; CHECK-NEXT: vmv1r.v v11, v8
10312 ; CHECK-NEXT: vmv1r.v v12, v8
10313 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10314 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
10315 ; CHECK-NEXT: ret
10316 entry:
10317 tail call void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10318 ret void
10319 }
10321 define void @test_vsoxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10322 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_nxv2i8:
10323 ; CHECK: # %bb.0: # %entry
10324 ; CHECK-NEXT: vmv1r.v v10, v8
10325 ; CHECK-NEXT: vmv1r.v v11, v8
10326 ; CHECK-NEXT: vmv1r.v v12, v8
10327 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10328 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
10329 ; CHECK-NEXT: ret
10330 entry:
10331 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10332 ret void
10333 }
10335 declare void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10336 declare void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10338 define void @test_vsoxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10339 ; CHECK-LABEL: test_vsoxseg3_nxv2i16_nxv2i16:
10340 ; CHECK: # %bb.0: # %entry
10341 ; CHECK-NEXT: vmv1r.v v10, v8
10342 ; CHECK-NEXT: vmv1r.v v11, v8
10343 ; CHECK-NEXT: vmv1r.v v12, v8
10344 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10345 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
10346 ; CHECK-NEXT: ret
10347 entry:
10348 tail call void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10349 ret void
10350 }
10352 define void @test_vsoxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10353 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_nxv2i16:
10354 ; CHECK: # %bb.0: # %entry
10355 ; CHECK-NEXT: vmv1r.v v10, v8
10356 ; CHECK-NEXT: vmv1r.v v11, v8
10357 ; CHECK-NEXT: vmv1r.v v12, v8
10358 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10359 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
10360 ; CHECK-NEXT: ret
10361 entry:
10362 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10363 ret void
10364 }
10366 declare void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10367 declare void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10369 define void @test_vsoxseg3_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10370 ; CHECK-LABEL: test_vsoxseg3_nxv2i16_nxv2i64:
10371 ; CHECK: # %bb.0: # %entry
10372 ; CHECK-NEXT: vmv1r.v v9, v8
10373 ; CHECK-NEXT: vmv2r.v v12, v10
10374 ; CHECK-NEXT: vmv1r.v v10, v8
10375 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10376 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
10377 ; CHECK-NEXT: ret
10378 entry:
10379 tail call void @llvm.riscv.vsoxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10380 ret void
10381 }
10383 define void @test_vsoxseg3_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10384 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_nxv2i64:
10385 ; CHECK: # %bb.0: # %entry
10386 ; CHECK-NEXT: vmv1r.v v9, v8
10387 ; CHECK-NEXT: vmv2r.v v12, v10
10388 ; CHECK-NEXT: vmv1r.v v10, v8
10389 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10390 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
10391 ; CHECK-NEXT: ret
10392 entry:
10393 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10394 ret void
10395 }
10397 declare void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10398 declare void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10400 define void @test_vsoxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10401 ; CHECK-LABEL: test_vsoxseg4_nxv2i16_nxv2i32:
10402 ; CHECK: # %bb.0: # %entry
10403 ; CHECK-NEXT: vmv1r.v v10, v8
10404 ; CHECK-NEXT: vmv1r.v v11, v8
10405 ; CHECK-NEXT: vmv1r.v v12, v8
10406 ; CHECK-NEXT: vmv1r.v v13, v8
10407 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10408 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
10409 ; CHECK-NEXT: ret
10410 entry:
10411 tail call void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10412 ret void
10413 }
10415 define void @test_vsoxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10416 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_nxv2i32:
10417 ; CHECK: # %bb.0: # %entry
10418 ; CHECK-NEXT: vmv1r.v v10, v8
10419 ; CHECK-NEXT: vmv1r.v v11, v8
10420 ; CHECK-NEXT: vmv1r.v v12, v8
10421 ; CHECK-NEXT: vmv1r.v v13, v8
10422 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10423 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
10424 ; CHECK-NEXT: ret
10425 entry:
10426 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10427 ret void
10428 }
10430 declare void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10431 declare void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10433 define void @test_vsoxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10434 ; CHECK-LABEL: test_vsoxseg4_nxv2i16_nxv2i8:
10435 ; CHECK: # %bb.0: # %entry
10436 ; CHECK-NEXT: vmv1r.v v10, v8
10437 ; CHECK-NEXT: vmv1r.v v11, v8
10438 ; CHECK-NEXT: vmv1r.v v12, v8
10439 ; CHECK-NEXT: vmv1r.v v13, v8
10440 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10441 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
10442 ; CHECK-NEXT: ret
10443 entry:
10444 tail call void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10445 ret void
10446 }
10448 define void @test_vsoxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10449 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_nxv2i8:
10450 ; CHECK: # %bb.0: # %entry
10451 ; CHECK-NEXT: vmv1r.v v10, v8
10452 ; CHECK-NEXT: vmv1r.v v11, v8
10453 ; CHECK-NEXT: vmv1r.v v12, v8
10454 ; CHECK-NEXT: vmv1r.v v13, v8
10455 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10456 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
10457 ; CHECK-NEXT: ret
10458 entry:
10459 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10460 ret void
10461 }
10463 declare void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10464 declare void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10466 define void @test_vsoxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10467 ; CHECK-LABEL: test_vsoxseg4_nxv2i16_nxv2i16:
10468 ; CHECK: # %bb.0: # %entry
10469 ; CHECK-NEXT: vmv1r.v v10, v8
10470 ; CHECK-NEXT: vmv1r.v v11, v8
10471 ; CHECK-NEXT: vmv1r.v v12, v8
10472 ; CHECK-NEXT: vmv1r.v v13, v8
10473 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10474 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
10475 ; CHECK-NEXT: ret
10476 entry:
10477 tail call void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10478 ret void
10479 }
10481 define void @test_vsoxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10482 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_nxv2i16:
10483 ; CHECK: # %bb.0: # %entry
10484 ; CHECK-NEXT: vmv1r.v v10, v8
10485 ; CHECK-NEXT: vmv1r.v v11, v8
10486 ; CHECK-NEXT: vmv1r.v v12, v8
10487 ; CHECK-NEXT: vmv1r.v v13, v8
10488 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10489 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
10490 ; CHECK-NEXT: ret
10491 entry:
10492 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10493 ret void
10494 }
10496 declare void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10497 declare void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10499 define void @test_vsoxseg4_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10500 ; CHECK-LABEL: test_vsoxseg4_nxv2i16_nxv2i64:
10501 ; CHECK: # %bb.0: # %entry
10502 ; CHECK-NEXT: vmv1r.v v12, v8
10503 ; CHECK-NEXT: vmv1r.v v13, v8
10504 ; CHECK-NEXT: vmv1r.v v14, v8
10505 ; CHECK-NEXT: vmv1r.v v15, v8
10506 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10507 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
10508 ; CHECK-NEXT: ret
10509 entry:
10510 tail call void @llvm.riscv.vsoxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10511 ret void
10512 }
10514 define void @test_vsoxseg4_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10515 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_nxv2i64:
10516 ; CHECK: # %bb.0: # %entry
10517 ; CHECK-NEXT: vmv1r.v v12, v8
10518 ; CHECK-NEXT: vmv1r.v v13, v8
10519 ; CHECK-NEXT: vmv1r.v v14, v8
10520 ; CHECK-NEXT: vmv1r.v v15, v8
10521 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10522 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
10523 ; CHECK-NEXT: ret
10524 entry:
10525 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10526 ret void
10527 }
10529 declare void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10530 declare void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10532 define void @test_vsoxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10533 ; CHECK-LABEL: test_vsoxseg5_nxv2i16_nxv2i32:
10534 ; CHECK: # %bb.0: # %entry
10535 ; CHECK-NEXT: vmv1r.v v10, v8
10536 ; CHECK-NEXT: vmv1r.v v11, v8
10537 ; CHECK-NEXT: vmv1r.v v12, v8
10538 ; CHECK-NEXT: vmv1r.v v13, v8
10539 ; CHECK-NEXT: vmv1r.v v14, v8
10540 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10541 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
10542 ; CHECK-NEXT: ret
10543 entry:
10544 tail call void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10545 ret void
10546 }
10548 define void @test_vsoxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10549 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_nxv2i32:
10550 ; CHECK: # %bb.0: # %entry
10551 ; CHECK-NEXT: vmv1r.v v10, v8
10552 ; CHECK-NEXT: vmv1r.v v11, v8
10553 ; CHECK-NEXT: vmv1r.v v12, v8
10554 ; CHECK-NEXT: vmv1r.v v13, v8
10555 ; CHECK-NEXT: vmv1r.v v14, v8
10556 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10557 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
10558 ; CHECK-NEXT: ret
10559 entry:
10560 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10561 ret void
10562 }
10564 declare void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10565 declare void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10567 define void @test_vsoxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10568 ; CHECK-LABEL: test_vsoxseg5_nxv2i16_nxv2i8:
10569 ; CHECK: # %bb.0: # %entry
10570 ; CHECK-NEXT: vmv1r.v v10, v8
10571 ; CHECK-NEXT: vmv1r.v v11, v8
10572 ; CHECK-NEXT: vmv1r.v v12, v8
10573 ; CHECK-NEXT: vmv1r.v v13, v8
10574 ; CHECK-NEXT: vmv1r.v v14, v8
10575 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10576 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
10577 ; CHECK-NEXT: ret
10578 entry:
10579 tail call void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10580 ret void
10581 }
10583 define void @test_vsoxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10584 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_nxv2i8:
10585 ; CHECK: # %bb.0: # %entry
10586 ; CHECK-NEXT: vmv1r.v v10, v8
10587 ; CHECK-NEXT: vmv1r.v v11, v8
10588 ; CHECK-NEXT: vmv1r.v v12, v8
10589 ; CHECK-NEXT: vmv1r.v v13, v8
10590 ; CHECK-NEXT: vmv1r.v v14, v8
10591 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10592 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
10593 ; CHECK-NEXT: ret
10594 entry:
10595 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10596 ret void
10597 }
10599 declare void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10600 declare void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10602 define void @test_vsoxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10603 ; CHECK-LABEL: test_vsoxseg5_nxv2i16_nxv2i16:
10604 ; CHECK: # %bb.0: # %entry
10605 ; CHECK-NEXT: vmv1r.v v10, v8
10606 ; CHECK-NEXT: vmv1r.v v11, v8
10607 ; CHECK-NEXT: vmv1r.v v12, v8
10608 ; CHECK-NEXT: vmv1r.v v13, v8
10609 ; CHECK-NEXT: vmv1r.v v14, v8
10610 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10611 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
10612 ; CHECK-NEXT: ret
10613 entry:
10614 tail call void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10615 ret void
10616 }
10618 define void @test_vsoxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10619 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_nxv2i16:
10620 ; CHECK: # %bb.0: # %entry
10621 ; CHECK-NEXT: vmv1r.v v10, v8
10622 ; CHECK-NEXT: vmv1r.v v11, v8
10623 ; CHECK-NEXT: vmv1r.v v12, v8
10624 ; CHECK-NEXT: vmv1r.v v13, v8
10625 ; CHECK-NEXT: vmv1r.v v14, v8
10626 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10627 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
10628 ; CHECK-NEXT: ret
10629 entry:
10630 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10631 ret void
10632 }
10634 declare void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10635 declare void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10637 define void @test_vsoxseg5_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10638 ; CHECK-LABEL: test_vsoxseg5_nxv2i16_nxv2i64:
10639 ; CHECK: # %bb.0: # %entry
10640 ; CHECK-NEXT: vmv1r.v v12, v8
10641 ; CHECK-NEXT: vmv1r.v v13, v8
10642 ; CHECK-NEXT: vmv1r.v v14, v8
10643 ; CHECK-NEXT: vmv1r.v v15, v8
10644 ; CHECK-NEXT: vmv1r.v v16, v8
10645 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10646 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10
10647 ; CHECK-NEXT: ret
10648 entry:
10649 tail call void @llvm.riscv.vsoxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10650 ret void
10651 }
10653 define void @test_vsoxseg5_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10654 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_nxv2i64:
10655 ; CHECK: # %bb.0: # %entry
10656 ; CHECK-NEXT: vmv1r.v v12, v8
10657 ; CHECK-NEXT: vmv1r.v v13, v8
10658 ; CHECK-NEXT: vmv1r.v v14, v8
10659 ; CHECK-NEXT: vmv1r.v v15, v8
10660 ; CHECK-NEXT: vmv1r.v v16, v8
10661 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10662 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10, v0.t
10663 ; CHECK-NEXT: ret
10664 entry:
10665 tail call void @llvm.riscv.vsoxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10666 ret void
10667 }
10669 declare void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10670 declare void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10672 define void @test_vsoxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10673 ; CHECK-LABEL: test_vsoxseg6_nxv2i16_nxv2i32:
10674 ; CHECK: # %bb.0: # %entry
10675 ; CHECK-NEXT: vmv1r.v v10, v8
10676 ; CHECK-NEXT: vmv1r.v v11, v8
10677 ; CHECK-NEXT: vmv1r.v v12, v8
10678 ; CHECK-NEXT: vmv1r.v v13, v8
10679 ; CHECK-NEXT: vmv1r.v v14, v8
10680 ; CHECK-NEXT: vmv1r.v v15, v8
10681 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10682 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
10683 ; CHECK-NEXT: ret
10684 entry:
10685 tail call void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10686 ret void
10687 }
10689 define void @test_vsoxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10690 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_nxv2i32:
10691 ; CHECK: # %bb.0: # %entry
10692 ; CHECK-NEXT: vmv1r.v v10, v8
10693 ; CHECK-NEXT: vmv1r.v v11, v8
10694 ; CHECK-NEXT: vmv1r.v v12, v8
10695 ; CHECK-NEXT: vmv1r.v v13, v8
10696 ; CHECK-NEXT: vmv1r.v v14, v8
10697 ; CHECK-NEXT: vmv1r.v v15, v8
10698 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10699 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
10700 ; CHECK-NEXT: ret
10701 entry:
10702 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10703 ret void
10704 }
10706 declare void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10707 declare void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10709 define void @test_vsoxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10710 ; CHECK-LABEL: test_vsoxseg6_nxv2i16_nxv2i8:
10711 ; CHECK: # %bb.0: # %entry
10712 ; CHECK-NEXT: vmv1r.v v10, v8
10713 ; CHECK-NEXT: vmv1r.v v11, v8
10714 ; CHECK-NEXT: vmv1r.v v12, v8
10715 ; CHECK-NEXT: vmv1r.v v13, v8
10716 ; CHECK-NEXT: vmv1r.v v14, v8
10717 ; CHECK-NEXT: vmv1r.v v15, v8
10718 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10719 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
10720 ; CHECK-NEXT: ret
10721 entry:
10722 tail call void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10723 ret void
10724 }
10726 define void @test_vsoxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10727 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_nxv2i8:
10728 ; CHECK: # %bb.0: # %entry
10729 ; CHECK-NEXT: vmv1r.v v10, v8
10730 ; CHECK-NEXT: vmv1r.v v11, v8
10731 ; CHECK-NEXT: vmv1r.v v12, v8
10732 ; CHECK-NEXT: vmv1r.v v13, v8
10733 ; CHECK-NEXT: vmv1r.v v14, v8
10734 ; CHECK-NEXT: vmv1r.v v15, v8
10735 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10736 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
10737 ; CHECK-NEXT: ret
10738 entry:
10739 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10740 ret void
10741 }
10743 declare void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10744 declare void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10746 define void @test_vsoxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10747 ; CHECK-LABEL: test_vsoxseg6_nxv2i16_nxv2i16:
10748 ; CHECK: # %bb.0: # %entry
10749 ; CHECK-NEXT: vmv1r.v v10, v8
10750 ; CHECK-NEXT: vmv1r.v v11, v8
10751 ; CHECK-NEXT: vmv1r.v v12, v8
10752 ; CHECK-NEXT: vmv1r.v v13, v8
10753 ; CHECK-NEXT: vmv1r.v v14, v8
10754 ; CHECK-NEXT: vmv1r.v v15, v8
10755 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10756 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
10757 ; CHECK-NEXT: ret
10758 entry:
10759 tail call void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10760 ret void
10761 }
10763 define void @test_vsoxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10764 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_nxv2i16:
10765 ; CHECK: # %bb.0: # %entry
10766 ; CHECK-NEXT: vmv1r.v v10, v8
10767 ; CHECK-NEXT: vmv1r.v v11, v8
10768 ; CHECK-NEXT: vmv1r.v v12, v8
10769 ; CHECK-NEXT: vmv1r.v v13, v8
10770 ; CHECK-NEXT: vmv1r.v v14, v8
10771 ; CHECK-NEXT: vmv1r.v v15, v8
10772 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10773 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
10774 ; CHECK-NEXT: ret
10775 entry:
10776 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10777 ret void
10778 }
10780 declare void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10781 declare void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10783 define void @test_vsoxseg6_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10784 ; CHECK-LABEL: test_vsoxseg6_nxv2i16_nxv2i64:
10785 ; CHECK: # %bb.0: # %entry
10786 ; CHECK-NEXT: vmv1r.v v12, v8
10787 ; CHECK-NEXT: vmv1r.v v13, v8
10788 ; CHECK-NEXT: vmv1r.v v14, v8
10789 ; CHECK-NEXT: vmv1r.v v15, v8
10790 ; CHECK-NEXT: vmv1r.v v16, v8
10791 ; CHECK-NEXT: vmv1r.v v17, v8
10792 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10793 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10
10794 ; CHECK-NEXT: ret
10795 entry:
10796 tail call void @llvm.riscv.vsoxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10797 ret void
10798 }
10800 define void @test_vsoxseg6_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10801 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_nxv2i64:
10802 ; CHECK: # %bb.0: # %entry
10803 ; CHECK-NEXT: vmv1r.v v12, v8
10804 ; CHECK-NEXT: vmv1r.v v13, v8
10805 ; CHECK-NEXT: vmv1r.v v14, v8
10806 ; CHECK-NEXT: vmv1r.v v15, v8
10807 ; CHECK-NEXT: vmv1r.v v16, v8
10808 ; CHECK-NEXT: vmv1r.v v17, v8
10809 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10810 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10, v0.t
10811 ; CHECK-NEXT: ret
10812 entry:
10813 tail call void @llvm.riscv.vsoxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10814 ret void
10815 }
10817 declare void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10818 declare void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10820 define void @test_vsoxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10821 ; CHECK-LABEL: test_vsoxseg7_nxv2i16_nxv2i32:
10822 ; CHECK: # %bb.0: # %entry
10823 ; CHECK-NEXT: vmv1r.v v10, v8
10824 ; CHECK-NEXT: vmv1r.v v11, v8
10825 ; CHECK-NEXT: vmv1r.v v12, v8
10826 ; CHECK-NEXT: vmv1r.v v13, v8
10827 ; CHECK-NEXT: vmv1r.v v14, v8
10828 ; CHECK-NEXT: vmv1r.v v15, v8
10829 ; CHECK-NEXT: vmv1r.v v16, v8
10830 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10831 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
10832 ; CHECK-NEXT: ret
10833 entry:
10834 tail call void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10835 ret void
10836 }
10838 define void @test_vsoxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10839 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_nxv2i32:
10840 ; CHECK: # %bb.0: # %entry
10841 ; CHECK-NEXT: vmv1r.v v10, v8
10842 ; CHECK-NEXT: vmv1r.v v11, v8
10843 ; CHECK-NEXT: vmv1r.v v12, v8
10844 ; CHECK-NEXT: vmv1r.v v13, v8
10845 ; CHECK-NEXT: vmv1r.v v14, v8
10846 ; CHECK-NEXT: vmv1r.v v15, v8
10847 ; CHECK-NEXT: vmv1r.v v16, v8
10848 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10849 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
10850 ; CHECK-NEXT: ret
10851 entry:
10852 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
10853 ret void
10854 }
10856 declare void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
10857 declare void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
10859 define void @test_vsoxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
10860 ; CHECK-LABEL: test_vsoxseg7_nxv2i16_nxv2i8:
10861 ; CHECK: # %bb.0: # %entry
10862 ; CHECK-NEXT: vmv1r.v v10, v8
10863 ; CHECK-NEXT: vmv1r.v v11, v8
10864 ; CHECK-NEXT: vmv1r.v v12, v8
10865 ; CHECK-NEXT: vmv1r.v v13, v8
10866 ; CHECK-NEXT: vmv1r.v v14, v8
10867 ; CHECK-NEXT: vmv1r.v v15, v8
10868 ; CHECK-NEXT: vmv1r.v v16, v8
10869 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10870 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
10871 ; CHECK-NEXT: ret
10872 entry:
10873 tail call void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
10874 ret void
10875 }
10877 define void @test_vsoxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10878 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_nxv2i8:
10879 ; CHECK: # %bb.0: # %entry
10880 ; CHECK-NEXT: vmv1r.v v10, v8
10881 ; CHECK-NEXT: vmv1r.v v11, v8
10882 ; CHECK-NEXT: vmv1r.v v12, v8
10883 ; CHECK-NEXT: vmv1r.v v13, v8
10884 ; CHECK-NEXT: vmv1r.v v14, v8
10885 ; CHECK-NEXT: vmv1r.v v15, v8
10886 ; CHECK-NEXT: vmv1r.v v16, v8
10887 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10888 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
10889 ; CHECK-NEXT: ret
10890 entry:
10891 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
10892 ret void
10893 }
10895 declare void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
10896 declare void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
10898 define void @test_vsoxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
10899 ; CHECK-LABEL: test_vsoxseg7_nxv2i16_nxv2i16:
10900 ; CHECK: # %bb.0: # %entry
10901 ; CHECK-NEXT: vmv1r.v v10, v8
10902 ; CHECK-NEXT: vmv1r.v v11, v8
10903 ; CHECK-NEXT: vmv1r.v v12, v8
10904 ; CHECK-NEXT: vmv1r.v v13, v8
10905 ; CHECK-NEXT: vmv1r.v v14, v8
10906 ; CHECK-NEXT: vmv1r.v v15, v8
10907 ; CHECK-NEXT: vmv1r.v v16, v8
10908 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10909 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
10910 ; CHECK-NEXT: ret
10911 entry:
10912 tail call void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
10913 ret void
10914 }
10916 define void @test_vsoxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10917 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_nxv2i16:
10918 ; CHECK: # %bb.0: # %entry
10919 ; CHECK-NEXT: vmv1r.v v10, v8
10920 ; CHECK-NEXT: vmv1r.v v11, v8
10921 ; CHECK-NEXT: vmv1r.v v12, v8
10922 ; CHECK-NEXT: vmv1r.v v13, v8
10923 ; CHECK-NEXT: vmv1r.v v14, v8
10924 ; CHECK-NEXT: vmv1r.v v15, v8
10925 ; CHECK-NEXT: vmv1r.v v16, v8
10926 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10927 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
10928 ; CHECK-NEXT: ret
10929 entry:
10930 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
10931 ret void
10932 }
10934 declare void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
10935 declare void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
10937 define void @test_vsoxseg7_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
10938 ; CHECK-LABEL: test_vsoxseg7_nxv2i16_nxv2i64:
10939 ; CHECK: # %bb.0: # %entry
10940 ; CHECK-NEXT: vmv1r.v v12, v8
10941 ; CHECK-NEXT: vmv1r.v v13, v8
10942 ; CHECK-NEXT: vmv1r.v v14, v8
10943 ; CHECK-NEXT: vmv1r.v v15, v8
10944 ; CHECK-NEXT: vmv1r.v v16, v8
10945 ; CHECK-NEXT: vmv1r.v v17, v8
10946 ; CHECK-NEXT: vmv1r.v v18, v8
10947 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10948 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10
10949 ; CHECK-NEXT: ret
10950 entry:
10951 tail call void @llvm.riscv.vsoxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
10952 ret void
10953 }
10955 define void @test_vsoxseg7_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10956 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_nxv2i64:
10957 ; CHECK: # %bb.0: # %entry
10958 ; CHECK-NEXT: vmv1r.v v12, v8
10959 ; CHECK-NEXT: vmv1r.v v13, v8
10960 ; CHECK-NEXT: vmv1r.v v14, v8
10961 ; CHECK-NEXT: vmv1r.v v15, v8
10962 ; CHECK-NEXT: vmv1r.v v16, v8
10963 ; CHECK-NEXT: vmv1r.v v17, v8
10964 ; CHECK-NEXT: vmv1r.v v18, v8
10965 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10966 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10, v0.t
10967 ; CHECK-NEXT: ret
10968 entry:
10969 tail call void @llvm.riscv.vsoxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
10970 ret void
10971 }
10973 declare void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, i64)
10974 declare void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
10976 define void @test_vsoxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
10977 ; CHECK-LABEL: test_vsoxseg8_nxv2i16_nxv2i32:
10978 ; CHECK: # %bb.0: # %entry
10979 ; CHECK-NEXT: vmv1r.v v10, v8
10980 ; CHECK-NEXT: vmv1r.v v11, v8
10981 ; CHECK-NEXT: vmv1r.v v12, v8
10982 ; CHECK-NEXT: vmv1r.v v13, v8
10983 ; CHECK-NEXT: vmv1r.v v14, v8
10984 ; CHECK-NEXT: vmv1r.v v15, v8
10985 ; CHECK-NEXT: vmv1r.v v16, v8
10986 ; CHECK-NEXT: vmv1r.v v17, v8
10987 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
10988 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
10989 ; CHECK-NEXT: ret
10990 entry:
10991 tail call void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
10992 ret void
10993 }
10995 define void @test_vsoxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
10996 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_nxv2i32:
10997 ; CHECK: # %bb.0: # %entry
10998 ; CHECK-NEXT: vmv1r.v v10, v8
10999 ; CHECK-NEXT: vmv1r.v v11, v8
11000 ; CHECK-NEXT: vmv1r.v v12, v8
11001 ; CHECK-NEXT: vmv1r.v v13, v8
11002 ; CHECK-NEXT: vmv1r.v v14, v8
11003 ; CHECK-NEXT: vmv1r.v v15, v8
11004 ; CHECK-NEXT: vmv1r.v v16, v8
11005 ; CHECK-NEXT: vmv1r.v v17, v8
11006 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11007 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
11008 ; CHECK-NEXT: ret
11009 entry:
11010 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
11011 ret void
11012 }
11014 declare void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, i64)
11015 declare void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
11017 define void @test_vsoxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
11018 ; CHECK-LABEL: test_vsoxseg8_nxv2i16_nxv2i8:
11019 ; CHECK: # %bb.0: # %entry
11020 ; CHECK-NEXT: vmv1r.v v10, v8
11021 ; CHECK-NEXT: vmv1r.v v11, v8
11022 ; CHECK-NEXT: vmv1r.v v12, v8
11023 ; CHECK-NEXT: vmv1r.v v13, v8
11024 ; CHECK-NEXT: vmv1r.v v14, v8
11025 ; CHECK-NEXT: vmv1r.v v15, v8
11026 ; CHECK-NEXT: vmv1r.v v16, v8
11027 ; CHECK-NEXT: vmv1r.v v17, v8
11028 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11029 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
11030 ; CHECK-NEXT: ret
11031 entry:
11032 tail call void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
11033 ret void
11034 }
11036 define void @test_vsoxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11037 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_nxv2i8:
11038 ; CHECK: # %bb.0: # %entry
11039 ; CHECK-NEXT: vmv1r.v v10, v8
11040 ; CHECK-NEXT: vmv1r.v v11, v8
11041 ; CHECK-NEXT: vmv1r.v v12, v8
11042 ; CHECK-NEXT: vmv1r.v v13, v8
11043 ; CHECK-NEXT: vmv1r.v v14, v8
11044 ; CHECK-NEXT: vmv1r.v v15, v8
11045 ; CHECK-NEXT: vmv1r.v v16, v8
11046 ; CHECK-NEXT: vmv1r.v v17, v8
11047 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11048 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
11049 ; CHECK-NEXT: ret
11050 entry:
11051 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
11052 ret void
11053 }
11055 declare void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, i64)
11056 declare void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
11058 define void @test_vsoxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
11059 ; CHECK-LABEL: test_vsoxseg8_nxv2i16_nxv2i16:
11060 ; CHECK: # %bb.0: # %entry
11061 ; CHECK-NEXT: vmv1r.v v10, v8
11062 ; CHECK-NEXT: vmv1r.v v11, v8
11063 ; CHECK-NEXT: vmv1r.v v12, v8
11064 ; CHECK-NEXT: vmv1r.v v13, v8
11065 ; CHECK-NEXT: vmv1r.v v14, v8
11066 ; CHECK-NEXT: vmv1r.v v15, v8
11067 ; CHECK-NEXT: vmv1r.v v16, v8
11068 ; CHECK-NEXT: vmv1r.v v17, v8
11069 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11070 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
11071 ; CHECK-NEXT: ret
11072 entry:
11073 tail call void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
11074 ret void
11075 }
11077 define void @test_vsoxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11078 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_nxv2i16:
11079 ; CHECK: # %bb.0: # %entry
11080 ; CHECK-NEXT: vmv1r.v v10, v8
11081 ; CHECK-NEXT: vmv1r.v v11, v8
11082 ; CHECK-NEXT: vmv1r.v v12, v8
11083 ; CHECK-NEXT: vmv1r.v v13, v8
11084 ; CHECK-NEXT: vmv1r.v v14, v8
11085 ; CHECK-NEXT: vmv1r.v v15, v8
11086 ; CHECK-NEXT: vmv1r.v v16, v8
11087 ; CHECK-NEXT: vmv1r.v v17, v8
11088 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11089 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
11090 ; CHECK-NEXT: ret
11091 entry:
11092 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
11093 ret void
11094 }
11096 declare void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, i64)
11097 declare void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
11099 define void @test_vsoxseg8_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
11100 ; CHECK-LABEL: test_vsoxseg8_nxv2i16_nxv2i64:
11101 ; CHECK: # %bb.0: # %entry
11102 ; CHECK-NEXT: vmv1r.v v12, v8
11103 ; CHECK-NEXT: vmv1r.v v13, v8
11104 ; CHECK-NEXT: vmv1r.v v14, v8
11105 ; CHECK-NEXT: vmv1r.v v15, v8
11106 ; CHECK-NEXT: vmv1r.v v16, v8
11107 ; CHECK-NEXT: vmv1r.v v17, v8
11108 ; CHECK-NEXT: vmv1r.v v18, v8
11109 ; CHECK-NEXT: vmv1r.v v19, v8
11110 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11111 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10
11112 ; CHECK-NEXT: ret
11113 entry:
11114 tail call void @llvm.riscv.vsoxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
11115 ret void
11116 }
11118 define void @test_vsoxseg8_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11119 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_nxv2i64:
11120 ; CHECK: # %bb.0: # %entry
11121 ; CHECK-NEXT: vmv1r.v v12, v8
11122 ; CHECK-NEXT: vmv1r.v v13, v8
11123 ; CHECK-NEXT: vmv1r.v v14, v8
11124 ; CHECK-NEXT: vmv1r.v v15, v8
11125 ; CHECK-NEXT: vmv1r.v v16, v8
11126 ; CHECK-NEXT: vmv1r.v v17, v8
11127 ; CHECK-NEXT: vmv1r.v v18, v8
11128 ; CHECK-NEXT: vmv1r.v v19, v8
11129 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
11130 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10, v0.t
11131 ; CHECK-NEXT: ret
11132 entry:
11133 tail call void @llvm.riscv.vsoxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
11134 ret void
11135 }
11137 declare void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, i64)
11138 declare void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
11140 define void @test_vsoxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
11141 ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i32:
11142 ; CHECK: # %bb.0: # %entry
11143 ; CHECK-NEXT: vmv1r.v v12, v10
11144 ; CHECK-NEXT: vmv2r.v v10, v8
11145 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11146 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
11147 ; CHECK-NEXT: ret
11148 entry:
11149 tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
11150 ret void
11151 }
11153 define void @test_vsoxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11154 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i32:
11155 ; CHECK: # %bb.0: # %entry
11156 ; CHECK-NEXT: vmv1r.v v12, v10
11157 ; CHECK-NEXT: vmv2r.v v10, v8
11158 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11159 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
11160 ; CHECK-NEXT: ret
11161 entry:
11162 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
11163 ret void
11164 }
11166 declare void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, i64)
11167 declare void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
11169 define void @test_vsoxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
11170 ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i8:
11171 ; CHECK: # %bb.0: # %entry
11172 ; CHECK-NEXT: vmv1r.v v12, v10
11173 ; CHECK-NEXT: vmv2r.v v10, v8
11174 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11175 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
11176 ; CHECK-NEXT: ret
11177 entry:
11178 tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
11179 ret void
11180 }
11182 define void @test_vsoxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11183 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i8:
11184 ; CHECK: # %bb.0: # %entry
11185 ; CHECK-NEXT: vmv1r.v v12, v10
11186 ; CHECK-NEXT: vmv2r.v v10, v8
11187 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11188 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
11189 ; CHECK-NEXT: ret
11190 entry:
11191 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
11192 ret void
11193 }
11195 declare void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, i64)
11196 declare void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
11198 define void @test_vsoxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
11199 ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i16:
11200 ; CHECK: # %bb.0: # %entry
11201 ; CHECK-NEXT: vmv1r.v v12, v10
11202 ; CHECK-NEXT: vmv2r.v v10, v8
11203 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11204 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
11205 ; CHECK-NEXT: ret
11206 entry:
11207 tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
11208 ret void
11209 }
11211 define void @test_vsoxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11212 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i16:
11213 ; CHECK: # %bb.0: # %entry
11214 ; CHECK-NEXT: vmv1r.v v12, v10
11215 ; CHECK-NEXT: vmv2r.v v10, v8
11216 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11217 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
11218 ; CHECK-NEXT: ret
11219 entry:
11220 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
11221 ret void
11222 }
11224 declare void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, i64)
11225 declare void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
11227 define void @test_vsoxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
11228 ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i64:
11229 ; CHECK: # %bb.0: # %entry
11230 ; CHECK-NEXT: vmv2r.v v12, v10
11231 ; CHECK-NEXT: vmv2r.v v10, v8
11232 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11233 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
11234 ; CHECK-NEXT: ret
11235 entry:
11236 tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
11237 ret void
11238 }
11240 define void @test_vsoxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11241 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i64:
11242 ; CHECK: # %bb.0: # %entry
11243 ; CHECK-NEXT: vmv2r.v v12, v10
11244 ; CHECK-NEXT: vmv2r.v v10, v8
11245 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11246 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
11247 ; CHECK-NEXT: ret
11248 entry:
11249 tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
11250 ret void
11251 }
11253 declare void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, i64)
11254 declare void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
11256 define void @test_vsoxseg3_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
11257 ; CHECK-LABEL: test_vsoxseg3_nxv2i64_nxv2i32:
11258 ; CHECK: # %bb.0: # %entry
11259 ; CHECK-NEXT: vmv2r.v v12, v8
11260 ; CHECK-NEXT: vmv2r.v v14, v8
11261 ; CHECK-NEXT: vmv2r.v v16, v8
11262 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11263 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10
11264 ; CHECK-NEXT: ret
11265 entry:
11266 tail call void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
11267 ret void
11268 }
11270 define void @test_vsoxseg3_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11271 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_nxv2i32:
11272 ; CHECK: # %bb.0: # %entry
11273 ; CHECK-NEXT: vmv2r.v v12, v8
11274 ; CHECK-NEXT: vmv2r.v v14, v8
11275 ; CHECK-NEXT: vmv2r.v v16, v8
11276 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11277 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10, v0.t
11278 ; CHECK-NEXT: ret
11279 entry:
11280 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
11281 ret void
11282 }
11284 declare void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, i64)
11285 declare void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
11287 define void @test_vsoxseg3_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
11288 ; CHECK-LABEL: test_vsoxseg3_nxv2i64_nxv2i8:
11289 ; CHECK: # %bb.0: # %entry
11290 ; CHECK-NEXT: vmv2r.v v12, v8
11291 ; CHECK-NEXT: vmv2r.v v14, v8
11292 ; CHECK-NEXT: vmv2r.v v16, v8
11293 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11294 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
11295 ; CHECK-NEXT: ret
11296 entry:
11297 tail call void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
11298 ret void
11299 }
11301 define void @test_vsoxseg3_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11302 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_nxv2i8:
11303 ; CHECK: # %bb.0: # %entry
11304 ; CHECK-NEXT: vmv2r.v v12, v8
11305 ; CHECK-NEXT: vmv2r.v v14, v8
11306 ; CHECK-NEXT: vmv2r.v v16, v8
11307 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11308 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
11309 ; CHECK-NEXT: ret
11310 entry:
11311 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
11312 ret void
11313 }
11315 declare void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, i64)
11316 declare void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
11318 define void @test_vsoxseg3_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
11319 ; CHECK-LABEL: test_vsoxseg3_nxv2i64_nxv2i16:
11320 ; CHECK: # %bb.0: # %entry
11321 ; CHECK-NEXT: vmv2r.v v12, v8
11322 ; CHECK-NEXT: vmv2r.v v14, v8
11323 ; CHECK-NEXT: vmv2r.v v16, v8
11324 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11325 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
11326 ; CHECK-NEXT: ret
11327 entry:
11328 tail call void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
11329 ret void
11330 }
11332 define void @test_vsoxseg3_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11333 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_nxv2i16:
11334 ; CHECK: # %bb.0: # %entry
11335 ; CHECK-NEXT: vmv2r.v v12, v8
11336 ; CHECK-NEXT: vmv2r.v v14, v8
11337 ; CHECK-NEXT: vmv2r.v v16, v8
11338 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11339 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
11340 ; CHECK-NEXT: ret
11341 entry:
11342 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
11343 ret void
11344 }
11346 declare void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, i64)
11347 declare void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
11349 define void @test_vsoxseg3_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
11350 ; CHECK-LABEL: test_vsoxseg3_nxv2i64_nxv2i64:
11351 ; CHECK: # %bb.0: # %entry
11352 ; CHECK-NEXT: vmv2r.v v12, v8
11353 ; CHECK-NEXT: vmv2r.v v14, v8
11354 ; CHECK-NEXT: vmv2r.v v16, v8
11355 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11356 ; CHECK-NEXT: vsoxseg3ei64.v v12, (a0), v10
11357 ; CHECK-NEXT: ret
11358 entry:
11359 tail call void @llvm.riscv.vsoxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
11360 ret void
11361 }
11363 define void @test_vsoxseg3_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11364 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_nxv2i64:
11365 ; CHECK: # %bb.0: # %entry
11366 ; CHECK-NEXT: vmv2r.v v12, v8
11367 ; CHECK-NEXT: vmv2r.v v14, v8
11368 ; CHECK-NEXT: vmv2r.v v16, v8
11369 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11370 ; CHECK-NEXT: vsoxseg3ei64.v v12, (a0), v10, v0.t
11371 ; CHECK-NEXT: ret
11372 entry:
11373 tail call void @llvm.riscv.vsoxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
11374 ret void
11375 }
11377 declare void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, i64)
11378 declare void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
11380 define void @test_vsoxseg4_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
11381 ; CHECK-LABEL: test_vsoxseg4_nxv2i64_nxv2i32:
11382 ; CHECK: # %bb.0: # %entry
11383 ; CHECK-NEXT: vmv2r.v v12, v8
11384 ; CHECK-NEXT: vmv2r.v v14, v8
11385 ; CHECK-NEXT: vmv2r.v v16, v8
11386 ; CHECK-NEXT: vmv2r.v v18, v8
11387 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11388 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
11389 ; CHECK-NEXT: ret
11390 entry:
11391 tail call void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
11392 ret void
11393 }
11395 define void @test_vsoxseg4_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11396 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_nxv2i32:
11397 ; CHECK: # %bb.0: # %entry
11398 ; CHECK-NEXT: vmv2r.v v12, v8
11399 ; CHECK-NEXT: vmv2r.v v14, v8
11400 ; CHECK-NEXT: vmv2r.v v16, v8
11401 ; CHECK-NEXT: vmv2r.v v18, v8
11402 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11403 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
11404 ; CHECK-NEXT: ret
11405 entry:
11406 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
11407 ret void
11408 }
11410 declare void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, i64)
11411 declare void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
11413 define void @test_vsoxseg4_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
11414 ; CHECK-LABEL: test_vsoxseg4_nxv2i64_nxv2i8:
11415 ; CHECK: # %bb.0: # %entry
11416 ; CHECK-NEXT: vmv2r.v v12, v8
11417 ; CHECK-NEXT: vmv2r.v v14, v8
11418 ; CHECK-NEXT: vmv2r.v v16, v8
11419 ; CHECK-NEXT: vmv2r.v v18, v8
11420 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11421 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
11422 ; CHECK-NEXT: ret
11423 entry:
11424 tail call void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
11425 ret void
11426 }
11428 define void @test_vsoxseg4_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11429 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_nxv2i8:
11430 ; CHECK: # %bb.0: # %entry
11431 ; CHECK-NEXT: vmv2r.v v12, v8
11432 ; CHECK-NEXT: vmv2r.v v14, v8
11433 ; CHECK-NEXT: vmv2r.v v16, v8
11434 ; CHECK-NEXT: vmv2r.v v18, v8
11435 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11436 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
11437 ; CHECK-NEXT: ret
11438 entry:
11439 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
11440 ret void
11441 }
11443 declare void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, i64)
11444 declare void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
11446 define void @test_vsoxseg4_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
11447 ; CHECK-LABEL: test_vsoxseg4_nxv2i64_nxv2i16:
11448 ; CHECK: # %bb.0: # %entry
11449 ; CHECK-NEXT: vmv2r.v v12, v8
11450 ; CHECK-NEXT: vmv2r.v v14, v8
11451 ; CHECK-NEXT: vmv2r.v v16, v8
11452 ; CHECK-NEXT: vmv2r.v v18, v8
11453 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11454 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
11455 ; CHECK-NEXT: ret
11456 entry:
11457 tail call void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
11458 ret void
11459 }
11461 define void @test_vsoxseg4_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11462 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_nxv2i16:
11463 ; CHECK: # %bb.0: # %entry
11464 ; CHECK-NEXT: vmv2r.v v12, v8
11465 ; CHECK-NEXT: vmv2r.v v14, v8
11466 ; CHECK-NEXT: vmv2r.v v16, v8
11467 ; CHECK-NEXT: vmv2r.v v18, v8
11468 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11469 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
11470 ; CHECK-NEXT: ret
11471 entry:
11472 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
11473 ret void
11474 }
11476 declare void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, i64)
11477 declare void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
11479 define void @test_vsoxseg4_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
11480 ; CHECK-LABEL: test_vsoxseg4_nxv2i64_nxv2i64:
11481 ; CHECK: # %bb.0: # %entry
11482 ; CHECK-NEXT: vmv2r.v v12, v8
11483 ; CHECK-NEXT: vmv2r.v v14, v8
11484 ; CHECK-NEXT: vmv2r.v v16, v8
11485 ; CHECK-NEXT: vmv2r.v v18, v8
11486 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11487 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
11488 ; CHECK-NEXT: ret
11489 entry:
11490 tail call void @llvm.riscv.vsoxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
11491 ret void
11492 }
11494 define void @test_vsoxseg4_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
11495 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_nxv2i64:
11496 ; CHECK: # %bb.0: # %entry
11497 ; CHECK-NEXT: vmv2r.v v12, v8
11498 ; CHECK-NEXT: vmv2r.v v14, v8
11499 ; CHECK-NEXT: vmv2r.v v16, v8
11500 ; CHECK-NEXT: vmv2r.v v18, v8
11501 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
11502 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
11503 ; CHECK-NEXT: ret
11504 entry:
11505 tail call void @llvm.riscv.vsoxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
11506 ret void
11507 }
11509 declare void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i16>, i64)
11510 declare void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
11512 define void @test_vsoxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {
11513 ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i16:
11514 ; CHECK: # %bb.0: # %entry
11515 ; CHECK-NEXT: vmv4r.v v16, v12
11516 ; CHECK-NEXT: vmv4r.v v12, v8
11517 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11518 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
11519 ; CHECK-NEXT: ret
11520 entry:
11521 tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl)
11522 ret void
11523 }
11525 define void @test_vsoxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
11526 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i16:
11527 ; CHECK: # %bb.0: # %entry
11528 ; CHECK-NEXT: vmv4r.v v16, v12
11529 ; CHECK-NEXT: vmv4r.v v12, v8
11530 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11531 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
11532 ; CHECK-NEXT: ret
11533 entry:
11534 tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
11535 ret void
11536 }
11538 declare void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i8>, i64)
11539 declare void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
11541 define void @test_vsoxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {
11542 ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i8:
11543 ; CHECK: # %bb.0: # %entry
11544 ; CHECK-NEXT: vmv2r.v v16, v12
11545 ; CHECK-NEXT: vmv4r.v v12, v8
11546 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11547 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
11548 ; CHECK-NEXT: ret
11549 entry:
11550 tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl)
11551 ret void
11552 }
11554 define void @test_vsoxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
11555 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i8:
11556 ; CHECK: # %bb.0: # %entry
11557 ; CHECK-NEXT: vmv2r.v v16, v12
11558 ; CHECK-NEXT: vmv4r.v v12, v8
11559 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11560 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
11561 ; CHECK-NEXT: ret
11562 entry:
11563 tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
11564 ret void
11565 }
11567 declare void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i32>, i64)
11568 declare void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
11570 define void @test_vsoxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {
11571 ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i32:
11572 ; CHECK: # %bb.0: # %entry
11573 ; CHECK-NEXT: vmv4r.v v12, v8
11574 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11575 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
11576 ; CHECK-NEXT: ret
11577 entry:
11578 tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl)
11579 ret void
11580 }
11582 define void @test_vsoxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
11583 ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i32:
11584 ; CHECK: # %bb.0: # %entry
11585 ; CHECK-NEXT: vmv4r.v v12, v8
11586 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
11587 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
11588 ; CHECK-NEXT: ret
11589 entry:
11590 tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
11591 ret void
11592 }
11594 declare void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i32>, i64)
11595 declare void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
11597 define void @test_vsoxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
11598 ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i32:
11599 ; CHECK: # %bb.0: # %entry
11600 ; CHECK-NEXT: vmv2r.v v16, v12
11601 ; CHECK-NEXT: vmv4r.v v12, v8
11602 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11603 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
11604 ; CHECK-NEXT: ret
11605 entry:
11606 tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
11607 ret void
11608 }
11610 define void @test_vsoxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
11611 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i32:
11612 ; CHECK: # %bb.0: # %entry
11613 ; CHECK-NEXT: vmv2r.v v16, v12
11614 ; CHECK-NEXT: vmv4r.v v12, v8
11615 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11616 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
11617 ; CHECK-NEXT: ret
11618 entry:
11619 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
11620 ret void
11621 }
11623 declare void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i8>, i64)
11624 declare void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
11626 define void @test_vsoxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
11627 ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i8:
11628 ; CHECK: # %bb.0: # %entry
11629 ; CHECK-NEXT: vmv1r.v v16, v12
11630 ; CHECK-NEXT: vmv4r.v v12, v8
11631 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11632 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
11633 ; CHECK-NEXT: ret
11634 entry:
11635 tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
11636 ret void
11637 }
11639 define void @test_vsoxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
11640 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i8:
11641 ; CHECK: # %bb.0: # %entry
11642 ; CHECK-NEXT: vmv1r.v v16, v12
11643 ; CHECK-NEXT: vmv4r.v v12, v8
11644 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11645 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
11646 ; CHECK-NEXT: ret
11647 entry:
11648 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
11649 ret void
11650 }
11652 declare void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i64>, i64)
11653 declare void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
11655 define void @test_vsoxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
11656 ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i64:
11657 ; CHECK: # %bb.0: # %entry
11658 ; CHECK-NEXT: vmv4r.v v16, v12
11659 ; CHECK-NEXT: vmv4r.v v12, v8
11660 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11661 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
11662 ; CHECK-NEXT: ret
11663 entry:
11664 tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
11665 ret void
11666 }
11668 define void @test_vsoxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
11669 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i64:
11670 ; CHECK: # %bb.0: # %entry
11671 ; CHECK-NEXT: vmv4r.v v16, v12
11672 ; CHECK-NEXT: vmv4r.v v12, v8
11673 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11674 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
11675 ; CHECK-NEXT: ret
11676 entry:
11677 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
11678 ret void
11679 }
11681 declare void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i16>, i64)
11682 declare void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
11684 define void @test_vsoxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
11685 ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i16:
11686 ; CHECK: # %bb.0: # %entry
11687 ; CHECK-NEXT: vmv1r.v v16, v12
11688 ; CHECK-NEXT: vmv4r.v v12, v8
11689 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11690 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
11691 ; CHECK-NEXT: ret
11692 entry:
11693 tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
11694 ret void
11695 }
11697 define void @test_vsoxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
11698 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i16:
11699 ; CHECK: # %bb.0: # %entry
11700 ; CHECK-NEXT: vmv1r.v v16, v12
11701 ; CHECK-NEXT: vmv4r.v v12, v8
11702 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
11703 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
11704 ; CHECK-NEXT: ret
11705 entry:
11706 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
11707 ret void
11708 }
11710 declare void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
11711 declare void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
11713 define void @test_vsoxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
11714 ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i64:
11715 ; CHECK: # %bb.0: # %entry
11716 ; CHECK-NEXT: vmv1r.v v10, v9
11717 ; CHECK-NEXT: vmv1r.v v9, v8
11718 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11719 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
11720 ; CHECK-NEXT: ret
11721 entry:
11722 tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
11723 ret void
11724 }
11726 define void @test_vsoxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11727 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i64:
11728 ; CHECK: # %bb.0: # %entry
11729 ; CHECK-NEXT: vmv1r.v v10, v9
11730 ; CHECK-NEXT: vmv1r.v v9, v8
11731 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11732 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
11733 ; CHECK-NEXT: ret
11734 entry:
11735 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
11736 ret void
11737 }
11739 declare void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
11740 declare void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
11742 define void @test_vsoxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
11743 ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i32:
11744 ; CHECK: # %bb.0: # %entry
11745 ; CHECK-NEXT: vmv1r.v v10, v9
11746 ; CHECK-NEXT: vmv1r.v v9, v8
11747 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11748 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
11749 ; CHECK-NEXT: ret
11750 entry:
11751 tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
11752 ret void
11753 }
11755 define void @test_vsoxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11756 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i32:
11757 ; CHECK: # %bb.0: # %entry
11758 ; CHECK-NEXT: vmv1r.v v10, v9
11759 ; CHECK-NEXT: vmv1r.v v9, v8
11760 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11761 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
11762 ; CHECK-NEXT: ret
11763 entry:
11764 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
11765 ret void
11766 }
11768 declare void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
11769 declare void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
11771 define void @test_vsoxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
11772 ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i16:
11773 ; CHECK: # %bb.0: # %entry
11774 ; CHECK-NEXT: vmv1r.v v10, v9
11775 ; CHECK-NEXT: vmv1r.v v9, v8
11776 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11777 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
11778 ; CHECK-NEXT: ret
11779 entry:
11780 tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
11781 ret void
11782 }
11784 define void @test_vsoxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11785 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i16:
11786 ; CHECK: # %bb.0: # %entry
11787 ; CHECK-NEXT: vmv1r.v v10, v9
11788 ; CHECK-NEXT: vmv1r.v v9, v8
11789 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11790 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
11791 ; CHECK-NEXT: ret
11792 entry:
11793 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
11794 ret void
11795 }
11797 declare void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
11798 declare void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
11800 define void @test_vsoxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
11801 ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i8:
11802 ; CHECK: # %bb.0: # %entry
11803 ; CHECK-NEXT: vmv1r.v v10, v9
11804 ; CHECK-NEXT: vmv1r.v v9, v8
11805 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11806 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
11807 ; CHECK-NEXT: ret
11808 entry:
11809 tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
11810 ret void
11811 }
11813 define void @test_vsoxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11814 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i8:
11815 ; CHECK: # %bb.0: # %entry
11816 ; CHECK-NEXT: vmv1r.v v10, v9
11817 ; CHECK-NEXT: vmv1r.v v9, v8
11818 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11819 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
11820 ; CHECK-NEXT: ret
11821 entry:
11822 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
11823 ret void
11824 }
11826 declare void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
11827 declare void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
11829 define void @test_vsoxseg3_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
11830 ; CHECK-LABEL: test_vsoxseg3_nxv1f64_nxv1i64:
11831 ; CHECK: # %bb.0: # %entry
11832 ; CHECK-NEXT: vmv1r.v v10, v8
11833 ; CHECK-NEXT: vmv1r.v v11, v8
11834 ; CHECK-NEXT: vmv1r.v v12, v8
11835 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11836 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
11837 ; CHECK-NEXT: ret
11838 entry:
11839 tail call void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
11840 ret void
11841 }
11843 define void @test_vsoxseg3_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11844 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_nxv1i64:
11845 ; CHECK: # %bb.0: # %entry
11846 ; CHECK-NEXT: vmv1r.v v10, v8
11847 ; CHECK-NEXT: vmv1r.v v11, v8
11848 ; CHECK-NEXT: vmv1r.v v12, v8
11849 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11850 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
11851 ; CHECK-NEXT: ret
11852 entry:
11853 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
11854 ret void
11855 }
11857 declare void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
11858 declare void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
11860 define void @test_vsoxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
11861 ; CHECK-LABEL: test_vsoxseg3_nxv1f64_nxv1i32:
11862 ; CHECK: # %bb.0: # %entry
11863 ; CHECK-NEXT: vmv1r.v v10, v8
11864 ; CHECK-NEXT: vmv1r.v v11, v8
11865 ; CHECK-NEXT: vmv1r.v v12, v8
11866 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11867 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
11868 ; CHECK-NEXT: ret
11869 entry:
11870 tail call void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
11871 ret void
11872 }
11874 define void @test_vsoxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11875 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_nxv1i32:
11876 ; CHECK: # %bb.0: # %entry
11877 ; CHECK-NEXT: vmv1r.v v10, v8
11878 ; CHECK-NEXT: vmv1r.v v11, v8
11879 ; CHECK-NEXT: vmv1r.v v12, v8
11880 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11881 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
11882 ; CHECK-NEXT: ret
11883 entry:
11884 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
11885 ret void
11886 }
11888 declare void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
11889 declare void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
11891 define void @test_vsoxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
11892 ; CHECK-LABEL: test_vsoxseg3_nxv1f64_nxv1i16:
11893 ; CHECK: # %bb.0: # %entry
11894 ; CHECK-NEXT: vmv1r.v v10, v8
11895 ; CHECK-NEXT: vmv1r.v v11, v8
11896 ; CHECK-NEXT: vmv1r.v v12, v8
11897 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11898 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
11899 ; CHECK-NEXT: ret
11900 entry:
11901 tail call void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
11902 ret void
11903 }
11905 define void @test_vsoxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11906 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_nxv1i16:
11907 ; CHECK: # %bb.0: # %entry
11908 ; CHECK-NEXT: vmv1r.v v10, v8
11909 ; CHECK-NEXT: vmv1r.v v11, v8
11910 ; CHECK-NEXT: vmv1r.v v12, v8
11911 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11912 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
11913 ; CHECK-NEXT: ret
11914 entry:
11915 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
11916 ret void
11917 }
11919 declare void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
11920 declare void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
11922 define void @test_vsoxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
11923 ; CHECK-LABEL: test_vsoxseg3_nxv1f64_nxv1i8:
11924 ; CHECK: # %bb.0: # %entry
11925 ; CHECK-NEXT: vmv1r.v v10, v8
11926 ; CHECK-NEXT: vmv1r.v v11, v8
11927 ; CHECK-NEXT: vmv1r.v v12, v8
11928 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11929 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
11930 ; CHECK-NEXT: ret
11931 entry:
11932 tail call void @llvm.riscv.vsoxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
11933 ret void
11934 }
11936 define void @test_vsoxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11937 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_nxv1i8:
11938 ; CHECK: # %bb.0: # %entry
11939 ; CHECK-NEXT: vmv1r.v v10, v8
11940 ; CHECK-NEXT: vmv1r.v v11, v8
11941 ; CHECK-NEXT: vmv1r.v v12, v8
11942 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11943 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
11944 ; CHECK-NEXT: ret
11945 entry:
11946 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
11947 ret void
11948 }
11950 declare void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
11951 declare void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
11953 define void @test_vsoxseg4_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
11954 ; CHECK-LABEL: test_vsoxseg4_nxv1f64_nxv1i64:
11955 ; CHECK: # %bb.0: # %entry
11956 ; CHECK-NEXT: vmv1r.v v10, v8
11957 ; CHECK-NEXT: vmv1r.v v11, v8
11958 ; CHECK-NEXT: vmv1r.v v12, v8
11959 ; CHECK-NEXT: vmv1r.v v13, v8
11960 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11961 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
11962 ; CHECK-NEXT: ret
11963 entry:
11964 tail call void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
11965 ret void
11966 }
11968 define void @test_vsoxseg4_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
11969 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_nxv1i64:
11970 ; CHECK: # %bb.0: # %entry
11971 ; CHECK-NEXT: vmv1r.v v10, v8
11972 ; CHECK-NEXT: vmv1r.v v11, v8
11973 ; CHECK-NEXT: vmv1r.v v12, v8
11974 ; CHECK-NEXT: vmv1r.v v13, v8
11975 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11976 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
11977 ; CHECK-NEXT: ret
11978 entry:
11979 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
11980 ret void
11981 }
11983 declare void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
11984 declare void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
11986 define void @test_vsoxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
11987 ; CHECK-LABEL: test_vsoxseg4_nxv1f64_nxv1i32:
11988 ; CHECK: # %bb.0: # %entry
11989 ; CHECK-NEXT: vmv1r.v v10, v8
11990 ; CHECK-NEXT: vmv1r.v v11, v8
11991 ; CHECK-NEXT: vmv1r.v v12, v8
11992 ; CHECK-NEXT: vmv1r.v v13, v8
11993 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
11994 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
11995 ; CHECK-NEXT: ret
11996 entry:
11997 tail call void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
11998 ret void
11999 }
12001 define void @test_vsoxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12002 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_nxv1i32:
12003 ; CHECK: # %bb.0: # %entry
12004 ; CHECK-NEXT: vmv1r.v v10, v8
12005 ; CHECK-NEXT: vmv1r.v v11, v8
12006 ; CHECK-NEXT: vmv1r.v v12, v8
12007 ; CHECK-NEXT: vmv1r.v v13, v8
12008 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12009 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
12010 ; CHECK-NEXT: ret
12011 entry:
12012 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
12013 ret void
12014 }
12016 declare void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
12017 declare void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
12019 define void @test_vsoxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
12020 ; CHECK-LABEL: test_vsoxseg4_nxv1f64_nxv1i16:
12021 ; CHECK: # %bb.0: # %entry
12022 ; CHECK-NEXT: vmv1r.v v10, v8
12023 ; CHECK-NEXT: vmv1r.v v11, v8
12024 ; CHECK-NEXT: vmv1r.v v12, v8
12025 ; CHECK-NEXT: vmv1r.v v13, v8
12026 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12027 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
12028 ; CHECK-NEXT: ret
12029 entry:
12030 tail call void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
12031 ret void
12032 }
12034 define void @test_vsoxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12035 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_nxv1i16:
12036 ; CHECK: # %bb.0: # %entry
12037 ; CHECK-NEXT: vmv1r.v v10, v8
12038 ; CHECK-NEXT: vmv1r.v v11, v8
12039 ; CHECK-NEXT: vmv1r.v v12, v8
12040 ; CHECK-NEXT: vmv1r.v v13, v8
12041 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12042 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
12043 ; CHECK-NEXT: ret
12044 entry:
12045 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
12046 ret void
12047 }
12049 declare void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
12050 declare void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
12052 define void @test_vsoxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
12053 ; CHECK-LABEL: test_vsoxseg4_nxv1f64_nxv1i8:
12054 ; CHECK: # %bb.0: # %entry
12055 ; CHECK-NEXT: vmv1r.v v10, v8
12056 ; CHECK-NEXT: vmv1r.v v11, v8
12057 ; CHECK-NEXT: vmv1r.v v12, v8
12058 ; CHECK-NEXT: vmv1r.v v13, v8
12059 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12060 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
12061 ; CHECK-NEXT: ret
12062 entry:
12063 tail call void @llvm.riscv.vsoxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
12064 ret void
12065 }
12067 define void @test_vsoxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12068 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_nxv1i8:
12069 ; CHECK: # %bb.0: # %entry
12070 ; CHECK-NEXT: vmv1r.v v10, v8
12071 ; CHECK-NEXT: vmv1r.v v11, v8
12072 ; CHECK-NEXT: vmv1r.v v12, v8
12073 ; CHECK-NEXT: vmv1r.v v13, v8
12074 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12075 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
12076 ; CHECK-NEXT: ret
12077 entry:
12078 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
12079 ret void
12080 }
12082 declare void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
12083 declare void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
12085 define void @test_vsoxseg5_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
12086 ; CHECK-LABEL: test_vsoxseg5_nxv1f64_nxv1i64:
12087 ; CHECK: # %bb.0: # %entry
12088 ; CHECK-NEXT: vmv1r.v v10, v8
12089 ; CHECK-NEXT: vmv1r.v v11, v8
12090 ; CHECK-NEXT: vmv1r.v v12, v8
12091 ; CHECK-NEXT: vmv1r.v v13, v8
12092 ; CHECK-NEXT: vmv1r.v v14, v8
12093 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12094 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
12095 ; CHECK-NEXT: ret
12096 entry:
12097 tail call void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
12098 ret void
12099 }
12101 define void @test_vsoxseg5_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12102 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_nxv1i64:
12103 ; CHECK: # %bb.0: # %entry
12104 ; CHECK-NEXT: vmv1r.v v10, v8
12105 ; CHECK-NEXT: vmv1r.v v11, v8
12106 ; CHECK-NEXT: vmv1r.v v12, v8
12107 ; CHECK-NEXT: vmv1r.v v13, v8
12108 ; CHECK-NEXT: vmv1r.v v14, v8
12109 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12110 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
12111 ; CHECK-NEXT: ret
12112 entry:
12113 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
12114 ret void
12115 }
12117 declare void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
12118 declare void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
12120 define void @test_vsoxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
12121 ; CHECK-LABEL: test_vsoxseg5_nxv1f64_nxv1i32:
12122 ; CHECK: # %bb.0: # %entry
12123 ; CHECK-NEXT: vmv1r.v v10, v8
12124 ; CHECK-NEXT: vmv1r.v v11, v8
12125 ; CHECK-NEXT: vmv1r.v v12, v8
12126 ; CHECK-NEXT: vmv1r.v v13, v8
12127 ; CHECK-NEXT: vmv1r.v v14, v8
12128 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12129 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
12130 ; CHECK-NEXT: ret
12131 entry:
12132 tail call void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
12133 ret void
12134 }
12136 define void @test_vsoxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12137 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_nxv1i32:
12138 ; CHECK: # %bb.0: # %entry
12139 ; CHECK-NEXT: vmv1r.v v10, v8
12140 ; CHECK-NEXT: vmv1r.v v11, v8
12141 ; CHECK-NEXT: vmv1r.v v12, v8
12142 ; CHECK-NEXT: vmv1r.v v13, v8
12143 ; CHECK-NEXT: vmv1r.v v14, v8
12144 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12145 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
12146 ; CHECK-NEXT: ret
12147 entry:
12148 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
12149 ret void
12150 }
12152 declare void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
12153 declare void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
12155 define void @test_vsoxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
12156 ; CHECK-LABEL: test_vsoxseg5_nxv1f64_nxv1i16:
12157 ; CHECK: # %bb.0: # %entry
12158 ; CHECK-NEXT: vmv1r.v v10, v8
12159 ; CHECK-NEXT: vmv1r.v v11, v8
12160 ; CHECK-NEXT: vmv1r.v v12, v8
12161 ; CHECK-NEXT: vmv1r.v v13, v8
12162 ; CHECK-NEXT: vmv1r.v v14, v8
12163 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12164 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
12165 ; CHECK-NEXT: ret
12166 entry:
12167 tail call void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
12168 ret void
12169 }
12171 define void @test_vsoxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12172 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_nxv1i16:
12173 ; CHECK: # %bb.0: # %entry
12174 ; CHECK-NEXT: vmv1r.v v10, v8
12175 ; CHECK-NEXT: vmv1r.v v11, v8
12176 ; CHECK-NEXT: vmv1r.v v12, v8
12177 ; CHECK-NEXT: vmv1r.v v13, v8
12178 ; CHECK-NEXT: vmv1r.v v14, v8
12179 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12180 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
12181 ; CHECK-NEXT: ret
12182 entry:
12183 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
12184 ret void
12185 }
12187 declare void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
12188 declare void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
12190 define void @test_vsoxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
12191 ; CHECK-LABEL: test_vsoxseg5_nxv1f64_nxv1i8:
12192 ; CHECK: # %bb.0: # %entry
12193 ; CHECK-NEXT: vmv1r.v v10, v8
12194 ; CHECK-NEXT: vmv1r.v v11, v8
12195 ; CHECK-NEXT: vmv1r.v v12, v8
12196 ; CHECK-NEXT: vmv1r.v v13, v8
12197 ; CHECK-NEXT: vmv1r.v v14, v8
12198 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12199 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
12200 ; CHECK-NEXT: ret
12201 entry:
12202 tail call void @llvm.riscv.vsoxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
12203 ret void
12204 }
12206 define void @test_vsoxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12207 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_nxv1i8:
12208 ; CHECK: # %bb.0: # %entry
12209 ; CHECK-NEXT: vmv1r.v v10, v8
12210 ; CHECK-NEXT: vmv1r.v v11, v8
12211 ; CHECK-NEXT: vmv1r.v v12, v8
12212 ; CHECK-NEXT: vmv1r.v v13, v8
12213 ; CHECK-NEXT: vmv1r.v v14, v8
12214 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12215 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
12216 ; CHECK-NEXT: ret
12217 entry:
12218 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
12219 ret void
12220 }
12222 declare void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
12223 declare void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
12225 define void @test_vsoxseg6_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
12226 ; CHECK-LABEL: test_vsoxseg6_nxv1f64_nxv1i64:
12227 ; CHECK: # %bb.0: # %entry
12228 ; CHECK-NEXT: vmv1r.v v10, v8
12229 ; CHECK-NEXT: vmv1r.v v11, v8
12230 ; CHECK-NEXT: vmv1r.v v12, v8
12231 ; CHECK-NEXT: vmv1r.v v13, v8
12232 ; CHECK-NEXT: vmv1r.v v14, v8
12233 ; CHECK-NEXT: vmv1r.v v15, v8
12234 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12235 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
12236 ; CHECK-NEXT: ret
12237 entry:
12238 tail call void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
12239 ret void
12240 }
12242 define void @test_vsoxseg6_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12243 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_nxv1i64:
12244 ; CHECK: # %bb.0: # %entry
12245 ; CHECK-NEXT: vmv1r.v v10, v8
12246 ; CHECK-NEXT: vmv1r.v v11, v8
12247 ; CHECK-NEXT: vmv1r.v v12, v8
12248 ; CHECK-NEXT: vmv1r.v v13, v8
12249 ; CHECK-NEXT: vmv1r.v v14, v8
12250 ; CHECK-NEXT: vmv1r.v v15, v8
12251 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12252 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
12253 ; CHECK-NEXT: ret
12254 entry:
12255 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
12256 ret void
12257 }
12259 declare void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
12260 declare void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
12262 define void @test_vsoxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
12263 ; CHECK-LABEL: test_vsoxseg6_nxv1f64_nxv1i32:
12264 ; CHECK: # %bb.0: # %entry
12265 ; CHECK-NEXT: vmv1r.v v10, v8
12266 ; CHECK-NEXT: vmv1r.v v11, v8
12267 ; CHECK-NEXT: vmv1r.v v12, v8
12268 ; CHECK-NEXT: vmv1r.v v13, v8
12269 ; CHECK-NEXT: vmv1r.v v14, v8
12270 ; CHECK-NEXT: vmv1r.v v15, v8
12271 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12272 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
12273 ; CHECK-NEXT: ret
12274 entry:
12275 tail call void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
12276 ret void
12277 }
12279 define void @test_vsoxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12280 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_nxv1i32:
12281 ; CHECK: # %bb.0: # %entry
12282 ; CHECK-NEXT: vmv1r.v v10, v8
12283 ; CHECK-NEXT: vmv1r.v v11, v8
12284 ; CHECK-NEXT: vmv1r.v v12, v8
12285 ; CHECK-NEXT: vmv1r.v v13, v8
12286 ; CHECK-NEXT: vmv1r.v v14, v8
12287 ; CHECK-NEXT: vmv1r.v v15, v8
12288 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12289 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
12290 ; CHECK-NEXT: ret
12291 entry:
12292 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
12293 ret void
12294 }
12296 declare void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
12297 declare void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
12299 define void @test_vsoxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
12300 ; CHECK-LABEL: test_vsoxseg6_nxv1f64_nxv1i16:
12301 ; CHECK: # %bb.0: # %entry
12302 ; CHECK-NEXT: vmv1r.v v10, v8
12303 ; CHECK-NEXT: vmv1r.v v11, v8
12304 ; CHECK-NEXT: vmv1r.v v12, v8
12305 ; CHECK-NEXT: vmv1r.v v13, v8
12306 ; CHECK-NEXT: vmv1r.v v14, v8
12307 ; CHECK-NEXT: vmv1r.v v15, v8
12308 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12309 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
12310 ; CHECK-NEXT: ret
12311 entry:
12312 tail call void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
12313 ret void
12314 }
12316 define void @test_vsoxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12317 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_nxv1i16:
12318 ; CHECK: # %bb.0: # %entry
12319 ; CHECK-NEXT: vmv1r.v v10, v8
12320 ; CHECK-NEXT: vmv1r.v v11, v8
12321 ; CHECK-NEXT: vmv1r.v v12, v8
12322 ; CHECK-NEXT: vmv1r.v v13, v8
12323 ; CHECK-NEXT: vmv1r.v v14, v8
12324 ; CHECK-NEXT: vmv1r.v v15, v8
12325 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12326 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
12327 ; CHECK-NEXT: ret
12328 entry:
12329 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
12330 ret void
12331 }
12333 declare void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
12334 declare void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
12336 define void @test_vsoxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
12337 ; CHECK-LABEL: test_vsoxseg6_nxv1f64_nxv1i8:
12338 ; CHECK: # %bb.0: # %entry
12339 ; CHECK-NEXT: vmv1r.v v10, v8
12340 ; CHECK-NEXT: vmv1r.v v11, v8
12341 ; CHECK-NEXT: vmv1r.v v12, v8
12342 ; CHECK-NEXT: vmv1r.v v13, v8
12343 ; CHECK-NEXT: vmv1r.v v14, v8
12344 ; CHECK-NEXT: vmv1r.v v15, v8
12345 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12346 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
12347 ; CHECK-NEXT: ret
12348 entry:
12349 tail call void @llvm.riscv.vsoxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
12350 ret void
12351 }
12353 define void @test_vsoxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12354 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_nxv1i8:
12355 ; CHECK: # %bb.0: # %entry
12356 ; CHECK-NEXT: vmv1r.v v10, v8
12357 ; CHECK-NEXT: vmv1r.v v11, v8
12358 ; CHECK-NEXT: vmv1r.v v12, v8
12359 ; CHECK-NEXT: vmv1r.v v13, v8
12360 ; CHECK-NEXT: vmv1r.v v14, v8
12361 ; CHECK-NEXT: vmv1r.v v15, v8
12362 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12363 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
12364 ; CHECK-NEXT: ret
12365 entry:
12366 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
12367 ret void
12368 }
12370 declare void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
12371 declare void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
12373 define void @test_vsoxseg7_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
12374 ; CHECK-LABEL: test_vsoxseg7_nxv1f64_nxv1i64:
12375 ; CHECK: # %bb.0: # %entry
12376 ; CHECK-NEXT: vmv1r.v v10, v8
12377 ; CHECK-NEXT: vmv1r.v v11, v8
12378 ; CHECK-NEXT: vmv1r.v v12, v8
12379 ; CHECK-NEXT: vmv1r.v v13, v8
12380 ; CHECK-NEXT: vmv1r.v v14, v8
12381 ; CHECK-NEXT: vmv1r.v v15, v8
12382 ; CHECK-NEXT: vmv1r.v v16, v8
12383 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12384 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
12385 ; CHECK-NEXT: ret
12386 entry:
12387 tail call void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
12388 ret void
12389 }
12391 define void @test_vsoxseg7_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12392 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_nxv1i64:
12393 ; CHECK: # %bb.0: # %entry
12394 ; CHECK-NEXT: vmv1r.v v10, v8
12395 ; CHECK-NEXT: vmv1r.v v11, v8
12396 ; CHECK-NEXT: vmv1r.v v12, v8
12397 ; CHECK-NEXT: vmv1r.v v13, v8
12398 ; CHECK-NEXT: vmv1r.v v14, v8
12399 ; CHECK-NEXT: vmv1r.v v15, v8
12400 ; CHECK-NEXT: vmv1r.v v16, v8
12401 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12402 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
12403 ; CHECK-NEXT: ret
12404 entry:
12405 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
12406 ret void
12407 }
12409 declare void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
12410 declare void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
12412 define void @test_vsoxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
12413 ; CHECK-LABEL: test_vsoxseg7_nxv1f64_nxv1i32:
12414 ; CHECK: # %bb.0: # %entry
12415 ; CHECK-NEXT: vmv1r.v v10, v8
12416 ; CHECK-NEXT: vmv1r.v v11, v8
12417 ; CHECK-NEXT: vmv1r.v v12, v8
12418 ; CHECK-NEXT: vmv1r.v v13, v8
12419 ; CHECK-NEXT: vmv1r.v v14, v8
12420 ; CHECK-NEXT: vmv1r.v v15, v8
12421 ; CHECK-NEXT: vmv1r.v v16, v8
12422 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12423 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
12424 ; CHECK-NEXT: ret
12425 entry:
12426 tail call void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
12427 ret void
12428 }
12430 define void @test_vsoxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12431 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_nxv1i32:
12432 ; CHECK: # %bb.0: # %entry
12433 ; CHECK-NEXT: vmv1r.v v10, v8
12434 ; CHECK-NEXT: vmv1r.v v11, v8
12435 ; CHECK-NEXT: vmv1r.v v12, v8
12436 ; CHECK-NEXT: vmv1r.v v13, v8
12437 ; CHECK-NEXT: vmv1r.v v14, v8
12438 ; CHECK-NEXT: vmv1r.v v15, v8
12439 ; CHECK-NEXT: vmv1r.v v16, v8
12440 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12441 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
12442 ; CHECK-NEXT: ret
12443 entry:
12444 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
12445 ret void
12446 }
12448 declare void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
12449 declare void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
12451 define void @test_vsoxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
12452 ; CHECK-LABEL: test_vsoxseg7_nxv1f64_nxv1i16:
12453 ; CHECK: # %bb.0: # %entry
12454 ; CHECK-NEXT: vmv1r.v v10, v8
12455 ; CHECK-NEXT: vmv1r.v v11, v8
12456 ; CHECK-NEXT: vmv1r.v v12, v8
12457 ; CHECK-NEXT: vmv1r.v v13, v8
12458 ; CHECK-NEXT: vmv1r.v v14, v8
12459 ; CHECK-NEXT: vmv1r.v v15, v8
12460 ; CHECK-NEXT: vmv1r.v v16, v8
12461 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12462 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
12463 ; CHECK-NEXT: ret
12464 entry:
12465 tail call void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
12466 ret void
12467 }
12469 define void @test_vsoxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12470 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_nxv1i16:
12471 ; CHECK: # %bb.0: # %entry
12472 ; CHECK-NEXT: vmv1r.v v10, v8
12473 ; CHECK-NEXT: vmv1r.v v11, v8
12474 ; CHECK-NEXT: vmv1r.v v12, v8
12475 ; CHECK-NEXT: vmv1r.v v13, v8
12476 ; CHECK-NEXT: vmv1r.v v14, v8
12477 ; CHECK-NEXT: vmv1r.v v15, v8
12478 ; CHECK-NEXT: vmv1r.v v16, v8
12479 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12480 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
12481 ; CHECK-NEXT: ret
12482 entry:
12483 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
12484 ret void
12485 }
12487 declare void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
12488 declare void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
12490 define void @test_vsoxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
12491 ; CHECK-LABEL: test_vsoxseg7_nxv1f64_nxv1i8:
12492 ; CHECK: # %bb.0: # %entry
12493 ; CHECK-NEXT: vmv1r.v v10, v8
12494 ; CHECK-NEXT: vmv1r.v v11, v8
12495 ; CHECK-NEXT: vmv1r.v v12, v8
12496 ; CHECK-NEXT: vmv1r.v v13, v8
12497 ; CHECK-NEXT: vmv1r.v v14, v8
12498 ; CHECK-NEXT: vmv1r.v v15, v8
12499 ; CHECK-NEXT: vmv1r.v v16, v8
12500 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12501 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
12502 ; CHECK-NEXT: ret
12503 entry:
12504 tail call void @llvm.riscv.vsoxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
12505 ret void
12506 }
12508 define void @test_vsoxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12509 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_nxv1i8:
12510 ; CHECK: # %bb.0: # %entry
12511 ; CHECK-NEXT: vmv1r.v v10, v8
12512 ; CHECK-NEXT: vmv1r.v v11, v8
12513 ; CHECK-NEXT: vmv1r.v v12, v8
12514 ; CHECK-NEXT: vmv1r.v v13, v8
12515 ; CHECK-NEXT: vmv1r.v v14, v8
12516 ; CHECK-NEXT: vmv1r.v v15, v8
12517 ; CHECK-NEXT: vmv1r.v v16, v8
12518 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12519 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
12520 ; CHECK-NEXT: ret
12521 entry:
12522 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
12523 ret void
12524 }
12526 declare void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, i64)
12527 declare void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
12529 define void @test_vsoxseg8_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
12530 ; CHECK-LABEL: test_vsoxseg8_nxv1f64_nxv1i64:
12531 ; CHECK: # %bb.0: # %entry
12532 ; CHECK-NEXT: vmv1r.v v10, v8
12533 ; CHECK-NEXT: vmv1r.v v11, v8
12534 ; CHECK-NEXT: vmv1r.v v12, v8
12535 ; CHECK-NEXT: vmv1r.v v13, v8
12536 ; CHECK-NEXT: vmv1r.v v14, v8
12537 ; CHECK-NEXT: vmv1r.v v15, v8
12538 ; CHECK-NEXT: vmv1r.v v16, v8
12539 ; CHECK-NEXT: vmv1r.v v17, v8
12540 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12541 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
12542 ; CHECK-NEXT: ret
12543 entry:
12544 tail call void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
12545 ret void
12546 }
12548 define void @test_vsoxseg8_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12549 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_nxv1i64:
12550 ; CHECK: # %bb.0: # %entry
12551 ; CHECK-NEXT: vmv1r.v v10, v8
12552 ; CHECK-NEXT: vmv1r.v v11, v8
12553 ; CHECK-NEXT: vmv1r.v v12, v8
12554 ; CHECK-NEXT: vmv1r.v v13, v8
12555 ; CHECK-NEXT: vmv1r.v v14, v8
12556 ; CHECK-NEXT: vmv1r.v v15, v8
12557 ; CHECK-NEXT: vmv1r.v v16, v8
12558 ; CHECK-NEXT: vmv1r.v v17, v8
12559 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12560 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
12561 ; CHECK-NEXT: ret
12562 entry:
12563 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
12564 ret void
12565 }
12567 declare void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, i64)
12568 declare void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
12570 define void @test_vsoxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
12571 ; CHECK-LABEL: test_vsoxseg8_nxv1f64_nxv1i32:
12572 ; CHECK: # %bb.0: # %entry
12573 ; CHECK-NEXT: vmv1r.v v10, v8
12574 ; CHECK-NEXT: vmv1r.v v11, v8
12575 ; CHECK-NEXT: vmv1r.v v12, v8
12576 ; CHECK-NEXT: vmv1r.v v13, v8
12577 ; CHECK-NEXT: vmv1r.v v14, v8
12578 ; CHECK-NEXT: vmv1r.v v15, v8
12579 ; CHECK-NEXT: vmv1r.v v16, v8
12580 ; CHECK-NEXT: vmv1r.v v17, v8
12581 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12582 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
12583 ; CHECK-NEXT: ret
12584 entry:
12585 tail call void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
12586 ret void
12587 }
12589 define void @test_vsoxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12590 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_nxv1i32:
12591 ; CHECK: # %bb.0: # %entry
12592 ; CHECK-NEXT: vmv1r.v v10, v8
12593 ; CHECK-NEXT: vmv1r.v v11, v8
12594 ; CHECK-NEXT: vmv1r.v v12, v8
12595 ; CHECK-NEXT: vmv1r.v v13, v8
12596 ; CHECK-NEXT: vmv1r.v v14, v8
12597 ; CHECK-NEXT: vmv1r.v v15, v8
12598 ; CHECK-NEXT: vmv1r.v v16, v8
12599 ; CHECK-NEXT: vmv1r.v v17, v8
12600 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12601 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
12602 ; CHECK-NEXT: ret
12603 entry:
12604 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
12605 ret void
12606 }
12608 declare void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, i64)
12609 declare void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
12611 define void @test_vsoxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
12612 ; CHECK-LABEL: test_vsoxseg8_nxv1f64_nxv1i16:
12613 ; CHECK: # %bb.0: # %entry
12614 ; CHECK-NEXT: vmv1r.v v10, v8
12615 ; CHECK-NEXT: vmv1r.v v11, v8
12616 ; CHECK-NEXT: vmv1r.v v12, v8
12617 ; CHECK-NEXT: vmv1r.v v13, v8
12618 ; CHECK-NEXT: vmv1r.v v14, v8
12619 ; CHECK-NEXT: vmv1r.v v15, v8
12620 ; CHECK-NEXT: vmv1r.v v16, v8
12621 ; CHECK-NEXT: vmv1r.v v17, v8
12622 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12623 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
12624 ; CHECK-NEXT: ret
12625 entry:
12626 tail call void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
12627 ret void
12628 }
12630 define void @test_vsoxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12631 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_nxv1i16:
12632 ; CHECK: # %bb.0: # %entry
12633 ; CHECK-NEXT: vmv1r.v v10, v8
12634 ; CHECK-NEXT: vmv1r.v v11, v8
12635 ; CHECK-NEXT: vmv1r.v v12, v8
12636 ; CHECK-NEXT: vmv1r.v v13, v8
12637 ; CHECK-NEXT: vmv1r.v v14, v8
12638 ; CHECK-NEXT: vmv1r.v v15, v8
12639 ; CHECK-NEXT: vmv1r.v v16, v8
12640 ; CHECK-NEXT: vmv1r.v v17, v8
12641 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12642 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
12643 ; CHECK-NEXT: ret
12644 entry:
12645 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
12646 ret void
12647 }
12649 declare void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, i64)
12650 declare void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
12652 define void @test_vsoxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
12653 ; CHECK-LABEL: test_vsoxseg8_nxv1f64_nxv1i8:
12654 ; CHECK: # %bb.0: # %entry
12655 ; CHECK-NEXT: vmv1r.v v10, v8
12656 ; CHECK-NEXT: vmv1r.v v11, v8
12657 ; CHECK-NEXT: vmv1r.v v12, v8
12658 ; CHECK-NEXT: vmv1r.v v13, v8
12659 ; CHECK-NEXT: vmv1r.v v14, v8
12660 ; CHECK-NEXT: vmv1r.v v15, v8
12661 ; CHECK-NEXT: vmv1r.v v16, v8
12662 ; CHECK-NEXT: vmv1r.v v17, v8
12663 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12664 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
12665 ; CHECK-NEXT: ret
12666 entry:
12667 tail call void @llvm.riscv.vsoxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
12668 ret void
12669 }
12671 define void @test_vsoxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
12672 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_nxv1i8:
12673 ; CHECK: # %bb.0: # %entry
12674 ; CHECK-NEXT: vmv1r.v v10, v8
12675 ; CHECK-NEXT: vmv1r.v v11, v8
12676 ; CHECK-NEXT: vmv1r.v v12, v8
12677 ; CHECK-NEXT: vmv1r.v v13, v8
12678 ; CHECK-NEXT: vmv1r.v v14, v8
12679 ; CHECK-NEXT: vmv1r.v v15, v8
12680 ; CHECK-NEXT: vmv1r.v v16, v8
12681 ; CHECK-NEXT: vmv1r.v v17, v8
12682 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
12683 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
12684 ; CHECK-NEXT: ret
12685 entry:
12686 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
12687 ret void
12688 }
12690 declare void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
12691 declare void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
12693 define void @test_vsoxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
12694 ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i32:
12695 ; CHECK: # %bb.0: # %entry
12696 ; CHECK-NEXT: vmv1r.v v10, v9
12697 ; CHECK-NEXT: vmv1r.v v9, v8
12698 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12699 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
12700 ; CHECK-NEXT: ret
12701 entry:
12702 tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
12703 ret void
12704 }
12706 define void @test_vsoxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12707 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i32:
12708 ; CHECK: # %bb.0: # %entry
12709 ; CHECK-NEXT: vmv1r.v v10, v9
12710 ; CHECK-NEXT: vmv1r.v v9, v8
12711 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12712 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
12713 ; CHECK-NEXT: ret
12714 entry:
12715 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
12716 ret void
12717 }
12719 declare void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
12720 declare void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
12722 define void @test_vsoxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
12723 ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i8:
12724 ; CHECK: # %bb.0: # %entry
12725 ; CHECK-NEXT: vmv1r.v v10, v9
12726 ; CHECK-NEXT: vmv1r.v v9, v8
12727 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12728 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
12729 ; CHECK-NEXT: ret
12730 entry:
12731 tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
12732 ret void
12733 }
12735 define void @test_vsoxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12736 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i8:
12737 ; CHECK: # %bb.0: # %entry
12738 ; CHECK-NEXT: vmv1r.v v10, v9
12739 ; CHECK-NEXT: vmv1r.v v9, v8
12740 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12741 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
12742 ; CHECK-NEXT: ret
12743 entry:
12744 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
12745 ret void
12746 }
12748 declare void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
12749 declare void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
12751 define void @test_vsoxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
12752 ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i16:
12753 ; CHECK: # %bb.0: # %entry
12754 ; CHECK-NEXT: vmv1r.v v10, v9
12755 ; CHECK-NEXT: vmv1r.v v9, v8
12756 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12757 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
12758 ; CHECK-NEXT: ret
12759 entry:
12760 tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
12761 ret void
12762 }
12764 define void @test_vsoxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12765 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i16:
12766 ; CHECK: # %bb.0: # %entry
12767 ; CHECK-NEXT: vmv1r.v v10, v9
12768 ; CHECK-NEXT: vmv1r.v v9, v8
12769 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12770 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
12771 ; CHECK-NEXT: ret
12772 entry:
12773 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
12774 ret void
12775 }
12777 declare void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
12778 declare void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
12780 define void @test_vsoxseg2_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
12781 ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i64:
12782 ; CHECK: # %bb.0: # %entry
12783 ; CHECK-NEXT: vmv1r.v v9, v8
12784 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12785 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
12786 ; CHECK-NEXT: ret
12787 entry:
12788 tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
12789 ret void
12790 }
12792 define void @test_vsoxseg2_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12793 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i64:
12794 ; CHECK: # %bb.0: # %entry
12795 ; CHECK-NEXT: vmv1r.v v9, v8
12796 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12797 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
12798 ; CHECK-NEXT: ret
12799 entry:
12800 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
12801 ret void
12802 }
12804 declare void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
12805 declare void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
12807 define void @test_vsoxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
12808 ; CHECK-LABEL: test_vsoxseg3_nxv2f32_nxv2i32:
12809 ; CHECK: # %bb.0: # %entry
12810 ; CHECK-NEXT: vmv1r.v v10, v8
12811 ; CHECK-NEXT: vmv1r.v v11, v8
12812 ; CHECK-NEXT: vmv1r.v v12, v8
12813 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12814 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
12815 ; CHECK-NEXT: ret
12816 entry:
12817 tail call void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
12818 ret void
12819 }
12821 define void @test_vsoxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12822 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_nxv2i32:
12823 ; CHECK: # %bb.0: # %entry
12824 ; CHECK-NEXT: vmv1r.v v10, v8
12825 ; CHECK-NEXT: vmv1r.v v11, v8
12826 ; CHECK-NEXT: vmv1r.v v12, v8
12827 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12828 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
12829 ; CHECK-NEXT: ret
12830 entry:
12831 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
12832 ret void
12833 }
12835 declare void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
12836 declare void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
12838 define void @test_vsoxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
12839 ; CHECK-LABEL: test_vsoxseg3_nxv2f32_nxv2i8:
12840 ; CHECK: # %bb.0: # %entry
12841 ; CHECK-NEXT: vmv1r.v v10, v8
12842 ; CHECK-NEXT: vmv1r.v v11, v8
12843 ; CHECK-NEXT: vmv1r.v v12, v8
12844 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12845 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
12846 ; CHECK-NEXT: ret
12847 entry:
12848 tail call void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
12849 ret void
12850 }
12852 define void @test_vsoxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12853 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_nxv2i8:
12854 ; CHECK: # %bb.0: # %entry
12855 ; CHECK-NEXT: vmv1r.v v10, v8
12856 ; CHECK-NEXT: vmv1r.v v11, v8
12857 ; CHECK-NEXT: vmv1r.v v12, v8
12858 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12859 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
12860 ; CHECK-NEXT: ret
12861 entry:
12862 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
12863 ret void
12864 }
12866 declare void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
12867 declare void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
12869 define void @test_vsoxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
12870 ; CHECK-LABEL: test_vsoxseg3_nxv2f32_nxv2i16:
12871 ; CHECK: # %bb.0: # %entry
12872 ; CHECK-NEXT: vmv1r.v v10, v8
12873 ; CHECK-NEXT: vmv1r.v v11, v8
12874 ; CHECK-NEXT: vmv1r.v v12, v8
12875 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12876 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
12877 ; CHECK-NEXT: ret
12878 entry:
12879 tail call void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
12880 ret void
12881 }
12883 define void @test_vsoxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12884 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_nxv2i16:
12885 ; CHECK: # %bb.0: # %entry
12886 ; CHECK-NEXT: vmv1r.v v10, v8
12887 ; CHECK-NEXT: vmv1r.v v11, v8
12888 ; CHECK-NEXT: vmv1r.v v12, v8
12889 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12890 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
12891 ; CHECK-NEXT: ret
12892 entry:
12893 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
12894 ret void
12895 }
12897 declare void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
12898 declare void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
12900 define void @test_vsoxseg3_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
12901 ; CHECK-LABEL: test_vsoxseg3_nxv2f32_nxv2i64:
12902 ; CHECK: # %bb.0: # %entry
12903 ; CHECK-NEXT: vmv1r.v v9, v8
12904 ; CHECK-NEXT: vmv2r.v v12, v10
12905 ; CHECK-NEXT: vmv1r.v v10, v8
12906 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12907 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
12908 ; CHECK-NEXT: ret
12909 entry:
12910 tail call void @llvm.riscv.vsoxseg3.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
12911 ret void
12912 }
12914 define void @test_vsoxseg3_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12915 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_nxv2i64:
12916 ; CHECK: # %bb.0: # %entry
12917 ; CHECK-NEXT: vmv1r.v v9, v8
12918 ; CHECK-NEXT: vmv2r.v v12, v10
12919 ; CHECK-NEXT: vmv1r.v v10, v8
12920 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12921 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
12922 ; CHECK-NEXT: ret
12923 entry:
12924 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
12925 ret void
12926 }
12928 declare void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
12929 declare void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
12931 define void @test_vsoxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
12932 ; CHECK-LABEL: test_vsoxseg4_nxv2f32_nxv2i32:
12933 ; CHECK: # %bb.0: # %entry
12934 ; CHECK-NEXT: vmv1r.v v10, v8
12935 ; CHECK-NEXT: vmv1r.v v11, v8
12936 ; CHECK-NEXT: vmv1r.v v12, v8
12937 ; CHECK-NEXT: vmv1r.v v13, v8
12938 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12939 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
12940 ; CHECK-NEXT: ret
12941 entry:
12942 tail call void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
12943 ret void
12944 }
12946 define void @test_vsoxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12947 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_nxv2i32:
12948 ; CHECK: # %bb.0: # %entry
12949 ; CHECK-NEXT: vmv1r.v v10, v8
12950 ; CHECK-NEXT: vmv1r.v v11, v8
12951 ; CHECK-NEXT: vmv1r.v v12, v8
12952 ; CHECK-NEXT: vmv1r.v v13, v8
12953 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12954 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
12955 ; CHECK-NEXT: ret
12956 entry:
12957 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
12958 ret void
12959 }
12961 declare void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
12962 declare void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
12964 define void @test_vsoxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
12965 ; CHECK-LABEL: test_vsoxseg4_nxv2f32_nxv2i8:
12966 ; CHECK: # %bb.0: # %entry
12967 ; CHECK-NEXT: vmv1r.v v10, v8
12968 ; CHECK-NEXT: vmv1r.v v11, v8
12969 ; CHECK-NEXT: vmv1r.v v12, v8
12970 ; CHECK-NEXT: vmv1r.v v13, v8
12971 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12972 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
12973 ; CHECK-NEXT: ret
12974 entry:
12975 tail call void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
12976 ret void
12977 }
12979 define void @test_vsoxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
12980 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_nxv2i8:
12981 ; CHECK: # %bb.0: # %entry
12982 ; CHECK-NEXT: vmv1r.v v10, v8
12983 ; CHECK-NEXT: vmv1r.v v11, v8
12984 ; CHECK-NEXT: vmv1r.v v12, v8
12985 ; CHECK-NEXT: vmv1r.v v13, v8
12986 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
12987 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
12988 ; CHECK-NEXT: ret
12989 entry:
12990 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
12991 ret void
12992 }
12994 declare void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
12995 declare void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
12997 define void @test_vsoxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
12998 ; CHECK-LABEL: test_vsoxseg4_nxv2f32_nxv2i16:
12999 ; CHECK: # %bb.0: # %entry
13000 ; CHECK-NEXT: vmv1r.v v10, v8
13001 ; CHECK-NEXT: vmv1r.v v11, v8
13002 ; CHECK-NEXT: vmv1r.v v12, v8
13003 ; CHECK-NEXT: vmv1r.v v13, v8
13004 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13005 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
13006 ; CHECK-NEXT: ret
13007 entry:
13008 tail call void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
13009 ret void
13010 }
13012 define void @test_vsoxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13013 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_nxv2i16:
13014 ; CHECK: # %bb.0: # %entry
13015 ; CHECK-NEXT: vmv1r.v v10, v8
13016 ; CHECK-NEXT: vmv1r.v v11, v8
13017 ; CHECK-NEXT: vmv1r.v v12, v8
13018 ; CHECK-NEXT: vmv1r.v v13, v8
13019 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13020 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
13021 ; CHECK-NEXT: ret
13022 entry:
13023 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
13024 ret void
13025 }
13027 declare void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
13028 declare void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
13030 define void @test_vsoxseg4_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
13031 ; CHECK-LABEL: test_vsoxseg4_nxv2f32_nxv2i64:
13032 ; CHECK: # %bb.0: # %entry
13033 ; CHECK-NEXT: vmv1r.v v12, v8
13034 ; CHECK-NEXT: vmv1r.v v13, v8
13035 ; CHECK-NEXT: vmv1r.v v14, v8
13036 ; CHECK-NEXT: vmv1r.v v15, v8
13037 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13038 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
13039 ; CHECK-NEXT: ret
13040 entry:
13041 tail call void @llvm.riscv.vsoxseg4.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
13042 ret void
13043 }
13045 define void @test_vsoxseg4_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13046 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_nxv2i64:
13047 ; CHECK: # %bb.0: # %entry
13048 ; CHECK-NEXT: vmv1r.v v12, v8
13049 ; CHECK-NEXT: vmv1r.v v13, v8
13050 ; CHECK-NEXT: vmv1r.v v14, v8
13051 ; CHECK-NEXT: vmv1r.v v15, v8
13052 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13053 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
13054 ; CHECK-NEXT: ret
13055 entry:
13056 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
13057 ret void
13058 }
13060 declare void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
13061 declare void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
13063 define void @test_vsoxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
13064 ; CHECK-LABEL: test_vsoxseg5_nxv2f32_nxv2i32:
13065 ; CHECK: # %bb.0: # %entry
13066 ; CHECK-NEXT: vmv1r.v v10, v8
13067 ; CHECK-NEXT: vmv1r.v v11, v8
13068 ; CHECK-NEXT: vmv1r.v v12, v8
13069 ; CHECK-NEXT: vmv1r.v v13, v8
13070 ; CHECK-NEXT: vmv1r.v v14, v8
13071 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13072 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
13073 ; CHECK-NEXT: ret
13074 entry:
13075 tail call void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
13076 ret void
13077 }
13079 define void @test_vsoxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13080 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_nxv2i32:
13081 ; CHECK: # %bb.0: # %entry
13082 ; CHECK-NEXT: vmv1r.v v10, v8
13083 ; CHECK-NEXT: vmv1r.v v11, v8
13084 ; CHECK-NEXT: vmv1r.v v12, v8
13085 ; CHECK-NEXT: vmv1r.v v13, v8
13086 ; CHECK-NEXT: vmv1r.v v14, v8
13087 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13088 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
13089 ; CHECK-NEXT: ret
13090 entry:
13091 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
13092 ret void
13093 }
13095 declare void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
13096 declare void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
13098 define void @test_vsoxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
13099 ; CHECK-LABEL: test_vsoxseg5_nxv2f32_nxv2i8:
13100 ; CHECK: # %bb.0: # %entry
13101 ; CHECK-NEXT: vmv1r.v v10, v8
13102 ; CHECK-NEXT: vmv1r.v v11, v8
13103 ; CHECK-NEXT: vmv1r.v v12, v8
13104 ; CHECK-NEXT: vmv1r.v v13, v8
13105 ; CHECK-NEXT: vmv1r.v v14, v8
13106 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13107 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
13108 ; CHECK-NEXT: ret
13109 entry:
13110 tail call void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
13111 ret void
13112 }
13114 define void @test_vsoxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13115 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_nxv2i8:
13116 ; CHECK: # %bb.0: # %entry
13117 ; CHECK-NEXT: vmv1r.v v10, v8
13118 ; CHECK-NEXT: vmv1r.v v11, v8
13119 ; CHECK-NEXT: vmv1r.v v12, v8
13120 ; CHECK-NEXT: vmv1r.v v13, v8
13121 ; CHECK-NEXT: vmv1r.v v14, v8
13122 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13123 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
13124 ; CHECK-NEXT: ret
13125 entry:
13126 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
13127 ret void
13128 }
13130 declare void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
13131 declare void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
13133 define void @test_vsoxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
13134 ; CHECK-LABEL: test_vsoxseg5_nxv2f32_nxv2i16:
13135 ; CHECK: # %bb.0: # %entry
13136 ; CHECK-NEXT: vmv1r.v v10, v8
13137 ; CHECK-NEXT: vmv1r.v v11, v8
13138 ; CHECK-NEXT: vmv1r.v v12, v8
13139 ; CHECK-NEXT: vmv1r.v v13, v8
13140 ; CHECK-NEXT: vmv1r.v v14, v8
13141 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13142 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
13143 ; CHECK-NEXT: ret
13144 entry:
13145 tail call void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
13146 ret void
13147 }
13149 define void @test_vsoxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13150 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_nxv2i16:
13151 ; CHECK: # %bb.0: # %entry
13152 ; CHECK-NEXT: vmv1r.v v10, v8
13153 ; CHECK-NEXT: vmv1r.v v11, v8
13154 ; CHECK-NEXT: vmv1r.v v12, v8
13155 ; CHECK-NEXT: vmv1r.v v13, v8
13156 ; CHECK-NEXT: vmv1r.v v14, v8
13157 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13158 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
13159 ; CHECK-NEXT: ret
13160 entry:
13161 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
13162 ret void
13163 }
13165 declare void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
13166 declare void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
13168 define void @test_vsoxseg5_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
13169 ; CHECK-LABEL: test_vsoxseg5_nxv2f32_nxv2i64:
13170 ; CHECK: # %bb.0: # %entry
13171 ; CHECK-NEXT: vmv1r.v v12, v8
13172 ; CHECK-NEXT: vmv1r.v v13, v8
13173 ; CHECK-NEXT: vmv1r.v v14, v8
13174 ; CHECK-NEXT: vmv1r.v v15, v8
13175 ; CHECK-NEXT: vmv1r.v v16, v8
13176 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13177 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10
13178 ; CHECK-NEXT: ret
13179 entry:
13180 tail call void @llvm.riscv.vsoxseg5.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
13181 ret void
13182 }
13184 define void @test_vsoxseg5_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13185 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_nxv2i64:
13186 ; CHECK: # %bb.0: # %entry
13187 ; CHECK-NEXT: vmv1r.v v12, v8
13188 ; CHECK-NEXT: vmv1r.v v13, v8
13189 ; CHECK-NEXT: vmv1r.v v14, v8
13190 ; CHECK-NEXT: vmv1r.v v15, v8
13191 ; CHECK-NEXT: vmv1r.v v16, v8
13192 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13193 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10, v0.t
13194 ; CHECK-NEXT: ret
13195 entry:
13196 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
13197 ret void
13198 }
13200 declare void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
13201 declare void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
13203 define void @test_vsoxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
13204 ; CHECK-LABEL: test_vsoxseg6_nxv2f32_nxv2i32:
13205 ; CHECK: # %bb.0: # %entry
13206 ; CHECK-NEXT: vmv1r.v v10, v8
13207 ; CHECK-NEXT: vmv1r.v v11, v8
13208 ; CHECK-NEXT: vmv1r.v v12, v8
13209 ; CHECK-NEXT: vmv1r.v v13, v8
13210 ; CHECK-NEXT: vmv1r.v v14, v8
13211 ; CHECK-NEXT: vmv1r.v v15, v8
13212 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13213 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
13214 ; CHECK-NEXT: ret
13215 entry:
13216 tail call void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
13217 ret void
13218 }
13220 define void @test_vsoxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13221 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_nxv2i32:
13222 ; CHECK: # %bb.0: # %entry
13223 ; CHECK-NEXT: vmv1r.v v10, v8
13224 ; CHECK-NEXT: vmv1r.v v11, v8
13225 ; CHECK-NEXT: vmv1r.v v12, v8
13226 ; CHECK-NEXT: vmv1r.v v13, v8
13227 ; CHECK-NEXT: vmv1r.v v14, v8
13228 ; CHECK-NEXT: vmv1r.v v15, v8
13229 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13230 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
13231 ; CHECK-NEXT: ret
13232 entry:
13233 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
13234 ret void
13235 }
13237 declare void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
13238 declare void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
13240 define void @test_vsoxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
13241 ; CHECK-LABEL: test_vsoxseg6_nxv2f32_nxv2i8:
13242 ; CHECK: # %bb.0: # %entry
13243 ; CHECK-NEXT: vmv1r.v v10, v8
13244 ; CHECK-NEXT: vmv1r.v v11, v8
13245 ; CHECK-NEXT: vmv1r.v v12, v8
13246 ; CHECK-NEXT: vmv1r.v v13, v8
13247 ; CHECK-NEXT: vmv1r.v v14, v8
13248 ; CHECK-NEXT: vmv1r.v v15, v8
13249 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13250 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
13251 ; CHECK-NEXT: ret
13252 entry:
13253 tail call void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
13254 ret void
13255 }
13257 define void @test_vsoxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13258 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_nxv2i8:
13259 ; CHECK: # %bb.0: # %entry
13260 ; CHECK-NEXT: vmv1r.v v10, v8
13261 ; CHECK-NEXT: vmv1r.v v11, v8
13262 ; CHECK-NEXT: vmv1r.v v12, v8
13263 ; CHECK-NEXT: vmv1r.v v13, v8
13264 ; CHECK-NEXT: vmv1r.v v14, v8
13265 ; CHECK-NEXT: vmv1r.v v15, v8
13266 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13267 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
13268 ; CHECK-NEXT: ret
13269 entry:
13270 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
13271 ret void
13272 }
13274 declare void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
13275 declare void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
13277 define void @test_vsoxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
13278 ; CHECK-LABEL: test_vsoxseg6_nxv2f32_nxv2i16:
13279 ; CHECK: # %bb.0: # %entry
13280 ; CHECK-NEXT: vmv1r.v v10, v8
13281 ; CHECK-NEXT: vmv1r.v v11, v8
13282 ; CHECK-NEXT: vmv1r.v v12, v8
13283 ; CHECK-NEXT: vmv1r.v v13, v8
13284 ; CHECK-NEXT: vmv1r.v v14, v8
13285 ; CHECK-NEXT: vmv1r.v v15, v8
13286 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13287 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
13288 ; CHECK-NEXT: ret
13289 entry:
13290 tail call void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
13291 ret void
13292 }
13294 define void @test_vsoxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13295 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_nxv2i16:
13296 ; CHECK: # %bb.0: # %entry
13297 ; CHECK-NEXT: vmv1r.v v10, v8
13298 ; CHECK-NEXT: vmv1r.v v11, v8
13299 ; CHECK-NEXT: vmv1r.v v12, v8
13300 ; CHECK-NEXT: vmv1r.v v13, v8
13301 ; CHECK-NEXT: vmv1r.v v14, v8
13302 ; CHECK-NEXT: vmv1r.v v15, v8
13303 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13304 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
13305 ; CHECK-NEXT: ret
13306 entry:
13307 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
13308 ret void
13309 }
13311 declare void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
13312 declare void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
13314 define void @test_vsoxseg6_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
13315 ; CHECK-LABEL: test_vsoxseg6_nxv2f32_nxv2i64:
13316 ; CHECK: # %bb.0: # %entry
13317 ; CHECK-NEXT: vmv1r.v v12, v8
13318 ; CHECK-NEXT: vmv1r.v v13, v8
13319 ; CHECK-NEXT: vmv1r.v v14, v8
13320 ; CHECK-NEXT: vmv1r.v v15, v8
13321 ; CHECK-NEXT: vmv1r.v v16, v8
13322 ; CHECK-NEXT: vmv1r.v v17, v8
13323 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13324 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10
13325 ; CHECK-NEXT: ret
13326 entry:
13327 tail call void @llvm.riscv.vsoxseg6.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
13328 ret void
13329 }
13331 define void @test_vsoxseg6_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13332 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_nxv2i64:
13333 ; CHECK: # %bb.0: # %entry
13334 ; CHECK-NEXT: vmv1r.v v12, v8
13335 ; CHECK-NEXT: vmv1r.v v13, v8
13336 ; CHECK-NEXT: vmv1r.v v14, v8
13337 ; CHECK-NEXT: vmv1r.v v15, v8
13338 ; CHECK-NEXT: vmv1r.v v16, v8
13339 ; CHECK-NEXT: vmv1r.v v17, v8
13340 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13341 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10, v0.t
13342 ; CHECK-NEXT: ret
13343 entry:
13344 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
13345 ret void
13346 }
13348 declare void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
13349 declare void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
13351 define void @test_vsoxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
13352 ; CHECK-LABEL: test_vsoxseg7_nxv2f32_nxv2i32:
13353 ; CHECK: # %bb.0: # %entry
13354 ; CHECK-NEXT: vmv1r.v v10, v8
13355 ; CHECK-NEXT: vmv1r.v v11, v8
13356 ; CHECK-NEXT: vmv1r.v v12, v8
13357 ; CHECK-NEXT: vmv1r.v v13, v8
13358 ; CHECK-NEXT: vmv1r.v v14, v8
13359 ; CHECK-NEXT: vmv1r.v v15, v8
13360 ; CHECK-NEXT: vmv1r.v v16, v8
13361 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13362 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
13363 ; CHECK-NEXT: ret
13364 entry:
13365 tail call void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
13366 ret void
13367 }
13369 define void @test_vsoxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13370 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_nxv2i32:
13371 ; CHECK: # %bb.0: # %entry
13372 ; CHECK-NEXT: vmv1r.v v10, v8
13373 ; CHECK-NEXT: vmv1r.v v11, v8
13374 ; CHECK-NEXT: vmv1r.v v12, v8
13375 ; CHECK-NEXT: vmv1r.v v13, v8
13376 ; CHECK-NEXT: vmv1r.v v14, v8
13377 ; CHECK-NEXT: vmv1r.v v15, v8
13378 ; CHECK-NEXT: vmv1r.v v16, v8
13379 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13380 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
13381 ; CHECK-NEXT: ret
13382 entry:
13383 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
13384 ret void
13385 }
13387 declare void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
13388 declare void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
13390 define void @test_vsoxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
13391 ; CHECK-LABEL: test_vsoxseg7_nxv2f32_nxv2i8:
13392 ; CHECK: # %bb.0: # %entry
13393 ; CHECK-NEXT: vmv1r.v v10, v8
13394 ; CHECK-NEXT: vmv1r.v v11, v8
13395 ; CHECK-NEXT: vmv1r.v v12, v8
13396 ; CHECK-NEXT: vmv1r.v v13, v8
13397 ; CHECK-NEXT: vmv1r.v v14, v8
13398 ; CHECK-NEXT: vmv1r.v v15, v8
13399 ; CHECK-NEXT: vmv1r.v v16, v8
13400 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13401 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
13402 ; CHECK-NEXT: ret
13403 entry:
13404 tail call void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
13405 ret void
13406 }
13408 define void @test_vsoxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13409 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_nxv2i8:
13410 ; CHECK: # %bb.0: # %entry
13411 ; CHECK-NEXT: vmv1r.v v10, v8
13412 ; CHECK-NEXT: vmv1r.v v11, v8
13413 ; CHECK-NEXT: vmv1r.v v12, v8
13414 ; CHECK-NEXT: vmv1r.v v13, v8
13415 ; CHECK-NEXT: vmv1r.v v14, v8
13416 ; CHECK-NEXT: vmv1r.v v15, v8
13417 ; CHECK-NEXT: vmv1r.v v16, v8
13418 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13419 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
13420 ; CHECK-NEXT: ret
13421 entry:
13422 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
13423 ret void
13424 }
13426 declare void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
13427 declare void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
13429 define void @test_vsoxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
13430 ; CHECK-LABEL: test_vsoxseg7_nxv2f32_nxv2i16:
13431 ; CHECK: # %bb.0: # %entry
13432 ; CHECK-NEXT: vmv1r.v v10, v8
13433 ; CHECK-NEXT: vmv1r.v v11, v8
13434 ; CHECK-NEXT: vmv1r.v v12, v8
13435 ; CHECK-NEXT: vmv1r.v v13, v8
13436 ; CHECK-NEXT: vmv1r.v v14, v8
13437 ; CHECK-NEXT: vmv1r.v v15, v8
13438 ; CHECK-NEXT: vmv1r.v v16, v8
13439 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13440 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
13441 ; CHECK-NEXT: ret
13442 entry:
13443 tail call void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
13444 ret void
13445 }
13447 define void @test_vsoxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13448 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_nxv2i16:
13449 ; CHECK: # %bb.0: # %entry
13450 ; CHECK-NEXT: vmv1r.v v10, v8
13451 ; CHECK-NEXT: vmv1r.v v11, v8
13452 ; CHECK-NEXT: vmv1r.v v12, v8
13453 ; CHECK-NEXT: vmv1r.v v13, v8
13454 ; CHECK-NEXT: vmv1r.v v14, v8
13455 ; CHECK-NEXT: vmv1r.v v15, v8
13456 ; CHECK-NEXT: vmv1r.v v16, v8
13457 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13458 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
13459 ; CHECK-NEXT: ret
13460 entry:
13461 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
13462 ret void
13463 }
13465 declare void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
13466 declare void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
13468 define void @test_vsoxseg7_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
13469 ; CHECK-LABEL: test_vsoxseg7_nxv2f32_nxv2i64:
13470 ; CHECK: # %bb.0: # %entry
13471 ; CHECK-NEXT: vmv1r.v v12, v8
13472 ; CHECK-NEXT: vmv1r.v v13, v8
13473 ; CHECK-NEXT: vmv1r.v v14, v8
13474 ; CHECK-NEXT: vmv1r.v v15, v8
13475 ; CHECK-NEXT: vmv1r.v v16, v8
13476 ; CHECK-NEXT: vmv1r.v v17, v8
13477 ; CHECK-NEXT: vmv1r.v v18, v8
13478 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13479 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10
13480 ; CHECK-NEXT: ret
13481 entry:
13482 tail call void @llvm.riscv.vsoxseg7.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
13483 ret void
13484 }
13486 define void @test_vsoxseg7_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13487 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_nxv2i64:
13488 ; CHECK: # %bb.0: # %entry
13489 ; CHECK-NEXT: vmv1r.v v12, v8
13490 ; CHECK-NEXT: vmv1r.v v13, v8
13491 ; CHECK-NEXT: vmv1r.v v14, v8
13492 ; CHECK-NEXT: vmv1r.v v15, v8
13493 ; CHECK-NEXT: vmv1r.v v16, v8
13494 ; CHECK-NEXT: vmv1r.v v17, v8
13495 ; CHECK-NEXT: vmv1r.v v18, v8
13496 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13497 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10, v0.t
13498 ; CHECK-NEXT: ret
13499 entry:
13500 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
13501 ret void
13502 }
13504 declare void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, i64)
13505 declare void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
13507 define void @test_vsoxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
13508 ; CHECK-LABEL: test_vsoxseg8_nxv2f32_nxv2i32:
13509 ; CHECK: # %bb.0: # %entry
13510 ; CHECK-NEXT: vmv1r.v v10, v8
13511 ; CHECK-NEXT: vmv1r.v v11, v8
13512 ; CHECK-NEXT: vmv1r.v v12, v8
13513 ; CHECK-NEXT: vmv1r.v v13, v8
13514 ; CHECK-NEXT: vmv1r.v v14, v8
13515 ; CHECK-NEXT: vmv1r.v v15, v8
13516 ; CHECK-NEXT: vmv1r.v v16, v8
13517 ; CHECK-NEXT: vmv1r.v v17, v8
13518 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13519 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
13520 ; CHECK-NEXT: ret
13521 entry:
13522 tail call void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
13523 ret void
13524 }
13526 define void @test_vsoxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13527 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_nxv2i32:
13528 ; CHECK: # %bb.0: # %entry
13529 ; CHECK-NEXT: vmv1r.v v10, v8
13530 ; CHECK-NEXT: vmv1r.v v11, v8
13531 ; CHECK-NEXT: vmv1r.v v12, v8
13532 ; CHECK-NEXT: vmv1r.v v13, v8
13533 ; CHECK-NEXT: vmv1r.v v14, v8
13534 ; CHECK-NEXT: vmv1r.v v15, v8
13535 ; CHECK-NEXT: vmv1r.v v16, v8
13536 ; CHECK-NEXT: vmv1r.v v17, v8
13537 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13538 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
13539 ; CHECK-NEXT: ret
13540 entry:
13541 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
13542 ret void
13543 }
13545 declare void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, i64)
13546 declare void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
13548 define void @test_vsoxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
13549 ; CHECK-LABEL: test_vsoxseg8_nxv2f32_nxv2i8:
13550 ; CHECK: # %bb.0: # %entry
13551 ; CHECK-NEXT: vmv1r.v v10, v8
13552 ; CHECK-NEXT: vmv1r.v v11, v8
13553 ; CHECK-NEXT: vmv1r.v v12, v8
13554 ; CHECK-NEXT: vmv1r.v v13, v8
13555 ; CHECK-NEXT: vmv1r.v v14, v8
13556 ; CHECK-NEXT: vmv1r.v v15, v8
13557 ; CHECK-NEXT: vmv1r.v v16, v8
13558 ; CHECK-NEXT: vmv1r.v v17, v8
13559 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13560 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
13561 ; CHECK-NEXT: ret
13562 entry:
13563 tail call void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
13564 ret void
13565 }
13567 define void @test_vsoxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13568 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_nxv2i8:
13569 ; CHECK: # %bb.0: # %entry
13570 ; CHECK-NEXT: vmv1r.v v10, v8
13571 ; CHECK-NEXT: vmv1r.v v11, v8
13572 ; CHECK-NEXT: vmv1r.v v12, v8
13573 ; CHECK-NEXT: vmv1r.v v13, v8
13574 ; CHECK-NEXT: vmv1r.v v14, v8
13575 ; CHECK-NEXT: vmv1r.v v15, v8
13576 ; CHECK-NEXT: vmv1r.v v16, v8
13577 ; CHECK-NEXT: vmv1r.v v17, v8
13578 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13579 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
13580 ; CHECK-NEXT: ret
13581 entry:
13582 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
13583 ret void
13584 }
13586 declare void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, i64)
13587 declare void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
13589 define void @test_vsoxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
13590 ; CHECK-LABEL: test_vsoxseg8_nxv2f32_nxv2i16:
13591 ; CHECK: # %bb.0: # %entry
13592 ; CHECK-NEXT: vmv1r.v v10, v8
13593 ; CHECK-NEXT: vmv1r.v v11, v8
13594 ; CHECK-NEXT: vmv1r.v v12, v8
13595 ; CHECK-NEXT: vmv1r.v v13, v8
13596 ; CHECK-NEXT: vmv1r.v v14, v8
13597 ; CHECK-NEXT: vmv1r.v v15, v8
13598 ; CHECK-NEXT: vmv1r.v v16, v8
13599 ; CHECK-NEXT: vmv1r.v v17, v8
13600 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13601 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
13602 ; CHECK-NEXT: ret
13603 entry:
13604 tail call void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
13605 ret void
13606 }
13608 define void @test_vsoxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13609 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_nxv2i16:
13610 ; CHECK: # %bb.0: # %entry
13611 ; CHECK-NEXT: vmv1r.v v10, v8
13612 ; CHECK-NEXT: vmv1r.v v11, v8
13613 ; CHECK-NEXT: vmv1r.v v12, v8
13614 ; CHECK-NEXT: vmv1r.v v13, v8
13615 ; CHECK-NEXT: vmv1r.v v14, v8
13616 ; CHECK-NEXT: vmv1r.v v15, v8
13617 ; CHECK-NEXT: vmv1r.v v16, v8
13618 ; CHECK-NEXT: vmv1r.v v17, v8
13619 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13620 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
13621 ; CHECK-NEXT: ret
13622 entry:
13623 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
13624 ret void
13625 }
13627 declare void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, i64)
13628 declare void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
13630 define void @test_vsoxseg8_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
13631 ; CHECK-LABEL: test_vsoxseg8_nxv2f32_nxv2i64:
13632 ; CHECK: # %bb.0: # %entry
13633 ; CHECK-NEXT: vmv1r.v v12, v8
13634 ; CHECK-NEXT: vmv1r.v v13, v8
13635 ; CHECK-NEXT: vmv1r.v v14, v8
13636 ; CHECK-NEXT: vmv1r.v v15, v8
13637 ; CHECK-NEXT: vmv1r.v v16, v8
13638 ; CHECK-NEXT: vmv1r.v v17, v8
13639 ; CHECK-NEXT: vmv1r.v v18, v8
13640 ; CHECK-NEXT: vmv1r.v v19, v8
13641 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13642 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10
13643 ; CHECK-NEXT: ret
13644 entry:
13645 tail call void @llvm.riscv.vsoxseg8.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
13646 ret void
13647 }
13649 define void @test_vsoxseg8_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
13650 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_nxv2i64:
13651 ; CHECK: # %bb.0: # %entry
13652 ; CHECK-NEXT: vmv1r.v v12, v8
13653 ; CHECK-NEXT: vmv1r.v v13, v8
13654 ; CHECK-NEXT: vmv1r.v v14, v8
13655 ; CHECK-NEXT: vmv1r.v v15, v8
13656 ; CHECK-NEXT: vmv1r.v v16, v8
13657 ; CHECK-NEXT: vmv1r.v v17, v8
13658 ; CHECK-NEXT: vmv1r.v v18, v8
13659 ; CHECK-NEXT: vmv1r.v v19, v8
13660 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
13661 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10, v0.t
13662 ; CHECK-NEXT: ret
13663 entry:
13664 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
13665 ret void
13666 }
13668 declare void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
13669 declare void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
13671 define void @test_vsoxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
13672 ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i64:
13673 ; CHECK: # %bb.0: # %entry
13674 ; CHECK-NEXT: vmv1r.v v10, v9
13675 ; CHECK-NEXT: vmv1r.v v9, v8
13676 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13677 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
13678 ; CHECK-NEXT: ret
13679 entry:
13680 tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
13681 ret void
13682 }
13684 define void @test_vsoxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13685 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i64:
13686 ; CHECK: # %bb.0: # %entry
13687 ; CHECK-NEXT: vmv1r.v v10, v9
13688 ; CHECK-NEXT: vmv1r.v v9, v8
13689 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13690 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
13691 ; CHECK-NEXT: ret
13692 entry:
13693 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
13694 ret void
13695 }
13697 declare void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
13698 declare void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
13700 define void @test_vsoxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
13701 ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i32:
13702 ; CHECK: # %bb.0: # %entry
13703 ; CHECK-NEXT: vmv1r.v v10, v9
13704 ; CHECK-NEXT: vmv1r.v v9, v8
13705 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13706 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
13707 ; CHECK-NEXT: ret
13708 entry:
13709 tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
13710 ret void
13711 }
13713 define void @test_vsoxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13714 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i32:
13715 ; CHECK: # %bb.0: # %entry
13716 ; CHECK-NEXT: vmv1r.v v10, v9
13717 ; CHECK-NEXT: vmv1r.v v9, v8
13718 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13719 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
13720 ; CHECK-NEXT: ret
13721 entry:
13722 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
13723 ret void
13724 }
13726 declare void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
13727 declare void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
13729 define void @test_vsoxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
13730 ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i16:
13731 ; CHECK: # %bb.0: # %entry
13732 ; CHECK-NEXT: vmv1r.v v10, v9
13733 ; CHECK-NEXT: vmv1r.v v9, v8
13734 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13735 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
13736 ; CHECK-NEXT: ret
13737 entry:
13738 tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
13739 ret void
13740 }
13742 define void @test_vsoxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13743 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i16:
13744 ; CHECK: # %bb.0: # %entry
13745 ; CHECK-NEXT: vmv1r.v v10, v9
13746 ; CHECK-NEXT: vmv1r.v v9, v8
13747 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13748 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
13749 ; CHECK-NEXT: ret
13750 entry:
13751 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
13752 ret void
13753 }
13755 declare void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
13756 declare void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
13758 define void @test_vsoxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
13759 ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i8:
13760 ; CHECK: # %bb.0: # %entry
13761 ; CHECK-NEXT: vmv1r.v v10, v9
13762 ; CHECK-NEXT: vmv1r.v v9, v8
13763 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13764 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
13765 ; CHECK-NEXT: ret
13766 entry:
13767 tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
13768 ret void
13769 }
13771 define void @test_vsoxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13772 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i8:
13773 ; CHECK: # %bb.0: # %entry
13774 ; CHECK-NEXT: vmv1r.v v10, v9
13775 ; CHECK-NEXT: vmv1r.v v9, v8
13776 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13777 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
13778 ; CHECK-NEXT: ret
13779 entry:
13780 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
13781 ret void
13782 }
13784 declare void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
13785 declare void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
13787 define void @test_vsoxseg3_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
13788 ; CHECK-LABEL: test_vsoxseg3_nxv1f16_nxv1i64:
13789 ; CHECK: # %bb.0: # %entry
13790 ; CHECK-NEXT: vmv1r.v v10, v8
13791 ; CHECK-NEXT: vmv1r.v v11, v8
13792 ; CHECK-NEXT: vmv1r.v v12, v8
13793 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13794 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
13795 ; CHECK-NEXT: ret
13796 entry:
13797 tail call void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
13798 ret void
13799 }
13801 define void @test_vsoxseg3_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13802 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_nxv1i64:
13803 ; CHECK: # %bb.0: # %entry
13804 ; CHECK-NEXT: vmv1r.v v10, v8
13805 ; CHECK-NEXT: vmv1r.v v11, v8
13806 ; CHECK-NEXT: vmv1r.v v12, v8
13807 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13808 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
13809 ; CHECK-NEXT: ret
13810 entry:
13811 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
13812 ret void
13813 }
13815 declare void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
13816 declare void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
13818 define void @test_vsoxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
13819 ; CHECK-LABEL: test_vsoxseg3_nxv1f16_nxv1i32:
13820 ; CHECK: # %bb.0: # %entry
13821 ; CHECK-NEXT: vmv1r.v v10, v8
13822 ; CHECK-NEXT: vmv1r.v v11, v8
13823 ; CHECK-NEXT: vmv1r.v v12, v8
13824 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13825 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
13826 ; CHECK-NEXT: ret
13827 entry:
13828 tail call void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
13829 ret void
13830 }
13832 define void @test_vsoxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13833 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_nxv1i32:
13834 ; CHECK: # %bb.0: # %entry
13835 ; CHECK-NEXT: vmv1r.v v10, v8
13836 ; CHECK-NEXT: vmv1r.v v11, v8
13837 ; CHECK-NEXT: vmv1r.v v12, v8
13838 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13839 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
13840 ; CHECK-NEXT: ret
13841 entry:
13842 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
13843 ret void
13844 }
13846 declare void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
13847 declare void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
13849 define void @test_vsoxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
13850 ; CHECK-LABEL: test_vsoxseg3_nxv1f16_nxv1i16:
13851 ; CHECK: # %bb.0: # %entry
13852 ; CHECK-NEXT: vmv1r.v v10, v8
13853 ; CHECK-NEXT: vmv1r.v v11, v8
13854 ; CHECK-NEXT: vmv1r.v v12, v8
13855 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13856 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
13857 ; CHECK-NEXT: ret
13858 entry:
13859 tail call void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
13860 ret void
13861 }
13863 define void @test_vsoxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13864 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_nxv1i16:
13865 ; CHECK: # %bb.0: # %entry
13866 ; CHECK-NEXT: vmv1r.v v10, v8
13867 ; CHECK-NEXT: vmv1r.v v11, v8
13868 ; CHECK-NEXT: vmv1r.v v12, v8
13869 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13870 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
13871 ; CHECK-NEXT: ret
13872 entry:
13873 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
13874 ret void
13875 }
13877 declare void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
13878 declare void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
13880 define void @test_vsoxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
13881 ; CHECK-LABEL: test_vsoxseg3_nxv1f16_nxv1i8:
13882 ; CHECK: # %bb.0: # %entry
13883 ; CHECK-NEXT: vmv1r.v v10, v8
13884 ; CHECK-NEXT: vmv1r.v v11, v8
13885 ; CHECK-NEXT: vmv1r.v v12, v8
13886 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13887 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
13888 ; CHECK-NEXT: ret
13889 entry:
13890 tail call void @llvm.riscv.vsoxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
13891 ret void
13892 }
13894 define void @test_vsoxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13895 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_nxv1i8:
13896 ; CHECK: # %bb.0: # %entry
13897 ; CHECK-NEXT: vmv1r.v v10, v8
13898 ; CHECK-NEXT: vmv1r.v v11, v8
13899 ; CHECK-NEXT: vmv1r.v v12, v8
13900 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13901 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
13902 ; CHECK-NEXT: ret
13903 entry:
13904 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
13905 ret void
13906 }
13908 declare void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
13909 declare void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
13911 define void @test_vsoxseg4_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
13912 ; CHECK-LABEL: test_vsoxseg4_nxv1f16_nxv1i64:
13913 ; CHECK: # %bb.0: # %entry
13914 ; CHECK-NEXT: vmv1r.v v10, v8
13915 ; CHECK-NEXT: vmv1r.v v11, v8
13916 ; CHECK-NEXT: vmv1r.v v12, v8
13917 ; CHECK-NEXT: vmv1r.v v13, v8
13918 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13919 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
13920 ; CHECK-NEXT: ret
13921 entry:
13922 tail call void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
13923 ret void
13924 }
13926 define void @test_vsoxseg4_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13927 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_nxv1i64:
13928 ; CHECK: # %bb.0: # %entry
13929 ; CHECK-NEXT: vmv1r.v v10, v8
13930 ; CHECK-NEXT: vmv1r.v v11, v8
13931 ; CHECK-NEXT: vmv1r.v v12, v8
13932 ; CHECK-NEXT: vmv1r.v v13, v8
13933 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13934 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
13935 ; CHECK-NEXT: ret
13936 entry:
13937 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
13938 ret void
13939 }
13941 declare void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
13942 declare void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
13944 define void @test_vsoxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
13945 ; CHECK-LABEL: test_vsoxseg4_nxv1f16_nxv1i32:
13946 ; CHECK: # %bb.0: # %entry
13947 ; CHECK-NEXT: vmv1r.v v10, v8
13948 ; CHECK-NEXT: vmv1r.v v11, v8
13949 ; CHECK-NEXT: vmv1r.v v12, v8
13950 ; CHECK-NEXT: vmv1r.v v13, v8
13951 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13952 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
13953 ; CHECK-NEXT: ret
13954 entry:
13955 tail call void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
13956 ret void
13957 }
13959 define void @test_vsoxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13960 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_nxv1i32:
13961 ; CHECK: # %bb.0: # %entry
13962 ; CHECK-NEXT: vmv1r.v v10, v8
13963 ; CHECK-NEXT: vmv1r.v v11, v8
13964 ; CHECK-NEXT: vmv1r.v v12, v8
13965 ; CHECK-NEXT: vmv1r.v v13, v8
13966 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13967 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
13968 ; CHECK-NEXT: ret
13969 entry:
13970 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
13971 ret void
13972 }
13974 declare void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
13975 declare void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
13977 define void @test_vsoxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
13978 ; CHECK-LABEL: test_vsoxseg4_nxv1f16_nxv1i16:
13979 ; CHECK: # %bb.0: # %entry
13980 ; CHECK-NEXT: vmv1r.v v10, v8
13981 ; CHECK-NEXT: vmv1r.v v11, v8
13982 ; CHECK-NEXT: vmv1r.v v12, v8
13983 ; CHECK-NEXT: vmv1r.v v13, v8
13984 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
13985 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
13986 ; CHECK-NEXT: ret
13987 entry:
13988 tail call void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
13989 ret void
13990 }
13992 define void @test_vsoxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
13993 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_nxv1i16:
13994 ; CHECK: # %bb.0: # %entry
13995 ; CHECK-NEXT: vmv1r.v v10, v8
13996 ; CHECK-NEXT: vmv1r.v v11, v8
13997 ; CHECK-NEXT: vmv1r.v v12, v8
13998 ; CHECK-NEXT: vmv1r.v v13, v8
13999 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14000 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
14001 ; CHECK-NEXT: ret
14002 entry:
14003 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14004 ret void
14005 }
14007 declare void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
14008 declare void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14010 define void @test_vsoxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14011 ; CHECK-LABEL: test_vsoxseg4_nxv1f16_nxv1i8:
14012 ; CHECK: # %bb.0: # %entry
14013 ; CHECK-NEXT: vmv1r.v v10, v8
14014 ; CHECK-NEXT: vmv1r.v v11, v8
14015 ; CHECK-NEXT: vmv1r.v v12, v8
14016 ; CHECK-NEXT: vmv1r.v v13, v8
14017 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14018 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
14019 ; CHECK-NEXT: ret
14020 entry:
14021 tail call void @llvm.riscv.vsoxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14022 ret void
14023 }
14025 define void @test_vsoxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14026 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_nxv1i8:
14027 ; CHECK: # %bb.0: # %entry
14028 ; CHECK-NEXT: vmv1r.v v10, v8
14029 ; CHECK-NEXT: vmv1r.v v11, v8
14030 ; CHECK-NEXT: vmv1r.v v12, v8
14031 ; CHECK-NEXT: vmv1r.v v13, v8
14032 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14033 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
14034 ; CHECK-NEXT: ret
14035 entry:
14036 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14037 ret void
14038 }
14040 declare void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
14041 declare void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14043 define void @test_vsoxseg5_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14044 ; CHECK-LABEL: test_vsoxseg5_nxv1f16_nxv1i64:
14045 ; CHECK: # %bb.0: # %entry
14046 ; CHECK-NEXT: vmv1r.v v10, v8
14047 ; CHECK-NEXT: vmv1r.v v11, v8
14048 ; CHECK-NEXT: vmv1r.v v12, v8
14049 ; CHECK-NEXT: vmv1r.v v13, v8
14050 ; CHECK-NEXT: vmv1r.v v14, v8
14051 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14052 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
14053 ; CHECK-NEXT: ret
14054 entry:
14055 tail call void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14056 ret void
14057 }
14059 define void @test_vsoxseg5_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14060 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_nxv1i64:
14061 ; CHECK: # %bb.0: # %entry
14062 ; CHECK-NEXT: vmv1r.v v10, v8
14063 ; CHECK-NEXT: vmv1r.v v11, v8
14064 ; CHECK-NEXT: vmv1r.v v12, v8
14065 ; CHECK-NEXT: vmv1r.v v13, v8
14066 ; CHECK-NEXT: vmv1r.v v14, v8
14067 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14068 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
14069 ; CHECK-NEXT: ret
14070 entry:
14071 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14072 ret void
14073 }
14075 declare void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
14076 declare void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14078 define void @test_vsoxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14079 ; CHECK-LABEL: test_vsoxseg5_nxv1f16_nxv1i32:
14080 ; CHECK: # %bb.0: # %entry
14081 ; CHECK-NEXT: vmv1r.v v10, v8
14082 ; CHECK-NEXT: vmv1r.v v11, v8
14083 ; CHECK-NEXT: vmv1r.v v12, v8
14084 ; CHECK-NEXT: vmv1r.v v13, v8
14085 ; CHECK-NEXT: vmv1r.v v14, v8
14086 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14087 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
14088 ; CHECK-NEXT: ret
14089 entry:
14090 tail call void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14091 ret void
14092 }
14094 define void @test_vsoxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14095 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_nxv1i32:
14096 ; CHECK: # %bb.0: # %entry
14097 ; CHECK-NEXT: vmv1r.v v10, v8
14098 ; CHECK-NEXT: vmv1r.v v11, v8
14099 ; CHECK-NEXT: vmv1r.v v12, v8
14100 ; CHECK-NEXT: vmv1r.v v13, v8
14101 ; CHECK-NEXT: vmv1r.v v14, v8
14102 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14103 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
14104 ; CHECK-NEXT: ret
14105 entry:
14106 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14107 ret void
14108 }
14110 declare void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
14111 declare void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14113 define void @test_vsoxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14114 ; CHECK-LABEL: test_vsoxseg5_nxv1f16_nxv1i16:
14115 ; CHECK: # %bb.0: # %entry
14116 ; CHECK-NEXT: vmv1r.v v10, v8
14117 ; CHECK-NEXT: vmv1r.v v11, v8
14118 ; CHECK-NEXT: vmv1r.v v12, v8
14119 ; CHECK-NEXT: vmv1r.v v13, v8
14120 ; CHECK-NEXT: vmv1r.v v14, v8
14121 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14122 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
14123 ; CHECK-NEXT: ret
14124 entry:
14125 tail call void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14126 ret void
14127 }
14129 define void @test_vsoxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14130 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_nxv1i16:
14131 ; CHECK: # %bb.0: # %entry
14132 ; CHECK-NEXT: vmv1r.v v10, v8
14133 ; CHECK-NEXT: vmv1r.v v11, v8
14134 ; CHECK-NEXT: vmv1r.v v12, v8
14135 ; CHECK-NEXT: vmv1r.v v13, v8
14136 ; CHECK-NEXT: vmv1r.v v14, v8
14137 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14138 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
14139 ; CHECK-NEXT: ret
14140 entry:
14141 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14142 ret void
14143 }
14145 declare void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
14146 declare void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14148 define void @test_vsoxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14149 ; CHECK-LABEL: test_vsoxseg5_nxv1f16_nxv1i8:
14150 ; CHECK: # %bb.0: # %entry
14151 ; CHECK-NEXT: vmv1r.v v10, v8
14152 ; CHECK-NEXT: vmv1r.v v11, v8
14153 ; CHECK-NEXT: vmv1r.v v12, v8
14154 ; CHECK-NEXT: vmv1r.v v13, v8
14155 ; CHECK-NEXT: vmv1r.v v14, v8
14156 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14157 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
14158 ; CHECK-NEXT: ret
14159 entry:
14160 tail call void @llvm.riscv.vsoxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14161 ret void
14162 }
14164 define void @test_vsoxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14165 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_nxv1i8:
14166 ; CHECK: # %bb.0: # %entry
14167 ; CHECK-NEXT: vmv1r.v v10, v8
14168 ; CHECK-NEXT: vmv1r.v v11, v8
14169 ; CHECK-NEXT: vmv1r.v v12, v8
14170 ; CHECK-NEXT: vmv1r.v v13, v8
14171 ; CHECK-NEXT: vmv1r.v v14, v8
14172 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14173 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
14174 ; CHECK-NEXT: ret
14175 entry:
14176 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14177 ret void
14178 }
14180 declare void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
14181 declare void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14183 define void @test_vsoxseg6_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14184 ; CHECK-LABEL: test_vsoxseg6_nxv1f16_nxv1i64:
14185 ; CHECK: # %bb.0: # %entry
14186 ; CHECK-NEXT: vmv1r.v v10, v8
14187 ; CHECK-NEXT: vmv1r.v v11, v8
14188 ; CHECK-NEXT: vmv1r.v v12, v8
14189 ; CHECK-NEXT: vmv1r.v v13, v8
14190 ; CHECK-NEXT: vmv1r.v v14, v8
14191 ; CHECK-NEXT: vmv1r.v v15, v8
14192 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14193 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
14194 ; CHECK-NEXT: ret
14195 entry:
14196 tail call void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14197 ret void
14198 }
14200 define void @test_vsoxseg6_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14201 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_nxv1i64:
14202 ; CHECK: # %bb.0: # %entry
14203 ; CHECK-NEXT: vmv1r.v v10, v8
14204 ; CHECK-NEXT: vmv1r.v v11, v8
14205 ; CHECK-NEXT: vmv1r.v v12, v8
14206 ; CHECK-NEXT: vmv1r.v v13, v8
14207 ; CHECK-NEXT: vmv1r.v v14, v8
14208 ; CHECK-NEXT: vmv1r.v v15, v8
14209 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14210 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
14211 ; CHECK-NEXT: ret
14212 entry:
14213 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14214 ret void
14215 }
14217 declare void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
14218 declare void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14220 define void @test_vsoxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14221 ; CHECK-LABEL: test_vsoxseg6_nxv1f16_nxv1i32:
14222 ; CHECK: # %bb.0: # %entry
14223 ; CHECK-NEXT: vmv1r.v v10, v8
14224 ; CHECK-NEXT: vmv1r.v v11, v8
14225 ; CHECK-NEXT: vmv1r.v v12, v8
14226 ; CHECK-NEXT: vmv1r.v v13, v8
14227 ; CHECK-NEXT: vmv1r.v v14, v8
14228 ; CHECK-NEXT: vmv1r.v v15, v8
14229 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14230 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
14231 ; CHECK-NEXT: ret
14232 entry:
14233 tail call void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14234 ret void
14235 }
14237 define void @test_vsoxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14238 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_nxv1i32:
14239 ; CHECK: # %bb.0: # %entry
14240 ; CHECK-NEXT: vmv1r.v v10, v8
14241 ; CHECK-NEXT: vmv1r.v v11, v8
14242 ; CHECK-NEXT: vmv1r.v v12, v8
14243 ; CHECK-NEXT: vmv1r.v v13, v8
14244 ; CHECK-NEXT: vmv1r.v v14, v8
14245 ; CHECK-NEXT: vmv1r.v v15, v8
14246 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14247 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
14248 ; CHECK-NEXT: ret
14249 entry:
14250 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14251 ret void
14252 }
14254 declare void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
14255 declare void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14257 define void @test_vsoxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14258 ; CHECK-LABEL: test_vsoxseg6_nxv1f16_nxv1i16:
14259 ; CHECK: # %bb.0: # %entry
14260 ; CHECK-NEXT: vmv1r.v v10, v8
14261 ; CHECK-NEXT: vmv1r.v v11, v8
14262 ; CHECK-NEXT: vmv1r.v v12, v8
14263 ; CHECK-NEXT: vmv1r.v v13, v8
14264 ; CHECK-NEXT: vmv1r.v v14, v8
14265 ; CHECK-NEXT: vmv1r.v v15, v8
14266 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14267 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
14268 ; CHECK-NEXT: ret
14269 entry:
14270 tail call void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14271 ret void
14272 }
14274 define void @test_vsoxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14275 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_nxv1i16:
14276 ; CHECK: # %bb.0: # %entry
14277 ; CHECK-NEXT: vmv1r.v v10, v8
14278 ; CHECK-NEXT: vmv1r.v v11, v8
14279 ; CHECK-NEXT: vmv1r.v v12, v8
14280 ; CHECK-NEXT: vmv1r.v v13, v8
14281 ; CHECK-NEXT: vmv1r.v v14, v8
14282 ; CHECK-NEXT: vmv1r.v v15, v8
14283 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14284 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
14285 ; CHECK-NEXT: ret
14286 entry:
14287 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14288 ret void
14289 }
14291 declare void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
14292 declare void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14294 define void @test_vsoxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14295 ; CHECK-LABEL: test_vsoxseg6_nxv1f16_nxv1i8:
14296 ; CHECK: # %bb.0: # %entry
14297 ; CHECK-NEXT: vmv1r.v v10, v8
14298 ; CHECK-NEXT: vmv1r.v v11, v8
14299 ; CHECK-NEXT: vmv1r.v v12, v8
14300 ; CHECK-NEXT: vmv1r.v v13, v8
14301 ; CHECK-NEXT: vmv1r.v v14, v8
14302 ; CHECK-NEXT: vmv1r.v v15, v8
14303 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14304 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
14305 ; CHECK-NEXT: ret
14306 entry:
14307 tail call void @llvm.riscv.vsoxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14308 ret void
14309 }
14311 define void @test_vsoxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14312 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_nxv1i8:
14313 ; CHECK: # %bb.0: # %entry
14314 ; CHECK-NEXT: vmv1r.v v10, v8
14315 ; CHECK-NEXT: vmv1r.v v11, v8
14316 ; CHECK-NEXT: vmv1r.v v12, v8
14317 ; CHECK-NEXT: vmv1r.v v13, v8
14318 ; CHECK-NEXT: vmv1r.v v14, v8
14319 ; CHECK-NEXT: vmv1r.v v15, v8
14320 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14321 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
14322 ; CHECK-NEXT: ret
14323 entry:
14324 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14325 ret void
14326 }
14328 declare void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
14329 declare void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14331 define void @test_vsoxseg7_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14332 ; CHECK-LABEL: test_vsoxseg7_nxv1f16_nxv1i64:
14333 ; CHECK: # %bb.0: # %entry
14334 ; CHECK-NEXT: vmv1r.v v10, v8
14335 ; CHECK-NEXT: vmv1r.v v11, v8
14336 ; CHECK-NEXT: vmv1r.v v12, v8
14337 ; CHECK-NEXT: vmv1r.v v13, v8
14338 ; CHECK-NEXT: vmv1r.v v14, v8
14339 ; CHECK-NEXT: vmv1r.v v15, v8
14340 ; CHECK-NEXT: vmv1r.v v16, v8
14341 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14342 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
14343 ; CHECK-NEXT: ret
14344 entry:
14345 tail call void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14346 ret void
14347 }
14349 define void @test_vsoxseg7_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14350 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_nxv1i64:
14351 ; CHECK: # %bb.0: # %entry
14352 ; CHECK-NEXT: vmv1r.v v10, v8
14353 ; CHECK-NEXT: vmv1r.v v11, v8
14354 ; CHECK-NEXT: vmv1r.v v12, v8
14355 ; CHECK-NEXT: vmv1r.v v13, v8
14356 ; CHECK-NEXT: vmv1r.v v14, v8
14357 ; CHECK-NEXT: vmv1r.v v15, v8
14358 ; CHECK-NEXT: vmv1r.v v16, v8
14359 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14360 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
14361 ; CHECK-NEXT: ret
14362 entry:
14363 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14364 ret void
14365 }
14367 declare void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
14368 declare void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14370 define void @test_vsoxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14371 ; CHECK-LABEL: test_vsoxseg7_nxv1f16_nxv1i32:
14372 ; CHECK: # %bb.0: # %entry
14373 ; CHECK-NEXT: vmv1r.v v10, v8
14374 ; CHECK-NEXT: vmv1r.v v11, v8
14375 ; CHECK-NEXT: vmv1r.v v12, v8
14376 ; CHECK-NEXT: vmv1r.v v13, v8
14377 ; CHECK-NEXT: vmv1r.v v14, v8
14378 ; CHECK-NEXT: vmv1r.v v15, v8
14379 ; CHECK-NEXT: vmv1r.v v16, v8
14380 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14381 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
14382 ; CHECK-NEXT: ret
14383 entry:
14384 tail call void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14385 ret void
14386 }
14388 define void @test_vsoxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14389 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_nxv1i32:
14390 ; CHECK: # %bb.0: # %entry
14391 ; CHECK-NEXT: vmv1r.v v10, v8
14392 ; CHECK-NEXT: vmv1r.v v11, v8
14393 ; CHECK-NEXT: vmv1r.v v12, v8
14394 ; CHECK-NEXT: vmv1r.v v13, v8
14395 ; CHECK-NEXT: vmv1r.v v14, v8
14396 ; CHECK-NEXT: vmv1r.v v15, v8
14397 ; CHECK-NEXT: vmv1r.v v16, v8
14398 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14399 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
14400 ; CHECK-NEXT: ret
14401 entry:
14402 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14403 ret void
14404 }
14406 declare void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
14407 declare void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14409 define void @test_vsoxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14410 ; CHECK-LABEL: test_vsoxseg7_nxv1f16_nxv1i16:
14411 ; CHECK: # %bb.0: # %entry
14412 ; CHECK-NEXT: vmv1r.v v10, v8
14413 ; CHECK-NEXT: vmv1r.v v11, v8
14414 ; CHECK-NEXT: vmv1r.v v12, v8
14415 ; CHECK-NEXT: vmv1r.v v13, v8
14416 ; CHECK-NEXT: vmv1r.v v14, v8
14417 ; CHECK-NEXT: vmv1r.v v15, v8
14418 ; CHECK-NEXT: vmv1r.v v16, v8
14419 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14420 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
14421 ; CHECK-NEXT: ret
14422 entry:
14423 tail call void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14424 ret void
14425 }
14427 define void @test_vsoxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14428 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_nxv1i16:
14429 ; CHECK: # %bb.0: # %entry
14430 ; CHECK-NEXT: vmv1r.v v10, v8
14431 ; CHECK-NEXT: vmv1r.v v11, v8
14432 ; CHECK-NEXT: vmv1r.v v12, v8
14433 ; CHECK-NEXT: vmv1r.v v13, v8
14434 ; CHECK-NEXT: vmv1r.v v14, v8
14435 ; CHECK-NEXT: vmv1r.v v15, v8
14436 ; CHECK-NEXT: vmv1r.v v16, v8
14437 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14438 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
14439 ; CHECK-NEXT: ret
14440 entry:
14441 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14442 ret void
14443 }
14445 declare void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
14446 declare void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14448 define void @test_vsoxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14449 ; CHECK-LABEL: test_vsoxseg7_nxv1f16_nxv1i8:
14450 ; CHECK: # %bb.0: # %entry
14451 ; CHECK-NEXT: vmv1r.v v10, v8
14452 ; CHECK-NEXT: vmv1r.v v11, v8
14453 ; CHECK-NEXT: vmv1r.v v12, v8
14454 ; CHECK-NEXT: vmv1r.v v13, v8
14455 ; CHECK-NEXT: vmv1r.v v14, v8
14456 ; CHECK-NEXT: vmv1r.v v15, v8
14457 ; CHECK-NEXT: vmv1r.v v16, v8
14458 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14459 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
14460 ; CHECK-NEXT: ret
14461 entry:
14462 tail call void @llvm.riscv.vsoxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14463 ret void
14464 }
14466 define void @test_vsoxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14467 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_nxv1i8:
14468 ; CHECK: # %bb.0: # %entry
14469 ; CHECK-NEXT: vmv1r.v v10, v8
14470 ; CHECK-NEXT: vmv1r.v v11, v8
14471 ; CHECK-NEXT: vmv1r.v v12, v8
14472 ; CHECK-NEXT: vmv1r.v v13, v8
14473 ; CHECK-NEXT: vmv1r.v v14, v8
14474 ; CHECK-NEXT: vmv1r.v v15, v8
14475 ; CHECK-NEXT: vmv1r.v v16, v8
14476 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14477 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
14478 ; CHECK-NEXT: ret
14479 entry:
14480 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14481 ret void
14482 }
14484 declare void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, i64)
14485 declare void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14487 define void @test_vsoxseg8_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14488 ; CHECK-LABEL: test_vsoxseg8_nxv1f16_nxv1i64:
14489 ; CHECK: # %bb.0: # %entry
14490 ; CHECK-NEXT: vmv1r.v v10, v8
14491 ; CHECK-NEXT: vmv1r.v v11, v8
14492 ; CHECK-NEXT: vmv1r.v v12, v8
14493 ; CHECK-NEXT: vmv1r.v v13, v8
14494 ; CHECK-NEXT: vmv1r.v v14, v8
14495 ; CHECK-NEXT: vmv1r.v v15, v8
14496 ; CHECK-NEXT: vmv1r.v v16, v8
14497 ; CHECK-NEXT: vmv1r.v v17, v8
14498 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14499 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
14500 ; CHECK-NEXT: ret
14501 entry:
14502 tail call void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14503 ret void
14504 }
14506 define void @test_vsoxseg8_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14507 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_nxv1i64:
14508 ; CHECK: # %bb.0: # %entry
14509 ; CHECK-NEXT: vmv1r.v v10, v8
14510 ; CHECK-NEXT: vmv1r.v v11, v8
14511 ; CHECK-NEXT: vmv1r.v v12, v8
14512 ; CHECK-NEXT: vmv1r.v v13, v8
14513 ; CHECK-NEXT: vmv1r.v v14, v8
14514 ; CHECK-NEXT: vmv1r.v v15, v8
14515 ; CHECK-NEXT: vmv1r.v v16, v8
14516 ; CHECK-NEXT: vmv1r.v v17, v8
14517 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14518 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
14519 ; CHECK-NEXT: ret
14520 entry:
14521 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14522 ret void
14523 }
14525 declare void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, i64)
14526 declare void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14528 define void @test_vsoxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14529 ; CHECK-LABEL: test_vsoxseg8_nxv1f16_nxv1i32:
14530 ; CHECK: # %bb.0: # %entry
14531 ; CHECK-NEXT: vmv1r.v v10, v8
14532 ; CHECK-NEXT: vmv1r.v v11, v8
14533 ; CHECK-NEXT: vmv1r.v v12, v8
14534 ; CHECK-NEXT: vmv1r.v v13, v8
14535 ; CHECK-NEXT: vmv1r.v v14, v8
14536 ; CHECK-NEXT: vmv1r.v v15, v8
14537 ; CHECK-NEXT: vmv1r.v v16, v8
14538 ; CHECK-NEXT: vmv1r.v v17, v8
14539 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14540 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
14541 ; CHECK-NEXT: ret
14542 entry:
14543 tail call void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14544 ret void
14545 }
14547 define void @test_vsoxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14548 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_nxv1i32:
14549 ; CHECK: # %bb.0: # %entry
14550 ; CHECK-NEXT: vmv1r.v v10, v8
14551 ; CHECK-NEXT: vmv1r.v v11, v8
14552 ; CHECK-NEXT: vmv1r.v v12, v8
14553 ; CHECK-NEXT: vmv1r.v v13, v8
14554 ; CHECK-NEXT: vmv1r.v v14, v8
14555 ; CHECK-NEXT: vmv1r.v v15, v8
14556 ; CHECK-NEXT: vmv1r.v v16, v8
14557 ; CHECK-NEXT: vmv1r.v v17, v8
14558 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14559 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
14560 ; CHECK-NEXT: ret
14561 entry:
14562 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14563 ret void
14564 }
14566 declare void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, i64)
14567 declare void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14569 define void @test_vsoxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14570 ; CHECK-LABEL: test_vsoxseg8_nxv1f16_nxv1i16:
14571 ; CHECK: # %bb.0: # %entry
14572 ; CHECK-NEXT: vmv1r.v v10, v8
14573 ; CHECK-NEXT: vmv1r.v v11, v8
14574 ; CHECK-NEXT: vmv1r.v v12, v8
14575 ; CHECK-NEXT: vmv1r.v v13, v8
14576 ; CHECK-NEXT: vmv1r.v v14, v8
14577 ; CHECK-NEXT: vmv1r.v v15, v8
14578 ; CHECK-NEXT: vmv1r.v v16, v8
14579 ; CHECK-NEXT: vmv1r.v v17, v8
14580 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14581 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
14582 ; CHECK-NEXT: ret
14583 entry:
14584 tail call void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14585 ret void
14586 }
14588 define void @test_vsoxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14589 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_nxv1i16:
14590 ; CHECK: # %bb.0: # %entry
14591 ; CHECK-NEXT: vmv1r.v v10, v8
14592 ; CHECK-NEXT: vmv1r.v v11, v8
14593 ; CHECK-NEXT: vmv1r.v v12, v8
14594 ; CHECK-NEXT: vmv1r.v v13, v8
14595 ; CHECK-NEXT: vmv1r.v v14, v8
14596 ; CHECK-NEXT: vmv1r.v v15, v8
14597 ; CHECK-NEXT: vmv1r.v v16, v8
14598 ; CHECK-NEXT: vmv1r.v v17, v8
14599 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14600 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
14601 ; CHECK-NEXT: ret
14602 entry:
14603 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14604 ret void
14605 }
14607 declare void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, i64)
14608 declare void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14610 define void @test_vsoxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14611 ; CHECK-LABEL: test_vsoxseg8_nxv1f16_nxv1i8:
14612 ; CHECK: # %bb.0: # %entry
14613 ; CHECK-NEXT: vmv1r.v v10, v8
14614 ; CHECK-NEXT: vmv1r.v v11, v8
14615 ; CHECK-NEXT: vmv1r.v v12, v8
14616 ; CHECK-NEXT: vmv1r.v v13, v8
14617 ; CHECK-NEXT: vmv1r.v v14, v8
14618 ; CHECK-NEXT: vmv1r.v v15, v8
14619 ; CHECK-NEXT: vmv1r.v v16, v8
14620 ; CHECK-NEXT: vmv1r.v v17, v8
14621 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14622 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
14623 ; CHECK-NEXT: ret
14624 entry:
14625 tail call void @llvm.riscv.vsoxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14626 ret void
14627 }
14629 define void @test_vsoxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14630 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_nxv1i8:
14631 ; CHECK: # %bb.0: # %entry
14632 ; CHECK-NEXT: vmv1r.v v10, v8
14633 ; CHECK-NEXT: vmv1r.v v11, v8
14634 ; CHECK-NEXT: vmv1r.v v12, v8
14635 ; CHECK-NEXT: vmv1r.v v13, v8
14636 ; CHECK-NEXT: vmv1r.v v14, v8
14637 ; CHECK-NEXT: vmv1r.v v15, v8
14638 ; CHECK-NEXT: vmv1r.v v16, v8
14639 ; CHECK-NEXT: vmv1r.v v17, v8
14640 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
14641 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
14642 ; CHECK-NEXT: ret
14643 entry:
14644 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14645 ret void
14646 }
14648 declare void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
14649 declare void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14651 define void @test_vsoxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14652 ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i64:
14653 ; CHECK: # %bb.0: # %entry
14654 ; CHECK-NEXT: vmv1r.v v10, v9
14655 ; CHECK-NEXT: vmv1r.v v9, v8
14656 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14657 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
14658 ; CHECK-NEXT: ret
14659 entry:
14660 tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14661 ret void
14662 }
14664 define void @test_vsoxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14665 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i64:
14666 ; CHECK: # %bb.0: # %entry
14667 ; CHECK-NEXT: vmv1r.v v10, v9
14668 ; CHECK-NEXT: vmv1r.v v9, v8
14669 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14670 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
14671 ; CHECK-NEXT: ret
14672 entry:
14673 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14674 ret void
14675 }
14677 declare void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
14678 declare void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14680 define void @test_vsoxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14681 ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i32:
14682 ; CHECK: # %bb.0: # %entry
14683 ; CHECK-NEXT: vmv1r.v v10, v9
14684 ; CHECK-NEXT: vmv1r.v v9, v8
14685 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14686 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
14687 ; CHECK-NEXT: ret
14688 entry:
14689 tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14690 ret void
14691 }
14693 define void @test_vsoxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14694 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i32:
14695 ; CHECK: # %bb.0: # %entry
14696 ; CHECK-NEXT: vmv1r.v v10, v9
14697 ; CHECK-NEXT: vmv1r.v v9, v8
14698 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14699 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
14700 ; CHECK-NEXT: ret
14701 entry:
14702 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14703 ret void
14704 }
14706 declare void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
14707 declare void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14709 define void @test_vsoxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14710 ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i16:
14711 ; CHECK: # %bb.0: # %entry
14712 ; CHECK-NEXT: vmv1r.v v10, v9
14713 ; CHECK-NEXT: vmv1r.v v9, v8
14714 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14715 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
14716 ; CHECK-NEXT: ret
14717 entry:
14718 tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14719 ret void
14720 }
14722 define void @test_vsoxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14723 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i16:
14724 ; CHECK: # %bb.0: # %entry
14725 ; CHECK-NEXT: vmv1r.v v10, v9
14726 ; CHECK-NEXT: vmv1r.v v9, v8
14727 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14728 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
14729 ; CHECK-NEXT: ret
14730 entry:
14731 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14732 ret void
14733 }
14735 declare void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
14736 declare void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14738 define void @test_vsoxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14739 ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i8:
14740 ; CHECK: # %bb.0: # %entry
14741 ; CHECK-NEXT: vmv1r.v v10, v9
14742 ; CHECK-NEXT: vmv1r.v v9, v8
14743 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14744 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
14745 ; CHECK-NEXT: ret
14746 entry:
14747 tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14748 ret void
14749 }
14751 define void @test_vsoxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14752 ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i8:
14753 ; CHECK: # %bb.0: # %entry
14754 ; CHECK-NEXT: vmv1r.v v10, v9
14755 ; CHECK-NEXT: vmv1r.v v9, v8
14756 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14757 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
14758 ; CHECK-NEXT: ret
14759 entry:
14760 tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14761 ret void
14762 }
14764 declare void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
14765 declare void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14767 define void @test_vsoxseg3_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14768 ; CHECK-LABEL: test_vsoxseg3_nxv1f32_nxv1i64:
14769 ; CHECK: # %bb.0: # %entry
14770 ; CHECK-NEXT: vmv1r.v v10, v8
14771 ; CHECK-NEXT: vmv1r.v v11, v8
14772 ; CHECK-NEXT: vmv1r.v v12, v8
14773 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14774 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9
14775 ; CHECK-NEXT: ret
14776 entry:
14777 tail call void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14778 ret void
14779 }
14781 define void @test_vsoxseg3_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14782 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_nxv1i64:
14783 ; CHECK: # %bb.0: # %entry
14784 ; CHECK-NEXT: vmv1r.v v10, v8
14785 ; CHECK-NEXT: vmv1r.v v11, v8
14786 ; CHECK-NEXT: vmv1r.v v12, v8
14787 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14788 ; CHECK-NEXT: vsoxseg3ei64.v v10, (a0), v9, v0.t
14789 ; CHECK-NEXT: ret
14790 entry:
14791 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14792 ret void
14793 }
14795 declare void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
14796 declare void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14798 define void @test_vsoxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14799 ; CHECK-LABEL: test_vsoxseg3_nxv1f32_nxv1i32:
14800 ; CHECK: # %bb.0: # %entry
14801 ; CHECK-NEXT: vmv1r.v v10, v8
14802 ; CHECK-NEXT: vmv1r.v v11, v8
14803 ; CHECK-NEXT: vmv1r.v v12, v8
14804 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14805 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
14806 ; CHECK-NEXT: ret
14807 entry:
14808 tail call void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14809 ret void
14810 }
14812 define void @test_vsoxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14813 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_nxv1i32:
14814 ; CHECK: # %bb.0: # %entry
14815 ; CHECK-NEXT: vmv1r.v v10, v8
14816 ; CHECK-NEXT: vmv1r.v v11, v8
14817 ; CHECK-NEXT: vmv1r.v v12, v8
14818 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14819 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
14820 ; CHECK-NEXT: ret
14821 entry:
14822 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14823 ret void
14824 }
14826 declare void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
14827 declare void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14829 define void @test_vsoxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14830 ; CHECK-LABEL: test_vsoxseg3_nxv1f32_nxv1i16:
14831 ; CHECK: # %bb.0: # %entry
14832 ; CHECK-NEXT: vmv1r.v v10, v8
14833 ; CHECK-NEXT: vmv1r.v v11, v8
14834 ; CHECK-NEXT: vmv1r.v v12, v8
14835 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14836 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
14837 ; CHECK-NEXT: ret
14838 entry:
14839 tail call void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14840 ret void
14841 }
14843 define void @test_vsoxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14844 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_nxv1i16:
14845 ; CHECK: # %bb.0: # %entry
14846 ; CHECK-NEXT: vmv1r.v v10, v8
14847 ; CHECK-NEXT: vmv1r.v v11, v8
14848 ; CHECK-NEXT: vmv1r.v v12, v8
14849 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14850 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
14851 ; CHECK-NEXT: ret
14852 entry:
14853 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14854 ret void
14855 }
14857 declare void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
14858 declare void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14860 define void @test_vsoxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14861 ; CHECK-LABEL: test_vsoxseg3_nxv1f32_nxv1i8:
14862 ; CHECK: # %bb.0: # %entry
14863 ; CHECK-NEXT: vmv1r.v v10, v8
14864 ; CHECK-NEXT: vmv1r.v v11, v8
14865 ; CHECK-NEXT: vmv1r.v v12, v8
14866 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14867 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
14868 ; CHECK-NEXT: ret
14869 entry:
14870 tail call void @llvm.riscv.vsoxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
14871 ret void
14872 }
14874 define void @test_vsoxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14875 ; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_nxv1i8:
14876 ; CHECK: # %bb.0: # %entry
14877 ; CHECK-NEXT: vmv1r.v v10, v8
14878 ; CHECK-NEXT: vmv1r.v v11, v8
14879 ; CHECK-NEXT: vmv1r.v v12, v8
14880 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14881 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
14882 ; CHECK-NEXT: ret
14883 entry:
14884 tail call void @llvm.riscv.vsoxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
14885 ret void
14886 }
14888 declare void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
14889 declare void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
14891 define void @test_vsoxseg4_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
14892 ; CHECK-LABEL: test_vsoxseg4_nxv1f32_nxv1i64:
14893 ; CHECK: # %bb.0: # %entry
14894 ; CHECK-NEXT: vmv1r.v v10, v8
14895 ; CHECK-NEXT: vmv1r.v v11, v8
14896 ; CHECK-NEXT: vmv1r.v v12, v8
14897 ; CHECK-NEXT: vmv1r.v v13, v8
14898 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14899 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9
14900 ; CHECK-NEXT: ret
14901 entry:
14902 tail call void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
14903 ret void
14904 }
14906 define void @test_vsoxseg4_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14907 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_nxv1i64:
14908 ; CHECK: # %bb.0: # %entry
14909 ; CHECK-NEXT: vmv1r.v v10, v8
14910 ; CHECK-NEXT: vmv1r.v v11, v8
14911 ; CHECK-NEXT: vmv1r.v v12, v8
14912 ; CHECK-NEXT: vmv1r.v v13, v8
14913 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14914 ; CHECK-NEXT: vsoxseg4ei64.v v10, (a0), v9, v0.t
14915 ; CHECK-NEXT: ret
14916 entry:
14917 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
14918 ret void
14919 }
14921 declare void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
14922 declare void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
14924 define void @test_vsoxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
14925 ; CHECK-LABEL: test_vsoxseg4_nxv1f32_nxv1i32:
14926 ; CHECK: # %bb.0: # %entry
14927 ; CHECK-NEXT: vmv1r.v v10, v8
14928 ; CHECK-NEXT: vmv1r.v v11, v8
14929 ; CHECK-NEXT: vmv1r.v v12, v8
14930 ; CHECK-NEXT: vmv1r.v v13, v8
14931 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14932 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
14933 ; CHECK-NEXT: ret
14934 entry:
14935 tail call void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
14936 ret void
14937 }
14939 define void @test_vsoxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14940 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_nxv1i32:
14941 ; CHECK: # %bb.0: # %entry
14942 ; CHECK-NEXT: vmv1r.v v10, v8
14943 ; CHECK-NEXT: vmv1r.v v11, v8
14944 ; CHECK-NEXT: vmv1r.v v12, v8
14945 ; CHECK-NEXT: vmv1r.v v13, v8
14946 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14947 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
14948 ; CHECK-NEXT: ret
14949 entry:
14950 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
14951 ret void
14952 }
14954 declare void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
14955 declare void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
14957 define void @test_vsoxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
14958 ; CHECK-LABEL: test_vsoxseg4_nxv1f32_nxv1i16:
14959 ; CHECK: # %bb.0: # %entry
14960 ; CHECK-NEXT: vmv1r.v v10, v8
14961 ; CHECK-NEXT: vmv1r.v v11, v8
14962 ; CHECK-NEXT: vmv1r.v v12, v8
14963 ; CHECK-NEXT: vmv1r.v v13, v8
14964 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14965 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
14966 ; CHECK-NEXT: ret
14967 entry:
14968 tail call void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
14969 ret void
14970 }
14972 define void @test_vsoxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
14973 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_nxv1i16:
14974 ; CHECK: # %bb.0: # %entry
14975 ; CHECK-NEXT: vmv1r.v v10, v8
14976 ; CHECK-NEXT: vmv1r.v v11, v8
14977 ; CHECK-NEXT: vmv1r.v v12, v8
14978 ; CHECK-NEXT: vmv1r.v v13, v8
14979 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14980 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
14981 ; CHECK-NEXT: ret
14982 entry:
14983 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
14984 ret void
14985 }
14987 declare void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
14988 declare void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
14990 define void @test_vsoxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
14991 ; CHECK-LABEL: test_vsoxseg4_nxv1f32_nxv1i8:
14992 ; CHECK: # %bb.0: # %entry
14993 ; CHECK-NEXT: vmv1r.v v10, v8
14994 ; CHECK-NEXT: vmv1r.v v11, v8
14995 ; CHECK-NEXT: vmv1r.v v12, v8
14996 ; CHECK-NEXT: vmv1r.v v13, v8
14997 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
14998 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
14999 ; CHECK-NEXT: ret
15000 entry:
15001 tail call void @llvm.riscv.vsoxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
15002 ret void
15003 }
15005 define void @test_vsoxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15006 ; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_nxv1i8:
15007 ; CHECK: # %bb.0: # %entry
15008 ; CHECK-NEXT: vmv1r.v v10, v8
15009 ; CHECK-NEXT: vmv1r.v v11, v8
15010 ; CHECK-NEXT: vmv1r.v v12, v8
15011 ; CHECK-NEXT: vmv1r.v v13, v8
15012 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15013 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
15014 ; CHECK-NEXT: ret
15015 entry:
15016 tail call void @llvm.riscv.vsoxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
15017 ret void
15018 }
15020 declare void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
15021 declare void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
15023 define void @test_vsoxseg5_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
15024 ; CHECK-LABEL: test_vsoxseg5_nxv1f32_nxv1i64:
15025 ; CHECK: # %bb.0: # %entry
15026 ; CHECK-NEXT: vmv1r.v v10, v8
15027 ; CHECK-NEXT: vmv1r.v v11, v8
15028 ; CHECK-NEXT: vmv1r.v v12, v8
15029 ; CHECK-NEXT: vmv1r.v v13, v8
15030 ; CHECK-NEXT: vmv1r.v v14, v8
15031 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15032 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9
15033 ; CHECK-NEXT: ret
15034 entry:
15035 tail call void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
15036 ret void
15037 }
15039 define void @test_vsoxseg5_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15040 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_nxv1i64:
15041 ; CHECK: # %bb.0: # %entry
15042 ; CHECK-NEXT: vmv1r.v v10, v8
15043 ; CHECK-NEXT: vmv1r.v v11, v8
15044 ; CHECK-NEXT: vmv1r.v v12, v8
15045 ; CHECK-NEXT: vmv1r.v v13, v8
15046 ; CHECK-NEXT: vmv1r.v v14, v8
15047 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15048 ; CHECK-NEXT: vsoxseg5ei64.v v10, (a0), v9, v0.t
15049 ; CHECK-NEXT: ret
15050 entry:
15051 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
15052 ret void
15053 }
15055 declare void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
15056 declare void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
15058 define void @test_vsoxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
15059 ; CHECK-LABEL: test_vsoxseg5_nxv1f32_nxv1i32:
15060 ; CHECK: # %bb.0: # %entry
15061 ; CHECK-NEXT: vmv1r.v v10, v8
15062 ; CHECK-NEXT: vmv1r.v v11, v8
15063 ; CHECK-NEXT: vmv1r.v v12, v8
15064 ; CHECK-NEXT: vmv1r.v v13, v8
15065 ; CHECK-NEXT: vmv1r.v v14, v8
15066 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15067 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
15068 ; CHECK-NEXT: ret
15069 entry:
15070 tail call void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
15071 ret void
15072 }
15074 define void @test_vsoxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15075 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_nxv1i32:
15076 ; CHECK: # %bb.0: # %entry
15077 ; CHECK-NEXT: vmv1r.v v10, v8
15078 ; CHECK-NEXT: vmv1r.v v11, v8
15079 ; CHECK-NEXT: vmv1r.v v12, v8
15080 ; CHECK-NEXT: vmv1r.v v13, v8
15081 ; CHECK-NEXT: vmv1r.v v14, v8
15082 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15083 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
15084 ; CHECK-NEXT: ret
15085 entry:
15086 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
15087 ret void
15088 }
15090 declare void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
15091 declare void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
15093 define void @test_vsoxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
15094 ; CHECK-LABEL: test_vsoxseg5_nxv1f32_nxv1i16:
15095 ; CHECK: # %bb.0: # %entry
15096 ; CHECK-NEXT: vmv1r.v v10, v8
15097 ; CHECK-NEXT: vmv1r.v v11, v8
15098 ; CHECK-NEXT: vmv1r.v v12, v8
15099 ; CHECK-NEXT: vmv1r.v v13, v8
15100 ; CHECK-NEXT: vmv1r.v v14, v8
15101 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15102 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
15103 ; CHECK-NEXT: ret
15104 entry:
15105 tail call void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
15106 ret void
15107 }
15109 define void @test_vsoxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15110 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_nxv1i16:
15111 ; CHECK: # %bb.0: # %entry
15112 ; CHECK-NEXT: vmv1r.v v10, v8
15113 ; CHECK-NEXT: vmv1r.v v11, v8
15114 ; CHECK-NEXT: vmv1r.v v12, v8
15115 ; CHECK-NEXT: vmv1r.v v13, v8
15116 ; CHECK-NEXT: vmv1r.v v14, v8
15117 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15118 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
15119 ; CHECK-NEXT: ret
15120 entry:
15121 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
15122 ret void
15123 }
15125 declare void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
15126 declare void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
15128 define void @test_vsoxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
15129 ; CHECK-LABEL: test_vsoxseg5_nxv1f32_nxv1i8:
15130 ; CHECK: # %bb.0: # %entry
15131 ; CHECK-NEXT: vmv1r.v v10, v8
15132 ; CHECK-NEXT: vmv1r.v v11, v8
15133 ; CHECK-NEXT: vmv1r.v v12, v8
15134 ; CHECK-NEXT: vmv1r.v v13, v8
15135 ; CHECK-NEXT: vmv1r.v v14, v8
15136 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15137 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
15138 ; CHECK-NEXT: ret
15139 entry:
15140 tail call void @llvm.riscv.vsoxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
15141 ret void
15142 }
15144 define void @test_vsoxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15145 ; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_nxv1i8:
15146 ; CHECK: # %bb.0: # %entry
15147 ; CHECK-NEXT: vmv1r.v v10, v8
15148 ; CHECK-NEXT: vmv1r.v v11, v8
15149 ; CHECK-NEXT: vmv1r.v v12, v8
15150 ; CHECK-NEXT: vmv1r.v v13, v8
15151 ; CHECK-NEXT: vmv1r.v v14, v8
15152 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15153 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
15154 ; CHECK-NEXT: ret
15155 entry:
15156 tail call void @llvm.riscv.vsoxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
15157 ret void
15158 }
15160 declare void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
15161 declare void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
15163 define void @test_vsoxseg6_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
15164 ; CHECK-LABEL: test_vsoxseg6_nxv1f32_nxv1i64:
15165 ; CHECK: # %bb.0: # %entry
15166 ; CHECK-NEXT: vmv1r.v v10, v8
15167 ; CHECK-NEXT: vmv1r.v v11, v8
15168 ; CHECK-NEXT: vmv1r.v v12, v8
15169 ; CHECK-NEXT: vmv1r.v v13, v8
15170 ; CHECK-NEXT: vmv1r.v v14, v8
15171 ; CHECK-NEXT: vmv1r.v v15, v8
15172 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15173 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9
15174 ; CHECK-NEXT: ret
15175 entry:
15176 tail call void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
15177 ret void
15178 }
15180 define void @test_vsoxseg6_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15181 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_nxv1i64:
15182 ; CHECK: # %bb.0: # %entry
15183 ; CHECK-NEXT: vmv1r.v v10, v8
15184 ; CHECK-NEXT: vmv1r.v v11, v8
15185 ; CHECK-NEXT: vmv1r.v v12, v8
15186 ; CHECK-NEXT: vmv1r.v v13, v8
15187 ; CHECK-NEXT: vmv1r.v v14, v8
15188 ; CHECK-NEXT: vmv1r.v v15, v8
15189 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15190 ; CHECK-NEXT: vsoxseg6ei64.v v10, (a0), v9, v0.t
15191 ; CHECK-NEXT: ret
15192 entry:
15193 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
15194 ret void
15195 }
15197 declare void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
15198 declare void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
15200 define void @test_vsoxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
15201 ; CHECK-LABEL: test_vsoxseg6_nxv1f32_nxv1i32:
15202 ; CHECK: # %bb.0: # %entry
15203 ; CHECK-NEXT: vmv1r.v v10, v8
15204 ; CHECK-NEXT: vmv1r.v v11, v8
15205 ; CHECK-NEXT: vmv1r.v v12, v8
15206 ; CHECK-NEXT: vmv1r.v v13, v8
15207 ; CHECK-NEXT: vmv1r.v v14, v8
15208 ; CHECK-NEXT: vmv1r.v v15, v8
15209 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15210 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
15211 ; CHECK-NEXT: ret
15212 entry:
15213 tail call void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
15214 ret void
15215 }
15217 define void @test_vsoxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15218 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_nxv1i32:
15219 ; CHECK: # %bb.0: # %entry
15220 ; CHECK-NEXT: vmv1r.v v10, v8
15221 ; CHECK-NEXT: vmv1r.v v11, v8
15222 ; CHECK-NEXT: vmv1r.v v12, v8
15223 ; CHECK-NEXT: vmv1r.v v13, v8
15224 ; CHECK-NEXT: vmv1r.v v14, v8
15225 ; CHECK-NEXT: vmv1r.v v15, v8
15226 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15227 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
15228 ; CHECK-NEXT: ret
15229 entry:
15230 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
15231 ret void
15232 }
15234 declare void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
15235 declare void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
15237 define void @test_vsoxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
15238 ; CHECK-LABEL: test_vsoxseg6_nxv1f32_nxv1i16:
15239 ; CHECK: # %bb.0: # %entry
15240 ; CHECK-NEXT: vmv1r.v v10, v8
15241 ; CHECK-NEXT: vmv1r.v v11, v8
15242 ; CHECK-NEXT: vmv1r.v v12, v8
15243 ; CHECK-NEXT: vmv1r.v v13, v8
15244 ; CHECK-NEXT: vmv1r.v v14, v8
15245 ; CHECK-NEXT: vmv1r.v v15, v8
15246 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15247 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
15248 ; CHECK-NEXT: ret
15249 entry:
15250 tail call void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
15251 ret void
15252 }
15254 define void @test_vsoxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15255 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_nxv1i16:
15256 ; CHECK: # %bb.0: # %entry
15257 ; CHECK-NEXT: vmv1r.v v10, v8
15258 ; CHECK-NEXT: vmv1r.v v11, v8
15259 ; CHECK-NEXT: vmv1r.v v12, v8
15260 ; CHECK-NEXT: vmv1r.v v13, v8
15261 ; CHECK-NEXT: vmv1r.v v14, v8
15262 ; CHECK-NEXT: vmv1r.v v15, v8
15263 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15264 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
15265 ; CHECK-NEXT: ret
15266 entry:
15267 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
15268 ret void
15269 }
15271 declare void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
15272 declare void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
15274 define void @test_vsoxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
15275 ; CHECK-LABEL: test_vsoxseg6_nxv1f32_nxv1i8:
15276 ; CHECK: # %bb.0: # %entry
15277 ; CHECK-NEXT: vmv1r.v v10, v8
15278 ; CHECK-NEXT: vmv1r.v v11, v8
15279 ; CHECK-NEXT: vmv1r.v v12, v8
15280 ; CHECK-NEXT: vmv1r.v v13, v8
15281 ; CHECK-NEXT: vmv1r.v v14, v8
15282 ; CHECK-NEXT: vmv1r.v v15, v8
15283 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15284 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
15285 ; CHECK-NEXT: ret
15286 entry:
15287 tail call void @llvm.riscv.vsoxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
15288 ret void
15289 }
15291 define void @test_vsoxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15292 ; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_nxv1i8:
15293 ; CHECK: # %bb.0: # %entry
15294 ; CHECK-NEXT: vmv1r.v v10, v8
15295 ; CHECK-NEXT: vmv1r.v v11, v8
15296 ; CHECK-NEXT: vmv1r.v v12, v8
15297 ; CHECK-NEXT: vmv1r.v v13, v8
15298 ; CHECK-NEXT: vmv1r.v v14, v8
15299 ; CHECK-NEXT: vmv1r.v v15, v8
15300 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15301 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
15302 ; CHECK-NEXT: ret
15303 entry:
15304 tail call void @llvm.riscv.vsoxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
15305 ret void
15306 }
15308 declare void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
15309 declare void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
15311 define void @test_vsoxseg7_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
15312 ; CHECK-LABEL: test_vsoxseg7_nxv1f32_nxv1i64:
15313 ; CHECK: # %bb.0: # %entry
15314 ; CHECK-NEXT: vmv1r.v v10, v8
15315 ; CHECK-NEXT: vmv1r.v v11, v8
15316 ; CHECK-NEXT: vmv1r.v v12, v8
15317 ; CHECK-NEXT: vmv1r.v v13, v8
15318 ; CHECK-NEXT: vmv1r.v v14, v8
15319 ; CHECK-NEXT: vmv1r.v v15, v8
15320 ; CHECK-NEXT: vmv1r.v v16, v8
15321 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15322 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9
15323 ; CHECK-NEXT: ret
15324 entry:
15325 tail call void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
15326 ret void
15327 }
15329 define void @test_vsoxseg7_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15330 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_nxv1i64:
15331 ; CHECK: # %bb.0: # %entry
15332 ; CHECK-NEXT: vmv1r.v v10, v8
15333 ; CHECK-NEXT: vmv1r.v v11, v8
15334 ; CHECK-NEXT: vmv1r.v v12, v8
15335 ; CHECK-NEXT: vmv1r.v v13, v8
15336 ; CHECK-NEXT: vmv1r.v v14, v8
15337 ; CHECK-NEXT: vmv1r.v v15, v8
15338 ; CHECK-NEXT: vmv1r.v v16, v8
15339 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15340 ; CHECK-NEXT: vsoxseg7ei64.v v10, (a0), v9, v0.t
15341 ; CHECK-NEXT: ret
15342 entry:
15343 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
15344 ret void
15345 }
15347 declare void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
15348 declare void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
15350 define void @test_vsoxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
15351 ; CHECK-LABEL: test_vsoxseg7_nxv1f32_nxv1i32:
15352 ; CHECK: # %bb.0: # %entry
15353 ; CHECK-NEXT: vmv1r.v v10, v8
15354 ; CHECK-NEXT: vmv1r.v v11, v8
15355 ; CHECK-NEXT: vmv1r.v v12, v8
15356 ; CHECK-NEXT: vmv1r.v v13, v8
15357 ; CHECK-NEXT: vmv1r.v v14, v8
15358 ; CHECK-NEXT: vmv1r.v v15, v8
15359 ; CHECK-NEXT: vmv1r.v v16, v8
15360 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15361 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
15362 ; CHECK-NEXT: ret
15363 entry:
15364 tail call void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
15365 ret void
15366 }
15368 define void @test_vsoxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15369 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_nxv1i32:
15370 ; CHECK: # %bb.0: # %entry
15371 ; CHECK-NEXT: vmv1r.v v10, v8
15372 ; CHECK-NEXT: vmv1r.v v11, v8
15373 ; CHECK-NEXT: vmv1r.v v12, v8
15374 ; CHECK-NEXT: vmv1r.v v13, v8
15375 ; CHECK-NEXT: vmv1r.v v14, v8
15376 ; CHECK-NEXT: vmv1r.v v15, v8
15377 ; CHECK-NEXT: vmv1r.v v16, v8
15378 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15379 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
15380 ; CHECK-NEXT: ret
15381 entry:
15382 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
15383 ret void
15384 }
15386 declare void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
15387 declare void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
15389 define void @test_vsoxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
15390 ; CHECK-LABEL: test_vsoxseg7_nxv1f32_nxv1i16:
15391 ; CHECK: # %bb.0: # %entry
15392 ; CHECK-NEXT: vmv1r.v v10, v8
15393 ; CHECK-NEXT: vmv1r.v v11, v8
15394 ; CHECK-NEXT: vmv1r.v v12, v8
15395 ; CHECK-NEXT: vmv1r.v v13, v8
15396 ; CHECK-NEXT: vmv1r.v v14, v8
15397 ; CHECK-NEXT: vmv1r.v v15, v8
15398 ; CHECK-NEXT: vmv1r.v v16, v8
15399 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15400 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
15401 ; CHECK-NEXT: ret
15402 entry:
15403 tail call void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
15404 ret void
15405 }
15407 define void @test_vsoxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15408 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_nxv1i16:
15409 ; CHECK: # %bb.0: # %entry
15410 ; CHECK-NEXT: vmv1r.v v10, v8
15411 ; CHECK-NEXT: vmv1r.v v11, v8
15412 ; CHECK-NEXT: vmv1r.v v12, v8
15413 ; CHECK-NEXT: vmv1r.v v13, v8
15414 ; CHECK-NEXT: vmv1r.v v14, v8
15415 ; CHECK-NEXT: vmv1r.v v15, v8
15416 ; CHECK-NEXT: vmv1r.v v16, v8
15417 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15418 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
15419 ; CHECK-NEXT: ret
15420 entry:
15421 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
15422 ret void
15423 }
15425 declare void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
15426 declare void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
15428 define void @test_vsoxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
15429 ; CHECK-LABEL: test_vsoxseg7_nxv1f32_nxv1i8:
15430 ; CHECK: # %bb.0: # %entry
15431 ; CHECK-NEXT: vmv1r.v v10, v8
15432 ; CHECK-NEXT: vmv1r.v v11, v8
15433 ; CHECK-NEXT: vmv1r.v v12, v8
15434 ; CHECK-NEXT: vmv1r.v v13, v8
15435 ; CHECK-NEXT: vmv1r.v v14, v8
15436 ; CHECK-NEXT: vmv1r.v v15, v8
15437 ; CHECK-NEXT: vmv1r.v v16, v8
15438 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15439 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
15440 ; CHECK-NEXT: ret
15441 entry:
15442 tail call void @llvm.riscv.vsoxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
15443 ret void
15444 }
15446 define void @test_vsoxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15447 ; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_nxv1i8:
15448 ; CHECK: # %bb.0: # %entry
15449 ; CHECK-NEXT: vmv1r.v v10, v8
15450 ; CHECK-NEXT: vmv1r.v v11, v8
15451 ; CHECK-NEXT: vmv1r.v v12, v8
15452 ; CHECK-NEXT: vmv1r.v v13, v8
15453 ; CHECK-NEXT: vmv1r.v v14, v8
15454 ; CHECK-NEXT: vmv1r.v v15, v8
15455 ; CHECK-NEXT: vmv1r.v v16, v8
15456 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15457 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
15458 ; CHECK-NEXT: ret
15459 entry:
15460 tail call void @llvm.riscv.vsoxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
15461 ret void
15462 }
15464 declare void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, i64)
15465 declare void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
15467 define void @test_vsoxseg8_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {
15468 ; CHECK-LABEL: test_vsoxseg8_nxv1f32_nxv1i64:
15469 ; CHECK: # %bb.0: # %entry
15470 ; CHECK-NEXT: vmv1r.v v10, v8
15471 ; CHECK-NEXT: vmv1r.v v11, v8
15472 ; CHECK-NEXT: vmv1r.v v12, v8
15473 ; CHECK-NEXT: vmv1r.v v13, v8
15474 ; CHECK-NEXT: vmv1r.v v14, v8
15475 ; CHECK-NEXT: vmv1r.v v15, v8
15476 ; CHECK-NEXT: vmv1r.v v16, v8
15477 ; CHECK-NEXT: vmv1r.v v17, v8
15478 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15479 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9
15480 ; CHECK-NEXT: ret
15481 entry:
15482 tail call void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl)
15483 ret void
15484 }
15486 define void @test_vsoxseg8_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15487 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_nxv1i64:
15488 ; CHECK: # %bb.0: # %entry
15489 ; CHECK-NEXT: vmv1r.v v10, v8
15490 ; CHECK-NEXT: vmv1r.v v11, v8
15491 ; CHECK-NEXT: vmv1r.v v12, v8
15492 ; CHECK-NEXT: vmv1r.v v13, v8
15493 ; CHECK-NEXT: vmv1r.v v14, v8
15494 ; CHECK-NEXT: vmv1r.v v15, v8
15495 ; CHECK-NEXT: vmv1r.v v16, v8
15496 ; CHECK-NEXT: vmv1r.v v17, v8
15497 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15498 ; CHECK-NEXT: vsoxseg8ei64.v v10, (a0), v9, v0.t
15499 ; CHECK-NEXT: ret
15500 entry:
15501 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
15502 ret void
15503 }
15505 declare void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, i64)
15506 declare void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
15508 define void @test_vsoxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {
15509 ; CHECK-LABEL: test_vsoxseg8_nxv1f32_nxv1i32:
15510 ; CHECK: # %bb.0: # %entry
15511 ; CHECK-NEXT: vmv1r.v v10, v8
15512 ; CHECK-NEXT: vmv1r.v v11, v8
15513 ; CHECK-NEXT: vmv1r.v v12, v8
15514 ; CHECK-NEXT: vmv1r.v v13, v8
15515 ; CHECK-NEXT: vmv1r.v v14, v8
15516 ; CHECK-NEXT: vmv1r.v v15, v8
15517 ; CHECK-NEXT: vmv1r.v v16, v8
15518 ; CHECK-NEXT: vmv1r.v v17, v8
15519 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15520 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
15521 ; CHECK-NEXT: ret
15522 entry:
15523 tail call void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl)
15524 ret void
15525 }
15527 define void @test_vsoxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15528 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_nxv1i32:
15529 ; CHECK: # %bb.0: # %entry
15530 ; CHECK-NEXT: vmv1r.v v10, v8
15531 ; CHECK-NEXT: vmv1r.v v11, v8
15532 ; CHECK-NEXT: vmv1r.v v12, v8
15533 ; CHECK-NEXT: vmv1r.v v13, v8
15534 ; CHECK-NEXT: vmv1r.v v14, v8
15535 ; CHECK-NEXT: vmv1r.v v15, v8
15536 ; CHECK-NEXT: vmv1r.v v16, v8
15537 ; CHECK-NEXT: vmv1r.v v17, v8
15538 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15539 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
15540 ; CHECK-NEXT: ret
15541 entry:
15542 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
15543 ret void
15544 }
15546 declare void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, i64)
15547 declare void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
15549 define void @test_vsoxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {
15550 ; CHECK-LABEL: test_vsoxseg8_nxv1f32_nxv1i16:
15551 ; CHECK: # %bb.0: # %entry
15552 ; CHECK-NEXT: vmv1r.v v10, v8
15553 ; CHECK-NEXT: vmv1r.v v11, v8
15554 ; CHECK-NEXT: vmv1r.v v12, v8
15555 ; CHECK-NEXT: vmv1r.v v13, v8
15556 ; CHECK-NEXT: vmv1r.v v14, v8
15557 ; CHECK-NEXT: vmv1r.v v15, v8
15558 ; CHECK-NEXT: vmv1r.v v16, v8
15559 ; CHECK-NEXT: vmv1r.v v17, v8
15560 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15561 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
15562 ; CHECK-NEXT: ret
15563 entry:
15564 tail call void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl)
15565 ret void
15566 }
15568 define void @test_vsoxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15569 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_nxv1i16:
15570 ; CHECK: # %bb.0: # %entry
15571 ; CHECK-NEXT: vmv1r.v v10, v8
15572 ; CHECK-NEXT: vmv1r.v v11, v8
15573 ; CHECK-NEXT: vmv1r.v v12, v8
15574 ; CHECK-NEXT: vmv1r.v v13, v8
15575 ; CHECK-NEXT: vmv1r.v v14, v8
15576 ; CHECK-NEXT: vmv1r.v v15, v8
15577 ; CHECK-NEXT: vmv1r.v v16, v8
15578 ; CHECK-NEXT: vmv1r.v v17, v8
15579 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15580 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
15581 ; CHECK-NEXT: ret
15582 entry:
15583 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
15584 ret void
15585 }
15587 declare void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, i64)
15588 declare void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
15590 define void @test_vsoxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {
15591 ; CHECK-LABEL: test_vsoxseg8_nxv1f32_nxv1i8:
15592 ; CHECK: # %bb.0: # %entry
15593 ; CHECK-NEXT: vmv1r.v v10, v8
15594 ; CHECK-NEXT: vmv1r.v v11, v8
15595 ; CHECK-NEXT: vmv1r.v v12, v8
15596 ; CHECK-NEXT: vmv1r.v v13, v8
15597 ; CHECK-NEXT: vmv1r.v v14, v8
15598 ; CHECK-NEXT: vmv1r.v v15, v8
15599 ; CHECK-NEXT: vmv1r.v v16, v8
15600 ; CHECK-NEXT: vmv1r.v v17, v8
15601 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15602 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
15603 ; CHECK-NEXT: ret
15604 entry:
15605 tail call void @llvm.riscv.vsoxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl)
15606 ret void
15607 }
15609 define void @test_vsoxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
15610 ; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_nxv1i8:
15611 ; CHECK: # %bb.0: # %entry
15612 ; CHECK-NEXT: vmv1r.v v10, v8
15613 ; CHECK-NEXT: vmv1r.v v11, v8
15614 ; CHECK-NEXT: vmv1r.v v12, v8
15615 ; CHECK-NEXT: vmv1r.v v13, v8
15616 ; CHECK-NEXT: vmv1r.v v14, v8
15617 ; CHECK-NEXT: vmv1r.v v15, v8
15618 ; CHECK-NEXT: vmv1r.v v16, v8
15619 ; CHECK-NEXT: vmv1r.v v17, v8
15620 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
15621 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
15622 ; CHECK-NEXT: ret
15623 entry:
15624 tail call void @llvm.riscv.vsoxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
15625 ret void
15626 }
15628 declare void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, i64)
15629 declare void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
15631 define void @test_vsoxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
15632 ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i16:
15633 ; CHECK: # %bb.0: # %entry
15634 ; CHECK-NEXT: vmv2r.v v12, v10
15635 ; CHECK-NEXT: vmv2r.v v10, v8
15636 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15637 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
15638 ; CHECK-NEXT: ret
15639 entry:
15640 tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
15641 ret void
15642 }
15644 define void @test_vsoxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15645 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i16:
15646 ; CHECK: # %bb.0: # %entry
15647 ; CHECK-NEXT: vmv2r.v v12, v10
15648 ; CHECK-NEXT: vmv2r.v v10, v8
15649 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15650 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
15651 ; CHECK-NEXT: ret
15652 entry:
15653 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
15654 ret void
15655 }
15657 declare void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, i64)
15658 declare void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
15660 define void @test_vsoxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
15661 ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i8:
15662 ; CHECK: # %bb.0: # %entry
15663 ; CHECK-NEXT: vmv1r.v v12, v10
15664 ; CHECK-NEXT: vmv2r.v v10, v8
15665 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15666 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
15667 ; CHECK-NEXT: ret
15668 entry:
15669 tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
15670 ret void
15671 }
15673 define void @test_vsoxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15674 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i8:
15675 ; CHECK: # %bb.0: # %entry
15676 ; CHECK-NEXT: vmv1r.v v12, v10
15677 ; CHECK-NEXT: vmv2r.v v10, v8
15678 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15679 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
15680 ; CHECK-NEXT: ret
15681 entry:
15682 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
15683 ret void
15684 }
15686 declare void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, i64)
15687 declare void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
15689 define void @test_vsoxseg2_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
15690 ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i64:
15691 ; CHECK: # %bb.0: # %entry
15692 ; CHECK-NEXT: vmv2r.v v10, v8
15693 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15694 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
15695 ; CHECK-NEXT: ret
15696 entry:
15697 tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
15698 ret void
15699 }
15701 define void @test_vsoxseg2_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15702 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i64:
15703 ; CHECK: # %bb.0: # %entry
15704 ; CHECK-NEXT: vmv2r.v v10, v8
15705 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15706 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
15707 ; CHECK-NEXT: ret
15708 entry:
15709 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
15710 ret void
15711 }
15713 declare void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, i64)
15714 declare void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
15716 define void @test_vsoxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
15717 ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i32:
15718 ; CHECK: # %bb.0: # %entry
15719 ; CHECK-NEXT: vmv2r.v v10, v8
15720 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15721 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
15722 ; CHECK-NEXT: ret
15723 entry:
15724 tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
15725 ret void
15726 }
15728 define void @test_vsoxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15729 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i32:
15730 ; CHECK: # %bb.0: # %entry
15731 ; CHECK-NEXT: vmv2r.v v10, v8
15732 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15733 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
15734 ; CHECK-NEXT: ret
15735 entry:
15736 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
15737 ret void
15738 }
15740 declare void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, i64)
15741 declare void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
15743 define void @test_vsoxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
15744 ; CHECK-LABEL: test_vsoxseg3_nxv8f16_nxv8i16:
15745 ; CHECK: # %bb.0: # %entry
15746 ; CHECK-NEXT: vmv2r.v v12, v8
15747 ; CHECK-NEXT: vmv2r.v v14, v8
15748 ; CHECK-NEXT: vmv2r.v v16, v8
15749 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15750 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
15751 ; CHECK-NEXT: ret
15752 entry:
15753 tail call void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
15754 ret void
15755 }
15757 define void @test_vsoxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15758 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_nxv8i16:
15759 ; CHECK: # %bb.0: # %entry
15760 ; CHECK-NEXT: vmv2r.v v12, v8
15761 ; CHECK-NEXT: vmv2r.v v14, v8
15762 ; CHECK-NEXT: vmv2r.v v16, v8
15763 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15764 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
15765 ; CHECK-NEXT: ret
15766 entry:
15767 tail call void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
15768 ret void
15769 }
15771 declare void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, i64)
15772 declare void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
15774 define void @test_vsoxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
15775 ; CHECK-LABEL: test_vsoxseg3_nxv8f16_nxv8i8:
15776 ; CHECK: # %bb.0: # %entry
15777 ; CHECK-NEXT: vmv2r.v v12, v8
15778 ; CHECK-NEXT: vmv2r.v v14, v8
15779 ; CHECK-NEXT: vmv2r.v v16, v8
15780 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15781 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
15782 ; CHECK-NEXT: ret
15783 entry:
15784 tail call void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
15785 ret void
15786 }
15788 define void @test_vsoxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15789 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_nxv8i8:
15790 ; CHECK: # %bb.0: # %entry
15791 ; CHECK-NEXT: vmv2r.v v12, v8
15792 ; CHECK-NEXT: vmv2r.v v14, v8
15793 ; CHECK-NEXT: vmv2r.v v16, v8
15794 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15795 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
15796 ; CHECK-NEXT: ret
15797 entry:
15798 tail call void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
15799 ret void
15800 }
15802 declare void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, i64)
15803 declare void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
15805 define void @test_vsoxseg3_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
15806 ; CHECK-LABEL: test_vsoxseg3_nxv8f16_nxv8i64:
15807 ; CHECK: # %bb.0: # %entry
15808 ; CHECK-NEXT: vmv2r.v v10, v8
15809 ; CHECK-NEXT: vmv2r.v v12, v8
15810 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15811 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16
15812 ; CHECK-NEXT: ret
15813 entry:
15814 tail call void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
15815 ret void
15816 }
15818 define void @test_vsoxseg3_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15819 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_nxv8i64:
15820 ; CHECK: # %bb.0: # %entry
15821 ; CHECK-NEXT: vmv2r.v v10, v8
15822 ; CHECK-NEXT: vmv2r.v v12, v8
15823 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15824 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16, v0.t
15825 ; CHECK-NEXT: ret
15826 entry:
15827 tail call void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
15828 ret void
15829 }
15831 declare void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, i64)
15832 declare void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
15834 define void @test_vsoxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
15835 ; CHECK-LABEL: test_vsoxseg3_nxv8f16_nxv8i32:
15836 ; CHECK: # %bb.0: # %entry
15837 ; CHECK-NEXT: vmv2r.v v10, v8
15838 ; CHECK-NEXT: vmv4r.v v16, v12
15839 ; CHECK-NEXT: vmv2r.v v12, v8
15840 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15841 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16
15842 ; CHECK-NEXT: ret
15843 entry:
15844 tail call void @llvm.riscv.vsoxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
15845 ret void
15846 }
15848 define void @test_vsoxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15849 ; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_nxv8i32:
15850 ; CHECK: # %bb.0: # %entry
15851 ; CHECK-NEXT: vmv2r.v v10, v8
15852 ; CHECK-NEXT: vmv4r.v v16, v12
15853 ; CHECK-NEXT: vmv2r.v v12, v8
15854 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15855 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v16, v0.t
15856 ; CHECK-NEXT: ret
15857 entry:
15858 tail call void @llvm.riscv.vsoxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
15859 ret void
15860 }
15862 declare void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, i64)
15863 declare void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
15865 define void @test_vsoxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
15866 ; CHECK-LABEL: test_vsoxseg4_nxv8f16_nxv8i16:
15867 ; CHECK: # %bb.0: # %entry
15868 ; CHECK-NEXT: vmv2r.v v12, v8
15869 ; CHECK-NEXT: vmv2r.v v14, v8
15870 ; CHECK-NEXT: vmv2r.v v16, v8
15871 ; CHECK-NEXT: vmv2r.v v18, v8
15872 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15873 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
15874 ; CHECK-NEXT: ret
15875 entry:
15876 tail call void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
15877 ret void
15878 }
15880 define void @test_vsoxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15881 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_nxv8i16:
15882 ; CHECK: # %bb.0: # %entry
15883 ; CHECK-NEXT: vmv2r.v v12, v8
15884 ; CHECK-NEXT: vmv2r.v v14, v8
15885 ; CHECK-NEXT: vmv2r.v v16, v8
15886 ; CHECK-NEXT: vmv2r.v v18, v8
15887 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15888 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
15889 ; CHECK-NEXT: ret
15890 entry:
15891 tail call void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
15892 ret void
15893 }
15895 declare void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, i64)
15896 declare void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
15898 define void @test_vsoxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
15899 ; CHECK-LABEL: test_vsoxseg4_nxv8f16_nxv8i8:
15900 ; CHECK: # %bb.0: # %entry
15901 ; CHECK-NEXT: vmv2r.v v12, v8
15902 ; CHECK-NEXT: vmv2r.v v14, v8
15903 ; CHECK-NEXT: vmv2r.v v16, v8
15904 ; CHECK-NEXT: vmv2r.v v18, v8
15905 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15906 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
15907 ; CHECK-NEXT: ret
15908 entry:
15909 tail call void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
15910 ret void
15911 }
15913 define void @test_vsoxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15914 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_nxv8i8:
15915 ; CHECK: # %bb.0: # %entry
15916 ; CHECK-NEXT: vmv2r.v v12, v8
15917 ; CHECK-NEXT: vmv2r.v v14, v8
15918 ; CHECK-NEXT: vmv2r.v v16, v8
15919 ; CHECK-NEXT: vmv2r.v v18, v8
15920 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15921 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
15922 ; CHECK-NEXT: ret
15923 entry:
15924 tail call void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
15925 ret void
15926 }
15928 declare void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, i64)
15929 declare void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
15931 define void @test_vsoxseg4_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
15932 ; CHECK-LABEL: test_vsoxseg4_nxv8f16_nxv8i64:
15933 ; CHECK: # %bb.0: # %entry
15934 ; CHECK-NEXT: vmv2r.v v10, v8
15935 ; CHECK-NEXT: vmv2r.v v12, v8
15936 ; CHECK-NEXT: vmv2r.v v14, v8
15937 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15938 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16
15939 ; CHECK-NEXT: ret
15940 entry:
15941 tail call void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
15942 ret void
15943 }
15945 define void @test_vsoxseg4_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15946 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_nxv8i64:
15947 ; CHECK: # %bb.0: # %entry
15948 ; CHECK-NEXT: vmv2r.v v10, v8
15949 ; CHECK-NEXT: vmv2r.v v12, v8
15950 ; CHECK-NEXT: vmv2r.v v14, v8
15951 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15952 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v16, v0.t
15953 ; CHECK-NEXT: ret
15954 entry:
15955 tail call void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
15956 ret void
15957 }
15959 declare void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, i64)
15960 declare void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
15962 define void @test_vsoxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
15963 ; CHECK-LABEL: test_vsoxseg4_nxv8f16_nxv8i32:
15964 ; CHECK: # %bb.0: # %entry
15965 ; CHECK-NEXT: vmv2r.v v16, v8
15966 ; CHECK-NEXT: vmv2r.v v18, v8
15967 ; CHECK-NEXT: vmv2r.v v20, v8
15968 ; CHECK-NEXT: vmv2r.v v22, v8
15969 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15970 ; CHECK-NEXT: vsoxseg4ei32.v v16, (a0), v12
15971 ; CHECK-NEXT: ret
15972 entry:
15973 tail call void @llvm.riscv.vsoxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
15974 ret void
15975 }
15977 define void @test_vsoxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
15978 ; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_nxv8i32:
15979 ; CHECK: # %bb.0: # %entry
15980 ; CHECK-NEXT: vmv2r.v v16, v8
15981 ; CHECK-NEXT: vmv2r.v v18, v8
15982 ; CHECK-NEXT: vmv2r.v v20, v8
15983 ; CHECK-NEXT: vmv2r.v v22, v8
15984 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
15985 ; CHECK-NEXT: vsoxseg4ei32.v v16, (a0), v12, v0.t
15986 ; CHECK-NEXT: ret
15987 entry:
15988 tail call void @llvm.riscv.vsoxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
15989 ret void
15990 }
15992 declare void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i16>, i64)
15993 declare void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
15995 define void @test_vsoxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {
15996 ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i16:
15997 ; CHECK: # %bb.0: # %entry
15998 ; CHECK-NEXT: vmv2r.v v16, v12
15999 ; CHECK-NEXT: vmv4r.v v12, v8
16000 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16001 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
16002 ; CHECK-NEXT: ret
16003 entry:
16004 tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl)
16005 ret void
16006 }
16008 define void @test_vsoxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
16009 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i16:
16010 ; CHECK: # %bb.0: # %entry
16011 ; CHECK-NEXT: vmv2r.v v16, v12
16012 ; CHECK-NEXT: vmv4r.v v12, v8
16013 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16014 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
16015 ; CHECK-NEXT: ret
16016 entry:
16017 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
16018 ret void
16019 }
16021 declare void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i8>, i64)
16022 declare void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
16024 define void @test_vsoxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {
16025 ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i8:
16026 ; CHECK: # %bb.0: # %entry
16027 ; CHECK-NEXT: vmv1r.v v16, v12
16028 ; CHECK-NEXT: vmv4r.v v12, v8
16029 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16030 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
16031 ; CHECK-NEXT: ret
16032 entry:
16033 tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl)
16034 ret void
16035 }
16037 define void @test_vsoxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
16038 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i8:
16039 ; CHECK: # %bb.0: # %entry
16040 ; CHECK-NEXT: vmv1r.v v16, v12
16041 ; CHECK-NEXT: vmv4r.v v12, v8
16042 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16043 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
16044 ; CHECK-NEXT: ret
16045 entry:
16046 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
16047 ret void
16048 }
16050 declare void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i64>, i64)
16051 declare void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
16053 define void @test_vsoxseg2_nxv8f32_nxv8i64(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {
16054 ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i64:
16055 ; CHECK: # %bb.0: # %entry
16056 ; CHECK-NEXT: vmv4r.v v12, v8
16057 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16058 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
16059 ; CHECK-NEXT: ret
16060 entry:
16061 tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl)
16062 ret void
16063 }
16065 define void @test_vsoxseg2_mask_nxv8f32_nxv8i64(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
16066 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i64:
16067 ; CHECK: # %bb.0: # %entry
16068 ; CHECK-NEXT: vmv4r.v v12, v8
16069 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16070 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
16071 ; CHECK-NEXT: ret
16072 entry:
16073 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
16074 ret void
16075 }
16077 declare void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i32>, i64)
16078 declare void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
16080 define void @test_vsoxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {
16081 ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i32:
16082 ; CHECK: # %bb.0: # %entry
16083 ; CHECK-NEXT: vmv4r.v v16, v12
16084 ; CHECK-NEXT: vmv4r.v v12, v8
16085 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16086 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
16087 ; CHECK-NEXT: ret
16088 entry:
16089 tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl)
16090 ret void
16091 }
16093 define void @test_vsoxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
16094 ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i32:
16095 ; CHECK: # %bb.0: # %entry
16096 ; CHECK-NEXT: vmv4r.v v16, v12
16097 ; CHECK-NEXT: vmv4r.v v12, v8
16098 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
16099 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
16100 ; CHECK-NEXT: ret
16101 entry:
16102 tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
16103 ret void
16104 }
16106 declare void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, i64)
16107 declare void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
16109 define void @test_vsoxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
16110 ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i32:
16111 ; CHECK: # %bb.0: # %entry
16112 ; CHECK-NEXT: vmv1r.v v12, v10
16113 ; CHECK-NEXT: vmv2r.v v10, v8
16114 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16115 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
16116 ; CHECK-NEXT: ret
16117 entry:
16118 tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
16119 ret void
16120 }
16122 define void @test_vsoxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16123 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i32:
16124 ; CHECK: # %bb.0: # %entry
16125 ; CHECK-NEXT: vmv1r.v v12, v10
16126 ; CHECK-NEXT: vmv2r.v v10, v8
16127 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16128 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
16129 ; CHECK-NEXT: ret
16130 entry:
16131 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
16132 ret void
16133 }
16135 declare void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, i64)
16136 declare void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
16138 define void @test_vsoxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
16139 ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i8:
16140 ; CHECK: # %bb.0: # %entry
16141 ; CHECK-NEXT: vmv1r.v v12, v10
16142 ; CHECK-NEXT: vmv2r.v v10, v8
16143 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16144 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
16145 ; CHECK-NEXT: ret
16146 entry:
16147 tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
16148 ret void
16149 }
16151 define void @test_vsoxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16152 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i8:
16153 ; CHECK: # %bb.0: # %entry
16154 ; CHECK-NEXT: vmv1r.v v12, v10
16155 ; CHECK-NEXT: vmv2r.v v10, v8
16156 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16157 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
16158 ; CHECK-NEXT: ret
16159 entry:
16160 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
16161 ret void
16162 }
16164 declare void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, i64)
16165 declare void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
16167 define void @test_vsoxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
16168 ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i16:
16169 ; CHECK: # %bb.0: # %entry
16170 ; CHECK-NEXT: vmv1r.v v12, v10
16171 ; CHECK-NEXT: vmv2r.v v10, v8
16172 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16173 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
16174 ; CHECK-NEXT: ret
16175 entry:
16176 tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
16177 ret void
16178 }
16180 define void @test_vsoxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16181 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i16:
16182 ; CHECK: # %bb.0: # %entry
16183 ; CHECK-NEXT: vmv1r.v v12, v10
16184 ; CHECK-NEXT: vmv2r.v v10, v8
16185 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16186 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
16187 ; CHECK-NEXT: ret
16188 entry:
16189 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
16190 ret void
16191 }
16193 declare void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, i64)
16194 declare void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
16196 define void @test_vsoxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
16197 ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i64:
16198 ; CHECK: # %bb.0: # %entry
16199 ; CHECK-NEXT: vmv2r.v v12, v10
16200 ; CHECK-NEXT: vmv2r.v v10, v8
16201 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16202 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
16203 ; CHECK-NEXT: ret
16204 entry:
16205 tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
16206 ret void
16207 }
16209 define void @test_vsoxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16210 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i64:
16211 ; CHECK: # %bb.0: # %entry
16212 ; CHECK-NEXT: vmv2r.v v12, v10
16213 ; CHECK-NEXT: vmv2r.v v10, v8
16214 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16215 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
16216 ; CHECK-NEXT: ret
16217 entry:
16218 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
16219 ret void
16220 }
16222 declare void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, i64)
16223 declare void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
16225 define void @test_vsoxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
16226 ; CHECK-LABEL: test_vsoxseg3_nxv2f64_nxv2i32:
16227 ; CHECK: # %bb.0: # %entry
16228 ; CHECK-NEXT: vmv2r.v v12, v8
16229 ; CHECK-NEXT: vmv2r.v v14, v8
16230 ; CHECK-NEXT: vmv2r.v v16, v8
16231 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16232 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10
16233 ; CHECK-NEXT: ret
16234 entry:
16235 tail call void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
16236 ret void
16237 }
16239 define void @test_vsoxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16240 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_nxv2i32:
16241 ; CHECK: # %bb.0: # %entry
16242 ; CHECK-NEXT: vmv2r.v v12, v8
16243 ; CHECK-NEXT: vmv2r.v v14, v8
16244 ; CHECK-NEXT: vmv2r.v v16, v8
16245 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16246 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10, v0.t
16247 ; CHECK-NEXT: ret
16248 entry:
16249 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
16250 ret void
16251 }
16253 declare void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, i64)
16254 declare void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
16256 define void @test_vsoxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
16257 ; CHECK-LABEL: test_vsoxseg3_nxv2f64_nxv2i8:
16258 ; CHECK: # %bb.0: # %entry
16259 ; CHECK-NEXT: vmv2r.v v12, v8
16260 ; CHECK-NEXT: vmv2r.v v14, v8
16261 ; CHECK-NEXT: vmv2r.v v16, v8
16262 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16263 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
16264 ; CHECK-NEXT: ret
16265 entry:
16266 tail call void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
16267 ret void
16268 }
16270 define void @test_vsoxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16271 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_nxv2i8:
16272 ; CHECK: # %bb.0: # %entry
16273 ; CHECK-NEXT: vmv2r.v v12, v8
16274 ; CHECK-NEXT: vmv2r.v v14, v8
16275 ; CHECK-NEXT: vmv2r.v v16, v8
16276 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16277 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
16278 ; CHECK-NEXT: ret
16279 entry:
16280 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
16281 ret void
16282 }
16284 declare void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, i64)
16285 declare void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
16287 define void @test_vsoxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
16288 ; CHECK-LABEL: test_vsoxseg3_nxv2f64_nxv2i16:
16289 ; CHECK: # %bb.0: # %entry
16290 ; CHECK-NEXT: vmv2r.v v12, v8
16291 ; CHECK-NEXT: vmv2r.v v14, v8
16292 ; CHECK-NEXT: vmv2r.v v16, v8
16293 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16294 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
16295 ; CHECK-NEXT: ret
16296 entry:
16297 tail call void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
16298 ret void
16299 }
16301 define void @test_vsoxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16302 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_nxv2i16:
16303 ; CHECK: # %bb.0: # %entry
16304 ; CHECK-NEXT: vmv2r.v v12, v8
16305 ; CHECK-NEXT: vmv2r.v v14, v8
16306 ; CHECK-NEXT: vmv2r.v v16, v8
16307 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16308 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
16309 ; CHECK-NEXT: ret
16310 entry:
16311 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
16312 ret void
16313 }
16315 declare void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, i64)
16316 declare void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
16318 define void @test_vsoxseg3_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
16319 ; CHECK-LABEL: test_vsoxseg3_nxv2f64_nxv2i64:
16320 ; CHECK: # %bb.0: # %entry
16321 ; CHECK-NEXT: vmv2r.v v12, v8
16322 ; CHECK-NEXT: vmv2r.v v14, v8
16323 ; CHECK-NEXT: vmv2r.v v16, v8
16324 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16325 ; CHECK-NEXT: vsoxseg3ei64.v v12, (a0), v10
16326 ; CHECK-NEXT: ret
16327 entry:
16328 tail call void @llvm.riscv.vsoxseg3.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
16329 ret void
16330 }
16332 define void @test_vsoxseg3_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16333 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_nxv2i64:
16334 ; CHECK: # %bb.0: # %entry
16335 ; CHECK-NEXT: vmv2r.v v12, v8
16336 ; CHECK-NEXT: vmv2r.v v14, v8
16337 ; CHECK-NEXT: vmv2r.v v16, v8
16338 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16339 ; CHECK-NEXT: vsoxseg3ei64.v v12, (a0), v10, v0.t
16340 ; CHECK-NEXT: ret
16341 entry:
16342 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
16343 ret void
16344 }
16346 declare void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, i64)
16347 declare void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
16349 define void @test_vsoxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
16350 ; CHECK-LABEL: test_vsoxseg4_nxv2f64_nxv2i32:
16351 ; CHECK: # %bb.0: # %entry
16352 ; CHECK-NEXT: vmv2r.v v12, v8
16353 ; CHECK-NEXT: vmv2r.v v14, v8
16354 ; CHECK-NEXT: vmv2r.v v16, v8
16355 ; CHECK-NEXT: vmv2r.v v18, v8
16356 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16357 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
16358 ; CHECK-NEXT: ret
16359 entry:
16360 tail call void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
16361 ret void
16362 }
16364 define void @test_vsoxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16365 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_nxv2i32:
16366 ; CHECK: # %bb.0: # %entry
16367 ; CHECK-NEXT: vmv2r.v v12, v8
16368 ; CHECK-NEXT: vmv2r.v v14, v8
16369 ; CHECK-NEXT: vmv2r.v v16, v8
16370 ; CHECK-NEXT: vmv2r.v v18, v8
16371 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16372 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
16373 ; CHECK-NEXT: ret
16374 entry:
16375 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
16376 ret void
16377 }
16379 declare void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, i64)
16380 declare void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
16382 define void @test_vsoxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
16383 ; CHECK-LABEL: test_vsoxseg4_nxv2f64_nxv2i8:
16384 ; CHECK: # %bb.0: # %entry
16385 ; CHECK-NEXT: vmv2r.v v12, v8
16386 ; CHECK-NEXT: vmv2r.v v14, v8
16387 ; CHECK-NEXT: vmv2r.v v16, v8
16388 ; CHECK-NEXT: vmv2r.v v18, v8
16389 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16390 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
16391 ; CHECK-NEXT: ret
16392 entry:
16393 tail call void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
16394 ret void
16395 }
16397 define void @test_vsoxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16398 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_nxv2i8:
16399 ; CHECK: # %bb.0: # %entry
16400 ; CHECK-NEXT: vmv2r.v v12, v8
16401 ; CHECK-NEXT: vmv2r.v v14, v8
16402 ; CHECK-NEXT: vmv2r.v v16, v8
16403 ; CHECK-NEXT: vmv2r.v v18, v8
16404 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16405 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
16406 ; CHECK-NEXT: ret
16407 entry:
16408 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
16409 ret void
16410 }
16412 declare void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, i64)
16413 declare void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
16415 define void @test_vsoxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
16416 ; CHECK-LABEL: test_vsoxseg4_nxv2f64_nxv2i16:
16417 ; CHECK: # %bb.0: # %entry
16418 ; CHECK-NEXT: vmv2r.v v12, v8
16419 ; CHECK-NEXT: vmv2r.v v14, v8
16420 ; CHECK-NEXT: vmv2r.v v16, v8
16421 ; CHECK-NEXT: vmv2r.v v18, v8
16422 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16423 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
16424 ; CHECK-NEXT: ret
16425 entry:
16426 tail call void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
16427 ret void
16428 }
16430 define void @test_vsoxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16431 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_nxv2i16:
16432 ; CHECK: # %bb.0: # %entry
16433 ; CHECK-NEXT: vmv2r.v v12, v8
16434 ; CHECK-NEXT: vmv2r.v v14, v8
16435 ; CHECK-NEXT: vmv2r.v v16, v8
16436 ; CHECK-NEXT: vmv2r.v v18, v8
16437 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16438 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
16439 ; CHECK-NEXT: ret
16440 entry:
16441 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
16442 ret void
16443 }
16445 declare void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, i64)
16446 declare void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
16448 define void @test_vsoxseg4_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
16449 ; CHECK-LABEL: test_vsoxseg4_nxv2f64_nxv2i64:
16450 ; CHECK: # %bb.0: # %entry
16451 ; CHECK-NEXT: vmv2r.v v12, v8
16452 ; CHECK-NEXT: vmv2r.v v14, v8
16453 ; CHECK-NEXT: vmv2r.v v16, v8
16454 ; CHECK-NEXT: vmv2r.v v18, v8
16455 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16456 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
16457 ; CHECK-NEXT: ret
16458 entry:
16459 tail call void @llvm.riscv.vsoxseg4.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
16460 ret void
16461 }
16463 define void @test_vsoxseg4_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
16464 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_nxv2i64:
16465 ; CHECK: # %bb.0: # %entry
16466 ; CHECK-NEXT: vmv2r.v v12, v8
16467 ; CHECK-NEXT: vmv2r.v v14, v8
16468 ; CHECK-NEXT: vmv2r.v v16, v8
16469 ; CHECK-NEXT: vmv2r.v v18, v8
16470 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
16471 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
16472 ; CHECK-NEXT: ret
16473 entry:
16474 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
16475 ret void
16476 }
16478 declare void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
16479 declare void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
16481 define void @test_vsoxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
16482 ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i32:
16483 ; CHECK: # %bb.0: # %entry
16484 ; CHECK-NEXT: vmv1r.v v9, v8
16485 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16486 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
16487 ; CHECK-NEXT: ret
16488 entry:
16489 tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
16490 ret void
16491 }
16493 define void @test_vsoxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16494 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i32:
16495 ; CHECK: # %bb.0: # %entry
16496 ; CHECK-NEXT: vmv1r.v v9, v8
16497 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16498 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
16499 ; CHECK-NEXT: ret
16500 entry:
16501 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
16502 ret void
16503 }
16505 declare void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
16506 declare void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
16508 define void @test_vsoxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
16509 ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i8:
16510 ; CHECK: # %bb.0: # %entry
16511 ; CHECK-NEXT: vmv1r.v v10, v9
16512 ; CHECK-NEXT: vmv1r.v v9, v8
16513 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16514 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
16515 ; CHECK-NEXT: ret
16516 entry:
16517 tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
16518 ret void
16519 }
16521 define void @test_vsoxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16522 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i8:
16523 ; CHECK: # %bb.0: # %entry
16524 ; CHECK-NEXT: vmv1r.v v10, v9
16525 ; CHECK-NEXT: vmv1r.v v9, v8
16526 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16527 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
16528 ; CHECK-NEXT: ret
16529 entry:
16530 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
16531 ret void
16532 }
16534 declare void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
16535 declare void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
16537 define void @test_vsoxseg2_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
16538 ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i64:
16539 ; CHECK: # %bb.0: # %entry
16540 ; CHECK-NEXT: vmv1r.v v9, v8
16541 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16542 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
16543 ; CHECK-NEXT: ret
16544 entry:
16545 tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
16546 ret void
16547 }
16549 define void @test_vsoxseg2_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16550 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i64:
16551 ; CHECK: # %bb.0: # %entry
16552 ; CHECK-NEXT: vmv1r.v v9, v8
16553 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16554 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
16555 ; CHECK-NEXT: ret
16556 entry:
16557 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
16558 ret void
16559 }
16561 declare void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
16562 declare void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
16564 define void @test_vsoxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
16565 ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i16:
16566 ; CHECK: # %bb.0: # %entry
16567 ; CHECK-NEXT: vmv1r.v v10, v9
16568 ; CHECK-NEXT: vmv1r.v v9, v8
16569 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16570 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
16571 ; CHECK-NEXT: ret
16572 entry:
16573 tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
16574 ret void
16575 }
16577 define void @test_vsoxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16578 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i16:
16579 ; CHECK: # %bb.0: # %entry
16580 ; CHECK-NEXT: vmv1r.v v10, v9
16581 ; CHECK-NEXT: vmv1r.v v9, v8
16582 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16583 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
16584 ; CHECK-NEXT: ret
16585 entry:
16586 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
16587 ret void
16588 }
16590 declare void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
16591 declare void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
16593 define void @test_vsoxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
16594 ; CHECK-LABEL: test_vsoxseg3_nxv4f16_nxv4i32:
16595 ; CHECK: # %bb.0: # %entry
16596 ; CHECK-NEXT: vmv1r.v v9, v8
16597 ; CHECK-NEXT: vmv2r.v v12, v10
16598 ; CHECK-NEXT: vmv1r.v v10, v8
16599 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16600 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12
16601 ; CHECK-NEXT: ret
16602 entry:
16603 tail call void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
16604 ret void
16605 }
16607 define void @test_vsoxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16608 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_nxv4i32:
16609 ; CHECK: # %bb.0: # %entry
16610 ; CHECK-NEXT: vmv1r.v v9, v8
16611 ; CHECK-NEXT: vmv2r.v v12, v10
16612 ; CHECK-NEXT: vmv1r.v v10, v8
16613 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16614 ; CHECK-NEXT: vsoxseg3ei32.v v8, (a0), v12, v0.t
16615 ; CHECK-NEXT: ret
16616 entry:
16617 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
16618 ret void
16619 }
16621 declare void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
16622 declare void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
16624 define void @test_vsoxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
16625 ; CHECK-LABEL: test_vsoxseg3_nxv4f16_nxv4i8:
16626 ; CHECK: # %bb.0: # %entry
16627 ; CHECK-NEXT: vmv1r.v v10, v8
16628 ; CHECK-NEXT: vmv1r.v v11, v8
16629 ; CHECK-NEXT: vmv1r.v v12, v8
16630 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16631 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
16632 ; CHECK-NEXT: ret
16633 entry:
16634 tail call void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
16635 ret void
16636 }
16638 define void @test_vsoxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16639 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_nxv4i8:
16640 ; CHECK: # %bb.0: # %entry
16641 ; CHECK-NEXT: vmv1r.v v10, v8
16642 ; CHECK-NEXT: vmv1r.v v11, v8
16643 ; CHECK-NEXT: vmv1r.v v12, v8
16644 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16645 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
16646 ; CHECK-NEXT: ret
16647 entry:
16648 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
16649 ret void
16650 }
16652 declare void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
16653 declare void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
16655 define void @test_vsoxseg3_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
16656 ; CHECK-LABEL: test_vsoxseg3_nxv4f16_nxv4i64:
16657 ; CHECK: # %bb.0: # %entry
16658 ; CHECK-NEXT: vmv1r.v v9, v8
16659 ; CHECK-NEXT: vmv1r.v v10, v8
16660 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16661 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
16662 ; CHECK-NEXT: ret
16663 entry:
16664 tail call void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
16665 ret void
16666 }
16668 define void @test_vsoxseg3_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16669 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_nxv4i64:
16670 ; CHECK: # %bb.0: # %entry
16671 ; CHECK-NEXT: vmv1r.v v9, v8
16672 ; CHECK-NEXT: vmv1r.v v10, v8
16673 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16674 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
16675 ; CHECK-NEXT: ret
16676 entry:
16677 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
16678 ret void
16679 }
16681 declare void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
16682 declare void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
16684 define void @test_vsoxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
16685 ; CHECK-LABEL: test_vsoxseg3_nxv4f16_nxv4i16:
16686 ; CHECK: # %bb.0: # %entry
16687 ; CHECK-NEXT: vmv1r.v v10, v8
16688 ; CHECK-NEXT: vmv1r.v v11, v8
16689 ; CHECK-NEXT: vmv1r.v v12, v8
16690 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16691 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
16692 ; CHECK-NEXT: ret
16693 entry:
16694 tail call void @llvm.riscv.vsoxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
16695 ret void
16696 }
16698 define void @test_vsoxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16699 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_nxv4i16:
16700 ; CHECK: # %bb.0: # %entry
16701 ; CHECK-NEXT: vmv1r.v v10, v8
16702 ; CHECK-NEXT: vmv1r.v v11, v8
16703 ; CHECK-NEXT: vmv1r.v v12, v8
16704 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16705 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
16706 ; CHECK-NEXT: ret
16707 entry:
16708 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
16709 ret void
16710 }
16712 declare void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
16713 declare void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
16715 define void @test_vsoxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
16716 ; CHECK-LABEL: test_vsoxseg4_nxv4f16_nxv4i32:
16717 ; CHECK: # %bb.0: # %entry
16718 ; CHECK-NEXT: vmv1r.v v12, v8
16719 ; CHECK-NEXT: vmv1r.v v13, v8
16720 ; CHECK-NEXT: vmv1r.v v14, v8
16721 ; CHECK-NEXT: vmv1r.v v15, v8
16722 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16723 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
16724 ; CHECK-NEXT: ret
16725 entry:
16726 tail call void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
16727 ret void
16728 }
16730 define void @test_vsoxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16731 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_nxv4i32:
16732 ; CHECK: # %bb.0: # %entry
16733 ; CHECK-NEXT: vmv1r.v v12, v8
16734 ; CHECK-NEXT: vmv1r.v v13, v8
16735 ; CHECK-NEXT: vmv1r.v v14, v8
16736 ; CHECK-NEXT: vmv1r.v v15, v8
16737 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16738 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
16739 ; CHECK-NEXT: ret
16740 entry:
16741 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
16742 ret void
16743 }
16745 declare void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
16746 declare void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
16748 define void @test_vsoxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
16749 ; CHECK-LABEL: test_vsoxseg4_nxv4f16_nxv4i8:
16750 ; CHECK: # %bb.0: # %entry
16751 ; CHECK-NEXT: vmv1r.v v10, v8
16752 ; CHECK-NEXT: vmv1r.v v11, v8
16753 ; CHECK-NEXT: vmv1r.v v12, v8
16754 ; CHECK-NEXT: vmv1r.v v13, v8
16755 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16756 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
16757 ; CHECK-NEXT: ret
16758 entry:
16759 tail call void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
16760 ret void
16761 }
16763 define void @test_vsoxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16764 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_nxv4i8:
16765 ; CHECK: # %bb.0: # %entry
16766 ; CHECK-NEXT: vmv1r.v v10, v8
16767 ; CHECK-NEXT: vmv1r.v v11, v8
16768 ; CHECK-NEXT: vmv1r.v v12, v8
16769 ; CHECK-NEXT: vmv1r.v v13, v8
16770 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16771 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
16772 ; CHECK-NEXT: ret
16773 entry:
16774 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
16775 ret void
16776 }
16778 declare void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
16779 declare void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
16781 define void @test_vsoxseg4_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
16782 ; CHECK-LABEL: test_vsoxseg4_nxv4f16_nxv4i64:
16783 ; CHECK: # %bb.0: # %entry
16784 ; CHECK-NEXT: vmv1r.v v9, v8
16785 ; CHECK-NEXT: vmv1r.v v10, v8
16786 ; CHECK-NEXT: vmv1r.v v11, v8
16787 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16788 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12
16789 ; CHECK-NEXT: ret
16790 entry:
16791 tail call void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
16792 ret void
16793 }
16795 define void @test_vsoxseg4_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16796 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_nxv4i64:
16797 ; CHECK: # %bb.0: # %entry
16798 ; CHECK-NEXT: vmv1r.v v9, v8
16799 ; CHECK-NEXT: vmv1r.v v10, v8
16800 ; CHECK-NEXT: vmv1r.v v11, v8
16801 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16802 ; CHECK-NEXT: vsoxseg4ei64.v v8, (a0), v12, v0.t
16803 ; CHECK-NEXT: ret
16804 entry:
16805 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
16806 ret void
16807 }
16809 declare void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
16810 declare void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
16812 define void @test_vsoxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
16813 ; CHECK-LABEL: test_vsoxseg4_nxv4f16_nxv4i16:
16814 ; CHECK: # %bb.0: # %entry
16815 ; CHECK-NEXT: vmv1r.v v10, v8
16816 ; CHECK-NEXT: vmv1r.v v11, v8
16817 ; CHECK-NEXT: vmv1r.v v12, v8
16818 ; CHECK-NEXT: vmv1r.v v13, v8
16819 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16820 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
16821 ; CHECK-NEXT: ret
16822 entry:
16823 tail call void @llvm.riscv.vsoxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
16824 ret void
16825 }
16827 define void @test_vsoxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16828 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_nxv4i16:
16829 ; CHECK: # %bb.0: # %entry
16830 ; CHECK-NEXT: vmv1r.v v10, v8
16831 ; CHECK-NEXT: vmv1r.v v11, v8
16832 ; CHECK-NEXT: vmv1r.v v12, v8
16833 ; CHECK-NEXT: vmv1r.v v13, v8
16834 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16835 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
16836 ; CHECK-NEXT: ret
16837 entry:
16838 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
16839 ret void
16840 }
16842 declare void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
16843 declare void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
16845 define void @test_vsoxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
16846 ; CHECK-LABEL: test_vsoxseg5_nxv4f16_nxv4i32:
16847 ; CHECK: # %bb.0: # %entry
16848 ; CHECK-NEXT: vmv1r.v v12, v8
16849 ; CHECK-NEXT: vmv1r.v v13, v8
16850 ; CHECK-NEXT: vmv1r.v v14, v8
16851 ; CHECK-NEXT: vmv1r.v v15, v8
16852 ; CHECK-NEXT: vmv1r.v v16, v8
16853 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16854 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10
16855 ; CHECK-NEXT: ret
16856 entry:
16857 tail call void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
16858 ret void
16859 }
16861 define void @test_vsoxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16862 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_nxv4i32:
16863 ; CHECK: # %bb.0: # %entry
16864 ; CHECK-NEXT: vmv1r.v v12, v8
16865 ; CHECK-NEXT: vmv1r.v v13, v8
16866 ; CHECK-NEXT: vmv1r.v v14, v8
16867 ; CHECK-NEXT: vmv1r.v v15, v8
16868 ; CHECK-NEXT: vmv1r.v v16, v8
16869 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16870 ; CHECK-NEXT: vsoxseg5ei32.v v12, (a0), v10, v0.t
16871 ; CHECK-NEXT: ret
16872 entry:
16873 tail call void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
16874 ret void
16875 }
16877 declare void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
16878 declare void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
16880 define void @test_vsoxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
16881 ; CHECK-LABEL: test_vsoxseg5_nxv4f16_nxv4i8:
16882 ; CHECK: # %bb.0: # %entry
16883 ; CHECK-NEXT: vmv1r.v v10, v8
16884 ; CHECK-NEXT: vmv1r.v v11, v8
16885 ; CHECK-NEXT: vmv1r.v v12, v8
16886 ; CHECK-NEXT: vmv1r.v v13, v8
16887 ; CHECK-NEXT: vmv1r.v v14, v8
16888 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16889 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
16890 ; CHECK-NEXT: ret
16891 entry:
16892 tail call void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
16893 ret void
16894 }
16896 define void @test_vsoxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16897 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_nxv4i8:
16898 ; CHECK: # %bb.0: # %entry
16899 ; CHECK-NEXT: vmv1r.v v10, v8
16900 ; CHECK-NEXT: vmv1r.v v11, v8
16901 ; CHECK-NEXT: vmv1r.v v12, v8
16902 ; CHECK-NEXT: vmv1r.v v13, v8
16903 ; CHECK-NEXT: vmv1r.v v14, v8
16904 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16905 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
16906 ; CHECK-NEXT: ret
16907 entry:
16908 tail call void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
16909 ret void
16910 }
16912 declare void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
16913 declare void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
16915 define void @test_vsoxseg5_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
16916 ; CHECK-LABEL: test_vsoxseg5_nxv4f16_nxv4i64:
16917 ; CHECK: # %bb.0: # %entry
16918 ; CHECK-NEXT: vmv1r.v v9, v8
16919 ; CHECK-NEXT: vmv1r.v v10, v8
16920 ; CHECK-NEXT: vmv1r.v v11, v8
16921 ; CHECK-NEXT: vmv4r.v v16, v12
16922 ; CHECK-NEXT: vmv1r.v v12, v8
16923 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16924 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16
16925 ; CHECK-NEXT: ret
16926 entry:
16927 tail call void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
16928 ret void
16929 }
16931 define void @test_vsoxseg5_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16932 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_nxv4i64:
16933 ; CHECK: # %bb.0: # %entry
16934 ; CHECK-NEXT: vmv1r.v v9, v8
16935 ; CHECK-NEXT: vmv1r.v v10, v8
16936 ; CHECK-NEXT: vmv1r.v v11, v8
16937 ; CHECK-NEXT: vmv4r.v v16, v12
16938 ; CHECK-NEXT: vmv1r.v v12, v8
16939 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16940 ; CHECK-NEXT: vsoxseg5ei64.v v8, (a0), v16, v0.t
16941 ; CHECK-NEXT: ret
16942 entry:
16943 tail call void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
16944 ret void
16945 }
16947 declare void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
16948 declare void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
16950 define void @test_vsoxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
16951 ; CHECK-LABEL: test_vsoxseg5_nxv4f16_nxv4i16:
16952 ; CHECK: # %bb.0: # %entry
16953 ; CHECK-NEXT: vmv1r.v v10, v8
16954 ; CHECK-NEXT: vmv1r.v v11, v8
16955 ; CHECK-NEXT: vmv1r.v v12, v8
16956 ; CHECK-NEXT: vmv1r.v v13, v8
16957 ; CHECK-NEXT: vmv1r.v v14, v8
16958 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16959 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
16960 ; CHECK-NEXT: ret
16961 entry:
16962 tail call void @llvm.riscv.vsoxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
16963 ret void
16964 }
16966 define void @test_vsoxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
16967 ; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_nxv4i16:
16968 ; CHECK: # %bb.0: # %entry
16969 ; CHECK-NEXT: vmv1r.v v10, v8
16970 ; CHECK-NEXT: vmv1r.v v11, v8
16971 ; CHECK-NEXT: vmv1r.v v12, v8
16972 ; CHECK-NEXT: vmv1r.v v13, v8
16973 ; CHECK-NEXT: vmv1r.v v14, v8
16974 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16975 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
16976 ; CHECK-NEXT: ret
16977 entry:
16978 tail call void @llvm.riscv.vsoxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
16979 ret void
16980 }
16982 declare void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
16983 declare void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
16985 define void @test_vsoxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
16986 ; CHECK-LABEL: test_vsoxseg6_nxv4f16_nxv4i32:
16987 ; CHECK: # %bb.0: # %entry
16988 ; CHECK-NEXT: vmv1r.v v12, v8
16989 ; CHECK-NEXT: vmv1r.v v13, v8
16990 ; CHECK-NEXT: vmv1r.v v14, v8
16991 ; CHECK-NEXT: vmv1r.v v15, v8
16992 ; CHECK-NEXT: vmv1r.v v16, v8
16993 ; CHECK-NEXT: vmv1r.v v17, v8
16994 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
16995 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10
16996 ; CHECK-NEXT: ret
16997 entry:
16998 tail call void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
16999 ret void
17000 }
17002 define void @test_vsoxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17003 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_nxv4i32:
17004 ; CHECK: # %bb.0: # %entry
17005 ; CHECK-NEXT: vmv1r.v v12, v8
17006 ; CHECK-NEXT: vmv1r.v v13, v8
17007 ; CHECK-NEXT: vmv1r.v v14, v8
17008 ; CHECK-NEXT: vmv1r.v v15, v8
17009 ; CHECK-NEXT: vmv1r.v v16, v8
17010 ; CHECK-NEXT: vmv1r.v v17, v8
17011 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17012 ; CHECK-NEXT: vsoxseg6ei32.v v12, (a0), v10, v0.t
17013 ; CHECK-NEXT: ret
17014 entry:
17015 tail call void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
17016 ret void
17017 }
17019 declare void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
17020 declare void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
17022 define void @test_vsoxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
17023 ; CHECK-LABEL: test_vsoxseg6_nxv4f16_nxv4i8:
17024 ; CHECK: # %bb.0: # %entry
17025 ; CHECK-NEXT: vmv1r.v v10, v8
17026 ; CHECK-NEXT: vmv1r.v v11, v8
17027 ; CHECK-NEXT: vmv1r.v v12, v8
17028 ; CHECK-NEXT: vmv1r.v v13, v8
17029 ; CHECK-NEXT: vmv1r.v v14, v8
17030 ; CHECK-NEXT: vmv1r.v v15, v8
17031 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17032 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
17033 ; CHECK-NEXT: ret
17034 entry:
17035 tail call void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
17036 ret void
17037 }
17039 define void @test_vsoxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17040 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_nxv4i8:
17041 ; CHECK: # %bb.0: # %entry
17042 ; CHECK-NEXT: vmv1r.v v10, v8
17043 ; CHECK-NEXT: vmv1r.v v11, v8
17044 ; CHECK-NEXT: vmv1r.v v12, v8
17045 ; CHECK-NEXT: vmv1r.v v13, v8
17046 ; CHECK-NEXT: vmv1r.v v14, v8
17047 ; CHECK-NEXT: vmv1r.v v15, v8
17048 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17049 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
17050 ; CHECK-NEXT: ret
17051 entry:
17052 tail call void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
17053 ret void
17054 }
17056 declare void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
17057 declare void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
17059 define void @test_vsoxseg6_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
17060 ; CHECK-LABEL: test_vsoxseg6_nxv4f16_nxv4i64:
17061 ; CHECK: # %bb.0: # %entry
17062 ; CHECK-NEXT: vmv1r.v v16, v8
17063 ; CHECK-NEXT: vmv1r.v v17, v8
17064 ; CHECK-NEXT: vmv1r.v v18, v8
17065 ; CHECK-NEXT: vmv1r.v v19, v8
17066 ; CHECK-NEXT: vmv1r.v v20, v8
17067 ; CHECK-NEXT: vmv1r.v v21, v8
17068 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17069 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12
17070 ; CHECK-NEXT: ret
17071 entry:
17072 tail call void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
17073 ret void
17074 }
17076 define void @test_vsoxseg6_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17077 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_nxv4i64:
17078 ; CHECK: # %bb.0: # %entry
17079 ; CHECK-NEXT: vmv1r.v v16, v8
17080 ; CHECK-NEXT: vmv1r.v v17, v8
17081 ; CHECK-NEXT: vmv1r.v v18, v8
17082 ; CHECK-NEXT: vmv1r.v v19, v8
17083 ; CHECK-NEXT: vmv1r.v v20, v8
17084 ; CHECK-NEXT: vmv1r.v v21, v8
17085 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17086 ; CHECK-NEXT: vsoxseg6ei64.v v16, (a0), v12, v0.t
17087 ; CHECK-NEXT: ret
17088 entry:
17089 tail call void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
17090 ret void
17091 }
17093 declare void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
17094 declare void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
17096 define void @test_vsoxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
17097 ; CHECK-LABEL: test_vsoxseg6_nxv4f16_nxv4i16:
17098 ; CHECK: # %bb.0: # %entry
17099 ; CHECK-NEXT: vmv1r.v v10, v8
17100 ; CHECK-NEXT: vmv1r.v v11, v8
17101 ; CHECK-NEXT: vmv1r.v v12, v8
17102 ; CHECK-NEXT: vmv1r.v v13, v8
17103 ; CHECK-NEXT: vmv1r.v v14, v8
17104 ; CHECK-NEXT: vmv1r.v v15, v8
17105 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17106 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
17107 ; CHECK-NEXT: ret
17108 entry:
17109 tail call void @llvm.riscv.vsoxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
17110 ret void
17111 }
17113 define void @test_vsoxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17114 ; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_nxv4i16:
17115 ; CHECK: # %bb.0: # %entry
17116 ; CHECK-NEXT: vmv1r.v v10, v8
17117 ; CHECK-NEXT: vmv1r.v v11, v8
17118 ; CHECK-NEXT: vmv1r.v v12, v8
17119 ; CHECK-NEXT: vmv1r.v v13, v8
17120 ; CHECK-NEXT: vmv1r.v v14, v8
17121 ; CHECK-NEXT: vmv1r.v v15, v8
17122 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17123 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
17124 ; CHECK-NEXT: ret
17125 entry:
17126 tail call void @llvm.riscv.vsoxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
17127 ret void
17128 }
17130 declare void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
17131 declare void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
17133 define void @test_vsoxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
17134 ; CHECK-LABEL: test_vsoxseg7_nxv4f16_nxv4i32:
17135 ; CHECK: # %bb.0: # %entry
17136 ; CHECK-NEXT: vmv1r.v v12, v8
17137 ; CHECK-NEXT: vmv1r.v v13, v8
17138 ; CHECK-NEXT: vmv1r.v v14, v8
17139 ; CHECK-NEXT: vmv1r.v v15, v8
17140 ; CHECK-NEXT: vmv1r.v v16, v8
17141 ; CHECK-NEXT: vmv1r.v v17, v8
17142 ; CHECK-NEXT: vmv1r.v v18, v8
17143 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17144 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10
17145 ; CHECK-NEXT: ret
17146 entry:
17147 tail call void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
17148 ret void
17149 }
17151 define void @test_vsoxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17152 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_nxv4i32:
17153 ; CHECK: # %bb.0: # %entry
17154 ; CHECK-NEXT: vmv1r.v v12, v8
17155 ; CHECK-NEXT: vmv1r.v v13, v8
17156 ; CHECK-NEXT: vmv1r.v v14, v8
17157 ; CHECK-NEXT: vmv1r.v v15, v8
17158 ; CHECK-NEXT: vmv1r.v v16, v8
17159 ; CHECK-NEXT: vmv1r.v v17, v8
17160 ; CHECK-NEXT: vmv1r.v v18, v8
17161 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17162 ; CHECK-NEXT: vsoxseg7ei32.v v12, (a0), v10, v0.t
17163 ; CHECK-NEXT: ret
17164 entry:
17165 tail call void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
17166 ret void
17167 }
17169 declare void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
17170 declare void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
17172 define void @test_vsoxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
17173 ; CHECK-LABEL: test_vsoxseg7_nxv4f16_nxv4i8:
17174 ; CHECK: # %bb.0: # %entry
17175 ; CHECK-NEXT: vmv1r.v v10, v8
17176 ; CHECK-NEXT: vmv1r.v v11, v8
17177 ; CHECK-NEXT: vmv1r.v v12, v8
17178 ; CHECK-NEXT: vmv1r.v v13, v8
17179 ; CHECK-NEXT: vmv1r.v v14, v8
17180 ; CHECK-NEXT: vmv1r.v v15, v8
17181 ; CHECK-NEXT: vmv1r.v v16, v8
17182 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17183 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
17184 ; CHECK-NEXT: ret
17185 entry:
17186 tail call void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
17187 ret void
17188 }
17190 define void @test_vsoxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17191 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_nxv4i8:
17192 ; CHECK: # %bb.0: # %entry
17193 ; CHECK-NEXT: vmv1r.v v10, v8
17194 ; CHECK-NEXT: vmv1r.v v11, v8
17195 ; CHECK-NEXT: vmv1r.v v12, v8
17196 ; CHECK-NEXT: vmv1r.v v13, v8
17197 ; CHECK-NEXT: vmv1r.v v14, v8
17198 ; CHECK-NEXT: vmv1r.v v15, v8
17199 ; CHECK-NEXT: vmv1r.v v16, v8
17200 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17201 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
17202 ; CHECK-NEXT: ret
17203 entry:
17204 tail call void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
17205 ret void
17206 }
17208 declare void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
17209 declare void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
17211 define void @test_vsoxseg7_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
17212 ; CHECK-LABEL: test_vsoxseg7_nxv4f16_nxv4i64:
17213 ; CHECK: # %bb.0: # %entry
17214 ; CHECK-NEXT: vmv1r.v v16, v8
17215 ; CHECK-NEXT: vmv1r.v v17, v8
17216 ; CHECK-NEXT: vmv1r.v v18, v8
17217 ; CHECK-NEXT: vmv1r.v v19, v8
17218 ; CHECK-NEXT: vmv1r.v v20, v8
17219 ; CHECK-NEXT: vmv1r.v v21, v8
17220 ; CHECK-NEXT: vmv1r.v v22, v8
17221 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17222 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12
17223 ; CHECK-NEXT: ret
17224 entry:
17225 tail call void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
17226 ret void
17227 }
17229 define void @test_vsoxseg7_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17230 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_nxv4i64:
17231 ; CHECK: # %bb.0: # %entry
17232 ; CHECK-NEXT: vmv1r.v v16, v8
17233 ; CHECK-NEXT: vmv1r.v v17, v8
17234 ; CHECK-NEXT: vmv1r.v v18, v8
17235 ; CHECK-NEXT: vmv1r.v v19, v8
17236 ; CHECK-NEXT: vmv1r.v v20, v8
17237 ; CHECK-NEXT: vmv1r.v v21, v8
17238 ; CHECK-NEXT: vmv1r.v v22, v8
17239 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17240 ; CHECK-NEXT: vsoxseg7ei64.v v16, (a0), v12, v0.t
17241 ; CHECK-NEXT: ret
17242 entry:
17243 tail call void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
17244 ret void
17245 }
17247 declare void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
17248 declare void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
17250 define void @test_vsoxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
17251 ; CHECK-LABEL: test_vsoxseg7_nxv4f16_nxv4i16:
17252 ; CHECK: # %bb.0: # %entry
17253 ; CHECK-NEXT: vmv1r.v v10, v8
17254 ; CHECK-NEXT: vmv1r.v v11, v8
17255 ; CHECK-NEXT: vmv1r.v v12, v8
17256 ; CHECK-NEXT: vmv1r.v v13, v8
17257 ; CHECK-NEXT: vmv1r.v v14, v8
17258 ; CHECK-NEXT: vmv1r.v v15, v8
17259 ; CHECK-NEXT: vmv1r.v v16, v8
17260 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17261 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
17262 ; CHECK-NEXT: ret
17263 entry:
17264 tail call void @llvm.riscv.vsoxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
17265 ret void
17266 }
17268 define void @test_vsoxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17269 ; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_nxv4i16:
17270 ; CHECK: # %bb.0: # %entry
17271 ; CHECK-NEXT: vmv1r.v v10, v8
17272 ; CHECK-NEXT: vmv1r.v v11, v8
17273 ; CHECK-NEXT: vmv1r.v v12, v8
17274 ; CHECK-NEXT: vmv1r.v v13, v8
17275 ; CHECK-NEXT: vmv1r.v v14, v8
17276 ; CHECK-NEXT: vmv1r.v v15, v8
17277 ; CHECK-NEXT: vmv1r.v v16, v8
17278 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17279 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
17280 ; CHECK-NEXT: ret
17281 entry:
17282 tail call void @llvm.riscv.vsoxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
17283 ret void
17284 }
17286 declare void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, i64)
17287 declare void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
17289 define void @test_vsoxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
17290 ; CHECK-LABEL: test_vsoxseg8_nxv4f16_nxv4i32:
17291 ; CHECK: # %bb.0: # %entry
17292 ; CHECK-NEXT: vmv1r.v v12, v8
17293 ; CHECK-NEXT: vmv1r.v v13, v8
17294 ; CHECK-NEXT: vmv1r.v v14, v8
17295 ; CHECK-NEXT: vmv1r.v v15, v8
17296 ; CHECK-NEXT: vmv1r.v v16, v8
17297 ; CHECK-NEXT: vmv1r.v v17, v8
17298 ; CHECK-NEXT: vmv1r.v v18, v8
17299 ; CHECK-NEXT: vmv1r.v v19, v8
17300 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17301 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10
17302 ; CHECK-NEXT: ret
17303 entry:
17304 tail call void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
17305 ret void
17306 }
17308 define void @test_vsoxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17309 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_nxv4i32:
17310 ; CHECK: # %bb.0: # %entry
17311 ; CHECK-NEXT: vmv1r.v v12, v8
17312 ; CHECK-NEXT: vmv1r.v v13, v8
17313 ; CHECK-NEXT: vmv1r.v v14, v8
17314 ; CHECK-NEXT: vmv1r.v v15, v8
17315 ; CHECK-NEXT: vmv1r.v v16, v8
17316 ; CHECK-NEXT: vmv1r.v v17, v8
17317 ; CHECK-NEXT: vmv1r.v v18, v8
17318 ; CHECK-NEXT: vmv1r.v v19, v8
17319 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17320 ; CHECK-NEXT: vsoxseg8ei32.v v12, (a0), v10, v0.t
17321 ; CHECK-NEXT: ret
17322 entry:
17323 tail call void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
17324 ret void
17325 }
17327 declare void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, i64)
17328 declare void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
17330 define void @test_vsoxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
17331 ; CHECK-LABEL: test_vsoxseg8_nxv4f16_nxv4i8:
17332 ; CHECK: # %bb.0: # %entry
17333 ; CHECK-NEXT: vmv1r.v v10, v8
17334 ; CHECK-NEXT: vmv1r.v v11, v8
17335 ; CHECK-NEXT: vmv1r.v v12, v8
17336 ; CHECK-NEXT: vmv1r.v v13, v8
17337 ; CHECK-NEXT: vmv1r.v v14, v8
17338 ; CHECK-NEXT: vmv1r.v v15, v8
17339 ; CHECK-NEXT: vmv1r.v v16, v8
17340 ; CHECK-NEXT: vmv1r.v v17, v8
17341 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17342 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
17343 ; CHECK-NEXT: ret
17344 entry:
17345 tail call void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
17346 ret void
17347 }
17349 define void @test_vsoxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17350 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_nxv4i8:
17351 ; CHECK: # %bb.0: # %entry
17352 ; CHECK-NEXT: vmv1r.v v10, v8
17353 ; CHECK-NEXT: vmv1r.v v11, v8
17354 ; CHECK-NEXT: vmv1r.v v12, v8
17355 ; CHECK-NEXT: vmv1r.v v13, v8
17356 ; CHECK-NEXT: vmv1r.v v14, v8
17357 ; CHECK-NEXT: vmv1r.v v15, v8
17358 ; CHECK-NEXT: vmv1r.v v16, v8
17359 ; CHECK-NEXT: vmv1r.v v17, v8
17360 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17361 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
17362 ; CHECK-NEXT: ret
17363 entry:
17364 tail call void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
17365 ret void
17366 }
17368 declare void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, i64)
17369 declare void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
17371 define void @test_vsoxseg8_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
17372 ; CHECK-LABEL: test_vsoxseg8_nxv4f16_nxv4i64:
17373 ; CHECK: # %bb.0: # %entry
17374 ; CHECK-NEXT: vmv1r.v v16, v8
17375 ; CHECK-NEXT: vmv1r.v v17, v8
17376 ; CHECK-NEXT: vmv1r.v v18, v8
17377 ; CHECK-NEXT: vmv1r.v v19, v8
17378 ; CHECK-NEXT: vmv1r.v v20, v8
17379 ; CHECK-NEXT: vmv1r.v v21, v8
17380 ; CHECK-NEXT: vmv1r.v v22, v8
17381 ; CHECK-NEXT: vmv1r.v v23, v8
17382 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17383 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12
17384 ; CHECK-NEXT: ret
17385 entry:
17386 tail call void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
17387 ret void
17388 }
17390 define void @test_vsoxseg8_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17391 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_nxv4i64:
17392 ; CHECK: # %bb.0: # %entry
17393 ; CHECK-NEXT: vmv1r.v v16, v8
17394 ; CHECK-NEXT: vmv1r.v v17, v8
17395 ; CHECK-NEXT: vmv1r.v v18, v8
17396 ; CHECK-NEXT: vmv1r.v v19, v8
17397 ; CHECK-NEXT: vmv1r.v v20, v8
17398 ; CHECK-NEXT: vmv1r.v v21, v8
17399 ; CHECK-NEXT: vmv1r.v v22, v8
17400 ; CHECK-NEXT: vmv1r.v v23, v8
17401 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17402 ; CHECK-NEXT: vsoxseg8ei64.v v16, (a0), v12, v0.t
17403 ; CHECK-NEXT: ret
17404 entry:
17405 tail call void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
17406 ret void
17407 }
17409 declare void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, i64)
17410 declare void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
17412 define void @test_vsoxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
17413 ; CHECK-LABEL: test_vsoxseg8_nxv4f16_nxv4i16:
17414 ; CHECK: # %bb.0: # %entry
17415 ; CHECK-NEXT: vmv1r.v v10, v8
17416 ; CHECK-NEXT: vmv1r.v v11, v8
17417 ; CHECK-NEXT: vmv1r.v v12, v8
17418 ; CHECK-NEXT: vmv1r.v v13, v8
17419 ; CHECK-NEXT: vmv1r.v v14, v8
17420 ; CHECK-NEXT: vmv1r.v v15, v8
17421 ; CHECK-NEXT: vmv1r.v v16, v8
17422 ; CHECK-NEXT: vmv1r.v v17, v8
17423 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17424 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
17425 ; CHECK-NEXT: ret
17426 entry:
17427 tail call void @llvm.riscv.vsoxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
17428 ret void
17429 }
17431 define void @test_vsoxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
17432 ; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_nxv4i16:
17433 ; CHECK: # %bb.0: # %entry
17434 ; CHECK-NEXT: vmv1r.v v10, v8
17435 ; CHECK-NEXT: vmv1r.v v11, v8
17436 ; CHECK-NEXT: vmv1r.v v12, v8
17437 ; CHECK-NEXT: vmv1r.v v13, v8
17438 ; CHECK-NEXT: vmv1r.v v14, v8
17439 ; CHECK-NEXT: vmv1r.v v15, v8
17440 ; CHECK-NEXT: vmv1r.v v16, v8
17441 ; CHECK-NEXT: vmv1r.v v17, v8
17442 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
17443 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
17444 ; CHECK-NEXT: ret
17445 entry:
17446 tail call void @llvm.riscv.vsoxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
17447 ret void
17448 }
17450 declare void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
17451 declare void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
17453 define void @test_vsoxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
17454 ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i32:
17455 ; CHECK: # %bb.0: # %entry
17456 ; CHECK-NEXT: vmv1r.v v10, v9
17457 ; CHECK-NEXT: vmv1r.v v9, v8
17458 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17459 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
17460 ; CHECK-NEXT: ret
17461 entry:
17462 tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
17463 ret void
17464 }
17466 define void @test_vsoxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17467 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i32:
17468 ; CHECK: # %bb.0: # %entry
17469 ; CHECK-NEXT: vmv1r.v v10, v9
17470 ; CHECK-NEXT: vmv1r.v v9, v8
17471 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17472 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
17473 ; CHECK-NEXT: ret
17474 entry:
17475 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
17476 ret void
17477 }
17479 declare void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
17480 declare void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
17482 define void @test_vsoxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
17483 ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i8:
17484 ; CHECK: # %bb.0: # %entry
17485 ; CHECK-NEXT: vmv1r.v v10, v9
17486 ; CHECK-NEXT: vmv1r.v v9, v8
17487 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17488 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
17489 ; CHECK-NEXT: ret
17490 entry:
17491 tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
17492 ret void
17493 }
17495 define void @test_vsoxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17496 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i8:
17497 ; CHECK: # %bb.0: # %entry
17498 ; CHECK-NEXT: vmv1r.v v10, v9
17499 ; CHECK-NEXT: vmv1r.v v9, v8
17500 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17501 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
17502 ; CHECK-NEXT: ret
17503 entry:
17504 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
17505 ret void
17506 }
17508 declare void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
17509 declare void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
17511 define void @test_vsoxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
17512 ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i16:
17513 ; CHECK: # %bb.0: # %entry
17514 ; CHECK-NEXT: vmv1r.v v10, v9
17515 ; CHECK-NEXT: vmv1r.v v9, v8
17516 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17517 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
17518 ; CHECK-NEXT: ret
17519 entry:
17520 tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
17521 ret void
17522 }
17524 define void @test_vsoxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17525 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i16:
17526 ; CHECK: # %bb.0: # %entry
17527 ; CHECK-NEXT: vmv1r.v v10, v9
17528 ; CHECK-NEXT: vmv1r.v v9, v8
17529 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17530 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
17531 ; CHECK-NEXT: ret
17532 entry:
17533 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
17534 ret void
17535 }
17537 declare void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
17538 declare void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
17540 define void @test_vsoxseg2_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
17541 ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i64:
17542 ; CHECK: # %bb.0: # %entry
17543 ; CHECK-NEXT: vmv1r.v v9, v8
17544 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17545 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
17546 ; CHECK-NEXT: ret
17547 entry:
17548 tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
17549 ret void
17550 }
17552 define void @test_vsoxseg2_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17553 ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i64:
17554 ; CHECK: # %bb.0: # %entry
17555 ; CHECK-NEXT: vmv1r.v v9, v8
17556 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17557 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
17558 ; CHECK-NEXT: ret
17559 entry:
17560 tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
17561 ret void
17562 }
17564 declare void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
17565 declare void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
17567 define void @test_vsoxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
17568 ; CHECK-LABEL: test_vsoxseg3_nxv2f16_nxv2i32:
17569 ; CHECK: # %bb.0: # %entry
17570 ; CHECK-NEXT: vmv1r.v v10, v8
17571 ; CHECK-NEXT: vmv1r.v v11, v8
17572 ; CHECK-NEXT: vmv1r.v v12, v8
17573 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17574 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9
17575 ; CHECK-NEXT: ret
17576 entry:
17577 tail call void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
17578 ret void
17579 }
17581 define void @test_vsoxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17582 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_nxv2i32:
17583 ; CHECK: # %bb.0: # %entry
17584 ; CHECK-NEXT: vmv1r.v v10, v8
17585 ; CHECK-NEXT: vmv1r.v v11, v8
17586 ; CHECK-NEXT: vmv1r.v v12, v8
17587 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17588 ; CHECK-NEXT: vsoxseg3ei32.v v10, (a0), v9, v0.t
17589 ; CHECK-NEXT: ret
17590 entry:
17591 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
17592 ret void
17593 }
17595 declare void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
17596 declare void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
17598 define void @test_vsoxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
17599 ; CHECK-LABEL: test_vsoxseg3_nxv2f16_nxv2i8:
17600 ; CHECK: # %bb.0: # %entry
17601 ; CHECK-NEXT: vmv1r.v v10, v8
17602 ; CHECK-NEXT: vmv1r.v v11, v8
17603 ; CHECK-NEXT: vmv1r.v v12, v8
17604 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17605 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9
17606 ; CHECK-NEXT: ret
17607 entry:
17608 tail call void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
17609 ret void
17610 }
17612 define void @test_vsoxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17613 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_nxv2i8:
17614 ; CHECK: # %bb.0: # %entry
17615 ; CHECK-NEXT: vmv1r.v v10, v8
17616 ; CHECK-NEXT: vmv1r.v v11, v8
17617 ; CHECK-NEXT: vmv1r.v v12, v8
17618 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17619 ; CHECK-NEXT: vsoxseg3ei8.v v10, (a0), v9, v0.t
17620 ; CHECK-NEXT: ret
17621 entry:
17622 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
17623 ret void
17624 }
17626 declare void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
17627 declare void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
17629 define void @test_vsoxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
17630 ; CHECK-LABEL: test_vsoxseg3_nxv2f16_nxv2i16:
17631 ; CHECK: # %bb.0: # %entry
17632 ; CHECK-NEXT: vmv1r.v v10, v8
17633 ; CHECK-NEXT: vmv1r.v v11, v8
17634 ; CHECK-NEXT: vmv1r.v v12, v8
17635 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17636 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9
17637 ; CHECK-NEXT: ret
17638 entry:
17639 tail call void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
17640 ret void
17641 }
17643 define void @test_vsoxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17644 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_nxv2i16:
17645 ; CHECK: # %bb.0: # %entry
17646 ; CHECK-NEXT: vmv1r.v v10, v8
17647 ; CHECK-NEXT: vmv1r.v v11, v8
17648 ; CHECK-NEXT: vmv1r.v v12, v8
17649 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17650 ; CHECK-NEXT: vsoxseg3ei16.v v10, (a0), v9, v0.t
17651 ; CHECK-NEXT: ret
17652 entry:
17653 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
17654 ret void
17655 }
17657 declare void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
17658 declare void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
17660 define void @test_vsoxseg3_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
17661 ; CHECK-LABEL: test_vsoxseg3_nxv2f16_nxv2i64:
17662 ; CHECK: # %bb.0: # %entry
17663 ; CHECK-NEXT: vmv1r.v v9, v8
17664 ; CHECK-NEXT: vmv2r.v v12, v10
17665 ; CHECK-NEXT: vmv1r.v v10, v8
17666 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17667 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12
17668 ; CHECK-NEXT: ret
17669 entry:
17670 tail call void @llvm.riscv.vsoxseg3.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
17671 ret void
17672 }
17674 define void @test_vsoxseg3_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17675 ; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_nxv2i64:
17676 ; CHECK: # %bb.0: # %entry
17677 ; CHECK-NEXT: vmv1r.v v9, v8
17678 ; CHECK-NEXT: vmv2r.v v12, v10
17679 ; CHECK-NEXT: vmv1r.v v10, v8
17680 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17681 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v12, v0.t
17682 ; CHECK-NEXT: ret
17683 entry:
17684 tail call void @llvm.riscv.vsoxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
17685 ret void
17686 }
17688 declare void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
17689 declare void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
17691 define void @test_vsoxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
17692 ; CHECK-LABEL: test_vsoxseg4_nxv2f16_nxv2i32:
17693 ; CHECK: # %bb.0: # %entry
17694 ; CHECK-NEXT: vmv1r.v v10, v8
17695 ; CHECK-NEXT: vmv1r.v v11, v8
17696 ; CHECK-NEXT: vmv1r.v v12, v8
17697 ; CHECK-NEXT: vmv1r.v v13, v8
17698 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17699 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9
17700 ; CHECK-NEXT: ret
17701 entry:
17702 tail call void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
17703 ret void
17704 }
17706 define void @test_vsoxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17707 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_nxv2i32:
17708 ; CHECK: # %bb.0: # %entry
17709 ; CHECK-NEXT: vmv1r.v v10, v8
17710 ; CHECK-NEXT: vmv1r.v v11, v8
17711 ; CHECK-NEXT: vmv1r.v v12, v8
17712 ; CHECK-NEXT: vmv1r.v v13, v8
17713 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17714 ; CHECK-NEXT: vsoxseg4ei32.v v10, (a0), v9, v0.t
17715 ; CHECK-NEXT: ret
17716 entry:
17717 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
17718 ret void
17719 }
17721 declare void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
17722 declare void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
17724 define void @test_vsoxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
17725 ; CHECK-LABEL: test_vsoxseg4_nxv2f16_nxv2i8:
17726 ; CHECK: # %bb.0: # %entry
17727 ; CHECK-NEXT: vmv1r.v v10, v8
17728 ; CHECK-NEXT: vmv1r.v v11, v8
17729 ; CHECK-NEXT: vmv1r.v v12, v8
17730 ; CHECK-NEXT: vmv1r.v v13, v8
17731 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17732 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9
17733 ; CHECK-NEXT: ret
17734 entry:
17735 tail call void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
17736 ret void
17737 }
17739 define void @test_vsoxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17740 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_nxv2i8:
17741 ; CHECK: # %bb.0: # %entry
17742 ; CHECK-NEXT: vmv1r.v v10, v8
17743 ; CHECK-NEXT: vmv1r.v v11, v8
17744 ; CHECK-NEXT: vmv1r.v v12, v8
17745 ; CHECK-NEXT: vmv1r.v v13, v8
17746 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17747 ; CHECK-NEXT: vsoxseg4ei8.v v10, (a0), v9, v0.t
17748 ; CHECK-NEXT: ret
17749 entry:
17750 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
17751 ret void
17752 }
17754 declare void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
17755 declare void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
17757 define void @test_vsoxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
17758 ; CHECK-LABEL: test_vsoxseg4_nxv2f16_nxv2i16:
17759 ; CHECK: # %bb.0: # %entry
17760 ; CHECK-NEXT: vmv1r.v v10, v8
17761 ; CHECK-NEXT: vmv1r.v v11, v8
17762 ; CHECK-NEXT: vmv1r.v v12, v8
17763 ; CHECK-NEXT: vmv1r.v v13, v8
17764 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17765 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9
17766 ; CHECK-NEXT: ret
17767 entry:
17768 tail call void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
17769 ret void
17770 }
17772 define void @test_vsoxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17773 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_nxv2i16:
17774 ; CHECK: # %bb.0: # %entry
17775 ; CHECK-NEXT: vmv1r.v v10, v8
17776 ; CHECK-NEXT: vmv1r.v v11, v8
17777 ; CHECK-NEXT: vmv1r.v v12, v8
17778 ; CHECK-NEXT: vmv1r.v v13, v8
17779 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17780 ; CHECK-NEXT: vsoxseg4ei16.v v10, (a0), v9, v0.t
17781 ; CHECK-NEXT: ret
17782 entry:
17783 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
17784 ret void
17785 }
17787 declare void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
17788 declare void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
17790 define void @test_vsoxseg4_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
17791 ; CHECK-LABEL: test_vsoxseg4_nxv2f16_nxv2i64:
17792 ; CHECK: # %bb.0: # %entry
17793 ; CHECK-NEXT: vmv1r.v v12, v8
17794 ; CHECK-NEXT: vmv1r.v v13, v8
17795 ; CHECK-NEXT: vmv1r.v v14, v8
17796 ; CHECK-NEXT: vmv1r.v v15, v8
17797 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17798 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10
17799 ; CHECK-NEXT: ret
17800 entry:
17801 tail call void @llvm.riscv.vsoxseg4.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
17802 ret void
17803 }
17805 define void @test_vsoxseg4_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17806 ; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_nxv2i64:
17807 ; CHECK: # %bb.0: # %entry
17808 ; CHECK-NEXT: vmv1r.v v12, v8
17809 ; CHECK-NEXT: vmv1r.v v13, v8
17810 ; CHECK-NEXT: vmv1r.v v14, v8
17811 ; CHECK-NEXT: vmv1r.v v15, v8
17812 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17813 ; CHECK-NEXT: vsoxseg4ei64.v v12, (a0), v10, v0.t
17814 ; CHECK-NEXT: ret
17815 entry:
17816 tail call void @llvm.riscv.vsoxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
17817 ret void
17818 }
17820 declare void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
17821 declare void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
17823 define void @test_vsoxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
17824 ; CHECK-LABEL: test_vsoxseg5_nxv2f16_nxv2i32:
17825 ; CHECK: # %bb.0: # %entry
17826 ; CHECK-NEXT: vmv1r.v v10, v8
17827 ; CHECK-NEXT: vmv1r.v v11, v8
17828 ; CHECK-NEXT: vmv1r.v v12, v8
17829 ; CHECK-NEXT: vmv1r.v v13, v8
17830 ; CHECK-NEXT: vmv1r.v v14, v8
17831 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17832 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9
17833 ; CHECK-NEXT: ret
17834 entry:
17835 tail call void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
17836 ret void
17837 }
17839 define void @test_vsoxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17840 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_nxv2i32:
17841 ; CHECK: # %bb.0: # %entry
17842 ; CHECK-NEXT: vmv1r.v v10, v8
17843 ; CHECK-NEXT: vmv1r.v v11, v8
17844 ; CHECK-NEXT: vmv1r.v v12, v8
17845 ; CHECK-NEXT: vmv1r.v v13, v8
17846 ; CHECK-NEXT: vmv1r.v v14, v8
17847 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17848 ; CHECK-NEXT: vsoxseg5ei32.v v10, (a0), v9, v0.t
17849 ; CHECK-NEXT: ret
17850 entry:
17851 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
17852 ret void
17853 }
17855 declare void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
17856 declare void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
17858 define void @test_vsoxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
17859 ; CHECK-LABEL: test_vsoxseg5_nxv2f16_nxv2i8:
17860 ; CHECK: # %bb.0: # %entry
17861 ; CHECK-NEXT: vmv1r.v v10, v8
17862 ; CHECK-NEXT: vmv1r.v v11, v8
17863 ; CHECK-NEXT: vmv1r.v v12, v8
17864 ; CHECK-NEXT: vmv1r.v v13, v8
17865 ; CHECK-NEXT: vmv1r.v v14, v8
17866 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17867 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9
17868 ; CHECK-NEXT: ret
17869 entry:
17870 tail call void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
17871 ret void
17872 }
17874 define void @test_vsoxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17875 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_nxv2i8:
17876 ; CHECK: # %bb.0: # %entry
17877 ; CHECK-NEXT: vmv1r.v v10, v8
17878 ; CHECK-NEXT: vmv1r.v v11, v8
17879 ; CHECK-NEXT: vmv1r.v v12, v8
17880 ; CHECK-NEXT: vmv1r.v v13, v8
17881 ; CHECK-NEXT: vmv1r.v v14, v8
17882 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17883 ; CHECK-NEXT: vsoxseg5ei8.v v10, (a0), v9, v0.t
17884 ; CHECK-NEXT: ret
17885 entry:
17886 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
17887 ret void
17888 }
17890 declare void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
17891 declare void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
17893 define void @test_vsoxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
17894 ; CHECK-LABEL: test_vsoxseg5_nxv2f16_nxv2i16:
17895 ; CHECK: # %bb.0: # %entry
17896 ; CHECK-NEXT: vmv1r.v v10, v8
17897 ; CHECK-NEXT: vmv1r.v v11, v8
17898 ; CHECK-NEXT: vmv1r.v v12, v8
17899 ; CHECK-NEXT: vmv1r.v v13, v8
17900 ; CHECK-NEXT: vmv1r.v v14, v8
17901 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17902 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9
17903 ; CHECK-NEXT: ret
17904 entry:
17905 tail call void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
17906 ret void
17907 }
17909 define void @test_vsoxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17910 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_nxv2i16:
17911 ; CHECK: # %bb.0: # %entry
17912 ; CHECK-NEXT: vmv1r.v v10, v8
17913 ; CHECK-NEXT: vmv1r.v v11, v8
17914 ; CHECK-NEXT: vmv1r.v v12, v8
17915 ; CHECK-NEXT: vmv1r.v v13, v8
17916 ; CHECK-NEXT: vmv1r.v v14, v8
17917 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17918 ; CHECK-NEXT: vsoxseg5ei16.v v10, (a0), v9, v0.t
17919 ; CHECK-NEXT: ret
17920 entry:
17921 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
17922 ret void
17923 }
17925 declare void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
17926 declare void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
17928 define void @test_vsoxseg5_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
17929 ; CHECK-LABEL: test_vsoxseg5_nxv2f16_nxv2i64:
17930 ; CHECK: # %bb.0: # %entry
17931 ; CHECK-NEXT: vmv1r.v v12, v8
17932 ; CHECK-NEXT: vmv1r.v v13, v8
17933 ; CHECK-NEXT: vmv1r.v v14, v8
17934 ; CHECK-NEXT: vmv1r.v v15, v8
17935 ; CHECK-NEXT: vmv1r.v v16, v8
17936 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17937 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10
17938 ; CHECK-NEXT: ret
17939 entry:
17940 tail call void @llvm.riscv.vsoxseg5.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
17941 ret void
17942 }
17944 define void @test_vsoxseg5_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17945 ; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_nxv2i64:
17946 ; CHECK: # %bb.0: # %entry
17947 ; CHECK-NEXT: vmv1r.v v12, v8
17948 ; CHECK-NEXT: vmv1r.v v13, v8
17949 ; CHECK-NEXT: vmv1r.v v14, v8
17950 ; CHECK-NEXT: vmv1r.v v15, v8
17951 ; CHECK-NEXT: vmv1r.v v16, v8
17952 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17953 ; CHECK-NEXT: vsoxseg5ei64.v v12, (a0), v10, v0.t
17954 ; CHECK-NEXT: ret
17955 entry:
17956 tail call void @llvm.riscv.vsoxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
17957 ret void
17958 }
17960 declare void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
17961 declare void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
17963 define void @test_vsoxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
17964 ; CHECK-LABEL: test_vsoxseg6_nxv2f16_nxv2i32:
17965 ; CHECK: # %bb.0: # %entry
17966 ; CHECK-NEXT: vmv1r.v v10, v8
17967 ; CHECK-NEXT: vmv1r.v v11, v8
17968 ; CHECK-NEXT: vmv1r.v v12, v8
17969 ; CHECK-NEXT: vmv1r.v v13, v8
17970 ; CHECK-NEXT: vmv1r.v v14, v8
17971 ; CHECK-NEXT: vmv1r.v v15, v8
17972 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17973 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9
17974 ; CHECK-NEXT: ret
17975 entry:
17976 tail call void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
17977 ret void
17978 }
17980 define void @test_vsoxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
17981 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_nxv2i32:
17982 ; CHECK: # %bb.0: # %entry
17983 ; CHECK-NEXT: vmv1r.v v10, v8
17984 ; CHECK-NEXT: vmv1r.v v11, v8
17985 ; CHECK-NEXT: vmv1r.v v12, v8
17986 ; CHECK-NEXT: vmv1r.v v13, v8
17987 ; CHECK-NEXT: vmv1r.v v14, v8
17988 ; CHECK-NEXT: vmv1r.v v15, v8
17989 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
17990 ; CHECK-NEXT: vsoxseg6ei32.v v10, (a0), v9, v0.t
17991 ; CHECK-NEXT: ret
17992 entry:
17993 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
17994 ret void
17995 }
17997 declare void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
17998 declare void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
18000 define void @test_vsoxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
18001 ; CHECK-LABEL: test_vsoxseg6_nxv2f16_nxv2i8:
18002 ; CHECK: # %bb.0: # %entry
18003 ; CHECK-NEXT: vmv1r.v v10, v8
18004 ; CHECK-NEXT: vmv1r.v v11, v8
18005 ; CHECK-NEXT: vmv1r.v v12, v8
18006 ; CHECK-NEXT: vmv1r.v v13, v8
18007 ; CHECK-NEXT: vmv1r.v v14, v8
18008 ; CHECK-NEXT: vmv1r.v v15, v8
18009 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18010 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9
18011 ; CHECK-NEXT: ret
18012 entry:
18013 tail call void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
18014 ret void
18015 }
18017 define void @test_vsoxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18018 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_nxv2i8:
18019 ; CHECK: # %bb.0: # %entry
18020 ; CHECK-NEXT: vmv1r.v v10, v8
18021 ; CHECK-NEXT: vmv1r.v v11, v8
18022 ; CHECK-NEXT: vmv1r.v v12, v8
18023 ; CHECK-NEXT: vmv1r.v v13, v8
18024 ; CHECK-NEXT: vmv1r.v v14, v8
18025 ; CHECK-NEXT: vmv1r.v v15, v8
18026 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18027 ; CHECK-NEXT: vsoxseg6ei8.v v10, (a0), v9, v0.t
18028 ; CHECK-NEXT: ret
18029 entry:
18030 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
18031 ret void
18032 }
18034 declare void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
18035 declare void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
18037 define void @test_vsoxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
18038 ; CHECK-LABEL: test_vsoxseg6_nxv2f16_nxv2i16:
18039 ; CHECK: # %bb.0: # %entry
18040 ; CHECK-NEXT: vmv1r.v v10, v8
18041 ; CHECK-NEXT: vmv1r.v v11, v8
18042 ; CHECK-NEXT: vmv1r.v v12, v8
18043 ; CHECK-NEXT: vmv1r.v v13, v8
18044 ; CHECK-NEXT: vmv1r.v v14, v8
18045 ; CHECK-NEXT: vmv1r.v v15, v8
18046 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18047 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9
18048 ; CHECK-NEXT: ret
18049 entry:
18050 tail call void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
18051 ret void
18052 }
18054 define void @test_vsoxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18055 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_nxv2i16:
18056 ; CHECK: # %bb.0: # %entry
18057 ; CHECK-NEXT: vmv1r.v v10, v8
18058 ; CHECK-NEXT: vmv1r.v v11, v8
18059 ; CHECK-NEXT: vmv1r.v v12, v8
18060 ; CHECK-NEXT: vmv1r.v v13, v8
18061 ; CHECK-NEXT: vmv1r.v v14, v8
18062 ; CHECK-NEXT: vmv1r.v v15, v8
18063 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18064 ; CHECK-NEXT: vsoxseg6ei16.v v10, (a0), v9, v0.t
18065 ; CHECK-NEXT: ret
18066 entry:
18067 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
18068 ret void
18069 }
18071 declare void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
18072 declare void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
18074 define void @test_vsoxseg6_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
18075 ; CHECK-LABEL: test_vsoxseg6_nxv2f16_nxv2i64:
18076 ; CHECK: # %bb.0: # %entry
18077 ; CHECK-NEXT: vmv1r.v v12, v8
18078 ; CHECK-NEXT: vmv1r.v v13, v8
18079 ; CHECK-NEXT: vmv1r.v v14, v8
18080 ; CHECK-NEXT: vmv1r.v v15, v8
18081 ; CHECK-NEXT: vmv1r.v v16, v8
18082 ; CHECK-NEXT: vmv1r.v v17, v8
18083 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18084 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10
18085 ; CHECK-NEXT: ret
18086 entry:
18087 tail call void @llvm.riscv.vsoxseg6.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
18088 ret void
18089 }
18091 define void @test_vsoxseg6_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18092 ; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_nxv2i64:
18093 ; CHECK: # %bb.0: # %entry
18094 ; CHECK-NEXT: vmv1r.v v12, v8
18095 ; CHECK-NEXT: vmv1r.v v13, v8
18096 ; CHECK-NEXT: vmv1r.v v14, v8
18097 ; CHECK-NEXT: vmv1r.v v15, v8
18098 ; CHECK-NEXT: vmv1r.v v16, v8
18099 ; CHECK-NEXT: vmv1r.v v17, v8
18100 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18101 ; CHECK-NEXT: vsoxseg6ei64.v v12, (a0), v10, v0.t
18102 ; CHECK-NEXT: ret
18103 entry:
18104 tail call void @llvm.riscv.vsoxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
18105 ret void
18106 }
18108 declare void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
18109 declare void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
18111 define void @test_vsoxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
18112 ; CHECK-LABEL: test_vsoxseg7_nxv2f16_nxv2i32:
18113 ; CHECK: # %bb.0: # %entry
18114 ; CHECK-NEXT: vmv1r.v v10, v8
18115 ; CHECK-NEXT: vmv1r.v v11, v8
18116 ; CHECK-NEXT: vmv1r.v v12, v8
18117 ; CHECK-NEXT: vmv1r.v v13, v8
18118 ; CHECK-NEXT: vmv1r.v v14, v8
18119 ; CHECK-NEXT: vmv1r.v v15, v8
18120 ; CHECK-NEXT: vmv1r.v v16, v8
18121 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18122 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9
18123 ; CHECK-NEXT: ret
18124 entry:
18125 tail call void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
18126 ret void
18127 }
18129 define void @test_vsoxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18130 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_nxv2i32:
18131 ; CHECK: # %bb.0: # %entry
18132 ; CHECK-NEXT: vmv1r.v v10, v8
18133 ; CHECK-NEXT: vmv1r.v v11, v8
18134 ; CHECK-NEXT: vmv1r.v v12, v8
18135 ; CHECK-NEXT: vmv1r.v v13, v8
18136 ; CHECK-NEXT: vmv1r.v v14, v8
18137 ; CHECK-NEXT: vmv1r.v v15, v8
18138 ; CHECK-NEXT: vmv1r.v v16, v8
18139 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18140 ; CHECK-NEXT: vsoxseg7ei32.v v10, (a0), v9, v0.t
18141 ; CHECK-NEXT: ret
18142 entry:
18143 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
18144 ret void
18145 }
18147 declare void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
18148 declare void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
18150 define void @test_vsoxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
18151 ; CHECK-LABEL: test_vsoxseg7_nxv2f16_nxv2i8:
18152 ; CHECK: # %bb.0: # %entry
18153 ; CHECK-NEXT: vmv1r.v v10, v8
18154 ; CHECK-NEXT: vmv1r.v v11, v8
18155 ; CHECK-NEXT: vmv1r.v v12, v8
18156 ; CHECK-NEXT: vmv1r.v v13, v8
18157 ; CHECK-NEXT: vmv1r.v v14, v8
18158 ; CHECK-NEXT: vmv1r.v v15, v8
18159 ; CHECK-NEXT: vmv1r.v v16, v8
18160 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18161 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9
18162 ; CHECK-NEXT: ret
18163 entry:
18164 tail call void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
18165 ret void
18166 }
18168 define void @test_vsoxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18169 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_nxv2i8:
18170 ; CHECK: # %bb.0: # %entry
18171 ; CHECK-NEXT: vmv1r.v v10, v8
18172 ; CHECK-NEXT: vmv1r.v v11, v8
18173 ; CHECK-NEXT: vmv1r.v v12, v8
18174 ; CHECK-NEXT: vmv1r.v v13, v8
18175 ; CHECK-NEXT: vmv1r.v v14, v8
18176 ; CHECK-NEXT: vmv1r.v v15, v8
18177 ; CHECK-NEXT: vmv1r.v v16, v8
18178 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18179 ; CHECK-NEXT: vsoxseg7ei8.v v10, (a0), v9, v0.t
18180 ; CHECK-NEXT: ret
18181 entry:
18182 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
18183 ret void
18184 }
18186 declare void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
18187 declare void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
18189 define void @test_vsoxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
18190 ; CHECK-LABEL: test_vsoxseg7_nxv2f16_nxv2i16:
18191 ; CHECK: # %bb.0: # %entry
18192 ; CHECK-NEXT: vmv1r.v v10, v8
18193 ; CHECK-NEXT: vmv1r.v v11, v8
18194 ; CHECK-NEXT: vmv1r.v v12, v8
18195 ; CHECK-NEXT: vmv1r.v v13, v8
18196 ; CHECK-NEXT: vmv1r.v v14, v8
18197 ; CHECK-NEXT: vmv1r.v v15, v8
18198 ; CHECK-NEXT: vmv1r.v v16, v8
18199 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18200 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9
18201 ; CHECK-NEXT: ret
18202 entry:
18203 tail call void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
18204 ret void
18205 }
18207 define void @test_vsoxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18208 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_nxv2i16:
18209 ; CHECK: # %bb.0: # %entry
18210 ; CHECK-NEXT: vmv1r.v v10, v8
18211 ; CHECK-NEXT: vmv1r.v v11, v8
18212 ; CHECK-NEXT: vmv1r.v v12, v8
18213 ; CHECK-NEXT: vmv1r.v v13, v8
18214 ; CHECK-NEXT: vmv1r.v v14, v8
18215 ; CHECK-NEXT: vmv1r.v v15, v8
18216 ; CHECK-NEXT: vmv1r.v v16, v8
18217 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18218 ; CHECK-NEXT: vsoxseg7ei16.v v10, (a0), v9, v0.t
18219 ; CHECK-NEXT: ret
18220 entry:
18221 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
18222 ret void
18223 }
18225 declare void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
18226 declare void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
18228 define void @test_vsoxseg7_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
18229 ; CHECK-LABEL: test_vsoxseg7_nxv2f16_nxv2i64:
18230 ; CHECK: # %bb.0: # %entry
18231 ; CHECK-NEXT: vmv1r.v v12, v8
18232 ; CHECK-NEXT: vmv1r.v v13, v8
18233 ; CHECK-NEXT: vmv1r.v v14, v8
18234 ; CHECK-NEXT: vmv1r.v v15, v8
18235 ; CHECK-NEXT: vmv1r.v v16, v8
18236 ; CHECK-NEXT: vmv1r.v v17, v8
18237 ; CHECK-NEXT: vmv1r.v v18, v8
18238 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18239 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10
18240 ; CHECK-NEXT: ret
18241 entry:
18242 tail call void @llvm.riscv.vsoxseg7.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
18243 ret void
18244 }
18246 define void @test_vsoxseg7_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18247 ; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_nxv2i64:
18248 ; CHECK: # %bb.0: # %entry
18249 ; CHECK-NEXT: vmv1r.v v12, v8
18250 ; CHECK-NEXT: vmv1r.v v13, v8
18251 ; CHECK-NEXT: vmv1r.v v14, v8
18252 ; CHECK-NEXT: vmv1r.v v15, v8
18253 ; CHECK-NEXT: vmv1r.v v16, v8
18254 ; CHECK-NEXT: vmv1r.v v17, v8
18255 ; CHECK-NEXT: vmv1r.v v18, v8
18256 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18257 ; CHECK-NEXT: vsoxseg7ei64.v v12, (a0), v10, v0.t
18258 ; CHECK-NEXT: ret
18259 entry:
18260 tail call void @llvm.riscv.vsoxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
18261 ret void
18262 }
18264 declare void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, i64)
18265 declare void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
18267 define void @test_vsoxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {
18268 ; CHECK-LABEL: test_vsoxseg8_nxv2f16_nxv2i32:
18269 ; CHECK: # %bb.0: # %entry
18270 ; CHECK-NEXT: vmv1r.v v10, v8
18271 ; CHECK-NEXT: vmv1r.v v11, v8
18272 ; CHECK-NEXT: vmv1r.v v12, v8
18273 ; CHECK-NEXT: vmv1r.v v13, v8
18274 ; CHECK-NEXT: vmv1r.v v14, v8
18275 ; CHECK-NEXT: vmv1r.v v15, v8
18276 ; CHECK-NEXT: vmv1r.v v16, v8
18277 ; CHECK-NEXT: vmv1r.v v17, v8
18278 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18279 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9
18280 ; CHECK-NEXT: ret
18281 entry:
18282 tail call void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl)
18283 ret void
18284 }
18286 define void @test_vsoxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18287 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_nxv2i32:
18288 ; CHECK: # %bb.0: # %entry
18289 ; CHECK-NEXT: vmv1r.v v10, v8
18290 ; CHECK-NEXT: vmv1r.v v11, v8
18291 ; CHECK-NEXT: vmv1r.v v12, v8
18292 ; CHECK-NEXT: vmv1r.v v13, v8
18293 ; CHECK-NEXT: vmv1r.v v14, v8
18294 ; CHECK-NEXT: vmv1r.v v15, v8
18295 ; CHECK-NEXT: vmv1r.v v16, v8
18296 ; CHECK-NEXT: vmv1r.v v17, v8
18297 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18298 ; CHECK-NEXT: vsoxseg8ei32.v v10, (a0), v9, v0.t
18299 ; CHECK-NEXT: ret
18300 entry:
18301 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
18302 ret void
18303 }
18305 declare void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, i64)
18306 declare void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
18308 define void @test_vsoxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {
18309 ; CHECK-LABEL: test_vsoxseg8_nxv2f16_nxv2i8:
18310 ; CHECK: # %bb.0: # %entry
18311 ; CHECK-NEXT: vmv1r.v v10, v8
18312 ; CHECK-NEXT: vmv1r.v v11, v8
18313 ; CHECK-NEXT: vmv1r.v v12, v8
18314 ; CHECK-NEXT: vmv1r.v v13, v8
18315 ; CHECK-NEXT: vmv1r.v v14, v8
18316 ; CHECK-NEXT: vmv1r.v v15, v8
18317 ; CHECK-NEXT: vmv1r.v v16, v8
18318 ; CHECK-NEXT: vmv1r.v v17, v8
18319 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18320 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9
18321 ; CHECK-NEXT: ret
18322 entry:
18323 tail call void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl)
18324 ret void
18325 }
18327 define void @test_vsoxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18328 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_nxv2i8:
18329 ; CHECK: # %bb.0: # %entry
18330 ; CHECK-NEXT: vmv1r.v v10, v8
18331 ; CHECK-NEXT: vmv1r.v v11, v8
18332 ; CHECK-NEXT: vmv1r.v v12, v8
18333 ; CHECK-NEXT: vmv1r.v v13, v8
18334 ; CHECK-NEXT: vmv1r.v v14, v8
18335 ; CHECK-NEXT: vmv1r.v v15, v8
18336 ; CHECK-NEXT: vmv1r.v v16, v8
18337 ; CHECK-NEXT: vmv1r.v v17, v8
18338 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18339 ; CHECK-NEXT: vsoxseg8ei8.v v10, (a0), v9, v0.t
18340 ; CHECK-NEXT: ret
18341 entry:
18342 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
18343 ret void
18344 }
18346 declare void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, i64)
18347 declare void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
18349 define void @test_vsoxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {
18350 ; CHECK-LABEL: test_vsoxseg8_nxv2f16_nxv2i16:
18351 ; CHECK: # %bb.0: # %entry
18352 ; CHECK-NEXT: vmv1r.v v10, v8
18353 ; CHECK-NEXT: vmv1r.v v11, v8
18354 ; CHECK-NEXT: vmv1r.v v12, v8
18355 ; CHECK-NEXT: vmv1r.v v13, v8
18356 ; CHECK-NEXT: vmv1r.v v14, v8
18357 ; CHECK-NEXT: vmv1r.v v15, v8
18358 ; CHECK-NEXT: vmv1r.v v16, v8
18359 ; CHECK-NEXT: vmv1r.v v17, v8
18360 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18361 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9
18362 ; CHECK-NEXT: ret
18363 entry:
18364 tail call void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl)
18365 ret void
18366 }
18368 define void @test_vsoxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18369 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_nxv2i16:
18370 ; CHECK: # %bb.0: # %entry
18371 ; CHECK-NEXT: vmv1r.v v10, v8
18372 ; CHECK-NEXT: vmv1r.v v11, v8
18373 ; CHECK-NEXT: vmv1r.v v12, v8
18374 ; CHECK-NEXT: vmv1r.v v13, v8
18375 ; CHECK-NEXT: vmv1r.v v14, v8
18376 ; CHECK-NEXT: vmv1r.v v15, v8
18377 ; CHECK-NEXT: vmv1r.v v16, v8
18378 ; CHECK-NEXT: vmv1r.v v17, v8
18379 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18380 ; CHECK-NEXT: vsoxseg8ei16.v v10, (a0), v9, v0.t
18381 ; CHECK-NEXT: ret
18382 entry:
18383 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
18384 ret void
18385 }
18387 declare void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, i64)
18388 declare void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, ptr, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
18390 define void @test_vsoxseg8_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {
18391 ; CHECK-LABEL: test_vsoxseg8_nxv2f16_nxv2i64:
18392 ; CHECK: # %bb.0: # %entry
18393 ; CHECK-NEXT: vmv1r.v v12, v8
18394 ; CHECK-NEXT: vmv1r.v v13, v8
18395 ; CHECK-NEXT: vmv1r.v v14, v8
18396 ; CHECK-NEXT: vmv1r.v v15, v8
18397 ; CHECK-NEXT: vmv1r.v v16, v8
18398 ; CHECK-NEXT: vmv1r.v v17, v8
18399 ; CHECK-NEXT: vmv1r.v v18, v8
18400 ; CHECK-NEXT: vmv1r.v v19, v8
18401 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18402 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10
18403 ; CHECK-NEXT: ret
18404 entry:
18405 tail call void @llvm.riscv.vsoxseg8.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl)
18406 ret void
18407 }
18409 define void @test_vsoxseg8_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
18410 ; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_nxv2i64:
18411 ; CHECK: # %bb.0: # %entry
18412 ; CHECK-NEXT: vmv1r.v v12, v8
18413 ; CHECK-NEXT: vmv1r.v v13, v8
18414 ; CHECK-NEXT: vmv1r.v v14, v8
18415 ; CHECK-NEXT: vmv1r.v v15, v8
18416 ; CHECK-NEXT: vmv1r.v v16, v8
18417 ; CHECK-NEXT: vmv1r.v v17, v8
18418 ; CHECK-NEXT: vmv1r.v v18, v8
18419 ; CHECK-NEXT: vmv1r.v v19, v8
18420 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
18421 ; CHECK-NEXT: vsoxseg8ei64.v v12, (a0), v10, v0.t
18422 ; CHECK-NEXT: ret
18423 entry:
18424 tail call void @llvm.riscv.vsoxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
18425 ret void
18426 }
18428 declare void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, i64)
18429 declare void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
18431 define void @test_vsoxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
18432 ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i32:
18433 ; CHECK: # %bb.0: # %entry
18434 ; CHECK-NEXT: vmv2r.v v12, v10
18435 ; CHECK-NEXT: vmv2r.v v10, v8
18436 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18437 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
18438 ; CHECK-NEXT: ret
18439 entry:
18440 tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
18441 ret void
18442 }
18444 define void @test_vsoxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18445 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i32:
18446 ; CHECK: # %bb.0: # %entry
18447 ; CHECK-NEXT: vmv2r.v v12, v10
18448 ; CHECK-NEXT: vmv2r.v v10, v8
18449 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18450 ; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
18451 ; CHECK-NEXT: ret
18452 entry:
18453 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
18454 ret void
18455 }
18457 declare void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, i64)
18458 declare void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
18460 define void @test_vsoxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
18461 ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i8:
18462 ; CHECK: # %bb.0: # %entry
18463 ; CHECK-NEXT: vmv1r.v v12, v10
18464 ; CHECK-NEXT: vmv2r.v v10, v8
18465 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18466 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
18467 ; CHECK-NEXT: ret
18468 entry:
18469 tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
18470 ret void
18471 }
18473 define void @test_vsoxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18474 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i8:
18475 ; CHECK: # %bb.0: # %entry
18476 ; CHECK-NEXT: vmv1r.v v12, v10
18477 ; CHECK-NEXT: vmv2r.v v10, v8
18478 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18479 ; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
18480 ; CHECK-NEXT: ret
18481 entry:
18482 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
18483 ret void
18484 }
18486 declare void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, i64)
18487 declare void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
18489 define void @test_vsoxseg2_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
18490 ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i64:
18491 ; CHECK: # %bb.0: # %entry
18492 ; CHECK-NEXT: vmv2r.v v10, v8
18493 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18494 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
18495 ; CHECK-NEXT: ret
18496 entry:
18497 tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
18498 ret void
18499 }
18501 define void @test_vsoxseg2_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18502 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i64:
18503 ; CHECK: # %bb.0: # %entry
18504 ; CHECK-NEXT: vmv2r.v v10, v8
18505 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18506 ; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
18507 ; CHECK-NEXT: ret
18508 entry:
18509 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
18510 ret void
18511 }
18513 declare void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, i64)
18514 declare void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
18516 define void @test_vsoxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
18517 ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i16:
18518 ; CHECK: # %bb.0: # %entry
18519 ; CHECK-NEXT: vmv1r.v v12, v10
18520 ; CHECK-NEXT: vmv2r.v v10, v8
18521 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18522 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
18523 ; CHECK-NEXT: ret
18524 entry:
18525 tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
18526 ret void
18527 }
18529 define void @test_vsoxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18530 ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i16:
18531 ; CHECK: # %bb.0: # %entry
18532 ; CHECK-NEXT: vmv1r.v v12, v10
18533 ; CHECK-NEXT: vmv2r.v v10, v8
18534 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18535 ; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
18536 ; CHECK-NEXT: ret
18537 entry:
18538 tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
18539 ret void
18540 }
18542 declare void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, i64)
18543 declare void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
18545 define void @test_vsoxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
18546 ; CHECK-LABEL: test_vsoxseg3_nxv4f32_nxv4i32:
18547 ; CHECK: # %bb.0: # %entry
18548 ; CHECK-NEXT: vmv2r.v v12, v8
18549 ; CHECK-NEXT: vmv2r.v v14, v8
18550 ; CHECK-NEXT: vmv2r.v v16, v8
18551 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18552 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10
18553 ; CHECK-NEXT: ret
18554 entry:
18555 tail call void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
18556 ret void
18557 }
18559 define void @test_vsoxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18560 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_nxv4i32:
18561 ; CHECK: # %bb.0: # %entry
18562 ; CHECK-NEXT: vmv2r.v v12, v8
18563 ; CHECK-NEXT: vmv2r.v v14, v8
18564 ; CHECK-NEXT: vmv2r.v v16, v8
18565 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18566 ; CHECK-NEXT: vsoxseg3ei32.v v12, (a0), v10, v0.t
18567 ; CHECK-NEXT: ret
18568 entry:
18569 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
18570 ret void
18571 }
18573 declare void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, i64)
18574 declare void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
18576 define void @test_vsoxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
18577 ; CHECK-LABEL: test_vsoxseg3_nxv4f32_nxv4i8:
18578 ; CHECK: # %bb.0: # %entry
18579 ; CHECK-NEXT: vmv2r.v v12, v8
18580 ; CHECK-NEXT: vmv2r.v v14, v8
18581 ; CHECK-NEXT: vmv2r.v v16, v8
18582 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18583 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10
18584 ; CHECK-NEXT: ret
18585 entry:
18586 tail call void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
18587 ret void
18588 }
18590 define void @test_vsoxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18591 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_nxv4i8:
18592 ; CHECK: # %bb.0: # %entry
18593 ; CHECK-NEXT: vmv2r.v v12, v8
18594 ; CHECK-NEXT: vmv2r.v v14, v8
18595 ; CHECK-NEXT: vmv2r.v v16, v8
18596 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18597 ; CHECK-NEXT: vsoxseg3ei8.v v12, (a0), v10, v0.t
18598 ; CHECK-NEXT: ret
18599 entry:
18600 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
18601 ret void
18602 }
18604 declare void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, i64)
18605 declare void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
18607 define void @test_vsoxseg3_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
18608 ; CHECK-LABEL: test_vsoxseg3_nxv4f32_nxv4i64:
18609 ; CHECK: # %bb.0: # %entry
18610 ; CHECK-NEXT: vmv2r.v v10, v8
18611 ; CHECK-NEXT: vmv4r.v v16, v12
18612 ; CHECK-NEXT: vmv2r.v v12, v8
18613 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18614 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16
18615 ; CHECK-NEXT: ret
18616 entry:
18617 tail call void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
18618 ret void
18619 }
18621 define void @test_vsoxseg3_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18622 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_nxv4i64:
18623 ; CHECK: # %bb.0: # %entry
18624 ; CHECK-NEXT: vmv2r.v v10, v8
18625 ; CHECK-NEXT: vmv4r.v v16, v12
18626 ; CHECK-NEXT: vmv2r.v v12, v8
18627 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18628 ; CHECK-NEXT: vsoxseg3ei64.v v8, (a0), v16, v0.t
18629 ; CHECK-NEXT: ret
18630 entry:
18631 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
18632 ret void
18633 }
18635 declare void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, i64)
18636 declare void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
18638 define void @test_vsoxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
18639 ; CHECK-LABEL: test_vsoxseg3_nxv4f32_nxv4i16:
18640 ; CHECK: # %bb.0: # %entry
18641 ; CHECK-NEXT: vmv2r.v v12, v8
18642 ; CHECK-NEXT: vmv2r.v v14, v8
18643 ; CHECK-NEXT: vmv2r.v v16, v8
18644 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18645 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10
18646 ; CHECK-NEXT: ret
18647 entry:
18648 tail call void @llvm.riscv.vsoxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
18649 ret void
18650 }
18652 define void @test_vsoxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18653 ; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_nxv4i16:
18654 ; CHECK: # %bb.0: # %entry
18655 ; CHECK-NEXT: vmv2r.v v12, v8
18656 ; CHECK-NEXT: vmv2r.v v14, v8
18657 ; CHECK-NEXT: vmv2r.v v16, v8
18658 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18659 ; CHECK-NEXT: vsoxseg3ei16.v v12, (a0), v10, v0.t
18660 ; CHECK-NEXT: ret
18661 entry:
18662 tail call void @llvm.riscv.vsoxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
18663 ret void
18664 }
18666 declare void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, i64)
18667 declare void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
18669 define void @test_vsoxseg4_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {
18670 ; CHECK-LABEL: test_vsoxseg4_nxv4f32_nxv4i32:
18671 ; CHECK: # %bb.0: # %entry
18672 ; CHECK-NEXT: vmv2r.v v12, v8
18673 ; CHECK-NEXT: vmv2r.v v14, v8
18674 ; CHECK-NEXT: vmv2r.v v16, v8
18675 ; CHECK-NEXT: vmv2r.v v18, v8
18676 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18677 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10
18678 ; CHECK-NEXT: ret
18679 entry:
18680 tail call void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl)
18681 ret void
18682 }
18684 define void @test_vsoxseg4_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18685 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_nxv4i32:
18686 ; CHECK: # %bb.0: # %entry
18687 ; CHECK-NEXT: vmv2r.v v12, v8
18688 ; CHECK-NEXT: vmv2r.v v14, v8
18689 ; CHECK-NEXT: vmv2r.v v16, v8
18690 ; CHECK-NEXT: vmv2r.v v18, v8
18691 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18692 ; CHECK-NEXT: vsoxseg4ei32.v v12, (a0), v10, v0.t
18693 ; CHECK-NEXT: ret
18694 entry:
18695 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
18696 ret void
18697 }
18699 declare void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, i64)
18700 declare void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
18702 define void @test_vsoxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {
18703 ; CHECK-LABEL: test_vsoxseg4_nxv4f32_nxv4i8:
18704 ; CHECK: # %bb.0: # %entry
18705 ; CHECK-NEXT: vmv2r.v v12, v8
18706 ; CHECK-NEXT: vmv2r.v v14, v8
18707 ; CHECK-NEXT: vmv2r.v v16, v8
18708 ; CHECK-NEXT: vmv2r.v v18, v8
18709 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18710 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10
18711 ; CHECK-NEXT: ret
18712 entry:
18713 tail call void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl)
18714 ret void
18715 }
18717 define void @test_vsoxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18718 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_nxv4i8:
18719 ; CHECK: # %bb.0: # %entry
18720 ; CHECK-NEXT: vmv2r.v v12, v8
18721 ; CHECK-NEXT: vmv2r.v v14, v8
18722 ; CHECK-NEXT: vmv2r.v v16, v8
18723 ; CHECK-NEXT: vmv2r.v v18, v8
18724 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18725 ; CHECK-NEXT: vsoxseg4ei8.v v12, (a0), v10, v0.t
18726 ; CHECK-NEXT: ret
18727 entry:
18728 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
18729 ret void
18730 }
18732 declare void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, i64)
18733 declare void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
18735 define void @test_vsoxseg4_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {
18736 ; CHECK-LABEL: test_vsoxseg4_nxv4f32_nxv4i64:
18737 ; CHECK: # %bb.0: # %entry
18738 ; CHECK-NEXT: vmv2r.v v16, v8
18739 ; CHECK-NEXT: vmv2r.v v18, v8
18740 ; CHECK-NEXT: vmv2r.v v20, v8
18741 ; CHECK-NEXT: vmv2r.v v22, v8
18742 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18743 ; CHECK-NEXT: vsoxseg4ei64.v v16, (a0), v12
18744 ; CHECK-NEXT: ret
18745 entry:
18746 tail call void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl)
18747 ret void
18748 }
18750 define void @test_vsoxseg4_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18751 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_nxv4i64:
18752 ; CHECK: # %bb.0: # %entry
18753 ; CHECK-NEXT: vmv2r.v v16, v8
18754 ; CHECK-NEXT: vmv2r.v v18, v8
18755 ; CHECK-NEXT: vmv2r.v v20, v8
18756 ; CHECK-NEXT: vmv2r.v v22, v8
18757 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18758 ; CHECK-NEXT: vsoxseg4ei64.v v16, (a0), v12, v0.t
18759 ; CHECK-NEXT: ret
18760 entry:
18761 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
18762 ret void
18763 }
18765 declare void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, i64)
18766 declare void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
18768 define void @test_vsoxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {
18769 ; CHECK-LABEL: test_vsoxseg4_nxv4f32_nxv4i16:
18770 ; CHECK: # %bb.0: # %entry
18771 ; CHECK-NEXT: vmv2r.v v12, v8
18772 ; CHECK-NEXT: vmv2r.v v14, v8
18773 ; CHECK-NEXT: vmv2r.v v16, v8
18774 ; CHECK-NEXT: vmv2r.v v18, v8
18775 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18776 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10
18777 ; CHECK-NEXT: ret
18778 entry:
18779 tail call void @llvm.riscv.vsoxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl)
18780 ret void
18781 }
18783 define void @test_vsoxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
18784 ; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_nxv4i16:
18785 ; CHECK: # %bb.0: # %entry
18786 ; CHECK-NEXT: vmv2r.v v12, v8
18787 ; CHECK-NEXT: vmv2r.v v14, v8
18788 ; CHECK-NEXT: vmv2r.v v16, v8
18789 ; CHECK-NEXT: vmv2r.v v18, v8
18790 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
18791 ; CHECK-NEXT: vsoxseg4ei16.v v12, (a0), v10, v0.t
18792 ; CHECK-NEXT: ret
18793 entry:
18794 tail call void @llvm.riscv.vsoxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
18795 ret void
18796 }