1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple riscv64 -mattr=+v -verify-machineinstrs -run-pass=postrapseudos %s -o - | FileCheck %s
9 ; CHECK-LABEL: name: copy_zvlsseg_N2
10 ; CHECK: $v2 = VMV1R_V $v4
11 ; CHECK-NEXT: $v3 = VMV1R_V $v5
12 ; CHECK-NEXT: $v3 = VMV1R_V $v4
13 ; CHECK-NEXT: $v4 = VMV1R_V $v5
14 ; CHECK-NEXT: $v6 = VMV1R_V $v5
15 ; CHECK-NEXT: $v5 = VMV1R_V $v4
16 ; CHECK-NEXT: $v6 = VMV1R_V $v4
17 ; CHECK-NEXT: $v7 = VMV1R_V $v5
18 ; CHECK-NEXT: $v0m2 = VMV2R_V $v4m2
19 ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m2
20 ; CHECK-NEXT: $v2m2 = VMV2R_V $v4m2
21 ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m2
22 ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m2
23 ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m2
24 ; CHECK-NEXT: $v8m2 = VMV2R_V $v4m2
25 ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2
26 ; CHECK-NEXT: $v0m4 = VMV4R_V $v8m4
27 ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4
28 ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m4
29 ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4
30 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4
31 ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m4
32 ; CHECK-NEXT: $v16m4 = VMV4R_V $v8m4
33 ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4
39 $v0m2_v2m2 = COPY $v4m2_v6m2
40 $v2m2_v4m2 = COPY $v4m2_v6m2
41 $v6m2_v8m2 = COPY $v4m2_v6m2
42 $v8m2_v10m2 = COPY $v4m2_v6m2
44 $v0m4_v4m4 = COPY $v8m4_v12m4
45 $v4m4_v8m4 = COPY $v8m4_v12m4
46 $v12m4_v16m4 = COPY $v8m4_v12m4
47 $v16m4_v20m4 = COPY $v8m4_v12m4
53 ; CHECK-LABEL: name: copy_zvlsseg_N3
54 ; CHECK: $v2 = VMV1R_V $v5
55 ; CHECK-NEXT: $v3 = VMV1R_V $v6
56 ; CHECK-NEXT: $v4 = VMV1R_V $v7
57 ; CHECK-NEXT: $v3 = VMV1R_V $v5
58 ; CHECK-NEXT: $v4 = VMV1R_V $v6
59 ; CHECK-NEXT: $v5 = VMV1R_V $v7
60 ; CHECK-NEXT: $v4 = VMV1R_V $v5
61 ; CHECK-NEXT: $v5 = VMV1R_V $v6
62 ; CHECK-NEXT: $v6 = VMV1R_V $v7
63 ; CHECK-NEXT: $v9 = VMV1R_V $v7
64 ; CHECK-NEXT: $v8 = VMV1R_V $v6
65 ; CHECK-NEXT: $v7 = VMV1R_V $v5
66 ; CHECK-NEXT: $v9 = VMV1R_V $v5
67 ; CHECK-NEXT: $v10 = VMV1R_V $v6
68 ; CHECK-NEXT: $v11 = VMV1R_V $v7
69 ; CHECK-NEXT: $v0m2 = VMV2R_V $v6m2
70 ; CHECK-NEXT: $v2m2 = VMV2R_V $v8m2
71 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2
72 ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m2
73 ; CHECK-NEXT: $v4m2 = VMV2R_V $v8m2
74 ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
75 ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2
76 ; CHECK-NEXT: $v12m2 = VMV2R_V $v8m2
77 ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2
78 ; CHECK-NEXT: $v12m2 = VMV2R_V $v6m2
79 ; CHECK-NEXT: $v14m2 = VMV2R_V $v8m2
80 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2
81 $v2_v3_v4 = COPY $v5_v6_v7
82 $v3_v4_v5 = COPY $v5_v6_v7
83 $v4_v5_v6 = COPY $v5_v6_v7
84 $v7_v8_v9 = COPY $v5_v6_v7
85 $v9_v10_v11 = COPY $v5_v6_v7
87 $v0m2_v2m2_v4m2 = COPY $v6m2_v8m2_v10m2
88 $v2m2_v4m2_v6m2 = COPY $v6m2_v8m2_v10m2
89 $v10m2_v12m2_v14m2 = COPY $v6m2_v8m2_v10m2
90 $v12m2_v14m2_v16m2 = COPY $v6m2_v8m2_v10m2
96 ; CHECK-LABEL: name: copy_zvlsseg_N4
97 ; CHECK: $v6 = VMV1R_V $v10
98 ; CHECK-NEXT: $v7 = VMV1R_V $v11
99 ; CHECK-NEXT: $v8 = VMV1R_V $v12
100 ; CHECK-NEXT: $v9 = VMV1R_V $v13
101 ; CHECK-NEXT: $v7 = VMV1R_V $v10
102 ; CHECK-NEXT: $v8 = VMV1R_V $v11
103 ; CHECK-NEXT: $v9 = VMV1R_V $v12
104 ; CHECK-NEXT: $v10 = VMV1R_V $v13
105 ; CHECK-NEXT: $v16 = VMV1R_V $v13
106 ; CHECK-NEXT: $v15 = VMV1R_V $v12
107 ; CHECK-NEXT: $v14 = VMV1R_V $v11
108 ; CHECK-NEXT: $v13 = VMV1R_V $v10
109 ; CHECK-NEXT: $v14 = VMV1R_V $v10
110 ; CHECK-NEXT: $v15 = VMV1R_V $v11
111 ; CHECK-NEXT: $v16 = VMV1R_V $v12
112 ; CHECK-NEXT: $v17 = VMV1R_V $v13
113 ; CHECK-NEXT: $v2m2 = VMV2R_V $v10m2
114 ; CHECK-NEXT: $v4m2 = VMV2R_V $v12m2
115 ; CHECK-NEXT: $v6m2 = VMV2R_V $v14m2
116 ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2
117 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2
118 ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2
119 ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2
120 ; CHECK-NEXT: $v10m2 = VMV2R_V $v16m2
121 ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2
122 ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2
123 ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2
124 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2
125 ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2
126 ; CHECK-NEXT: $v20m2 = VMV2R_V $v12m2
127 ; CHECK-NEXT: $v22m2 = VMV2R_V $v14m2
128 ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2
129 $v6_v7_v8_v9 = COPY $v10_v11_v12_v13
130 $v7_v8_v9_v10 = COPY $v10_v11_v12_v13
131 $v13_v14_v15_v16 = COPY $v10_v11_v12_v13
132 $v14_v15_v16_v17 = COPY $v10_v11_v12_v13
134 $v2m2_v4m2_v6m2_v8m2 = COPY $v10m2_v12m2_v14m2_v16m2
135 $v4m2_v6m2_v8m2_v10m2 = COPY $v10m2_v12m2_v14m2_v16m2
136 $v16m2_v18m2_v20m2_v22m2 = COPY $v10m2_v12m2_v14m2_v16m2
137 $v18m2_v20m2_v22m2_v24m2 = COPY $v10m2_v12m2_v14m2_v16m2
140 name: copy_zvlsseg_N5
143 ; CHECK-LABEL: name: copy_zvlsseg_N5
144 ; CHECK: $v5 = VMV1R_V $v10
145 ; CHECK-NEXT: $v6 = VMV1R_V $v11
146 ; CHECK-NEXT: $v7 = VMV1R_V $v12
147 ; CHECK-NEXT: $v8 = VMV1R_V $v13
148 ; CHECK-NEXT: $v9 = VMV1R_V $v14
149 ; CHECK-NEXT: $v6 = VMV1R_V $v10
150 ; CHECK-NEXT: $v7 = VMV1R_V $v11
151 ; CHECK-NEXT: $v8 = VMV1R_V $v12
152 ; CHECK-NEXT: $v9 = VMV1R_V $v13
153 ; CHECK-NEXT: $v10 = VMV1R_V $v14
154 ; CHECK-NEXT: $v18 = VMV1R_V $v14
155 ; CHECK-NEXT: $v17 = VMV1R_V $v13
156 ; CHECK-NEXT: $v16 = VMV1R_V $v12
157 ; CHECK-NEXT: $v15 = VMV1R_V $v11
158 ; CHECK-NEXT: $v14 = VMV1R_V $v10
159 ; CHECK-NEXT: $v15 = VMV1R_V $v10
160 ; CHECK-NEXT: $v16 = VMV1R_V $v11
161 ; CHECK-NEXT: $v17 = VMV1R_V $v12
162 ; CHECK-NEXT: $v18 = VMV1R_V $v13
163 ; CHECK-NEXT: $v19 = VMV1R_V $v14
164 $v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14
165 $v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14
166 $v14_v15_v16_v17_v18 = COPY $v10_v11_v12_v13_v14
167 $v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14
170 name: copy_zvlsseg_N6
173 ; CHECK-LABEL: name: copy_zvlsseg_N6
174 ; CHECK: $v4 = VMV1R_V $v10
175 ; CHECK-NEXT: $v5 = VMV1R_V $v11
176 ; CHECK-NEXT: $v6 = VMV1R_V $v12
177 ; CHECK-NEXT: $v7 = VMV1R_V $v13
178 ; CHECK-NEXT: $v8 = VMV1R_V $v14
179 ; CHECK-NEXT: $v9 = VMV1R_V $v15
180 ; CHECK-NEXT: $v5 = VMV1R_V $v10
181 ; CHECK-NEXT: $v6 = VMV1R_V $v11
182 ; CHECK-NEXT: $v7 = VMV1R_V $v12
183 ; CHECK-NEXT: $v8 = VMV1R_V $v13
184 ; CHECK-NEXT: $v9 = VMV1R_V $v14
185 ; CHECK-NEXT: $v10 = VMV1R_V $v15
186 ; CHECK-NEXT: $v20 = VMV1R_V $v15
187 ; CHECK-NEXT: $v19 = VMV1R_V $v14
188 ; CHECK-NEXT: $v18 = VMV1R_V $v13
189 ; CHECK-NEXT: $v17 = VMV1R_V $v12
190 ; CHECK-NEXT: $v16 = VMV1R_V $v11
191 ; CHECK-NEXT: $v15 = VMV1R_V $v10
192 ; CHECK-NEXT: $v16 = VMV1R_V $v10
193 ; CHECK-NEXT: $v17 = VMV1R_V $v11
194 ; CHECK-NEXT: $v18 = VMV1R_V $v12
195 ; CHECK-NEXT: $v19 = VMV1R_V $v13
196 ; CHECK-NEXT: $v20 = VMV1R_V $v14
197 ; CHECK-NEXT: $v21 = VMV1R_V $v15
198 $v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15
199 $v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15
200 $v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15
201 $v16_v17_v18_v19_v20_v21 = COPY $v10_v11_v12_v13_v14_v15
204 name: copy_zvlsseg_N7
207 ; CHECK-LABEL: name: copy_zvlsseg_N7
208 ; CHECK: $v3 = VMV1R_V $v10
209 ; CHECK-NEXT: $v4 = VMV1R_V $v11
210 ; CHECK-NEXT: $v5 = VMV1R_V $v12
211 ; CHECK-NEXT: $v6 = VMV1R_V $v13
212 ; CHECK-NEXT: $v7 = VMV1R_V $v14
213 ; CHECK-NEXT: $v8 = VMV1R_V $v15
214 ; CHECK-NEXT: $v9 = VMV1R_V $v16
215 ; CHECK-NEXT: $v4 = VMV1R_V $v10
216 ; CHECK-NEXT: $v5 = VMV1R_V $v11
217 ; CHECK-NEXT: $v6 = VMV1R_V $v12
218 ; CHECK-NEXT: $v7 = VMV1R_V $v13
219 ; CHECK-NEXT: $v8 = VMV1R_V $v14
220 ; CHECK-NEXT: $v9 = VMV1R_V $v15
221 ; CHECK-NEXT: $v10 = VMV1R_V $v16
222 ; CHECK-NEXT: $v22 = VMV1R_V $v16
223 ; CHECK-NEXT: $v21 = VMV1R_V $v15
224 ; CHECK-NEXT: $v20 = VMV1R_V $v14
225 ; CHECK-NEXT: $v19 = VMV1R_V $v13
226 ; CHECK-NEXT: $v18 = VMV1R_V $v12
227 ; CHECK-NEXT: $v17 = VMV1R_V $v11
228 ; CHECK-NEXT: $v16 = VMV1R_V $v10
229 ; CHECK-NEXT: $v17 = VMV1R_V $v10
230 ; CHECK-NEXT: $v18 = VMV1R_V $v11
231 ; CHECK-NEXT: $v19 = VMV1R_V $v12
232 ; CHECK-NEXT: $v20 = VMV1R_V $v13
233 ; CHECK-NEXT: $v21 = VMV1R_V $v14
234 ; CHECK-NEXT: $v22 = VMV1R_V $v15
235 ; CHECK-NEXT: $v23 = VMV1R_V $v16
236 $v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16
237 $v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16
238 $v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16
239 $v17_v18_v19_v20_v21_v22_v23 = COPY $v10_v11_v12_v13_v14_v15_v16
242 name: copy_zvlsseg_N8
245 ; CHECK-LABEL: name: copy_zvlsseg_N8
246 ; CHECK: $v2 = VMV1R_V $v10
247 ; CHECK-NEXT: $v3 = VMV1R_V $v11
248 ; CHECK-NEXT: $v4 = VMV1R_V $v12
249 ; CHECK-NEXT: $v5 = VMV1R_V $v13
250 ; CHECK-NEXT: $v6 = VMV1R_V $v14
251 ; CHECK-NEXT: $v7 = VMV1R_V $v15
252 ; CHECK-NEXT: $v8 = VMV1R_V $v16
253 ; CHECK-NEXT: $v9 = VMV1R_V $v17
254 ; CHECK-NEXT: $v3 = VMV1R_V $v10
255 ; CHECK-NEXT: $v4 = VMV1R_V $v11
256 ; CHECK-NEXT: $v5 = VMV1R_V $v12
257 ; CHECK-NEXT: $v6 = VMV1R_V $v13
258 ; CHECK-NEXT: $v7 = VMV1R_V $v14
259 ; CHECK-NEXT: $v8 = VMV1R_V $v15
260 ; CHECK-NEXT: $v9 = VMV1R_V $v16
261 ; CHECK-NEXT: $v10 = VMV1R_V $v17
262 ; CHECK-NEXT: $v24 = VMV1R_V $v17
263 ; CHECK-NEXT: $v23 = VMV1R_V $v16
264 ; CHECK-NEXT: $v22 = VMV1R_V $v15
265 ; CHECK-NEXT: $v21 = VMV1R_V $v14
266 ; CHECK-NEXT: $v20 = VMV1R_V $v13
267 ; CHECK-NEXT: $v19 = VMV1R_V $v12
268 ; CHECK-NEXT: $v18 = VMV1R_V $v11
269 ; CHECK-NEXT: $v17 = VMV1R_V $v10
270 ; CHECK-NEXT: $v18 = VMV1R_V $v10
271 ; CHECK-NEXT: $v19 = VMV1R_V $v11
272 ; CHECK-NEXT: $v20 = VMV1R_V $v12
273 ; CHECK-NEXT: $v21 = VMV1R_V $v13
274 ; CHECK-NEXT: $v22 = VMV1R_V $v14
275 ; CHECK-NEXT: $v23 = VMV1R_V $v15
276 ; CHECK-NEXT: $v24 = VMV1R_V $v16
277 ; CHECK-NEXT: $v25 = VMV1R_V $v17
278 $v2_v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
279 $v3_v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
280 $v17_v18_v19_v20_v21_v22_v23_v24 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
281 $v18_v19_v20_v21_v22_v23_v24_v25 = COPY $v10_v11_v12_v13_v14_v15_v16_v17