| blob | e536a993a0967df5b0b4ba721085b12edf1aca79 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
3 # RUN: | FileCheck -check-prefix=RV32I %s
4 # RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
5 # RUN: | FileCheck -check-prefix=RV64I %s
7 # Provide dummy definitions of functions and just enough metadata to create a
8 # DBG_VALUE.
9 --- |
10 define void @cmov_interleaved_bad() {
11 ret void
12 }
13 define void @cmov_interleaved_debug_value() {
14 ret void
15 }
16 ...
17 ---
18 # Here we have a sequence of select instructions with a non-select instruction
19 # in the middle. Because the non-select depends on the result of a previous
20 # select, we cannot optimize the sequence to share control-flow.
21 name: cmov_interleaved_bad
22 alignment: 4
23 tracksRegLiveness: true
24 registers:
25 - { id: 0, class: gpr }
26 - { id: 1, class: gpr }
27 - { id: 2, class: gpr }
28 - { id: 3, class: gpr }
29 - { id: 4, class: gpr }
30 - { id: 5, class: gpr }
31 - { id: 6, class: gpr }
32 - { id: 7, class: gpr }
33 - { id: 8, class: gpr }
34 - { id: 9, class: gpr }
35 - { id: 10, class: gpr }
36 liveins:
37 - { reg: '$x10', virtual-reg: '%0' }
38 - { reg: '$x11', virtual-reg: '%1' }
39 - { reg: '$x12', virtual-reg: '%2' }
40 - { reg: '$x13', virtual-reg: '%3' }
41 body: |
42 bb.0:
43 liveins: $x10, $x11, $x12, $x13
45 ; RV32I-LABEL: name: cmov_interleaved_bad
46 ; RV32I: successors: %bb.1, %bb.2
47 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
48 ; RV32I-NEXT: {{ $}}
49 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
50 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
51 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
52 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
53 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
54 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
55 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
56 ; RV32I-NEXT: {{ $}}
57 ; RV32I-NEXT: .1:
58 ; RV32I-NEXT: {{ $}}
59 ; RV32I-NEXT: .2:
60 ; RV32I-NEXT: successors: %bb.3, %bb.4
61 ; RV32I-NEXT: {{ $}}
62 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
63 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
64 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
65 ; RV32I-NEXT: {{ $}}
66 ; RV32I-NEXT: .3:
67 ; RV32I-NEXT: {{ $}}
68 ; RV32I-NEXT: .4:
69 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
70 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
71 ; RV32I-NEXT: $x10 = COPY [[ADD]]
72 ; RV32I-NEXT: PseudoRET implicit $x10
73 ; RV64I-LABEL: name: cmov_interleaved_bad
74 ; RV64I: successors: %bb.1, %bb.2
75 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
76 ; RV64I-NEXT: {{ $}}
77 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
78 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
79 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
80 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
81 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
82 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
83 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
84 ; RV64I-NEXT: {{ $}}
85 ; RV64I-NEXT: .1:
86 ; RV64I-NEXT: {{ $}}
87 ; RV64I-NEXT: .2:
88 ; RV64I-NEXT: successors: %bb.3, %bb.4
89 ; RV64I-NEXT: {{ $}}
90 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
91 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
92 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
93 ; RV64I-NEXT: {{ $}}
94 ; RV64I-NEXT: .3:
95 ; RV64I-NEXT: {{ $}}
96 ; RV64I-NEXT: .4:
97 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
98 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
99 ; RV64I-NEXT: $x10 = COPY [[ADD]]
100 ; RV64I-NEXT: PseudoRET implicit $x10
101 %3:gpr = COPY $x13
102 %2:gpr = COPY $x12
103 %1:gpr = COPY $x11
104 %0:gpr = COPY $x10
105 %5:gpr = ANDI %0, 1
106 %6:gpr = COPY $x0
107 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
108 %8:gpr = ADDI %7, 1
109 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
110 %10:gpr = ADD %7, killed %9
111 $x10 = COPY %10
112 PseudoRET implicit $x10
114 ...
115 ---
116 # Demonstrate that debug info associated with selects is correctly moved to
117 # the tail basic block, while debug info associated with non-selects is left
118 # in the head basic block.
119 name: cmov_interleaved_debug_value
120 alignment: 4
121 tracksRegLiveness: true
122 registers:
123 - { id: 0, class: gpr }
124 - { id: 1, class: gpr }
125 - { id: 2, class: gpr }
126 - { id: 3, class: gpr }
127 - { id: 4, class: gpr }
128 - { id: 5, class: gpr }
129 - { id: 6, class: gpr }
130 - { id: 7, class: gpr }
131 - { id: 8, class: gpr }
132 - { id: 9, class: gpr }
133 - { id: 10, class: gpr }
134 liveins:
135 - { reg: '$x10', virtual-reg: '%0' }
136 - { reg: '$x11', virtual-reg: '%1' }
137 - { reg: '$x12', virtual-reg: '%2' }
138 - { reg: '$x13', virtual-reg: '%3' }
139 body: |
140 bb.0:
141 liveins: $x10, $x11, $x12, $x13
143 ; RV32I-LABEL: name: cmov_interleaved_debug_value
144 ; RV32I: successors: %bb.1, %bb.2
145 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
146 ; RV32I-NEXT: {{ $}}
147 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
148 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
149 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
150 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
151 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
152 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
153 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
154 ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg
155 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
156 ; RV32I-NEXT: {{ $}}
157 ; RV32I-NEXT: .1:
158 ; RV32I-NEXT: {{ $}}
159 ; RV32I-NEXT: .2:
160 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
161 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
162 ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg
163 ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg
164 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
165 ; RV32I-NEXT: $x10 = COPY [[ADD]]
166 ; RV32I-NEXT: PseudoRET implicit $x10
167 ; RV64I-LABEL: name: cmov_interleaved_debug_value
168 ; RV64I: successors: %bb.1, %bb.2
169 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
170 ; RV64I-NEXT: {{ $}}
171 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
172 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
173 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
174 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
175 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
176 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
177 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
178 ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg
179 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
180 ; RV64I-NEXT: {{ $}}
181 ; RV64I-NEXT: .1:
182 ; RV64I-NEXT: {{ $}}
183 ; RV64I-NEXT: .2:
184 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
185 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
186 ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg
187 ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg
188 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
189 ; RV64I-NEXT: $x10 = COPY [[ADD]]
190 ; RV64I-NEXT: PseudoRET implicit $x10
191 %3:gpr = COPY $x13
192 %2:gpr = COPY $x12
193 %1:gpr = COPY $x11
194 %0:gpr = COPY $x10
195 %5:gpr = ANDI %0, 1
196 %6:gpr = COPY $x0
197 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
198 DBG_VALUE %7, $noreg
199 %8:gpr = ADDI %0, 1
200 DBG_VALUE %8, $noreg
201 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
202 DBG_VALUE %9, $noreg
203 %10:gpr = ADD %7, killed %9
204 $x10 = COPY %10
205 PseudoRET implicit $x10
207 ...
208 ---