1 ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3 ;;; Test vector or intrinsic instructions
6 ;;; We test VOR*vvl, VOR*vvl_v, VOR*rvl, VOR*rvl_v, VOR*vvml_v, VOR*rvml_v,
7 ;;; PVOR*vvl, PVOR*vvl_v, PVOR*rvl, PVOR*rvl_v, PVOR*vvml_v, and PVOR*rvml_v
10 ; Function Attrs: nounwind readnone
11 define fastcc <256 x double> @vor_vvvl(<256 x double> %0, <256 x double> %1) {
12 ; CHECK-LABEL: vor_vvvl:
14 ; CHECK-NEXT: lea %s0, 256
16 ; CHECK-NEXT: vor %v0, %v0, %v1
17 ; CHECK-NEXT: b.l.t (, %s10)
18 %3 = tail call fast <256 x double> @llvm.ve.vl.vor.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
22 ; Function Attrs: nounwind readnone
23 declare <256 x double> @llvm.ve.vl.vor.vvvl(<256 x double>, <256 x double>, i32)
25 ; Function Attrs: nounwind readnone
26 define fastcc <256 x double> @vor_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
27 ; CHECK-LABEL: vor_vvvvl:
29 ; CHECK-NEXT: lea %s0, 128
31 ; CHECK-NEXT: vor %v2, %v0, %v1
32 ; CHECK-NEXT: lea %s16, 256
33 ; CHECK-NEXT: lvl %s16
34 ; CHECK-NEXT: vor %v0, (0)1, %v2
35 ; CHECK-NEXT: b.l.t (, %s10)
36 %4 = tail call fast <256 x double> @llvm.ve.vl.vor.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
40 ; Function Attrs: nounwind readnone
41 declare <256 x double> @llvm.ve.vl.vor.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
43 ; Function Attrs: nounwind readnone
44 define fastcc <256 x double> @vor_vsvl(i64 %0, <256 x double> %1) {
45 ; CHECK-LABEL: vor_vsvl:
47 ; CHECK-NEXT: lea %s1, 256
49 ; CHECK-NEXT: vor %v0, %s0, %v0
50 ; CHECK-NEXT: b.l.t (, %s10)
51 %3 = tail call fast <256 x double> @llvm.ve.vl.vor.vsvl(i64 %0, <256 x double> %1, i32 256)
55 ; Function Attrs: nounwind readnone
56 declare <256 x double> @llvm.ve.vl.vor.vsvl(i64, <256 x double>, i32)
58 ; Function Attrs: nounwind readnone
59 define fastcc <256 x double> @vor_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
60 ; CHECK-LABEL: vor_vsvvl:
62 ; CHECK-NEXT: lea %s1, 128
64 ; CHECK-NEXT: vor %v1, %s0, %v0
65 ; CHECK-NEXT: lea %s16, 256
66 ; CHECK-NEXT: lvl %s16
67 ; CHECK-NEXT: vor %v0, (0)1, %v1
68 ; CHECK-NEXT: b.l.t (, %s10)
69 %4 = tail call fast <256 x double> @llvm.ve.vl.vor.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
73 ; Function Attrs: nounwind readnone
74 declare <256 x double> @llvm.ve.vl.vor.vsvvl(i64, <256 x double>, <256 x double>, i32)
76 ; Function Attrs: nounwind readnone
77 define fastcc <256 x double> @vor_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
78 ; CHECK-LABEL: vor_vvvmvl:
80 ; CHECK-NEXT: lea %s0, 128
82 ; CHECK-NEXT: vor %v2, %v0, %v1, %vm1
83 ; CHECK-NEXT: lea %s16, 256
84 ; CHECK-NEXT: lvl %s16
85 ; CHECK-NEXT: vor %v0, (0)1, %v2
86 ; CHECK-NEXT: b.l.t (, %s10)
87 %5 = tail call fast <256 x double> @llvm.ve.vl.vor.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
91 ; Function Attrs: nounwind readnone
92 declare <256 x double> @llvm.ve.vl.vor.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
94 ; Function Attrs: nounwind readnone
95 define fastcc <256 x double> @vor_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
96 ; CHECK-LABEL: vor_vsvmvl:
98 ; CHECK-NEXT: lea %s1, 128
100 ; CHECK-NEXT: vor %v1, %s0, %v0, %vm1
101 ; CHECK-NEXT: lea %s16, 256
102 ; CHECK-NEXT: lvl %s16
103 ; CHECK-NEXT: vor %v0, (0)1, %v1
104 ; CHECK-NEXT: b.l.t (, %s10)
105 %5 = tail call fast <256 x double> @llvm.ve.vl.vor.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
106 ret <256 x double> %5
109 ; Function Attrs: nounwind readnone
110 declare <256 x double> @llvm.ve.vl.vor.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
112 ; Function Attrs: nounwind readnone
113 define fastcc <256 x double> @pvor_vvvl(<256 x double> %0, <256 x double> %1) {
114 ; CHECK-LABEL: pvor_vvvl:
116 ; CHECK-NEXT: lea %s0, 256
117 ; CHECK-NEXT: lvl %s0
118 ; CHECK-NEXT: pvor %v0, %v0, %v1
119 ; CHECK-NEXT: b.l.t (, %s10)
120 %3 = tail call fast <256 x double> @llvm.ve.vl.pvor.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
121 ret <256 x double> %3
124 ; Function Attrs: nounwind readnone
125 declare <256 x double> @llvm.ve.vl.pvor.vvvl(<256 x double>, <256 x double>, i32)
127 ; Function Attrs: nounwind readnone
128 define fastcc <256 x double> @pvor_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
129 ; CHECK-LABEL: pvor_vvvvl:
131 ; CHECK-NEXT: lea %s0, 128
132 ; CHECK-NEXT: lvl %s0
133 ; CHECK-NEXT: pvor %v2, %v0, %v1
134 ; CHECK-NEXT: lea %s16, 256
135 ; CHECK-NEXT: lvl %s16
136 ; CHECK-NEXT: vor %v0, (0)1, %v2
137 ; CHECK-NEXT: b.l.t (, %s10)
138 %4 = tail call fast <256 x double> @llvm.ve.vl.pvor.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
139 ret <256 x double> %4
142 ; Function Attrs: nounwind readnone
143 declare <256 x double> @llvm.ve.vl.pvor.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
145 ; Function Attrs: nounwind readnone
146 define fastcc <256 x double> @pvor_vsvl(i64 %0, <256 x double> %1) {
147 ; CHECK-LABEL: pvor_vsvl:
149 ; CHECK-NEXT: lea %s1, 256
150 ; CHECK-NEXT: lvl %s1
151 ; CHECK-NEXT: pvor %v0, %s0, %v0
152 ; CHECK-NEXT: b.l.t (, %s10)
153 %3 = tail call fast <256 x double> @llvm.ve.vl.pvor.vsvl(i64 %0, <256 x double> %1, i32 256)
154 ret <256 x double> %3
157 ; Function Attrs: nounwind readnone
158 declare <256 x double> @llvm.ve.vl.pvor.vsvl(i64, <256 x double>, i32)
160 ; Function Attrs: nounwind readnone
161 define fastcc <256 x double> @pvor_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
162 ; CHECK-LABEL: pvor_vsvvl:
164 ; CHECK-NEXT: lea %s1, 128
165 ; CHECK-NEXT: lvl %s1
166 ; CHECK-NEXT: pvor %v1, %s0, %v0
167 ; CHECK-NEXT: lea %s16, 256
168 ; CHECK-NEXT: lvl %s16
169 ; CHECK-NEXT: vor %v0, (0)1, %v1
170 ; CHECK-NEXT: b.l.t (, %s10)
171 %4 = tail call fast <256 x double> @llvm.ve.vl.pvor.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
172 ret <256 x double> %4
175 ; Function Attrs: nounwind readnone
176 declare <256 x double> @llvm.ve.vl.pvor.vsvvl(i64, <256 x double>, <256 x double>, i32)
178 ; Function Attrs: nounwind readnone
179 define fastcc <256 x double> @pvor_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
180 ; CHECK-LABEL: pvor_vvvMvl:
182 ; CHECK-NEXT: lea %s0, 128
183 ; CHECK-NEXT: lvl %s0
184 ; CHECK-NEXT: pvor %v2, %v0, %v1, %vm2
185 ; CHECK-NEXT: lea %s16, 256
186 ; CHECK-NEXT: lvl %s16
187 ; CHECK-NEXT: vor %v0, (0)1, %v2
188 ; CHECK-NEXT: b.l.t (, %s10)
189 %5 = tail call fast <256 x double> @llvm.ve.vl.pvor.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
190 ret <256 x double> %5
193 ; Function Attrs: nounwind readnone
194 declare <256 x double> @llvm.ve.vl.pvor.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
196 ; Function Attrs: nounwind readnone
197 define fastcc <256 x double> @pvor_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
198 ; CHECK-LABEL: pvor_vsvMvl:
200 ; CHECK-NEXT: lea %s1, 128
201 ; CHECK-NEXT: lvl %s1
202 ; CHECK-NEXT: pvor %v1, %s0, %v0, %vm2
203 ; CHECK-NEXT: lea %s16, 256
204 ; CHECK-NEXT: lvl %s16
205 ; CHECK-NEXT: vor %v0, (0)1, %v1
206 ; CHECK-NEXT: b.l.t (, %s10)
207 %5 = tail call fast <256 x double> @llvm.ve.vl.pvor.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
208 ret <256 x double> %5
211 ; Function Attrs: nounwind readnone
212 declare <256 x double> @llvm.ve.vl.pvor.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)