| blob | 2046d790cc57e45a2c6eb26e29879f93f38de98d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefix=CHECK-32
3 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK-64
5 define i1 @isnan_f(float %x) {
6 ; CHECK-32-LABEL: isnan_f:
7 ; CHECK-32: # %bb.0: # %entry
8 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
9 ; CHECK-32-NEXT: fucomp %st(0)
10 ; CHECK-32-NEXT: fnstsw %ax
11 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
12 ; CHECK-32-NEXT: sahf
13 ; CHECK-32-NEXT: setp %al
14 ; CHECK-32-NEXT: retl
15 ;
16 ; CHECK-64-LABEL: isnan_f:
17 ; CHECK-64: # %bb.0: # %entry
18 ; CHECK-64-NEXT: ucomiss %xmm0, %xmm0
19 ; CHECK-64-NEXT: setp %al
20 ; CHECK-64-NEXT: retq
21 entry:
22 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; "nan"
23 ret i1 %0
24 }
26 define i1 @isnot_nan_f(float %x) {
27 ; CHECK-32-LABEL: isnot_nan_f:
28 ; CHECK-32: # %bb.0: # %entry
29 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
30 ; CHECK-32-NEXT: fucomp %st(0)
31 ; CHECK-32-NEXT: fnstsw %ax
32 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
33 ; CHECK-32-NEXT: sahf
34 ; CHECK-32-NEXT: setnp %al
35 ; CHECK-32-NEXT: retl
36 ;
37 ; CHECK-64-LABEL: isnot_nan_f:
38 ; CHECK-64: # %bb.0: # %entry
39 ; CHECK-64-NEXT: ucomiss %xmm0, %xmm0
40 ; CHECK-64-NEXT: setnp %al
41 ; CHECK-64-NEXT: retq
42 entry:
43 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
44 ret i1 %0
45 }
47 define i1 @issignaling_f(float %x) {
48 ; CHECK-32-LABEL: issignaling_f:
49 ; CHECK-32: # %bb.0: # %entry
50 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
51 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
52 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
53 ; CHECK-32-NEXT: setl %cl
54 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
55 ; CHECK-32-NEXT: setge %al
56 ; CHECK-32-NEXT: andb %cl, %al
57 ; CHECK-32-NEXT: retl
58 ;
59 ; CHECK-64-LABEL: issignaling_f:
60 ; CHECK-64: # %bb.0: # %entry
61 ; CHECK-64-NEXT: movd %xmm0, %eax
62 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
63 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
64 ; CHECK-64-NEXT: setl %cl
65 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
66 ; CHECK-64-NEXT: setge %al
67 ; CHECK-64-NEXT: andb %cl, %al
68 ; CHECK-64-NEXT: retq
69 entry:
70 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan"
71 ret i1 %0
72 }
74 define i1 @not_issignaling_f(float %x) {
75 ; CHECK-32-LABEL: not_issignaling_f:
76 ; CHECK-32: # %bb.0: # %entry
77 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
78 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
79 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
80 ; CHECK-32-NEXT: setge %cl
81 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
82 ; CHECK-32-NEXT: setl %al
83 ; CHECK-32-NEXT: orb %cl, %al
84 ; CHECK-32-NEXT: retl
85 ;
86 ; CHECK-64-LABEL: not_issignaling_f:
87 ; CHECK-64: # %bb.0: # %entry
88 ; CHECK-64-NEXT: movd %xmm0, %eax
89 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
90 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
91 ; CHECK-64-NEXT: setge %cl
92 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
93 ; CHECK-64-NEXT: setl %al
94 ; CHECK-64-NEXT: orb %cl, %al
95 ; CHECK-64-NEXT: retq
96 entry:
97 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1022) ; ~"snan"
98 ret i1 %0
99 }
101 define i1 @isquiet_f(float %x) {
102 ; CHECK-32-LABEL: isquiet_f:
103 ; CHECK-32: # %bb.0: # %entry
104 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
105 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
106 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
107 ; CHECK-32-NEXT: setge %al
108 ; CHECK-32-NEXT: retl
109 ;
110 ; CHECK-64-LABEL: isquiet_f:
111 ; CHECK-64: # %bb.0: # %entry
112 ; CHECK-64-NEXT: movd %xmm0, %eax
113 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
114 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
115 ; CHECK-64-NEXT: setge %al
116 ; CHECK-64-NEXT: retq
117 entry:
118 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan"
119 ret i1 %0
120 }
122 define i1 @not_isquiet_f(float %x) {
123 ; CHECK-32-LABEL: not_isquiet_f:
124 ; CHECK-32: # %bb.0: # %entry
125 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
126 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
127 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
128 ; CHECK-32-NEXT: setl %al
129 ; CHECK-32-NEXT: retl
130 ;
131 ; CHECK-64-LABEL: not_isquiet_f:
132 ; CHECK-64: # %bb.0: # %entry
133 ; CHECK-64-NEXT: movd %xmm0, %eax
134 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
135 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
136 ; CHECK-64-NEXT: setl %al
137 ; CHECK-64-NEXT: retq
138 entry:
139 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1021) ; ~"qnan"
140 ret i1 %0
141 }
143 define i1 @isinf_f(float %x) {
144 ; CHECK-32-LABEL: isinf_f:
145 ; CHECK-32: # %bb.0: # %entry
146 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
147 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
148 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
149 ; CHECK-32-NEXT: sete %al
150 ; CHECK-32-NEXT: retl
151 ;
152 ; CHECK-64-LABEL: isinf_f:
153 ; CHECK-64: # %bb.0: # %entry
154 ; CHECK-64-NEXT: movd %xmm0, %eax
155 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
156 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
157 ; CHECK-64-NEXT: sete %al
158 ; CHECK-64-NEXT: retq
159 entry:
160 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
161 ret i1 %0
162 }
164 define i1 @not_isinf_f(float %x) {
165 ; CHECK-32-LABEL: not_isinf_f:
166 ; CHECK-32: # %bb.0: # %entry
167 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
168 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
169 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
170 ; CHECK-32-NEXT: setne %al
171 ; CHECK-32-NEXT: retl
172 ;
173 ; CHECK-64-LABEL: not_isinf_f:
174 ; CHECK-64: # %bb.0: # %entry
175 ; CHECK-64-NEXT: movd %xmm0, %eax
176 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
177 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
178 ; CHECK-64-NEXT: setne %al
179 ; CHECK-64-NEXT: retq
180 entry:
181 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; ~0x204 = "~inf"
182 ret i1 %0
183 }
185 define i1 @is_plus_inf_f(float %x) {
186 ; CHECK-32-LABEL: is_plus_inf_f:
187 ; CHECK-32: # %bb.0: # %entry
188 ; CHECK-32-NEXT: cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
189 ; CHECK-32-NEXT: sete %al
190 ; CHECK-32-NEXT: retl
191 ;
192 ; CHECK-64-LABEL: is_plus_inf_f:
193 ; CHECK-64: # %bb.0: # %entry
194 ; CHECK-64-NEXT: movd %xmm0, %eax
195 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
196 ; CHECK-64-NEXT: sete %al
197 ; CHECK-64-NEXT: retq
198 entry:
199 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
200 ret i1 %0
201 }
203 define i1 @is_minus_inf_f(float %x) {
204 ; CHECK-32-LABEL: is_minus_inf_f:
205 ; CHECK-32: # %bb.0: # %entry
206 ; CHECK-32-NEXT: cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000
207 ; CHECK-32-NEXT: sete %al
208 ; CHECK-32-NEXT: retl
209 ;
210 ; CHECK-64-LABEL: is_minus_inf_f:
211 ; CHECK-64: # %bb.0: # %entry
212 ; CHECK-64-NEXT: movd %xmm0, %eax
213 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
214 ; CHECK-64-NEXT: sete %al
215 ; CHECK-64-NEXT: retq
216 entry:
217 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
218 ret i1 %0
219 }
221 define i1 @not_is_minus_inf_f(float %x) {
222 ; CHECK-32-LABEL: not_is_minus_inf_f:
223 ; CHECK-32: # %bb.0: # %entry
224 ; CHECK-32-NEXT: cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000
225 ; CHECK-32-NEXT: setne %al
226 ; CHECK-32-NEXT: retl
227 ;
228 ; CHECK-64-LABEL: not_is_minus_inf_f:
229 ; CHECK-64: # %bb.0: # %entry
230 ; CHECK-64-NEXT: movd %xmm0, %eax
231 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
232 ; CHECK-64-NEXT: setne %al
233 ; CHECK-64-NEXT: retq
234 entry:
235 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1019) ; ~"-inf"
236 ret i1 %0
237 }
239 define i1 @isfinite_f(float %x) {
240 ; CHECK-32-LABEL: isfinite_f:
241 ; CHECK-32: # %bb.0: # %entry
242 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
243 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
244 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
245 ; CHECK-32-NEXT: setl %al
246 ; CHECK-32-NEXT: retl
247 ;
248 ; CHECK-64-LABEL: isfinite_f:
249 ; CHECK-64: # %bb.0: # %entry
250 ; CHECK-64-NEXT: movd %xmm0, %eax
251 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
252 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
253 ; CHECK-64-NEXT: setl %al
254 ; CHECK-64-NEXT: retq
255 entry:
256 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
257 ret i1 %0
258 }
260 define i1 @not_isfinite_f(float %x) {
261 ; CHECK-32-LABEL: not_isfinite_f:
262 ; CHECK-32: # %bb.0: # %entry
263 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
264 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
265 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
266 ; CHECK-32-NEXT: setge %al
267 ; CHECK-32-NEXT: retl
268 ;
269 ; CHECK-64-LABEL: not_isfinite_f:
270 ; CHECK-64: # %bb.0: # %entry
271 ; CHECK-64-NEXT: movd %xmm0, %eax
272 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
273 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
274 ; CHECK-64-NEXT: setge %al
275 ; CHECK-64-NEXT: retq
276 entry:
277 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
278 ret i1 %0
279 }
281 define i1 @is_plus_finite_f(float %x) {
282 ; CHECK-32-LABEL: is_plus_finite_f:
283 ; CHECK-32: # %bb.0: # %entry
284 ; CHECK-32-NEXT: cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
285 ; CHECK-32-NEXT: setb %al
286 ; CHECK-32-NEXT: retl
287 ;
288 ; CHECK-64-LABEL: is_plus_finite_f:
289 ; CHECK-64: # %bb.0: # %entry
290 ; CHECK-64-NEXT: movd %xmm0, %eax
291 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
292 ; CHECK-64-NEXT: setb %al
293 ; CHECK-64-NEXT: retq
294 entry:
295 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
296 ret i1 %0
297 }
299 define i1 @not_is_plus_finite_f(float %x) {
300 ; CHECK-32-LABEL: not_is_plus_finite_f:
301 ; CHECK-32: # %bb.0: # %entry
302 ; CHECK-32-NEXT: cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
303 ; CHECK-32-NEXT: setae %al
304 ; CHECK-32-NEXT: retl
305 ;
306 ; CHECK-64-LABEL: not_is_plus_finite_f:
307 ; CHECK-64: # %bb.0: # %entry
308 ; CHECK-64-NEXT: movd %xmm0, %eax
309 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
310 ; CHECK-64-NEXT: setae %al
311 ; CHECK-64-NEXT: retq
312 entry:
313 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 575) ; ~0x1c0 = ~"+finite"
314 ret i1 %0
315 }
317 define i1 @is_minus_finite_f(float %x) {
318 ; CHECK-32-LABEL: is_minus_finite_f:
319 ; CHECK-32: # %bb.0: # %entry
320 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
321 ; CHECK-32-NEXT: testl %eax, %eax
322 ; CHECK-32-NEXT: sets %cl
323 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
324 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
325 ; CHECK-32-NEXT: setl %al
326 ; CHECK-32-NEXT: andb %cl, %al
327 ; CHECK-32-NEXT: retl
328 ;
329 ; CHECK-64-LABEL: is_minus_finite_f:
330 ; CHECK-64: # %bb.0: # %entry
331 ; CHECK-64-NEXT: movd %xmm0, %eax
332 ; CHECK-64-NEXT: testl %eax, %eax
333 ; CHECK-64-NEXT: sets %cl
334 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
335 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
336 ; CHECK-64-NEXT: setl %al
337 ; CHECK-64-NEXT: andb %cl, %al
338 ; CHECK-64-NEXT: retq
339 entry:
340 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"
341 ret i1 %0
342 }
344 define i1 @not_is_minus_finite_f(float %x) {
345 ; CHECK-32-LABEL: not_is_minus_finite_f:
346 ; CHECK-32: # %bb.0: # %entry
347 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
348 ; CHECK-32-NEXT: testl %eax, %eax
349 ; CHECK-32-NEXT: setns %cl
350 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
351 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
352 ; CHECK-32-NEXT: setge %al
353 ; CHECK-32-NEXT: orb %cl, %al
354 ; CHECK-32-NEXT: retl
355 ;
356 ; CHECK-64-LABEL: not_is_minus_finite_f:
357 ; CHECK-64: # %bb.0: # %entry
358 ; CHECK-64-NEXT: movd %xmm0, %eax
359 ; CHECK-64-NEXT: testl %eax, %eax
360 ; CHECK-64-NEXT: setns %cl
361 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
362 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
363 ; CHECK-64-NEXT: setge %al
364 ; CHECK-64-NEXT: orb %cl, %al
365 ; CHECK-64-NEXT: retq
366 entry:
367 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 967) ; ~0x38 = ~"-finite"
368 ret i1 %0
369 }
371 define i1 @isnormal_f(float %x) #1 {
372 ; CHECK-32-LABEL: isnormal_f:
373 ; CHECK-32: # %bb.0: # %entry
374 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
375 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
376 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
377 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
378 ; CHECK-32-NEXT: setb %al
379 ; CHECK-32-NEXT: retl
380 ;
381 ; CHECK-64-LABEL: isnormal_f:
382 ; CHECK-64: # %bb.0: # %entry
383 ; CHECK-64-NEXT: movd %xmm0, %eax
384 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
385 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
386 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
387 ; CHECK-64-NEXT: setb %al
388 ; CHECK-64-NEXT: retq
389 entry:
390 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal"
391 ret i1 %0
392 }
394 define i1 @not_isnormal_f(float %x) #1 {
395 ; CHECK-32-LABEL: not_isnormal_f:
396 ; CHECK-32: # %bb.0: # %entry
397 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
398 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
399 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
400 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
401 ; CHECK-32-NEXT: setae %al
402 ; CHECK-32-NEXT: retl
403 ;
404 ; CHECK-64-LABEL: not_isnormal_f:
405 ; CHECK-64: # %bb.0: # %entry
406 ; CHECK-64-NEXT: movd %xmm0, %eax
407 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
408 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
409 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
410 ; CHECK-64-NEXT: setae %al
411 ; CHECK-64-NEXT: retq
412 entry:
413 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 759) ; ~0x108 = "~normal"
414 ret i1 %0
415 }
417 define i1 @is_plus_normal_f(float %x) {
418 ; CHECK-32-LABEL: is_plus_normal_f:
419 ; CHECK-32: # %bb.0: # %entry
420 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
421 ; CHECK-32-NEXT: testl %eax, %eax
422 ; CHECK-32-NEXT: setns %cl
423 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
424 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
425 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
426 ; CHECK-32-NEXT: setb %al
427 ; CHECK-32-NEXT: andb %cl, %al
428 ; CHECK-32-NEXT: retl
429 ;
430 ; CHECK-64-LABEL: is_plus_normal_f:
431 ; CHECK-64: # %bb.0: # %entry
432 ; CHECK-64-NEXT: movd %xmm0, %eax
433 ; CHECK-64-NEXT: testl %eax, %eax
434 ; CHECK-64-NEXT: setns %cl
435 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
436 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
437 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
438 ; CHECK-64-NEXT: setb %al
439 ; CHECK-64-NEXT: andb %cl, %al
440 ; CHECK-64-NEXT: retq
441 entry:
442 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 256) ; 0x100 = "+normal"
443 ret i1 %0
444 }
446 define i1 @issubnormal_f(float %x) {
447 ; CHECK-32-LABEL: issubnormal_f:
448 ; CHECK-32: # %bb.0: # %entry
449 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
450 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
451 ; CHECK-32-NEXT: decl %eax
452 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
453 ; CHECK-32-NEXT: setb %al
454 ; CHECK-32-NEXT: retl
455 ;
456 ; CHECK-64-LABEL: issubnormal_f:
457 ; CHECK-64: # %bb.0: # %entry
458 ; CHECK-64-NEXT: movd %xmm0, %eax
459 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
460 ; CHECK-64-NEXT: decl %eax
461 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
462 ; CHECK-64-NEXT: setb %al
463 ; CHECK-64-NEXT: retq
464 entry:
465 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
466 ret i1 %0
467 }
469 define i1 @issubnormal_f_daz(float %x) #0 {
470 ; CHECK-32-LABEL: issubnormal_f_daz:
471 ; CHECK-32: # %bb.0: # %entry
472 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
473 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
474 ; CHECK-32-NEXT: decl %eax
475 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
476 ; CHECK-32-NEXT: setb %al
477 ; CHECK-32-NEXT: retl
478 ;
479 ; CHECK-64-LABEL: issubnormal_f_daz:
480 ; CHECK-64: # %bb.0: # %entry
481 ; CHECK-64-NEXT: movd %xmm0, %eax
482 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
483 ; CHECK-64-NEXT: decl %eax
484 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
485 ; CHECK-64-NEXT: setb %al
486 ; CHECK-64-NEXT: retq
487 entry:
488 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
489 ret i1 %0
490 }
492 define i1 @issubnormal_f_maybe_daz(float %x) #1 {
493 ; CHECK-32-LABEL: issubnormal_f_maybe_daz:
494 ; CHECK-32: # %bb.0: # %entry
495 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
496 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
497 ; CHECK-32-NEXT: decl %eax
498 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
499 ; CHECK-32-NEXT: setb %al
500 ; CHECK-32-NEXT: retl
501 ;
502 ; CHECK-64-LABEL: issubnormal_f_maybe_daz:
503 ; CHECK-64: # %bb.0: # %entry
504 ; CHECK-64-NEXT: movd %xmm0, %eax
505 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
506 ; CHECK-64-NEXT: decl %eax
507 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
508 ; CHECK-64-NEXT: setb %al
509 ; CHECK-64-NEXT: retq
510 entry:
511 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
512 ret i1 %0
513 }
515 define i1 @not_issubnormal_f(float %x) {
516 ; CHECK-32-LABEL: not_issubnormal_f:
517 ; CHECK-32: # %bb.0: # %entry
518 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
519 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
520 ; CHECK-32-NEXT: decl %eax
521 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
522 ; CHECK-32-NEXT: setae %al
523 ; CHECK-32-NEXT: retl
524 ;
525 ; CHECK-64-LABEL: not_issubnormal_f:
526 ; CHECK-64: # %bb.0: # %entry
527 ; CHECK-64-NEXT: movd %xmm0, %eax
528 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
529 ; CHECK-64-NEXT: decl %eax
530 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
531 ; CHECK-64-NEXT: setae %al
532 ; CHECK-64-NEXT: retq
533 entry:
534 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
535 ret i1 %0
536 }
538 define i1 @not_issubnormal_f_daz(float %x) #0 {
539 ; CHECK-32-LABEL: not_issubnormal_f_daz:
540 ; CHECK-32: # %bb.0: # %entry
541 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
542 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
543 ; CHECK-32-NEXT: decl %eax
544 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
545 ; CHECK-32-NEXT: setae %al
546 ; CHECK-32-NEXT: retl
547 ;
548 ; CHECK-64-LABEL: not_issubnormal_f_daz:
549 ; CHECK-64: # %bb.0: # %entry
550 ; CHECK-64-NEXT: movd %xmm0, %eax
551 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
552 ; CHECK-64-NEXT: decl %eax
553 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
554 ; CHECK-64-NEXT: setae %al
555 ; CHECK-64-NEXT: retq
556 entry:
557 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
558 ret i1 %0
559 }
561 define i1 @not_issubnormal_f_maybe_daz(float %x) #1 {
562 ; CHECK-32-LABEL: not_issubnormal_f_maybe_daz:
563 ; CHECK-32: # %bb.0: # %entry
564 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
565 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
566 ; CHECK-32-NEXT: decl %eax
567 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
568 ; CHECK-32-NEXT: setae %al
569 ; CHECK-32-NEXT: retl
570 ;
571 ; CHECK-64-LABEL: not_issubnormal_f_maybe_daz:
572 ; CHECK-64: # %bb.0: # %entry
573 ; CHECK-64-NEXT: movd %xmm0, %eax
574 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
575 ; CHECK-64-NEXT: decl %eax
576 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
577 ; CHECK-64-NEXT: setae %al
578 ; CHECK-64-NEXT: retq
579 entry:
580 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
581 ret i1 %0
582 }
584 define i1 @is_plus_subnormal_f(float %x) {
585 ; CHECK-32-LABEL: is_plus_subnormal_f:
586 ; CHECK-32: # %bb.0: # %entry
587 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
588 ; CHECK-32-NEXT: decl %eax
589 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
590 ; CHECK-32-NEXT: setb %al
591 ; CHECK-32-NEXT: retl
592 ;
593 ; CHECK-64-LABEL: is_plus_subnormal_f:
594 ; CHECK-64: # %bb.0: # %entry
595 ; CHECK-64-NEXT: movd %xmm0, %eax
596 ; CHECK-64-NEXT: decl %eax
597 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
598 ; CHECK-64-NEXT: setb %al
599 ; CHECK-64-NEXT: retq
600 entry:
601 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 128) ; 0x80 = "+subnormal"
602 ret i1 %0
603 }
605 define i1 @not_is_plus_subnormal_f(float %x) {
606 ; CHECK-32-LABEL: not_is_plus_subnormal_f:
607 ; CHECK-32: # %bb.0: # %entry
608 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
609 ; CHECK-32-NEXT: decl %eax
610 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
611 ; CHECK-32-NEXT: setae %al
612 ; CHECK-32-NEXT: retl
613 ;
614 ; CHECK-64-LABEL: not_is_plus_subnormal_f:
615 ; CHECK-64: # %bb.0: # %entry
616 ; CHECK-64-NEXT: movd %xmm0, %eax
617 ; CHECK-64-NEXT: decl %eax
618 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
619 ; CHECK-64-NEXT: setae %al
620 ; CHECK-64-NEXT: retq
621 entry:
622 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 895) ; ~0x80 = ~"+subnormal"
623 ret i1 %0
624 }
626 define i1 @is_minus_subnormal_f(float %x) {
627 ; CHECK-32-LABEL: is_minus_subnormal_f:
628 ; CHECK-32: # %bb.0: # %entry
629 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
630 ; CHECK-32-NEXT: testl %eax, %eax
631 ; CHECK-32-NEXT: sets %cl
632 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
633 ; CHECK-32-NEXT: decl %eax
634 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
635 ; CHECK-32-NEXT: setb %al
636 ; CHECK-32-NEXT: andb %cl, %al
637 ; CHECK-32-NEXT: retl
638 ;
639 ; CHECK-64-LABEL: is_minus_subnormal_f:
640 ; CHECK-64: # %bb.0: # %entry
641 ; CHECK-64-NEXT: movd %xmm0, %eax
642 ; CHECK-64-NEXT: testl %eax, %eax
643 ; CHECK-64-NEXT: sets %cl
644 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
645 ; CHECK-64-NEXT: decl %eax
646 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
647 ; CHECK-64-NEXT: setb %al
648 ; CHECK-64-NEXT: andb %cl, %al
649 ; CHECK-64-NEXT: retq
650 entry:
651 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 16) ; 0x10 = "-subnormal"
652 ret i1 %0
653 }
655 define i1 @not_is_minus_subnormal_f(float %x) {
656 ; CHECK-32-LABEL: not_is_minus_subnormal_f:
657 ; CHECK-32: # %bb.0: # %entry
658 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
659 ; CHECK-32-NEXT: testl %eax, %eax
660 ; CHECK-32-NEXT: setns %cl
661 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
662 ; CHECK-32-NEXT: decl %eax
663 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
664 ; CHECK-32-NEXT: setae %al
665 ; CHECK-32-NEXT: orb %cl, %al
666 ; CHECK-32-NEXT: retl
667 ;
668 ; CHECK-64-LABEL: not_is_minus_subnormal_f:
669 ; CHECK-64: # %bb.0: # %entry
670 ; CHECK-64-NEXT: movd %xmm0, %eax
671 ; CHECK-64-NEXT: testl %eax, %eax
672 ; CHECK-64-NEXT: setns %cl
673 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
674 ; CHECK-64-NEXT: decl %eax
675 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
676 ; CHECK-64-NEXT: setae %al
677 ; CHECK-64-NEXT: orb %cl, %al
678 ; CHECK-64-NEXT: retq
679 entry:
680 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1007) ; ~0x10 = ~"-subnormal"
681 ret i1 %0
682 }
684 define i1 @iszero_f(float %x) {
685 ; CHECK-32-LABEL: iszero_f:
686 ; CHECK-32: # %bb.0: # %entry
687 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
688 ; CHECK-32-NEXT: sete %al
689 ; CHECK-32-NEXT: retl
690 ;
691 ; CHECK-64-LABEL: iszero_f:
692 ; CHECK-64: # %bb.0: # %entry
693 ; CHECK-64-NEXT: movd %xmm0, %eax
694 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
695 ; CHECK-64-NEXT: sete %al
696 ; CHECK-64-NEXT: retq
697 entry:
698 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
699 ret i1 %0
700 }
702 define i1 @iszero_f_daz(float %x) #0 {
703 ; CHECK-32-LABEL: iszero_f_daz:
704 ; CHECK-32: # %bb.0: # %entry
705 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
706 ; CHECK-32-NEXT: sete %al
707 ; CHECK-32-NEXT: retl
708 ;
709 ; CHECK-64-LABEL: iszero_f_daz:
710 ; CHECK-64: # %bb.0: # %entry
711 ; CHECK-64-NEXT: movd %xmm0, %eax
712 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
713 ; CHECK-64-NEXT: sete %al
714 ; CHECK-64-NEXT: retq
715 entry:
716 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
717 ret i1 %0
718 }
720 define i1 @iszero_f_maybe_daz(float %x) #1 {
721 ; CHECK-32-LABEL: iszero_f_maybe_daz:
722 ; CHECK-32: # %bb.0: # %entry
723 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
724 ; CHECK-32-NEXT: sete %al
725 ; CHECK-32-NEXT: retl
726 ;
727 ; CHECK-64-LABEL: iszero_f_maybe_daz:
728 ; CHECK-64: # %bb.0: # %entry
729 ; CHECK-64-NEXT: movd %xmm0, %eax
730 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
731 ; CHECK-64-NEXT: sete %al
732 ; CHECK-64-NEXT: retq
733 entry:
734 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
735 ret i1 %0
736 }
738 define i1 @not_iszero_f(float %x) {
739 ; CHECK-32-LABEL: not_iszero_f:
740 ; CHECK-32: # %bb.0: # %entry
741 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
742 ; CHECK-32-NEXT: setne %al
743 ; CHECK-32-NEXT: retl
744 ;
745 ; CHECK-64-LABEL: not_iszero_f:
746 ; CHECK-64: # %bb.0: # %entry
747 ; CHECK-64-NEXT: movd %xmm0, %eax
748 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
749 ; CHECK-64-NEXT: setne %al
750 ; CHECK-64-NEXT: retq
751 entry:
752 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
753 ret i1 %0
754 }
756 define i1 @not_iszero_f_daz(float %x) #0 {
757 ; CHECK-32-LABEL: not_iszero_f_daz:
758 ; CHECK-32: # %bb.0: # %entry
759 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
760 ; CHECK-32-NEXT: setne %al
761 ; CHECK-32-NEXT: retl
762 ;
763 ; CHECK-64-LABEL: not_iszero_f_daz:
764 ; CHECK-64: # %bb.0: # %entry
765 ; CHECK-64-NEXT: movd %xmm0, %eax
766 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
767 ; CHECK-64-NEXT: setne %al
768 ; CHECK-64-NEXT: retq
769 entry:
770 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
771 ret i1 %0
772 }
774 define i1 @not_iszero_f_maybe_daz(float %x) #1 {
775 ; CHECK-32-LABEL: not_iszero_f_maybe_daz:
776 ; CHECK-32: # %bb.0: # %entry
777 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
778 ; CHECK-32-NEXT: setne %al
779 ; CHECK-32-NEXT: retl
780 ;
781 ; CHECK-64-LABEL: not_iszero_f_maybe_daz:
782 ; CHECK-64: # %bb.0: # %entry
783 ; CHECK-64-NEXT: movd %xmm0, %eax
784 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
785 ; CHECK-64-NEXT: setne %al
786 ; CHECK-64-NEXT: retq
787 entry:
788 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
789 ret i1 %0
790 }
792 define i1 @issubnormal_or_zero_f(float %x) {
793 ; CHECK-32-LABEL: issubnormal_or_zero_f:
794 ; CHECK-32: # %bb.0: # %entry
795 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
796 ; CHECK-32-NEXT: sete %al
797 ; CHECK-32-NEXT: retl
798 ;
799 ; CHECK-64-LABEL: issubnormal_or_zero_f:
800 ; CHECK-64: # %bb.0: # %entry
801 ; CHECK-64-NEXT: movd %xmm0, %eax
802 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
803 ; CHECK-64-NEXT: sete %al
804 ; CHECK-64-NEXT: retq
805 entry:
806 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
807 ret i1 %0
808 }
810 define i1 @issubnormal_or_zero_f_daz(float %x) #0 {
811 ; CHECK-32-LABEL: issubnormal_or_zero_f_daz:
812 ; CHECK-32: # %bb.0: # %entry
813 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
814 ; CHECK-32-NEXT: sete %al
815 ; CHECK-32-NEXT: retl
816 ;
817 ; CHECK-64-LABEL: issubnormal_or_zero_f_daz:
818 ; CHECK-64: # %bb.0: # %entry
819 ; CHECK-64-NEXT: movd %xmm0, %eax
820 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
821 ; CHECK-64-NEXT: sete %al
822 ; CHECK-64-NEXT: retq
823 entry:
824 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
825 ret i1 %0
826 }
828 define i1 @issubnormal_or_zero_f_maybe_daz(float %x) #1 {
829 ; CHECK-32-LABEL: issubnormal_or_zero_f_maybe_daz:
830 ; CHECK-32: # %bb.0: # %entry
831 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
832 ; CHECK-32-NEXT: sete %al
833 ; CHECK-32-NEXT: retl
834 ;
835 ; CHECK-64-LABEL: issubnormal_or_zero_f_maybe_daz:
836 ; CHECK-64: # %bb.0: # %entry
837 ; CHECK-64-NEXT: movd %xmm0, %eax
838 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
839 ; CHECK-64-NEXT: sete %al
840 ; CHECK-64-NEXT: retq
841 entry:
842 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
843 ret i1 %0
844 }
846 define i1 @not_issubnormal_or_zero_f(float %x) {
847 ; CHECK-32-LABEL: not_issubnormal_or_zero_f:
848 ; CHECK-32: # %bb.0: # %entry
849 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
850 ; CHECK-32-NEXT: setne %al
851 ; CHECK-32-NEXT: retl
852 ;
853 ; CHECK-64-LABEL: not_issubnormal_or_zero_f:
854 ; CHECK-64: # %bb.0: # %entry
855 ; CHECK-64-NEXT: movd %xmm0, %eax
856 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
857 ; CHECK-64-NEXT: setne %al
858 ; CHECK-64-NEXT: retq
859 entry:
860 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
861 ret i1 %0
862 }
864 define i1 @not_issubnormal_or_zero_f_daz(float %x) #0 {
865 ; CHECK-32-LABEL: not_issubnormal_or_zero_f_daz:
866 ; CHECK-32: # %bb.0: # %entry
867 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
868 ; CHECK-32-NEXT: setne %al
869 ; CHECK-32-NEXT: retl
870 ;
871 ; CHECK-64-LABEL: not_issubnormal_or_zero_f_daz:
872 ; CHECK-64: # %bb.0: # %entry
873 ; CHECK-64-NEXT: movd %xmm0, %eax
874 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
875 ; CHECK-64-NEXT: setne %al
876 ; CHECK-64-NEXT: retq
877 entry:
878 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
879 ret i1 %0
880 }
882 define i1 @not_issubnormal_or_zero_f_maybe_daz(float %x) #1 {
883 ; CHECK-32-LABEL: not_issubnormal_or_zero_f_maybe_daz:
884 ; CHECK-32: # %bb.0: # %entry
885 ; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
886 ; CHECK-32-NEXT: setne %al
887 ; CHECK-32-NEXT: retl
888 ;
889 ; CHECK-64-LABEL: not_issubnormal_or_zero_f_maybe_daz:
890 ; CHECK-64: # %bb.0: # %entry
891 ; CHECK-64-NEXT: movd %xmm0, %eax
892 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
893 ; CHECK-64-NEXT: setne %al
894 ; CHECK-64-NEXT: retq
895 entry:
896 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
897 ret i1 %0
898 }
900 define i1 @is_plus_zero_f(float %x) {
901 ; CHECK-32-LABEL: is_plus_zero_f:
902 ; CHECK-32: # %bb.0: # %entry
903 ; CHECK-32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
904 ; CHECK-32-NEXT: sete %al
905 ; CHECK-32-NEXT: retl
906 ;
907 ; CHECK-64-LABEL: is_plus_zero_f:
908 ; CHECK-64: # %bb.0: # %entry
909 ; CHECK-64-NEXT: movd %xmm0, %eax
910 ; CHECK-64-NEXT: testl %eax, %eax
911 ; CHECK-64-NEXT: sete %al
912 ; CHECK-64-NEXT: retq
913 entry:
914 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 64) ; 0x40 = "+zero"
915 ret i1 %0
916 }
918 define i1 @not_is_plus_zero_f(float %x) {
919 ; CHECK-32-LABEL: not_is_plus_zero_f:
920 ; CHECK-32: # %bb.0: # %entry
921 ; CHECK-32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
922 ; CHECK-32-NEXT: setne %al
923 ; CHECK-32-NEXT: retl
924 ;
925 ; CHECK-64-LABEL: not_is_plus_zero_f:
926 ; CHECK-64: # %bb.0: # %entry
927 ; CHECK-64-NEXT: movd %xmm0, %eax
928 ; CHECK-64-NEXT: testl %eax, %eax
929 ; CHECK-64-NEXT: setne %al
930 ; CHECK-64-NEXT: retq
931 entry:
932 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 959) ; ~0x40 = ~"+zero"
933 ret i1 %0
934 }
936 define i1 @is_minus_zero_f(float %x) {
937 ; CHECK-32-LABEL: is_minus_zero_f:
938 ; CHECK-32: # %bb.0: # %entry
939 ; CHECK-32-NEXT: cmpl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000
940 ; CHECK-32-NEXT: sete %al
941 ; CHECK-32-NEXT: retl
942 ;
943 ; CHECK-64-LABEL: is_minus_zero_f:
944 ; CHECK-64: # %bb.0: # %entry
945 ; CHECK-64-NEXT: movd %xmm0, %eax
946 ; CHECK-64-NEXT: cmpl $-2147483648, %eax # imm = 0x80000000
947 ; CHECK-64-NEXT: sete %al
948 ; CHECK-64-NEXT: retq
949 entry:
950 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 32) ; 0x20 = "-zero"
951 ret i1 %0
952 }
954 define i1 @not_is_minus_zero_f(float %x) {
955 ; CHECK-32-LABEL: not_is_minus_zero_f:
956 ; CHECK-32: # %bb.0: # %entry
957 ; CHECK-32-NEXT: cmpl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000
958 ; CHECK-32-NEXT: setne %al
959 ; CHECK-32-NEXT: retl
960 ;
961 ; CHECK-64-LABEL: not_is_minus_zero_f:
962 ; CHECK-64: # %bb.0: # %entry
963 ; CHECK-64-NEXT: movd %xmm0, %eax
964 ; CHECK-64-NEXT: cmpl $-2147483648, %eax # imm = 0x80000000
965 ; CHECK-64-NEXT: setne %al
966 ; CHECK-64-NEXT: retq
967 entry:
968 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 991) ; ~0x20 = ~"-zero"
969 ret i1 %0
970 }
972 define i1 @isnan_f_strictfp(float %x) strictfp {
973 ; CHECK-32-LABEL: isnan_f_strictfp:
974 ; CHECK-32: # %bb.0: # %entry
975 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
976 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
977 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
978 ; CHECK-32-NEXT: setge %al
979 ; CHECK-32-NEXT: retl
980 ;
981 ; CHECK-64-LABEL: isnan_f_strictfp:
982 ; CHECK-64: # %bb.0: # %entry
983 ; CHECK-64-NEXT: movd %xmm0, %eax
984 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
985 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
986 ; CHECK-64-NEXT: setge %al
987 ; CHECK-64-NEXT: retq
988 entry:
989 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp ; "nan"
990 ret i1 %0
991 }
993 define i1 @not_isnan_f_strictfp(float %x) strictfp {
994 ; CHECK-32-LABEL: not_isnan_f_strictfp:
995 ; CHECK-32: # %bb.0: # %entry
996 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
997 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
998 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
999 ; CHECK-32-NEXT: setl %al
1000 ; CHECK-32-NEXT: retl
1001 ;
1002 ; CHECK-64-LABEL: not_isnan_f_strictfp:
1003 ; CHECK-64: # %bb.0: # %entry
1004 ; CHECK-64-NEXT: movd %xmm0, %eax
1005 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1006 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1007 ; CHECK-64-NEXT: setl %al
1008 ; CHECK-64-NEXT: retq
1009 entry:
1010 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) strictfp ; ~"nan"
1011 ret i1 %0
1012 }
1014 define i1 @isfinite_f_strictfp(float %x) strictfp {
1015 ; CHECK-32-LABEL: isfinite_f_strictfp:
1016 ; CHECK-32: # %bb.0: # %entry
1017 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1018 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1019 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1020 ; CHECK-32-NEXT: setl %al
1021 ; CHECK-32-NEXT: retl
1022 ;
1023 ; CHECK-64-LABEL: isfinite_f_strictfp:
1024 ; CHECK-64: # %bb.0: # %entry
1025 ; CHECK-64-NEXT: movd %xmm0, %eax
1026 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1027 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1028 ; CHECK-64-NEXT: setl %al
1029 ; CHECK-64-NEXT: retq
1030 entry:
1031 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) strictfp ; 0x1f8 = "finite"
1032 ret i1 %0
1033 }
1035 define i1 @not_isfinite_f_strictfp(float %x) strictfp {
1036 ; CHECK-32-LABEL: not_isfinite_f_strictfp:
1037 ; CHECK-32: # %bb.0: # %entry
1038 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1039 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1040 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1041 ; CHECK-32-NEXT: setge %al
1042 ; CHECK-32-NEXT: retl
1043 ;
1044 ; CHECK-64-LABEL: not_isfinite_f_strictfp:
1045 ; CHECK-64: # %bb.0: # %entry
1046 ; CHECK-64-NEXT: movd %xmm0, %eax
1047 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1048 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1049 ; CHECK-64-NEXT: setge %al
1050 ; CHECK-64-NEXT: retq
1051 entry:
1052 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; ~0x1f8 = ~"finite"
1053 ret i1 %0
1054 }
1056 define i1 @iszero_f_strictfp(float %x) strictfp {
1057 ; CHECK-32-LABEL: iszero_f_strictfp:
1058 ; CHECK-32: # %bb.0: # %entry
1059 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
1060 ; CHECK-32-NEXT: sete %al
1061 ; CHECK-32-NEXT: retl
1062 ;
1063 ; CHECK-64-LABEL: iszero_f_strictfp:
1064 ; CHECK-64: # %bb.0: # %entry
1065 ; CHECK-64-NEXT: movd %xmm0, %eax
1066 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
1067 ; CHECK-64-NEXT: sete %al
1068 ; CHECK-64-NEXT: retq
1069 entry:
1070 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp ; 0x60 = "zero"
1071 ret i1 %0
1072 }
1074 define i1 @not_iszero_f_strictfp(float %x) strictfp {
1075 ; CHECK-32-LABEL: not_iszero_f_strictfp:
1076 ; CHECK-32: # %bb.0: # %entry
1077 ; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
1078 ; CHECK-32-NEXT: setne %al
1079 ; CHECK-32-NEXT: retl
1080 ;
1081 ; CHECK-64-LABEL: not_iszero_f_strictfp:
1082 ; CHECK-64: # %bb.0: # %entry
1083 ; CHECK-64-NEXT: movd %xmm0, %eax
1084 ; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
1085 ; CHECK-64-NEXT: setne %al
1086 ; CHECK-64-NEXT: retq
1087 entry:
1088 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) strictfp ; ~0x60 = ~"zero"
1089 ret i1 %0
1090 }
1092 define i1 @isnan_d(double %x) {
1093 ; CHECK-32-LABEL: isnan_d:
1094 ; CHECK-32: # %bb.0: # %entry
1095 ; CHECK-32-NEXT: fldl {{[0-9]+}}(%esp)
1096 ; CHECK-32-NEXT: fucomp %st(0)
1097 ; CHECK-32-NEXT: fnstsw %ax
1098 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1099 ; CHECK-32-NEXT: sahf
1100 ; CHECK-32-NEXT: setp %al
1101 ; CHECK-32-NEXT: retl
1102 ;
1103 ; CHECK-64-LABEL: isnan_d:
1104 ; CHECK-64: # %bb.0: # %entry
1105 ; CHECK-64-NEXT: ucomisd %xmm0, %xmm0
1106 ; CHECK-64-NEXT: setp %al
1107 ; CHECK-64-NEXT: retq
1108 entry:
1109 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan"
1110 ret i1 %0
1111 }
1113 define i1 @isinf_d(double %x) {
1114 ; CHECK-32-LABEL: isinf_d:
1115 ; CHECK-32: # %bb.0: # %entry
1116 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1117 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1118 ; CHECK-32-NEXT: xorl $2146435072, %eax # imm = 0x7FF00000
1119 ; CHECK-32-NEXT: orl {{[0-9]+}}(%esp), %eax
1120 ; CHECK-32-NEXT: sete %al
1121 ; CHECK-32-NEXT: retl
1122 ;
1123 ; CHECK-64-LABEL: isinf_d:
1124 ; CHECK-64: # %bb.0: # %entry
1125 ; CHECK-64-NEXT: movq %xmm0, %rax
1126 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1127 ; CHECK-64-NEXT: andq %rax, %rcx
1128 ; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
1129 ; CHECK-64-NEXT: cmpq %rax, %rcx
1130 ; CHECK-64-NEXT: sete %al
1131 ; CHECK-64-NEXT: retq
1132 entry:
1133 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; 0x204 = "inf"
1134 ret i1 %0
1135 }
1137 define i1 @isfinite_d(double %x) {
1138 ; CHECK-32-LABEL: isfinite_d:
1139 ; CHECK-32: # %bb.0: # %entry
1140 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1141 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1142 ; CHECK-32-NEXT: cmpl $2146435072, %eax # imm = 0x7FF00000
1143 ; CHECK-32-NEXT: setl %al
1144 ; CHECK-32-NEXT: retl
1145 ;
1146 ; CHECK-64-LABEL: isfinite_d:
1147 ; CHECK-64: # %bb.0: # %entry
1148 ; CHECK-64-NEXT: movq %xmm0, %rax
1149 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1150 ; CHECK-64-NEXT: andq %rax, %rcx
1151 ; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
1152 ; CHECK-64-NEXT: cmpq %rax, %rcx
1153 ; CHECK-64-NEXT: setl %al
1154 ; CHECK-64-NEXT: retq
1155 entry:
1156 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"
1157 ret i1 %0
1158 }
1160 define i1 @isnormal_d(double %x) {
1161 ; CHECK-32-LABEL: isnormal_d:
1162 ; CHECK-32: # %bb.0: # %entry
1163 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1164 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1165 ; CHECK-32-NEXT: addl $-1048576, %eax # imm = 0xFFF00000
1166 ; CHECK-32-NEXT: shrl $21, %eax
1167 ; CHECK-32-NEXT: cmpl $1023, %eax # imm = 0x3FF
1168 ; CHECK-32-NEXT: setb %al
1169 ; CHECK-32-NEXT: retl
1170 ;
1171 ; CHECK-64-LABEL: isnormal_d:
1172 ; CHECK-64: # %bb.0: # %entry
1173 ; CHECK-64-NEXT: movq %xmm0, %rax
1174 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1175 ; CHECK-64-NEXT: andq %rax, %rcx
1176 ; CHECK-64-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
1177 ; CHECK-64-NEXT: addq %rcx, %rax
1178 ; CHECK-64-NEXT: shrq $53, %rax
1179 ; CHECK-64-NEXT: cmpl $1023, %eax # imm = 0x3FF
1180 ; CHECK-64-NEXT: setb %al
1181 ; CHECK-64-NEXT: retq
1182 entry:
1183 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264) ; 0x108 = "normal"
1184 ret i1 %0
1185 }
1187 define i1 @issubnormal_d(double %x) {
1188 ; CHECK-32-LABEL: issubnormal_d:
1189 ; CHECK-32: # %bb.0: # %entry
1190 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
1191 ; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
1192 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx
1193 ; CHECK-32-NEXT: addl $-1, %eax
1194 ; CHECK-32-NEXT: adcl $-1, %ecx
1195 ; CHECK-32-NEXT: cmpl $-1, %eax
1196 ; CHECK-32-NEXT: sbbl $1048575, %ecx # imm = 0xFFFFF
1197 ; CHECK-32-NEXT: setb %al
1198 ; CHECK-32-NEXT: retl
1199 ;
1200 ; CHECK-64-LABEL: issubnormal_d:
1201 ; CHECK-64: # %bb.0: # %entry
1202 ; CHECK-64-NEXT: movq %xmm0, %rax
1203 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1204 ; CHECK-64-NEXT: andq %rax, %rcx
1205 ; CHECK-64-NEXT: decq %rcx
1206 ; CHECK-64-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
1207 ; CHECK-64-NEXT: cmpq %rax, %rcx
1208 ; CHECK-64-NEXT: setb %al
1209 ; CHECK-64-NEXT: retq
1210 entry:
1211 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144) ; 0x90 = "subnormal"
1212 ret i1 %0
1213 }
1215 define i1 @iszero_d(double %x) {
1216 ; CHECK-32-LABEL: iszero_d:
1217 ; CHECK-32: # %bb.0: # %entry
1218 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1219 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1220 ; CHECK-32-NEXT: orl {{[0-9]+}}(%esp), %eax
1221 ; CHECK-32-NEXT: sete %al
1222 ; CHECK-32-NEXT: retl
1223 ;
1224 ; CHECK-64-LABEL: iszero_d:
1225 ; CHECK-64: # %bb.0: # %entry
1226 ; CHECK-64-NEXT: movq %xmm0, %rax
1227 ; CHECK-64-NEXT: shlq %rax
1228 ; CHECK-64-NEXT: testq %rax, %rax
1229 ; CHECK-64-NEXT: sete %al
1230 ; CHECK-64-NEXT: retq
1231 entry:
1232 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero"
1233 ret i1 %0
1234 }
1236 define i1 @issignaling_d(double %x) {
1237 ; CHECK-32-LABEL: issignaling_d:
1238 ; CHECK-32: # %bb.0: # %entry
1239 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1240 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1241 ; CHECK-32-NEXT: xorl %ecx, %ecx
1242 ; CHECK-32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
1243 ; CHECK-32-NEXT: movl $2146435072, %ecx # imm = 0x7FF00000
1244 ; CHECK-32-NEXT: sbbl %eax, %ecx
1245 ; CHECK-32-NEXT: setl %cl
1246 ; CHECK-32-NEXT: cmpl $2146959360, %eax # imm = 0x7FF80000
1247 ; CHECK-32-NEXT: setl %al
1248 ; CHECK-32-NEXT: andb %cl, %al
1249 ; CHECK-32-NEXT: retl
1250 ;
1251 ; CHECK-64-LABEL: issignaling_d:
1252 ; CHECK-64: # %bb.0: # %entry
1253 ; CHECK-64-NEXT: movq %xmm0, %rax
1254 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1255 ; CHECK-64-NEXT: andq %rax, %rcx
1256 ; CHECK-64-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
1257 ; CHECK-64-NEXT: cmpq %rax, %rcx
1258 ; CHECK-64-NEXT: setl %dl
1259 ; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
1260 ; CHECK-64-NEXT: cmpq %rax, %rcx
1261 ; CHECK-64-NEXT: setg %al
1262 ; CHECK-64-NEXT: andb %dl, %al
1263 ; CHECK-64-NEXT: retq
1264 entry:
1265 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1) ; "snan"
1266 ret i1 %0
1267 }
1269 define i1 @isquiet_d(double %x) {
1270 ; CHECK-32-LABEL: isquiet_d:
1271 ; CHECK-32: # %bb.0: # %entry
1272 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1273 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1274 ; CHECK-32-NEXT: cmpl $2146959360, %eax # imm = 0x7FF80000
1275 ; CHECK-32-NEXT: setge %al
1276 ; CHECK-32-NEXT: retl
1277 ;
1278 ; CHECK-64-LABEL: isquiet_d:
1279 ; CHECK-64: # %bb.0: # %entry
1280 ; CHECK-64-NEXT: movq %xmm0, %rax
1281 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1282 ; CHECK-64-NEXT: andq %rax, %rcx
1283 ; CHECK-64-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
1284 ; CHECK-64-NEXT: cmpq %rax, %rcx
1285 ; CHECK-64-NEXT: setg %al
1286 ; CHECK-64-NEXT: retq
1287 entry:
1288 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2) ; "qnan"
1289 ret i1 %0
1290 }
1292 define i1 @isnan_d_strictfp(double %x) strictfp {
1293 ; CHECK-32-LABEL: isnan_d_strictfp:
1294 ; CHECK-32: # %bb.0: # %entry
1295 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1296 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1297 ; CHECK-32-NEXT: xorl %ecx, %ecx
1298 ; CHECK-32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
1299 ; CHECK-32-NEXT: movl $2146435072, %ecx # imm = 0x7FF00000
1300 ; CHECK-32-NEXT: sbbl %eax, %ecx
1301 ; CHECK-32-NEXT: setl %al
1302 ; CHECK-32-NEXT: retl
1303 ;
1304 ; CHECK-64-LABEL: isnan_d_strictfp:
1305 ; CHECK-64: # %bb.0: # %entry
1306 ; CHECK-64-NEXT: movq %xmm0, %rax
1307 ; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
1308 ; CHECK-64-NEXT: andq %rax, %rcx
1309 ; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
1310 ; CHECK-64-NEXT: cmpq %rax, %rcx
1311 ; CHECK-64-NEXT: setg %al
1312 ; CHECK-64-NEXT: retq
1313 entry:
1314 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) strictfp ; "nan"
1315 ret i1 %0
1316 }
1318 define i1 @iszero_d_strictfp(double %x) strictfp {
1319 ; CHECK-32-LABEL: iszero_d_strictfp:
1320 ; CHECK-32: # %bb.0: # %entry
1321 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1322 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1323 ; CHECK-32-NEXT: orl {{[0-9]+}}(%esp), %eax
1324 ; CHECK-32-NEXT: sete %al
1325 ; CHECK-32-NEXT: retl
1326 ;
1327 ; CHECK-64-LABEL: iszero_d_strictfp:
1328 ; CHECK-64: # %bb.0: # %entry
1329 ; CHECK-64-NEXT: movq %xmm0, %rax
1330 ; CHECK-64-NEXT: shlq %rax
1331 ; CHECK-64-NEXT: testq %rax, %rax
1332 ; CHECK-64-NEXT: sete %al
1333 ; CHECK-64-NEXT: retq
1334 entry:
1335 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) strictfp ; 0x60 = "zero"
1336 ret i1 %0
1337 }
1341 define <1 x i1> @isnan_v1f(<1 x float> %x) {
1342 ; CHECK-32-LABEL: isnan_v1f:
1343 ; CHECK-32: # %bb.0: # %entry
1344 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1345 ; CHECK-32-NEXT: fucomp %st(0)
1346 ; CHECK-32-NEXT: fnstsw %ax
1347 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1348 ; CHECK-32-NEXT: sahf
1349 ; CHECK-32-NEXT: setp %al
1350 ; CHECK-32-NEXT: retl
1351 ;
1352 ; CHECK-64-LABEL: isnan_v1f:
1353 ; CHECK-64: # %bb.0: # %entry
1354 ; CHECK-64-NEXT: ucomiss %xmm0, %xmm0
1355 ; CHECK-64-NEXT: setp %al
1356 ; CHECK-64-NEXT: retq
1357 entry:
1358 %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) ; "nan"
1359 ret <1 x i1> %0
1360 }
1362 define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp {
1363 ; CHECK-32-LABEL: isnan_v1f_strictfp:
1364 ; CHECK-32: # %bb.0: # %entry
1365 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1366 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1367 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1368 ; CHECK-32-NEXT: setge %al
1369 ; CHECK-32-NEXT: retl
1370 ;
1371 ; CHECK-64-LABEL: isnan_v1f_strictfp:
1372 ; CHECK-64: # %bb.0: # %entry
1373 ; CHECK-64-NEXT: movd %xmm0, %eax
1374 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1375 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1376 ; CHECK-64-NEXT: setge %al
1377 ; CHECK-64-NEXT: retq
1378 entry:
1379 %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) strictfp ; "nan"
1380 ret <1 x i1> %0
1381 }
1383 define <2 x i1> @isnan_v2f(<2 x float> %x) {
1384 ; CHECK-32-LABEL: isnan_v2f:
1385 ; CHECK-32: # %bb.0: # %entry
1386 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1387 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1388 ; CHECK-32-NEXT: fucomp %st(0)
1389 ; CHECK-32-NEXT: fnstsw %ax
1390 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1391 ; CHECK-32-NEXT: sahf
1392 ; CHECK-32-NEXT: setp %cl
1393 ; CHECK-32-NEXT: fucomp %st(0)
1394 ; CHECK-32-NEXT: fnstsw %ax
1395 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1396 ; CHECK-32-NEXT: sahf
1397 ; CHECK-32-NEXT: setp %dl
1398 ; CHECK-32-NEXT: movl %ecx, %eax
1399 ; CHECK-32-NEXT: retl
1400 ;
1401 ; CHECK-64-LABEL: isnan_v2f:
1402 ; CHECK-64: # %bb.0: # %entry
1403 ; CHECK-64-NEXT: cmpunordps %xmm0, %xmm0
1404 ; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
1405 ; CHECK-64-NEXT: retq
1406 entry:
1407 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) ; "nan"
1408 ret <2 x i1> %0
1409 }
1412 define <2 x i1> @isnot_nan_v2f(<2 x float> %x) {
1413 ; CHECK-32-LABEL: isnot_nan_v2f:
1414 ; CHECK-32: # %bb.0: # %entry
1415 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1416 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1417 ; CHECK-32-NEXT: fucomp %st(0)
1418 ; CHECK-32-NEXT: fnstsw %ax
1419 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1420 ; CHECK-32-NEXT: sahf
1421 ; CHECK-32-NEXT: setnp %cl
1422 ; CHECK-32-NEXT: fucomp %st(0)
1423 ; CHECK-32-NEXT: fnstsw %ax
1424 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1425 ; CHECK-32-NEXT: sahf
1426 ; CHECK-32-NEXT: setnp %dl
1427 ; CHECK-32-NEXT: movl %ecx, %eax
1428 ; CHECK-32-NEXT: retl
1429 ;
1430 ; CHECK-64-LABEL: isnot_nan_v2f:
1431 ; CHECK-64: # %bb.0: # %entry
1432 ; CHECK-64-NEXT: cmpordps %xmm0, %xmm0
1433 ; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
1434 ; CHECK-64-NEXT: retq
1435 entry:
1436 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
1437 ret <2 x i1> %0
1438 }
1440 define <2 x i1> @isnan_v2f_strictfp(<2 x float> %x) strictfp {
1441 ; CHECK-32-LABEL: isnan_v2f_strictfp:
1442 ; CHECK-32: # %bb.0: # %entry
1443 ; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
1444 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
1445 ; CHECK-32-NEXT: andl %ecx, %eax
1446 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1447 ; CHECK-32-NEXT: setge %al
1448 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx
1449 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
1450 ; CHECK-32-NEXT: setge %dl
1451 ; CHECK-32-NEXT: retl
1452 ;
1453 ; CHECK-64-LABEL: isnan_v2f_strictfp:
1454 ; CHECK-64: # %bb.0: # %entry
1455 ; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
1456 ; CHECK-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1457 ; CHECK-64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1458 ; CHECK-64-NEXT: retq
1459 entry:
1460 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) strictfp ; "nan"
1461 ret <2 x i1> %0
1462 }
1464 define <4 x i1> @isnan_v4f(<4 x float> %x) {
1465 ; CHECK-32-LABEL: isnan_v4f:
1466 ; CHECK-32: # %bb.0: # %entry
1467 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
1468 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1469 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1470 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1471 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1472 ; CHECK-32-NEXT: fucomp %st(0)
1473 ; CHECK-32-NEXT: fnstsw %ax
1474 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1475 ; CHECK-32-NEXT: sahf
1476 ; CHECK-32-NEXT: setp %dh
1477 ; CHECK-32-NEXT: shlb $2, %dh
1478 ; CHECK-32-NEXT: fucomp %st(0)
1479 ; CHECK-32-NEXT: fnstsw %ax
1480 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1481 ; CHECK-32-NEXT: sahf
1482 ; CHECK-32-NEXT: setp %dl
1483 ; CHECK-32-NEXT: shlb $3, %dl
1484 ; CHECK-32-NEXT: orb %dh, %dl
1485 ; CHECK-32-NEXT: fucomp %st(0)
1486 ; CHECK-32-NEXT: fnstsw %ax
1487 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1488 ; CHECK-32-NEXT: sahf
1489 ; CHECK-32-NEXT: setp %dh
1490 ; CHECK-32-NEXT: fucomp %st(0)
1491 ; CHECK-32-NEXT: fnstsw %ax
1492 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1493 ; CHECK-32-NEXT: sahf
1494 ; CHECK-32-NEXT: setp %al
1495 ; CHECK-32-NEXT: addb %al, %al
1496 ; CHECK-32-NEXT: orb %dh, %al
1497 ; CHECK-32-NEXT: orb %dl, %al
1498 ; CHECK-32-NEXT: movb %al, (%ecx)
1499 ; CHECK-32-NEXT: movl %ecx, %eax
1500 ; CHECK-32-NEXT: retl $4
1501 ;
1502 ; CHECK-64-LABEL: isnan_v4f:
1503 ; CHECK-64: # %bb.0: # %entry
1504 ; CHECK-64-NEXT: cmpunordps %xmm0, %xmm0
1505 ; CHECK-64-NEXT: retq
1506 entry:
1507 %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; "nan"
1508 ret <4 x i1> %0
1509 }
1511 define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
1512 ; CHECK-32-LABEL: isnan_v4f_strictfp:
1513 ; CHECK-32: # %bb.0: # %entry
1514 ; CHECK-32-NEXT: pushl %esi
1515 ; CHECK-32-NEXT: .cfi_def_cfa_offset 8
1516 ; CHECK-32-NEXT: .cfi_offset %esi, -8
1517 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
1518 ; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
1519 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx
1520 ; CHECK-32-NEXT: andl %ecx, %edx
1521 ; CHECK-32-NEXT: cmpl $2139095041, %edx # imm = 0x7F800001
1522 ; CHECK-32-NEXT: setge %dh
1523 ; CHECK-32-NEXT: shlb $2, %dh
1524 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %esi
1525 ; CHECK-32-NEXT: andl %ecx, %esi
1526 ; CHECK-32-NEXT: cmpl $2139095041, %esi # imm = 0x7F800001
1527 ; CHECK-32-NEXT: setge %dl
1528 ; CHECK-32-NEXT: shlb $3, %dl
1529 ; CHECK-32-NEXT: orb %dh, %dl
1530 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %esi
1531 ; CHECK-32-NEXT: andl %ecx, %esi
1532 ; CHECK-32-NEXT: cmpl $2139095041, %esi # imm = 0x7F800001
1533 ; CHECK-32-NEXT: setge %dh
1534 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx
1535 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
1536 ; CHECK-32-NEXT: setge %cl
1537 ; CHECK-32-NEXT: addb %cl, %cl
1538 ; CHECK-32-NEXT: orb %dh, %cl
1539 ; CHECK-32-NEXT: orb %dl, %cl
1540 ; CHECK-32-NEXT: movb %cl, (%eax)
1541 ; CHECK-32-NEXT: popl %esi
1542 ; CHECK-32-NEXT: .cfi_def_cfa_offset 4
1543 ; CHECK-32-NEXT: retl $4
1544 ;
1545 ; CHECK-64-LABEL: isnan_v4f_strictfp:
1546 ; CHECK-64: # %bb.0: # %entry
1547 ; CHECK-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1548 ; CHECK-64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1549 ; CHECK-64-NEXT: retq
1550 entry:
1551 %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) strictfp ; "nan"
1552 ret <4 x i1> %0
1553 }
1555 define i1 @isnone_f(float %x) {
1556 ; CHECK-32-LABEL: isnone_f:
1557 ; CHECK-32: # %bb.0: # %entry
1558 ; CHECK-32-NEXT: xorl %eax, %eax
1559 ; CHECK-32-NEXT: retl
1560 ;
1561 ; CHECK-64-LABEL: isnone_f:
1562 ; CHECK-64: # %bb.0: # %entry
1563 ; CHECK-64-NEXT: xorl %eax, %eax
1564 ; CHECK-64-NEXT: retq
1565 entry:
1566 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
1567 ret i1 %0
1568 }
1570 define i1 @isany_f(float %x) {
1571 ; CHECK-32-LABEL: isany_f:
1572 ; CHECK-32: # %bb.0: # %entry
1573 ; CHECK-32-NEXT: movb $1, %al
1574 ; CHECK-32-NEXT: retl
1575 ;
1576 ; CHECK-64-LABEL: isany_f:
1577 ; CHECK-64: # %bb.0: # %entry
1578 ; CHECK-64-NEXT: movb $1, %al
1579 ; CHECK-64-NEXT: retq
1580 entry:
1581 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
1582 ret i1 %0
1583 }
1586 define i1 @iszero_or_nan_f(float %x) {
1587 ; CHECK-32-LABEL: iszero_or_nan_f:
1588 ; CHECK-32: # %bb.0: # %entry
1589 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1590 ; CHECK-32-NEXT: fldz
1591 ; CHECK-32-NEXT: fucompp
1592 ; CHECK-32-NEXT: fnstsw %ax
1593 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1594 ; CHECK-32-NEXT: sahf
1595 ; CHECK-32-NEXT: sete %al
1596 ; CHECK-32-NEXT: retl
1597 ;
1598 ; CHECK-64-LABEL: iszero_or_nan_f:
1599 ; CHECK-64: # %bb.0: # %entry
1600 ; CHECK-64-NEXT: xorps %xmm1, %xmm1
1601 ; CHECK-64-NEXT: ucomiss %xmm1, %xmm0
1602 ; CHECK-64-NEXT: sete %al
1603 ; CHECK-64-NEXT: retq
1604 entry:
1605 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
1606 ret i1 %0
1607 }
1609 define i1 @iszero_or_nan_f_daz(float %x) #0 {
1610 ; CHECK-32-LABEL: iszero_or_nan_f_daz:
1611 ; CHECK-32: # %bb.0: # %entry
1612 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1613 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1614 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1615 ; CHECK-32-NEXT: setge %cl
1616 ; CHECK-32-NEXT: testl %eax, %eax
1617 ; CHECK-32-NEXT: sete %al
1618 ; CHECK-32-NEXT: orb %cl, %al
1619 ; CHECK-32-NEXT: retl
1620 ;
1621 ; CHECK-64-LABEL: iszero_or_nan_f_daz:
1622 ; CHECK-64: # %bb.0: # %entry
1623 ; CHECK-64-NEXT: movd %xmm0, %eax
1624 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1625 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1626 ; CHECK-64-NEXT: setge %cl
1627 ; CHECK-64-NEXT: testl %eax, %eax
1628 ; CHECK-64-NEXT: sete %al
1629 ; CHECK-64-NEXT: orb %cl, %al
1630 ; CHECK-64-NEXT: retq
1631 entry:
1632 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
1633 ret i1 %0
1634 }
1636 define i1 @iszero_or_nan_f_maybe_daz(float %x) #1 {
1637 ; CHECK-32-LABEL: iszero_or_nan_f_maybe_daz:
1638 ; CHECK-32: # %bb.0: # %entry
1639 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1640 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1641 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1642 ; CHECK-32-NEXT: setge %cl
1643 ; CHECK-32-NEXT: testl %eax, %eax
1644 ; CHECK-32-NEXT: sete %al
1645 ; CHECK-32-NEXT: orb %cl, %al
1646 ; CHECK-32-NEXT: retl
1647 ;
1648 ; CHECK-64-LABEL: iszero_or_nan_f_maybe_daz:
1649 ; CHECK-64: # %bb.0: # %entry
1650 ; CHECK-64-NEXT: movd %xmm0, %eax
1651 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1652 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1653 ; CHECK-64-NEXT: setge %cl
1654 ; CHECK-64-NEXT: testl %eax, %eax
1655 ; CHECK-64-NEXT: sete %al
1656 ; CHECK-64-NEXT: orb %cl, %al
1657 ; CHECK-64-NEXT: retq
1658 entry:
1659 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
1660 ret i1 %0
1661 }
1663 define i1 @not_iszero_or_nan_f(float %x) {
1664 ; CHECK-32-LABEL: not_iszero_or_nan_f:
1665 ; CHECK-32: # %bb.0: # %entry
1666 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
1667 ; CHECK-32-NEXT: fldz
1668 ; CHECK-32-NEXT: fucompp
1669 ; CHECK-32-NEXT: fnstsw %ax
1670 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
1671 ; CHECK-32-NEXT: sahf
1672 ; CHECK-32-NEXT: setne %al
1673 ; CHECK-32-NEXT: retl
1674 ;
1675 ; CHECK-64-LABEL: not_iszero_or_nan_f:
1676 ; CHECK-64: # %bb.0: # %entry
1677 ; CHECK-64-NEXT: xorps %xmm1, %xmm1
1678 ; CHECK-64-NEXT: ucomiss %xmm1, %xmm0
1679 ; CHECK-64-NEXT: setne %al
1680 ; CHECK-64-NEXT: retq
1681 entry:
1682 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~0x60 = "~(zero|nan)"
1683 ret i1 %0
1684 }
1686 define i1 @not_iszero_or_nan_f_daz(float %x) #0 {
1687 ; CHECK-32-LABEL: not_iszero_or_nan_f_daz:
1688 ; CHECK-32: # %bb.0: # %entry
1689 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1690 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1691 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1692 ; CHECK-32-NEXT: setl %cl
1693 ; CHECK-32-NEXT: testl %eax, %eax
1694 ; CHECK-32-NEXT: setne %al
1695 ; CHECK-32-NEXT: andb %cl, %al
1696 ; CHECK-32-NEXT: retl
1697 ;
1698 ; CHECK-64-LABEL: not_iszero_or_nan_f_daz:
1699 ; CHECK-64: # %bb.0: # %entry
1700 ; CHECK-64-NEXT: movd %xmm0, %eax
1701 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1702 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1703 ; CHECK-64-NEXT: setl %cl
1704 ; CHECK-64-NEXT: testl %eax, %eax
1705 ; CHECK-64-NEXT: setne %al
1706 ; CHECK-64-NEXT: andb %cl, %al
1707 ; CHECK-64-NEXT: retq
1708 entry:
1709 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
1710 ret i1 %0
1711 }
1713 define i1 @not_iszero_or_nan_f_maybe_daz(float %x) #1 {
1714 ; CHECK-32-LABEL: not_iszero_or_nan_f_maybe_daz:
1715 ; CHECK-32: # %bb.0: # %entry
1716 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1717 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1718 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1719 ; CHECK-32-NEXT: setl %cl
1720 ; CHECK-32-NEXT: testl %eax, %eax
1721 ; CHECK-32-NEXT: setne %al
1722 ; CHECK-32-NEXT: andb %cl, %al
1723 ; CHECK-32-NEXT: retl
1724 ;
1725 ; CHECK-64-LABEL: not_iszero_or_nan_f_maybe_daz:
1726 ; CHECK-64: # %bb.0: # %entry
1727 ; CHECK-64-NEXT: movd %xmm0, %eax
1728 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1729 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1730 ; CHECK-64-NEXT: setl %cl
1731 ; CHECK-64-NEXT: testl %eax, %eax
1732 ; CHECK-64-NEXT: setne %al
1733 ; CHECK-64-NEXT: andb %cl, %al
1734 ; CHECK-64-NEXT: retq
1735 entry:
1736 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
1737 ret i1 %0
1738 }
1740 define i1 @iszero_or_qnan_f(float %x) {
1741 ; CHECK-32-LABEL: iszero_or_qnan_f:
1742 ; CHECK-32: # %bb.0: # %entry
1743 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1744 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1745 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1746 ; CHECK-32-NEXT: setge %cl
1747 ; CHECK-32-NEXT: testl %eax, %eax
1748 ; CHECK-32-NEXT: sete %al
1749 ; CHECK-32-NEXT: orb %cl, %al
1750 ; CHECK-32-NEXT: retl
1751 ;
1752 ; CHECK-64-LABEL: iszero_or_qnan_f:
1753 ; CHECK-64: # %bb.0: # %entry
1754 ; CHECK-64-NEXT: movd %xmm0, %eax
1755 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1756 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1757 ; CHECK-64-NEXT: setge %cl
1758 ; CHECK-64-NEXT: testl %eax, %eax
1759 ; CHECK-64-NEXT: sete %al
1760 ; CHECK-64-NEXT: orb %cl, %al
1761 ; CHECK-64-NEXT: retq
1762 entry:
1763 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 98) ; 0x60|0x2 = "zero|qnan"
1764 ret i1 %0
1765 }
1767 define i1 @iszero_or_snan_f(float %x) {
1768 ; CHECK-32-LABEL: iszero_or_snan_f:
1769 ; CHECK-32: # %bb.0: # %entry
1770 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1771 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1772 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1773 ; CHECK-32-NEXT: setl %cl
1774 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1775 ; CHECK-32-NEXT: setge %dl
1776 ; CHECK-32-NEXT: andb %cl, %dl
1777 ; CHECK-32-NEXT: testl %eax, %eax
1778 ; CHECK-32-NEXT: sete %al
1779 ; CHECK-32-NEXT: orb %dl, %al
1780 ; CHECK-32-NEXT: retl
1781 ;
1782 ; CHECK-64-LABEL: iszero_or_snan_f:
1783 ; CHECK-64: # %bb.0: # %entry
1784 ; CHECK-64-NEXT: movd %xmm0, %eax
1785 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1786 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1787 ; CHECK-64-NEXT: setl %cl
1788 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1789 ; CHECK-64-NEXT: setge %dl
1790 ; CHECK-64-NEXT: andb %cl, %dl
1791 ; CHECK-64-NEXT: testl %eax, %eax
1792 ; CHECK-64-NEXT: sete %al
1793 ; CHECK-64-NEXT: orb %dl, %al
1794 ; CHECK-64-NEXT: retq
1795 entry:
1796 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 97) ; 0x60|0x1 = "zero|snan"
1797 ret i1 %0
1798 }
1800 define i1 @not_iszero_or_qnan_f(float %x) {
1801 ; CHECK-32-LABEL: not_iszero_or_qnan_f:
1802 ; CHECK-32: # %bb.0: # %entry
1803 ; CHECK-32-NEXT: pushl %esi
1804 ; CHECK-32-NEXT: .cfi_def_cfa_offset 8
1805 ; CHECK-32-NEXT: .cfi_offset %esi, -8
1806 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1807 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1808 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1809 ; CHECK-32-NEXT: setl %cl
1810 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1811 ; CHECK-32-NEXT: setge %dl
1812 ; CHECK-32-NEXT: andb %cl, %dl
1813 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1814 ; CHECK-32-NEXT: sete %cl
1815 ; CHECK-32-NEXT: leal -1(%eax), %esi
1816 ; CHECK-32-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
1817 ; CHECK-32-NEXT: setb %ch
1818 ; CHECK-32-NEXT: orb %cl, %ch
1819 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
1820 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
1821 ; CHECK-32-NEXT: setb %al
1822 ; CHECK-32-NEXT: orb %dl, %al
1823 ; CHECK-32-NEXT: orb %ch, %al
1824 ; CHECK-32-NEXT: popl %esi
1825 ; CHECK-32-NEXT: .cfi_def_cfa_offset 4
1826 ; CHECK-32-NEXT: retl
1827 ;
1828 ; CHECK-64-LABEL: not_iszero_or_qnan_f:
1829 ; CHECK-64: # %bb.0: # %entry
1830 ; CHECK-64-NEXT: movd %xmm0, %eax
1831 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1832 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1833 ; CHECK-64-NEXT: setl %cl
1834 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1835 ; CHECK-64-NEXT: setge %dl
1836 ; CHECK-64-NEXT: andb %cl, %dl
1837 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1838 ; CHECK-64-NEXT: sete %cl
1839 ; CHECK-64-NEXT: leal -1(%rax), %esi
1840 ; CHECK-64-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
1841 ; CHECK-64-NEXT: setb %sil
1842 ; CHECK-64-NEXT: orb %cl, %sil
1843 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
1844 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
1845 ; CHECK-64-NEXT: setb %al
1846 ; CHECK-64-NEXT: orb %dl, %al
1847 ; CHECK-64-NEXT: orb %sil, %al
1848 ; CHECK-64-NEXT: retq
1849 entry:
1850 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 925) ; ~(0x60|0x2) = "~(zero|qnan)"
1851 ret i1 %0
1852 }
1854 define i1 @not_iszero_or_snan_f(float %x) {
1855 ; CHECK-32-LABEL: not_iszero_or_snan_f:
1856 ; CHECK-32: # %bb.0: # %entry
1857 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1858 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1859 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1860 ; CHECK-32-NEXT: sete %cl
1861 ; CHECK-32-NEXT: leal -1(%eax), %edx
1862 ; CHECK-32-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
1863 ; CHECK-32-NEXT: setb %dl
1864 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1865 ; CHECK-32-NEXT: setge %ch
1866 ; CHECK-32-NEXT: orb %cl, %ch
1867 ; CHECK-32-NEXT: orb %dl, %ch
1868 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
1869 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
1870 ; CHECK-32-NEXT: setb %al
1871 ; CHECK-32-NEXT: orb %ch, %al
1872 ; CHECK-32-NEXT: retl
1873 ;
1874 ; CHECK-64-LABEL: not_iszero_or_snan_f:
1875 ; CHECK-64: # %bb.0: # %entry
1876 ; CHECK-64-NEXT: movd %xmm0, %eax
1877 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1878 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1879 ; CHECK-64-NEXT: sete %cl
1880 ; CHECK-64-NEXT: leal -1(%rax), %edx
1881 ; CHECK-64-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
1882 ; CHECK-64-NEXT: setb %dl
1883 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
1884 ; CHECK-64-NEXT: setge %sil
1885 ; CHECK-64-NEXT: orb %cl, %sil
1886 ; CHECK-64-NEXT: orb %dl, %sil
1887 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
1888 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
1889 ; CHECK-64-NEXT: setb %al
1890 ; CHECK-64-NEXT: orb %sil, %al
1891 ; CHECK-64-NEXT: retq
1892 entry:
1893 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 926) ; ~(0x60|0x1) = "~(zero|snan)"
1894 ret i1 %0
1895 }
1897 define i1 @isinf_or_nan_f(float %x) {
1898 ; CHECK-32-LABEL: isinf_or_nan_f:
1899 ; CHECK-32: # %bb.0: # %entry
1900 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1901 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1902 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1903 ; CHECK-32-NEXT: setge %al
1904 ; CHECK-32-NEXT: retl
1905 ;
1906 ; CHECK-64-LABEL: isinf_or_nan_f:
1907 ; CHECK-64: # %bb.0: # %entry
1908 ; CHECK-64-NEXT: movd %xmm0, %eax
1909 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1910 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1911 ; CHECK-64-NEXT: setge %al
1912 ; CHECK-64-NEXT: retq
1913 entry:
1914 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; 0x204|0x3 = "inf|nan"
1915 ret i1 %0
1916 }
1918 define i1 @not_isinf_or_nan_f(float %x) {
1919 ; CHECK-32-LABEL: not_isinf_or_nan_f:
1920 ; CHECK-32: # %bb.0: # %entry
1921 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1922 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1923 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1924 ; CHECK-32-NEXT: setl %al
1925 ; CHECK-32-NEXT: retl
1926 ;
1927 ; CHECK-64-LABEL: not_isinf_or_nan_f:
1928 ; CHECK-64: # %bb.0: # %entry
1929 ; CHECK-64-NEXT: movd %xmm0, %eax
1930 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1931 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1932 ; CHECK-64-NEXT: setl %al
1933 ; CHECK-64-NEXT: retq
1934 entry:
1935 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
1936 ret i1 %0
1937 }
1939 define i1 @isfinite_or_nan_f(float %x) {
1940 ; CHECK-32-LABEL: isfinite_or_nan_f:
1941 ; CHECK-32: # %bb.0: # %entry
1942 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1943 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1944 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1945 ; CHECK-32-NEXT: setne %al
1946 ; CHECK-32-NEXT: retl
1947 ;
1948 ; CHECK-64-LABEL: isfinite_or_nan_f:
1949 ; CHECK-64: # %bb.0: # %entry
1950 ; CHECK-64-NEXT: movd %xmm0, %eax
1951 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1952 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1953 ; CHECK-64-NEXT: setne %al
1954 ; CHECK-64-NEXT: retq
1955 entry:
1956 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; 0x1f8|0x3 = "finite|nan"
1957 ret i1 %0
1958 }
1960 define i1 @not_isfinite_or_nan_f(float %x) {
1961 ; CHECK-32-LABEL: not_isfinite_or_nan_f:
1962 ; CHECK-32: # %bb.0: # %entry
1963 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
1964 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
1965 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1966 ; CHECK-32-NEXT: sete %al
1967 ; CHECK-32-NEXT: retl
1968 ;
1969 ; CHECK-64-LABEL: not_isfinite_or_nan_f:
1970 ; CHECK-64: # %bb.0: # %entry
1971 ; CHECK-64-NEXT: movd %xmm0, %eax
1972 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1973 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1974 ; CHECK-64-NEXT: sete %al
1975 ; CHECK-64-NEXT: retq
1976 entry:
1977 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"
1978 ret i1 %0
1979 }
1981 define i1 @is_plus_inf_or_nan_f(float %x) {
1982 ; CHECK-32-LABEL: is_plus_inf_or_nan_f:
1983 ; CHECK-32: # %bb.0:
1984 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
1985 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1986 ; CHECK-32-NEXT: sete %cl
1987 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1988 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
1989 ; CHECK-32-NEXT: setge %al
1990 ; CHECK-32-NEXT: orb %cl, %al
1991 ; CHECK-32-NEXT: retl
1992 ;
1993 ; CHECK-64-LABEL: is_plus_inf_or_nan_f:
1994 ; CHECK-64: # %bb.0:
1995 ; CHECK-64-NEXT: movd %xmm0, %eax
1996 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
1997 ; CHECK-64-NEXT: sete %cl
1998 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
1999 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2000 ; CHECK-64-NEXT: setge %al
2001 ; CHECK-64-NEXT: orb %cl, %al
2002 ; CHECK-64-NEXT: retq
2003 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; 0x200|0x3 = "+inf|nan"
2004 ret i1 %class
2005 }
2007 define i1 @is_minus_inf_or_nan_f(float %x) {
2008 ; CHECK-32-LABEL: is_minus_inf_or_nan_f:
2009 ; CHECK-32: # %bb.0:
2010 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2011 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2012 ; CHECK-32-NEXT: sete %cl
2013 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2014 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2015 ; CHECK-32-NEXT: setge %al
2016 ; CHECK-32-NEXT: orb %cl, %al
2017 ; CHECK-32-NEXT: retl
2018 ;
2019 ; CHECK-64-LABEL: is_minus_inf_or_nan_f:
2020 ; CHECK-64: # %bb.0:
2021 ; CHECK-64-NEXT: movd %xmm0, %eax
2022 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2023 ; CHECK-64-NEXT: sete %cl
2024 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2025 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2026 ; CHECK-64-NEXT: setge %al
2027 ; CHECK-64-NEXT: orb %cl, %al
2028 ; CHECK-64-NEXT: retq
2029 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 7) ; "-inf|nan"
2030 ret i1 %class
2031 }
2033 define i1 @not_is_plus_inf_or_nan_f(float %x) {
2034 ; CHECK-32-LABEL: not_is_plus_inf_or_nan_f:
2035 ; CHECK-32: # %bb.0:
2036 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2037 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2038 ; CHECK-32-NEXT: sete %cl
2039 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2040 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2041 ; CHECK-32-NEXT: setl %al
2042 ; CHECK-32-NEXT: orb %cl, %al
2043 ; CHECK-32-NEXT: retl
2044 ;
2045 ; CHECK-64-LABEL: not_is_plus_inf_or_nan_f:
2046 ; CHECK-64: # %bb.0:
2047 ; CHECK-64-NEXT: movd %xmm0, %eax
2048 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2049 ; CHECK-64-NEXT: sete %cl
2050 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2051 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2052 ; CHECK-64-NEXT: setl %al
2053 ; CHECK-64-NEXT: orb %cl, %al
2054 ; CHECK-64-NEXT: retq
2055 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"
2056 ret i1 %class
2057 }
2059 define i1 @not_is_minus_inf_or_nan_f(float %x) {
2060 ; CHECK-32-LABEL: not_is_minus_inf_or_nan_f:
2061 ; CHECK-32: # %bb.0:
2062 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2063 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2064 ; CHECK-32-NEXT: sete %cl
2065 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2066 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2067 ; CHECK-32-NEXT: setl %al
2068 ; CHECK-32-NEXT: orb %cl, %al
2069 ; CHECK-32-NEXT: retl
2070 ;
2071 ; CHECK-64-LABEL: not_is_minus_inf_or_nan_f:
2072 ; CHECK-64: # %bb.0:
2073 ; CHECK-64-NEXT: movd %xmm0, %eax
2074 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2075 ; CHECK-64-NEXT: sete %cl
2076 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2077 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2078 ; CHECK-64-NEXT: setl %al
2079 ; CHECK-64-NEXT: orb %cl, %al
2080 ; CHECK-64-NEXT: retq
2081 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1016) ; "~(-inf|nan)"
2082 ret i1 %class
2083 }
2085 define i1 @is_plus_inf_or_snan_f(float %x) {
2086 ; CHECK-32-LABEL: is_plus_inf_or_snan_f:
2087 ; CHECK-32: # %bb.0:
2088 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2089 ; CHECK-32-NEXT: movl %eax, %ecx
2090 ; CHECK-32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2091 ; CHECK-32-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2092 ; CHECK-32-NEXT: setl %dl
2093 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2094 ; CHECK-32-NEXT: setge %cl
2095 ; CHECK-32-NEXT: andb %dl, %cl
2096 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2097 ; CHECK-32-NEXT: sete %al
2098 ; CHECK-32-NEXT: orb %cl, %al
2099 ; CHECK-32-NEXT: retl
2100 ;
2101 ; CHECK-64-LABEL: is_plus_inf_or_snan_f:
2102 ; CHECK-64: # %bb.0:
2103 ; CHECK-64-NEXT: movd %xmm0, %eax
2104 ; CHECK-64-NEXT: movl %eax, %ecx
2105 ; CHECK-64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2106 ; CHECK-64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2107 ; CHECK-64-NEXT: setl %dl
2108 ; CHECK-64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2109 ; CHECK-64-NEXT: setge %cl
2110 ; CHECK-64-NEXT: andb %dl, %cl
2111 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2112 ; CHECK-64-NEXT: sete %al
2113 ; CHECK-64-NEXT: orb %cl, %al
2114 ; CHECK-64-NEXT: retq
2115 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 513) ; 0x200|0x1 = "+inf|snan"
2116 ret i1 %class
2117 }
2119 define i1 @is_plus_inf_or_qnan_f(float %x) {
2120 ; CHECK-32-LABEL: is_plus_inf_or_qnan_f:
2121 ; CHECK-32: # %bb.0:
2122 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2123 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2124 ; CHECK-32-NEXT: sete %cl
2125 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2126 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2127 ; CHECK-32-NEXT: setge %al
2128 ; CHECK-32-NEXT: orb %cl, %al
2129 ; CHECK-32-NEXT: retl
2130 ;
2131 ; CHECK-64-LABEL: is_plus_inf_or_qnan_f:
2132 ; CHECK-64: # %bb.0:
2133 ; CHECK-64-NEXT: movd %xmm0, %eax
2134 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2135 ; CHECK-64-NEXT: sete %cl
2136 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2137 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2138 ; CHECK-64-NEXT: setge %al
2139 ; CHECK-64-NEXT: orb %cl, %al
2140 ; CHECK-64-NEXT: retq
2141 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 514) ; 0x200|0x1 = "+inf|qnan"
2142 ret i1 %class
2143 }
2145 define i1 @not_is_plus_inf_or_snan_f(float %x) {
2146 ; CHECK-32-LABEL: not_is_plus_inf_or_snan_f:
2147 ; CHECK-32: # %bb.0:
2148 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2149 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2150 ; CHECK-32-NEXT: sete %cl
2151 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2152 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2153 ; CHECK-32-NEXT: setl %dl
2154 ; CHECK-32-NEXT: orb %cl, %dl
2155 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2156 ; CHECK-32-NEXT: setge %al
2157 ; CHECK-32-NEXT: orb %dl, %al
2158 ; CHECK-32-NEXT: retl
2159 ;
2160 ; CHECK-64-LABEL: not_is_plus_inf_or_snan_f:
2161 ; CHECK-64: # %bb.0:
2162 ; CHECK-64-NEXT: movd %xmm0, %eax
2163 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2164 ; CHECK-64-NEXT: sete %cl
2165 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2166 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2167 ; CHECK-64-NEXT: setl %dl
2168 ; CHECK-64-NEXT: orb %cl, %dl
2169 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2170 ; CHECK-64-NEXT: setge %al
2171 ; CHECK-64-NEXT: orb %dl, %al
2172 ; CHECK-64-NEXT: retq
2173 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 510) ; ~(+inf|snan)
2174 ret i1 %class
2175 }
2177 define i1 @not_is_plus_inf_or_qnan_f(float %x) {
2178 ; CHECK-32-LABEL: not_is_plus_inf_or_qnan_f:
2179 ; CHECK-32: # %bb.0:
2180 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2181 ; CHECK-32-NEXT: movl %eax, %ecx
2182 ; CHECK-32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2183 ; CHECK-32-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2184 ; CHECK-32-NEXT: setl %dl
2185 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2186 ; CHECK-32-NEXT: setge %dh
2187 ; CHECK-32-NEXT: andb %dl, %dh
2188 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2189 ; CHECK-32-NEXT: sete %dl
2190 ; CHECK-32-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
2191 ; CHECK-32-NEXT: setl %al
2192 ; CHECK-32-NEXT: orb %dl, %al
2193 ; CHECK-32-NEXT: orb %dh, %al
2194 ; CHECK-32-NEXT: retl
2195 ;
2196 ; CHECK-64-LABEL: not_is_plus_inf_or_qnan_f:
2197 ; CHECK-64: # %bb.0:
2198 ; CHECK-64-NEXT: movd %xmm0, %eax
2199 ; CHECK-64-NEXT: movl %eax, %ecx
2200 ; CHECK-64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2201 ; CHECK-64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2202 ; CHECK-64-NEXT: setl %dl
2203 ; CHECK-64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2204 ; CHECK-64-NEXT: setge %sil
2205 ; CHECK-64-NEXT: andb %dl, %sil
2206 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2207 ; CHECK-64-NEXT: sete %dl
2208 ; CHECK-64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
2209 ; CHECK-64-NEXT: setl %al
2210 ; CHECK-64-NEXT: orb %dl, %al
2211 ; CHECK-64-NEXT: orb %sil, %al
2212 ; CHECK-64-NEXT: retq
2213 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 509) ; ~(+inf|qnan)
2214 ret i1 %class
2215 }
2217 define i1 @is_minus_inf_or_snan_f(float %x) {
2218 ; CHECK-32-LABEL: is_minus_inf_or_snan_f:
2219 ; CHECK-32: # %bb.0:
2220 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2221 ; CHECK-32-NEXT: movl %eax, %ecx
2222 ; CHECK-32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2223 ; CHECK-32-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2224 ; CHECK-32-NEXT: setl %dl
2225 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2226 ; CHECK-32-NEXT: setge %cl
2227 ; CHECK-32-NEXT: andb %dl, %cl
2228 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2229 ; CHECK-32-NEXT: sete %al
2230 ; CHECK-32-NEXT: orb %cl, %al
2231 ; CHECK-32-NEXT: retl
2232 ;
2233 ; CHECK-64-LABEL: is_minus_inf_or_snan_f:
2234 ; CHECK-64: # %bb.0:
2235 ; CHECK-64-NEXT: movd %xmm0, %eax
2236 ; CHECK-64-NEXT: movl %eax, %ecx
2237 ; CHECK-64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2238 ; CHECK-64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2239 ; CHECK-64-NEXT: setl %dl
2240 ; CHECK-64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2241 ; CHECK-64-NEXT: setge %cl
2242 ; CHECK-64-NEXT: andb %dl, %cl
2243 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2244 ; CHECK-64-NEXT: sete %al
2245 ; CHECK-64-NEXT: orb %cl, %al
2246 ; CHECK-64-NEXT: retq
2247 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 5) ; "-inf|snan"
2248 ret i1 %class
2249 }
2251 define i1 @is_minus_inf_or_qnan_f(float %x) {
2252 ; CHECK-32-LABEL: is_minus_inf_or_qnan_f:
2253 ; CHECK-32: # %bb.0:
2254 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2255 ; CHECK-32-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2256 ; CHECK-32-NEXT: sete %cl
2257 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2258 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2259 ; CHECK-32-NEXT: setge %al
2260 ; CHECK-32-NEXT: orb %cl, %al
2261 ; CHECK-32-NEXT: retl
2262 ;
2263 ; CHECK-64-LABEL: is_minus_inf_or_qnan_f:
2264 ; CHECK-64: # %bb.0:
2265 ; CHECK-64-NEXT: movd %xmm0, %eax
2266 ; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
2267 ; CHECK-64-NEXT: sete %cl
2268 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2269 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2270 ; CHECK-64-NEXT: setge %al
2271 ; CHECK-64-NEXT: orb %cl, %al
2272 ; CHECK-64-NEXT: retq
2273 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 6) ; "-inf|qnan"
2274 ret i1 %class
2275 }
2277 define i1 @not_is_minus_inf_or_snan_f(float %x) {
2278 ; CHECK-32-LABEL: not_is_minus_inf_or_snan_f:
2279 ; CHECK-32: # %bb.0:
2280 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2281 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2282 ; CHECK-32-NEXT: sete %cl
2283 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2284 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2285 ; CHECK-32-NEXT: setl %dl
2286 ; CHECK-32-NEXT: orb %cl, %dl
2287 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2288 ; CHECK-32-NEXT: setge %al
2289 ; CHECK-32-NEXT: orb %dl, %al
2290 ; CHECK-32-NEXT: retl
2291 ;
2292 ; CHECK-64-LABEL: not_is_minus_inf_or_snan_f:
2293 ; CHECK-64: # %bb.0:
2294 ; CHECK-64-NEXT: movd %xmm0, %eax
2295 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2296 ; CHECK-64-NEXT: sete %cl
2297 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2298 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2299 ; CHECK-64-NEXT: setl %dl
2300 ; CHECK-64-NEXT: orb %cl, %dl
2301 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2302 ; CHECK-64-NEXT: setge %al
2303 ; CHECK-64-NEXT: orb %dl, %al
2304 ; CHECK-64-NEXT: retq
2305 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1018) ; "~(-inf|snan)"
2306 ret i1 %class
2307 }
2309 define i1 @not_is_minus_inf_or_qnan_f(float %x) {
2310 ; CHECK-32-LABEL: not_is_minus_inf_or_qnan_f:
2311 ; CHECK-32: # %bb.0:
2312 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2313 ; CHECK-32-NEXT: movl %eax, %ecx
2314 ; CHECK-32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2315 ; CHECK-32-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2316 ; CHECK-32-NEXT: setl %dl
2317 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2318 ; CHECK-32-NEXT: setge %dh
2319 ; CHECK-32-NEXT: andb %dl, %dh
2320 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2321 ; CHECK-32-NEXT: sete %dl
2322 ; CHECK-32-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
2323 ; CHECK-32-NEXT: setl %al
2324 ; CHECK-32-NEXT: orb %dl, %al
2325 ; CHECK-32-NEXT: orb %dh, %al
2326 ; CHECK-32-NEXT: retl
2327 ;
2328 ; CHECK-64-LABEL: not_is_minus_inf_or_qnan_f:
2329 ; CHECK-64: # %bb.0:
2330 ; CHECK-64-NEXT: movd %xmm0, %eax
2331 ; CHECK-64-NEXT: movl %eax, %ecx
2332 ; CHECK-64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2333 ; CHECK-64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2334 ; CHECK-64-NEXT: setl %dl
2335 ; CHECK-64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2336 ; CHECK-64-NEXT: setge %sil
2337 ; CHECK-64-NEXT: andb %dl, %sil
2338 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2339 ; CHECK-64-NEXT: sete %dl
2340 ; CHECK-64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
2341 ; CHECK-64-NEXT: setl %al
2342 ; CHECK-64-NEXT: orb %dl, %al
2343 ; CHECK-64-NEXT: orb %sil, %al
2344 ; CHECK-64-NEXT: retq
2345 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1017) ; "-inf|qnan"
2346 ret i1 %class
2347 }
2349 define i1 @issubnormal_or_nan_f(float %x) {
2350 ; CHECK-32-LABEL: issubnormal_or_nan_f:
2351 ; CHECK-32: # %bb.0:
2352 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
2353 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
2354 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2355 ; CHECK-32-NEXT: setge %cl
2356 ; CHECK-32-NEXT: decl %eax
2357 ; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
2358 ; CHECK-32-NEXT: setb %al
2359 ; CHECK-32-NEXT: orb %cl, %al
2360 ; CHECK-32-NEXT: retl
2361 ;
2362 ; CHECK-64-LABEL: issubnormal_or_nan_f:
2363 ; CHECK-64: # %bb.0:
2364 ; CHECK-64-NEXT: movd %xmm0, %eax
2365 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2366 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2367 ; CHECK-64-NEXT: setge %cl
2368 ; CHECK-64-NEXT: decl %eax
2369 ; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
2370 ; CHECK-64-NEXT: setb %al
2371 ; CHECK-64-NEXT: orb %cl, %al
2372 ; CHECK-64-NEXT: retq
2373 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 147) ; 0x90|0x3 = "subnormal|nan"
2374 ret i1 %class
2375 }
2377 define i1 @issubnormal_or_zero_or_nan_f(float %x) {
2378 ; CHECK-32-LABEL: issubnormal_or_zero_or_nan_f:
2379 ; CHECK-32: # %bb.0:
2380 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2381 ; CHECK-32-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2382 ; CHECK-32-NEXT: sete %cl
2383 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2384 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2385 ; CHECK-32-NEXT: setge %al
2386 ; CHECK-32-NEXT: orb %cl, %al
2387 ; CHECK-32-NEXT: retl
2388 ;
2389 ; CHECK-64-LABEL: issubnormal_or_zero_or_nan_f:
2390 ; CHECK-64: # %bb.0:
2391 ; CHECK-64-NEXT: movd %xmm0, %eax
2392 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2393 ; CHECK-64-NEXT: sete %cl
2394 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2395 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2396 ; CHECK-64-NEXT: setge %al
2397 ; CHECK-64-NEXT: orb %cl, %al
2398 ; CHECK-64-NEXT: retq
2399 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
2400 ret i1 %class
2401 }
2403 define i1 @issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
2404 ; CHECK-32-LABEL: issubnormal_or_zero_or_nan_f_daz:
2405 ; CHECK-32: # %bb.0:
2406 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
2407 ; CHECK-32-NEXT: fldz
2408 ; CHECK-32-NEXT: fucompp
2409 ; CHECK-32-NEXT: fnstsw %ax
2410 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
2411 ; CHECK-32-NEXT: sahf
2412 ; CHECK-32-NEXT: sete %al
2413 ; CHECK-32-NEXT: retl
2414 ;
2415 ; CHECK-64-LABEL: issubnormal_or_zero_or_nan_f_daz:
2416 ; CHECK-64: # %bb.0:
2417 ; CHECK-64-NEXT: xorps %xmm1, %xmm1
2418 ; CHECK-64-NEXT: ucomiss %xmm1, %xmm0
2419 ; CHECK-64-NEXT: sete %al
2420 ; CHECK-64-NEXT: retq
2421 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
2422 ret i1 %class
2423 }
2425 define i1 @issubnormal_or_zero_or_snan_f(float %x) {
2426 ; CHECK-32-LABEL: issubnormal_or_zero_or_snan_f:
2427 ; CHECK-32: # %bb.0:
2428 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2429 ; CHECK-32-NEXT: movl %eax, %ecx
2430 ; CHECK-32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2431 ; CHECK-32-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2432 ; CHECK-32-NEXT: setl %dl
2433 ; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2434 ; CHECK-32-NEXT: setge %cl
2435 ; CHECK-32-NEXT: andb %dl, %cl
2436 ; CHECK-32-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2437 ; CHECK-32-NEXT: sete %al
2438 ; CHECK-32-NEXT: orb %cl, %al
2439 ; CHECK-32-NEXT: retl
2440 ;
2441 ; CHECK-64-LABEL: issubnormal_or_zero_or_snan_f:
2442 ; CHECK-64: # %bb.0:
2443 ; CHECK-64-NEXT: movd %xmm0, %eax
2444 ; CHECK-64-NEXT: movl %eax, %ecx
2445 ; CHECK-64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
2446 ; CHECK-64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
2447 ; CHECK-64-NEXT: setl %dl
2448 ; CHECK-64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
2449 ; CHECK-64-NEXT: setge %cl
2450 ; CHECK-64-NEXT: andb %dl, %cl
2451 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2452 ; CHECK-64-NEXT: sete %al
2453 ; CHECK-64-NEXT: orb %cl, %al
2454 ; CHECK-64-NEXT: retq
2455 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 241) ; 0x90|0x1 = "subnormal|snan"
2456 ret i1 %class
2457 }
2459 define i1 @issubnormal_or_zero_or_qnan_f(float %x) {
2460 ; CHECK-32-LABEL: issubnormal_or_zero_or_qnan_f:
2461 ; CHECK-32: # %bb.0:
2462 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2463 ; CHECK-32-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2464 ; CHECK-32-NEXT: sete %cl
2465 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2466 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2467 ; CHECK-32-NEXT: setge %al
2468 ; CHECK-32-NEXT: orb %cl, %al
2469 ; CHECK-32-NEXT: retl
2470 ;
2471 ; CHECK-64-LABEL: issubnormal_or_zero_or_qnan_f:
2472 ; CHECK-64: # %bb.0:
2473 ; CHECK-64-NEXT: movd %xmm0, %eax
2474 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2475 ; CHECK-64-NEXT: sete %cl
2476 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2477 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2478 ; CHECK-64-NEXT: setge %al
2479 ; CHECK-64-NEXT: orb %cl, %al
2480 ; CHECK-64-NEXT: retq
2481 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"
2482 ret i1 %class
2483 }
2485 define i1 @not_issubnormal_or_nan_f(float %x) {
2486 ; CHECK-32-LABEL: not_issubnormal_or_nan_f:
2487 ; CHECK-32: # %bb.0:
2488 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
2489 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
2490 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2491 ; CHECK-32-NEXT: sete %cl
2492 ; CHECK-32-NEXT: testl %eax, %eax
2493 ; CHECK-32-NEXT: sete %dl
2494 ; CHECK-32-NEXT: orb %cl, %dl
2495 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2496 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2497 ; CHECK-32-NEXT: setb %al
2498 ; CHECK-32-NEXT: orb %dl, %al
2499 ; CHECK-32-NEXT: retl
2500 ;
2501 ; CHECK-64-LABEL: not_issubnormal_or_nan_f:
2502 ; CHECK-64: # %bb.0:
2503 ; CHECK-64-NEXT: movd %xmm0, %eax
2504 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2505 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2506 ; CHECK-64-NEXT: sete %cl
2507 ; CHECK-64-NEXT: testl %eax, %eax
2508 ; CHECK-64-NEXT: sete %dl
2509 ; CHECK-64-NEXT: orb %cl, %dl
2510 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2511 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2512 ; CHECK-64-NEXT: setb %al
2513 ; CHECK-64-NEXT: orb %dl, %al
2514 ; CHECK-64-NEXT: retq
2515 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"
2516 ret i1 %class
2517 }
2519 define i1 @not_issubnormal_or_zero_or_nan_f(float %x) {
2520 ; CHECK-32-LABEL: not_issubnormal_or_zero_or_nan_f:
2521 ; CHECK-32: # %bb.0:
2522 ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax
2523 ; CHECK-32-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2524 ; CHECK-32-NEXT: setne %cl
2525 ; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2526 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2527 ; CHECK-32-NEXT: setl %al
2528 ; CHECK-32-NEXT: andb %cl, %al
2529 ; CHECK-32-NEXT: retl
2530 ;
2531 ; CHECK-64-LABEL: not_issubnormal_or_zero_or_nan_f:
2532 ; CHECK-64: # %bb.0:
2533 ; CHECK-64-NEXT: movd %xmm0, %eax
2534 ; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
2535 ; CHECK-64-NEXT: setne %cl
2536 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2537 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2538 ; CHECK-64-NEXT: setl %al
2539 ; CHECK-64-NEXT: andb %cl, %al
2540 ; CHECK-64-NEXT: retq
2541 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
2542 ret i1 %class
2543 }
2545 define i1 @not_issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
2546 ; CHECK-32-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
2547 ; CHECK-32: # %bb.0:
2548 ; CHECK-32-NEXT: flds {{[0-9]+}}(%esp)
2549 ; CHECK-32-NEXT: fldz
2550 ; CHECK-32-NEXT: fucompp
2551 ; CHECK-32-NEXT: fnstsw %ax
2552 ; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax
2553 ; CHECK-32-NEXT: sahf
2554 ; CHECK-32-NEXT: setne %al
2555 ; CHECK-32-NEXT: retl
2556 ;
2557 ; CHECK-64-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
2558 ; CHECK-64: # %bb.0:
2559 ; CHECK-64-NEXT: xorps %xmm1, %xmm1
2560 ; CHECK-64-NEXT: ucomiss %xmm1, %xmm0
2561 ; CHECK-64-NEXT: setne %al
2562 ; CHECK-64-NEXT: retq
2563 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
2564 ret i1 %class
2565 }
2567 define i1 @not_issubnormal_or_zero_or_snan_f(float %x) {
2568 ; CHECK-32-LABEL: not_issubnormal_or_zero_or_snan_f:
2569 ; CHECK-32: # %bb.0:
2570 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
2571 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
2572 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2573 ; CHECK-32-NEXT: setge %cl
2574 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2575 ; CHECK-32-NEXT: sete %dl
2576 ; CHECK-32-NEXT: orb %cl, %dl
2577 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2578 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2579 ; CHECK-32-NEXT: setb %al
2580 ; CHECK-32-NEXT: orb %dl, %al
2581 ; CHECK-32-NEXT: retl
2582 ;
2583 ; CHECK-64-LABEL: not_issubnormal_or_zero_or_snan_f:
2584 ; CHECK-64: # %bb.0:
2585 ; CHECK-64-NEXT: movd %xmm0, %eax
2586 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2587 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2588 ; CHECK-64-NEXT: setge %cl
2589 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2590 ; CHECK-64-NEXT: sete %dl
2591 ; CHECK-64-NEXT: orb %cl, %dl
2592 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2593 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2594 ; CHECK-64-NEXT: setb %al
2595 ; CHECK-64-NEXT: orb %dl, %al
2596 ; CHECK-64-NEXT: retq
2597 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"
2598 ret i1 %class
2599 }
2601 define i1 @not_issubnormal_or_zero_or_qnan_f(float %x) {
2602 ; CHECK-32-LABEL: not_issubnormal_or_zero_or_qnan_f:
2603 ; CHECK-32: # %bb.0:
2604 ; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
2605 ; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
2606 ; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2607 ; CHECK-32-NEXT: setl %cl
2608 ; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2609 ; CHECK-32-NEXT: setge %dl
2610 ; CHECK-32-NEXT: andb %cl, %dl
2611 ; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2612 ; CHECK-32-NEXT: sete %cl
2613 ; CHECK-32-NEXT: orb %dl, %cl
2614 ; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2615 ; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2616 ; CHECK-32-NEXT: setb %al
2617 ; CHECK-32-NEXT: orb %cl, %al
2618 ; CHECK-32-NEXT: retl
2619 ;
2620 ; CHECK-64-LABEL: not_issubnormal_or_zero_or_qnan_f:
2621 ; CHECK-64: # %bb.0:
2622 ; CHECK-64-NEXT: movd %xmm0, %eax
2623 ; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
2624 ; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
2625 ; CHECK-64-NEXT: setl %cl
2626 ; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
2627 ; CHECK-64-NEXT: setge %dl
2628 ; CHECK-64-NEXT: andb %cl, %dl
2629 ; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
2630 ; CHECK-64-NEXT: sete %cl
2631 ; CHECK-64-NEXT: orb %dl, %cl
2632 ; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
2633 ; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
2634 ; CHECK-64-NEXT: setb %al
2635 ; CHECK-64-NEXT: orb %cl, %al
2636 ; CHECK-64-NEXT: retq
2637 %class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"
2638 ret i1 %class
2639 }
2641 declare i1 @llvm.is.fpclass.f32(float, i32)
2642 declare i1 @llvm.is.fpclass.f64(double, i32)
2643 declare <1 x i1> @llvm.is.fpclass.v1f32(<1 x float>, i32)
2644 declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32)
2645 declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32)
2647 ; Assume DAZ
2648 attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" }
2650 ; Maybe daz
2651 attributes #1 = { "denormal-fp-math"="ieee,dynamic" }