llvm/test/TableGen/inhibit-pset.td

   1 // RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
   2
   3 include "reg-with-subregs-common.td"
   4
   5 // CHECK-DAG: GPR32_AND_XR32RegClassID =
   6 // CHECK-DAG: XR32RegClassID =
   7
   8 def X0 : Register <"x0">;
   9
  10 // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
  11 // CHECK-NEXT:    static const char *PressureNameTable[] = {
  12 // CHECK-NEXT:      "GPR32",
  13 // CHECK-NEXT:    };
  14 // CHECK-NEXT:    return PressureNameTable[Idx];
  15 // CHECK-NEXT:  }
  16
  17 // CHECK:      unsigned TestTargetGenRegisterInfo::
  18 // CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  19 // CHECK-NEXT:  static const uint16_t PressureLimitTable[] = {
  20 // CHECK-NEXT:    {{[0-9]+}},        // 0: GPR32
  21 // CHECK-NEXT:  };
  22 // CHECK-NEXT:  return PressureLimitTable[Idx];
  23 // CHECK-NEXT:}
  24
  25 // CHECK:      static const int RCSetsTable[] = {
  26 // CHECK-NEXT:   /* 0 */ 0, -1,
  27 // CHECK-NEXT: };
  28
  29 def XR32 : RegisterClass<"TestTarget", [i32], 32, (add X0)> {
  30   let GeneratePressureSet = 0;
  31 }
  32
  33 def GPR32_AND_XR32 : RegisterClass<"TestTarget", [i32], 32, (add GPR32, X0)>;