1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
4 ; This testcase corresponds to PR362, which notices that this horrible code
5 ; is generated by the C++ front-end and LLVM optimizers, which has lots of
6 ; loads and other stuff that are unneeded.
8 ; Instcombine should propagate the load through the select instructions to
9 ; allow elimination of the extra stuff by the mem2reg pass.
11 define void @_Z5test1RiS_(ptr %x, ptr %y) {
12 ; CHECK-LABEL: @_Z5test1RiS_(
14 ; CHECK-NEXT: [[TMP_1_I:%.*]] = load i32, ptr [[Y:%.*]], align 4
15 ; CHECK-NEXT: [[TMP_3_I:%.*]] = load i32, ptr [[X:%.*]], align 4
16 ; CHECK-NEXT: [[TMP_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP_1_I]], i32 [[TMP_3_I]])
17 ; CHECK-NEXT: store i32 [[TMP_4]], ptr [[X]], align 4
18 ; CHECK-NEXT: ret void
21 %tmp.1.i = load i32, ptr %y ; <i32> [#uses=1]
22 %tmp.3.i = load i32, ptr %x ; <i32> [#uses=1]
23 %tmp.4.i = icmp slt i32 %tmp.1.i, %tmp.3.i ; <i1> [#uses=1]
24 %retval.i = select i1 %tmp.4.i, ptr %y, ptr %x ; <ptr> [#uses=1]
25 %tmp.4 = load i32, ptr %retval.i ; <i32> [#uses=1]
26 store i32 %tmp.4, ptr %x
30 define void @_Z5test2RiS_(ptr %x, ptr %y) {
31 ; CHECK-LABEL: @_Z5test2RiS_(
33 ; CHECK-NEXT: [[TMP_2:%.*]] = load i32, ptr [[X:%.*]], align 4
34 ; CHECK-NEXT: [[TMP_3_I:%.*]] = load i32, ptr [[Y:%.*]], align 4
35 ; CHECK-NEXT: [[TMP_6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP_2]], i32 [[TMP_3_I]])
36 ; CHECK-NEXT: store i32 [[TMP_6]], ptr [[Y]], align 4
37 ; CHECK-NEXT: ret void
40 %tmp.0 = alloca i32 ; <ptr> [#uses=2]
41 %tmp.2 = load i32, ptr %x ; <i32> [#uses=2]
42 store i32 %tmp.2, ptr %tmp.0
43 %tmp.3.i = load i32, ptr %y ; <i32> [#uses=1]
44 %tmp.4.i = icmp slt i32 %tmp.2, %tmp.3.i ; <i1> [#uses=1]
45 %retval.i = select i1 %tmp.4.i, ptr %y, ptr %tmp.0 ; <ptr> [#uses=1]
46 %tmp.6 = load i32, ptr %retval.i ; <i32> [#uses=1]
47 store i32 %tmp.6, ptr %y