1 ; RUN: opt -passes='loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s
3 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
5 ; Make sure the selects generated from reduction are always emitted
6 ; in deterministic order.
9 ; CHECK: [[VEC_PHI_1:%.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[ADD_5:%.+]], %vector.body ]
10 ; CHECK: [[VEC_PHI_2:%.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[ADD_3:%.+]], %vector.body ]
11 ; CHECK: icmp ule <4 x i64>
12 ; CHECK-NEXT: [[ADD_3]] = add <4 x i32> <i32 3, i32 3, i32 3, i32 3>, [[VEC_PHI_2]]
13 ; CHECK-NEXT: [[ADD_5]] = add <4 x i32> [[VEC_PHI_1]], <i32 5, i32 5, i32 5, i32 5>
14 ; CHECK: select <4 x i1> {{.*}}, <4 x i32> [[ADD_5]], <4 x i32>
15 ; CHECK-NEXT: select <4 x i1> {{.*}}, <4 x i32> [[ADD_3]], <4 x i32>
16 ; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
18 define internal i64 @foo(ptr %t0) !prof !1 {
23 %t18 = phi i32 [ %t24, %t20 ]
24 %t19 = phi i32 [ %t28, %t20 ]
27 t20: ; preds = %t20, %t16
28 %t21 = phi i64 [ 0, %t16 ], [ %t29, %t20 ]
29 %t22 = phi i32 [ 0, %t16 ], [ %t28, %t20 ]
30 %t23 = phi i32 [ 0, %t16 ], [ %t24, %t20 ]
31 %t24 = add i32 3, %t23
32 %t28 = add i32 %t22, 5
33 %t29 = add nuw nsw i64 %t21, 1
34 %t30 = icmp eq i64 %t29, 10
35 br i1 %t30, label %t17, label %t20, !prof !2
41 ; Make sure we do not fail when checking for ordered reduction. This test just
42 ; exercises the path and bails out without performing vectorization.
44 ; CHECK-NOT: fadd <4 x
49 latch: ; preds = %header
50 %tmp = phi double [ %tmp6, %header ]
51 br i1 undef, label %header, label %bb2
54 %tmp3 = phi double [ %tmp, %latch ]
57 header: ; preds = %latch, %bb
58 %tmp5 = phi double [ 1.300000e+01, %bb ], [ %tmp, %latch ]
59 %tmp6 = fadd double %tmp5, 1.000000e+00
63 !1 = !{!"function_entry_count", i64 801}
64 !2 = !{!"branch_weights", i32 746, i32 1}