| blob | 48d8de2a96186816f3f2e9f60b7e5dd88158792c |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
3 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
4 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
5 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
6 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX
8 define void @store_i32(ptr nocapture %0, i32 %1, i32 %2) {
9 ; CHECK-LABEL: @store_i32(
10 ; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
11 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1:%.*]], i64 0
12 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> zeroinitializer
13 ; CHECK-NEXT: [[TMP7:%.*]] = mul <4 x i32> [[TMP5]], [[SHUFFLE]]
14 ; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i32> [[TMP7]], <i32 15, i32 15, i32 15, i32 15>
15 ; CHECK-NEXT: [[TMP9:%.*]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[TMP8]], <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
16 ; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[TMP0]], align 4, !tbaa [[TBAA0]]
17 ; CHECK-NEXT: ret void
18 ;
19 %4 = load i32, ptr %0, align 4, !tbaa !2
20 %5 = mul i32 %4, %1
21 %6 = lshr i32 %5, 15
22 %7 = icmp ult i32 %6, 255
23 %8 = select i1 %7, i32 %6, i32 255
24 store i32 %8, ptr %0, align 4, !tbaa !2
25 %9 = getelementptr inbounds i32, ptr %0, i64 1
26 %10 = load i32, ptr %9, align 4, !tbaa !2
27 %11 = mul i32 %10, %1
28 %12 = lshr i32 %11, 15
29 %13 = icmp ult i32 %12, 255
30 %14 = select i1 %13, i32 %12, i32 255
31 store i32 %14, ptr %9, align 4, !tbaa !2
32 %15 = getelementptr inbounds i32, ptr %0, i64 2
33 %16 = load i32, ptr %15, align 4, !tbaa !2
34 %17 = mul i32 %16, %1
35 %18 = lshr i32 %17, 15
36 %19 = icmp ult i32 %18, 255
37 %20 = select i1 %19, i32 %18, i32 255
38 store i32 %20, ptr %15, align 4, !tbaa !2
39 %21 = getelementptr inbounds i32, ptr %0, i64 3
40 %22 = load i32, ptr %21, align 4, !tbaa !2
41 %23 = mul i32 %22, %1
42 %24 = lshr i32 %23, 15
43 %25 = icmp ult i32 %24, 255
44 %26 = select i1 %25, i32 %24, i32 255
45 store i32 %26, ptr %21, align 4, !tbaa !2
46 ret void
47 }
49 define void @store_i8(ptr nocapture %0, i32 %1, i32 %2) {
50 ; CHECK-LABEL: @store_i8(
51 ; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr [[TMP0:%.*]], align 1, !tbaa [[TBAA4:![0-9]+]]
52 ; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i8> [[TMP5]] to <4 x i32>
53 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1:%.*]], i64 0
54 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> poison, <4 x i32> zeroinitializer
55 ; CHECK-NEXT: [[TMP8:%.*]] = mul <4 x i32> [[SHUFFLE]], [[TMP6]]
56 ; CHECK-NEXT: [[TMP9:%.*]] = lshr <4 x i32> [[TMP8]], <i32 15, i32 15, i32 15, i32 15>
57 ; CHECK-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[TMP9]], <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
58 ; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i32> [[TMP10]] to <4 x i8>
59 ; CHECK-NEXT: store <4 x i8> [[TMP11]], ptr [[TMP0]], align 1, !tbaa [[TBAA4]]
60 ; CHECK-NEXT: ret void
61 ;
62 %4 = load i8, ptr %0, align 1, !tbaa !6
63 %5 = zext i8 %4 to i32
64 %6 = mul i32 %5, %1
65 %7 = lshr i32 %6, 15
66 %8 = icmp ult i32 %7, 255
67 %9 = select i1 %8, i32 %7, i32 255
68 %10 = trunc i32 %9 to i8
69 store i8 %10, ptr %0, align 1, !tbaa !6
70 %11 = getelementptr inbounds i8, ptr %0, i64 1
71 %12 = load i8, ptr %11, align 1, !tbaa !6
72 %13 = zext i8 %12 to i32
73 %14 = mul i32 %13, %1
74 %15 = lshr i32 %14, 15
75 %16 = icmp ult i32 %15, 255
76 %17 = select i1 %16, i32 %15, i32 255
77 %18 = trunc i32 %17 to i8
78 store i8 %18, ptr %11, align 1, !tbaa !6
79 %19 = getelementptr inbounds i8, ptr %0, i64 2
80 %20 = load i8, ptr %19, align 1, !tbaa !6
81 %21 = zext i8 %20 to i32
82 %22 = mul i32 %21, %1
83 %23 = lshr i32 %22, 15
84 %24 = icmp ult i32 %23, 255
85 %25 = select i1 %24, i32 %23, i32 255
86 %26 = trunc i32 %25 to i8
87 store i8 %26, ptr %19, align 1, !tbaa !6
88 %27 = getelementptr inbounds i8, ptr %0, i64 3
89 %28 = load i8, ptr %27, align 1, !tbaa !6
90 %29 = zext i8 %28 to i32
91 %30 = mul i32 %29, %1
92 %31 = lshr i32 %30, 15
93 %32 = icmp ult i32 %31, 255
94 %33 = select i1 %32, i32 %31, i32 255
95 %34 = trunc i32 %33 to i8
96 store i8 %34, ptr %27, align 1, !tbaa !6
97 ret void
98 }
100 define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
101 ; SSE-LABEL: @store_i64(
102 ; SSE-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1:%.*]] to i64
103 ; SSE-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP0:%.*]], align 8, !tbaa [[TBAA5:![0-9]+]]
104 ; SSE-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], [[TMP4]]
105 ; SSE-NEXT: [[TMP7:%.*]] = lshr i64 [[TMP6]], 15
106 ; SSE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32
107 ; SSE-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 255
108 ; SSE-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 4294967295
109 ; SSE-NEXT: [[TMP11:%.*]] = select i1 [[TMP9]], i64 [[TMP10]], i64 255
110 ; SSE-NEXT: store i64 [[TMP11]], ptr [[TMP0]], align 8, !tbaa [[TBAA5]]
111 ; SSE-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 1
112 ; SSE-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8, !tbaa [[TBAA5]]
113 ; SSE-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], [[TMP4]]
114 ; SSE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP14]], 15
115 ; SSE-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
116 ; SSE-NEXT: [[TMP17:%.*]] = icmp ult i32 [[TMP16]], 255
117 ; SSE-NEXT: [[TMP18:%.*]] = and i64 [[TMP15]], 4294967295
118 ; SSE-NEXT: [[TMP19:%.*]] = select i1 [[TMP17]], i64 [[TMP18]], i64 255
119 ; SSE-NEXT: store i64 [[TMP19]], ptr [[TMP12]], align 8, !tbaa [[TBAA5]]
120 ; SSE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 2
121 ; SSE-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8, !tbaa [[TBAA5]]
122 ; SSE-NEXT: [[TMP22:%.*]] = mul i64 [[TMP21]], [[TMP4]]
123 ; SSE-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 15
124 ; SSE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
125 ; SSE-NEXT: [[TMP25:%.*]] = icmp ult i32 [[TMP24]], 255
126 ; SSE-NEXT: [[TMP26:%.*]] = and i64 [[TMP23]], 4294967295
127 ; SSE-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i64 [[TMP26]], i64 255
128 ; SSE-NEXT: store i64 [[TMP27]], ptr [[TMP20]], align 8, !tbaa [[TBAA5]]
129 ; SSE-NEXT: [[TMP28:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 3
130 ; SSE-NEXT: [[TMP29:%.*]] = load i64, ptr [[TMP28]], align 8, !tbaa [[TBAA5]]
131 ; SSE-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], [[TMP4]]
132 ; SSE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 15
133 ; SSE-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32
134 ; SSE-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], 255
135 ; SSE-NEXT: [[TMP34:%.*]] = and i64 [[TMP31]], 4294967295
136 ; SSE-NEXT: [[TMP35:%.*]] = select i1 [[TMP33]], i64 [[TMP34]], i64 255
137 ; SSE-NEXT: store i64 [[TMP35]], ptr [[TMP28]], align 8, !tbaa [[TBAA5]]
138 ; SSE-NEXT: ret void
139 ;
140 ; AVX-LABEL: @store_i64(
141 ; AVX-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1:%.*]] to i64
142 ; AVX-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 8, !tbaa [[TBAA5:![0-9]+]]
143 ; AVX-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0
144 ; AVX-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> zeroinitializer
145 ; AVX-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP6]], [[SHUFFLE]]
146 ; AVX-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], <i64 15, i64 15, i64 15, i64 15>
147 ; AVX-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i32>
148 ; AVX-NEXT: [[TMP11:%.*]] = icmp ult <4 x i32> [[TMP10]], <i32 255, i32 255, i32 255, i32 255>
149 ; AVX-NEXT: [[TMP12:%.*]] = and <4 x i64> [[TMP9]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
150 ; AVX-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i64> [[TMP12]], <4 x i64> <i64 255, i64 255, i64 255, i64 255>
151 ; AVX-NEXT: store <4 x i64> [[TMP13]], ptr [[TMP0]], align 8, !tbaa [[TBAA5]]
152 ; AVX-NEXT: ret void
153 ;
154 %4 = zext i32 %1 to i64
155 %5 = load i64, ptr %0, align 8, !tbaa !7
156 %6 = mul i64 %5, %4
157 %7 = lshr i64 %6, 15
158 %8 = trunc i64 %7 to i32
159 %9 = icmp ult i32 %8, 255
160 %10 = and i64 %7, 4294967295
161 %11 = select i1 %9, i64 %10, i64 255
162 store i64 %11, ptr %0, align 8, !tbaa !7
163 %12 = getelementptr inbounds i64, ptr %0, i64 1
164 %13 = load i64, ptr %12, align 8, !tbaa !7
165 %14 = mul i64 %13, %4
166 %15 = lshr i64 %14, 15
167 %16 = trunc i64 %15 to i32
168 %17 = icmp ult i32 %16, 255
169 %18 = and i64 %15, 4294967295
170 %19 = select i1 %17, i64 %18, i64 255
171 store i64 %19, ptr %12, align 8, !tbaa !7
172 %20 = getelementptr inbounds i64, ptr %0, i64 2
173 %21 = load i64, ptr %20, align 8, !tbaa !7
174 %22 = mul i64 %21, %4
175 %23 = lshr i64 %22, 15
176 %24 = trunc i64 %23 to i32
177 %25 = icmp ult i32 %24, 255
178 %26 = and i64 %23, 4294967295
179 %27 = select i1 %25, i64 %26, i64 255
180 store i64 %27, ptr %20, align 8, !tbaa !7
181 %28 = getelementptr inbounds i64, ptr %0, i64 3
182 %29 = load i64, ptr %28, align 8, !tbaa !7
183 %30 = mul i64 %29, %4
184 %31 = lshr i64 %30, 15
185 %32 = trunc i64 %31 to i32
186 %33 = icmp ult i32 %32, 255
187 %34 = and i64 %31, 4294967295
188 %35 = select i1 %33, i64 %34, i64 255
189 store i64 %35, ptr %28, align 8, !tbaa !7
190 ret void
191 }
193 !2 = !{!3, !3, i64 0}
194 !3 = !{!"int", !4, i64 0}
195 !4 = !{!"omnipotent char", !5, i64 0}
196 !5 = !{!"Simple C++ TBAA"}
197 !6 = !{!4, !4, i64 0}
198 !7 = !{!8, !8, i64 0}
199 !8 = !{!"long", !4, i64 0}