[X86][MC,LLD][NFC] Rename R_X86_64_REX2_GOTPCRELX (#116737)
[llvm-project.git] / llvm / test / MC / RISCV / option-relax.s
blob8a6a929ad0241f0afce9a3e64cfee991091e97c2
1 # RUN: llvm-mc -triple riscv32 < %s \
2 # RUN: | FileCheck -check-prefix=CHECK-INST %s
3 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
4 # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
6 # RUN: llvm-mc -triple riscv64 < %s \
7 # RUN: | FileCheck -check-prefix=CHECK-INST %s
8 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
9 # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
11 # Check .option relax causes R_RISCV_RELAX to be emitted, and .option
12 # norelax suppresses it. Also check that if .option relax was enabled
13 # at any point and an instruction may have been relaxed, diff & branch
14 # relocations are emitted to ensure correct codegen. See
15 # linker-relaxation.s and fixups-expr.s for behaviour of the relax
16 # attribute.
18 .L1:
19 .option norelax
20 # CHECK-INST: .option norelax
22 # CHECK-INST: call foo
23 # CHECK-RELOC: R_RISCV_CALL_PLT foo 0x0
24 # CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
25 call foo
27 # CHECK-RELOC-NEXT: R_RISCV_ADD64
28 # CHECK-RELOC-NEXT: R_RISCV_SUB64
29 .dword .L2-.L1
30 # CHECK-RELOC-NEXT: R_RISCV_JAL
31 jal zero, .L1
32 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
33 beq s1, s1, .L1
35 .L2:
36 .option relax
37 # CHECK-INST: .option relax
39 # CHECK-INST: call bar
40 # CHECK-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x0
41 # CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
42 call bar
44 # CHECK-RELOC-NEXT: R_RISCV_ADD64
45 # CHECK-RELOC-NEXT: R_RISCV_SUB64
46 .dword .L2-.L1
47 # CHECK-RELOC-NEXT: R_RISCV_JAL
48 jal zero, .L1
49 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
50 beq s1, s1, .L1
52 .option norelax
53 # CHECK-INST: .option norelax
55 # CHECK-INST: call baz
56 # CHECK-RELOC-NEXT: R_RISCV_CALL_PLT baz 0x0
57 # CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
58 call baz
60 # CHECK-RELOC-NEXT: R_RISCV_ADD64
61 # CHECK-RELOC-NEXT: R_RISCV_SUB64
62 .dword .L2-.L1
63 # CHECK-RELOC-NEXT: R_RISCV_JAL
64 jal zero, .L1
65 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
66 beq s1, s1, .L1
69 # CHECK-RELOC-NEXT: R_RISCV_PCREL_HI20 .L1
70 auipc t1, %pcrel_hi(.L1)
71 # CHECK-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0
72 addi t1, t1, %pcrel_lo(1b)