1 # RUN: llvm-mc -triple riscv32 < %s \
2 # RUN: | FileCheck -check-prefix=CHECK-INST %s
3 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
4 # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
6 # RUN: llvm-mc -triple riscv64 < %s \
7 # RUN: | FileCheck -check-prefix=CHECK-INST %s
8 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
9 # RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
11 # Check .option relax causes R_RISCV_RELAX to be emitted, and .option
12 # norelax suppresses it. Also check that if .option relax was enabled
13 # at any point and an instruction may have been relaxed, diff & branch
14 # relocations are emitted to ensure correct codegen. See
15 # linker-relaxation.s and fixups-expr.s for behaviour of the relax
20 # CHECK-INST: .option norelax
22 # CHECK-INST: call foo
23 # CHECK-RELOC: R_RISCV_CALL_PLT foo 0x0
24 # CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
27 # CHECK-RELOC-NEXT: R_RISCV_ADD64
28 # CHECK-RELOC-NEXT: R_RISCV_SUB64
30 # CHECK-RELOC-NEXT: R_RISCV_JAL
32 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
37 # CHECK-INST: .option relax
39 # CHECK-INST: call bar
40 # CHECK-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x0
41 # CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
44 # CHECK-RELOC-NEXT: R_RISCV_ADD64
45 # CHECK-RELOC-NEXT: R_RISCV_SUB64
47 # CHECK-RELOC-NEXT: R_RISCV_JAL
49 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
53 # CHECK-INST: .option norelax
55 # CHECK-INST: call baz
56 # CHECK-RELOC-NEXT: R_RISCV_CALL_PLT baz 0x0
57 # CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
60 # CHECK-RELOC-NEXT: R_RISCV_ADD64
61 # CHECK-RELOC-NEXT: R_RISCV_SUB64
63 # CHECK-RELOC-NEXT: R_RISCV_JAL
65 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
69 # CHECK-RELOC-NEXT: R_RISCV_PCREL_HI20 .L1
70 auipc t1
, %pcrel_hi
(.L1)
71 # CHECK-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0
72 addi t1
, t1
, %pcrel_lo
(1b)