llvm/lib/CodeGen/LiveVariables.cpp

   1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the LiveVariable analysis pass.  For each machine
  10 // instruction in the function, this pass calculates the set of registers that
  11 // are immediately dead after the instruction (i.e., the instruction calculates
  12 // the value, but it is never used) and the set of registers that are used by
  13 // the instruction, but are never used after the instruction (i.e., they are
  14 // killed).
  15 //
  16 // This class computes live variables using a sparse implementation based on
  17 // the machine code SSA form.  This class computes live variable information for
  18 // each virtual and _register allocatable_ physical register in a function.  It
  19 // uses the dominance properties of SSA form to efficiently compute live
  20 // variables for virtual registers, and assumes that physical registers are only
  21 // live within a single basic block (allowing it to do a single local analysis
  22 // to resolve physical register lifetimes in each basic block).  If a physical
  23 // register is not register allocatable, it is not tracked.  This is useful for
  24 // things like the stack pointer and condition codes.
  25 //
  26 //===----------------------------------------------------------------------===//
  27
  28 #include "llvm/CodeGen/LiveVariables.h"
  29 #include "llvm/ADT/DenseSet.h"
  30 #include "llvm/ADT/DepthFirstIterator.h"
  31 #include "llvm/ADT/STLExtras.h"
  32 #include "llvm/ADT/SmallPtrSet.h"
  33 #include "llvm/ADT/SmallSet.h"
  34 #include "llvm/CodeGen/MachineInstr.h"
  35 #include "llvm/CodeGen/MachineRegisterInfo.h"
  36 #include "llvm/CodeGen/Passes.h"
  37 #include "llvm/Config/llvm-config.h"
  38 #include "llvm/Support/Debug.h"
  39 #include "llvm/Support/ErrorHandling.h"
  40 #include "llvm/Support/raw_ostream.h"
  41 #include <algorithm>
  42 using namespace llvm;
  43
  44 char LiveVariables::ID = 0;
  45 char &llvm::LiveVariablesID = LiveVariables::ID;
  46 INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
  47                 "Live Variable Analysis", false, false)
  48 INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
  49 INITIALIZE_PASS_END(LiveVariables, "livevars",
  50                 "Live Variable Analysis", false, false)
  51
  52
  53 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
  54   AU.addRequiredID(UnreachableMachineBlockElimID);
  55   AU.setPreservesAll();
  56   MachineFunctionPass::getAnalysisUsage(AU);
  57 }
  58
  59 MachineInstr *
  60 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
  61   for (unsigned i = 0, e = Kills.size(); i != e; ++i)
  62     if (Kills[i]->getParent() == MBB)
  63       return Kills[i];
  64   return nullptr;
  65 }
  66
  67 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
  68 LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const {
  69   dbgs() << "  Alive in blocks: ";
  70   for (unsigned AB : AliveBlocks)
  71     dbgs() << AB << ", ";
  72   dbgs() << "\n  Killed by:";
  73   if (Kills.empty())
  74     dbgs() << " No instructions.\n";
  75   else {
  76     for (unsigned i = 0, e = Kills.size(); i != e; ++i)
  77       dbgs() << "\n    #" << i << ": " << *Kills[i];
  78     dbgs() << "\n";
  79   }
  80 }
  81 #endif
  82
  83 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
  84 LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) {
  85   assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");
  86   VirtRegInfo.grow(Reg);
  87   return VirtRegInfo[Reg];
  88 }
  89
  90 void LiveVariables::MarkVirtRegAliveInBlock(
  91     VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB,
  92     SmallVectorImpl<MachineBasicBlock *> &WorkList) {
  93   unsigned BBNum = MBB->getNumber();
  94
  95   // Check to see if this basic block is one of the killing blocks.  If so,
  96   // remove it.
  97   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
  98     if (VRInfo.Kills[i]->getParent() == MBB) {
  99       VRInfo.Kills.erase(VRInfo.Kills.begin()+i);  // Erase entry
 100       break;
 101     }
 102
 103   if (MBB == DefBlock) return;  // Terminate recursion
 104
 105   if (VRInfo.AliveBlocks.test(BBNum))
 106     return;  // We already know the block is live
 107
 108   // Mark the variable known alive in this bb
 109   VRInfo.AliveBlocks.set(BBNum);
 110
 111   assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
 112   WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
 113 }
 114
 115 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
 116                                             MachineBasicBlock *DefBlock,
 117                                             MachineBasicBlock *MBB) {
 118   SmallVector<MachineBasicBlock *, 16> WorkList;
 119   MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
 120
 121   while (!WorkList.empty()) {
 122     MachineBasicBlock *Pred = WorkList.back();
 123     WorkList.pop_back();
 124     MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
 125   }
 126 }
 127
 128 void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB,
 129                                      MachineInstr &MI) {
 130   assert(MRI->getVRegDef(Reg) && "Register use before def!");
 131
 132   unsigned BBNum = MBB->getNumber();
 133
 134   VarInfo &VRInfo = getVarInfo(Reg);
 135
 136   // Check to see if this basic block is already a kill block.
 137   if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
 138     // Yes, this register is killed in this basic block already. Increase the
 139     // live range by updating the kill instruction.
 140     VRInfo.Kills.back() = &MI;
 141     return;
 142   }
 143
 144 #ifndef NDEBUG
 145   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
 146     assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
 147 #endif
 148
 149   // This situation can occur:
 150   //
 151   //     ,------.
 152   //     |      |
 153   //     |      v
 154   //     |   t2 = phi ... t1 ...
 155   //     |      |
 156   //     |      v
 157   //     |   t1 = ...
 158   //     |  ... = ... t1 ...
 159   //     |      |
 160   //     `------'
 161   //
 162   // where there is a use in a PHI node that's a predecessor to the defining
 163   // block. We don't want to mark all predecessors as having the value "alive"
 164   // in this case.
 165   if (MBB == MRI->getVRegDef(Reg)->getParent())
 166     return;
 167
 168   // Add a new kill entry for this basic block. If this virtual register is
 169   // already marked as alive in this basic block, that means it is alive in at
 170   // least one of the successor blocks, it's not a kill.
 171   if (!VRInfo.AliveBlocks.test(BBNum))
 172     VRInfo.Kills.push_back(&MI);
 173
 174   // Update all dominating blocks to mark them as "known live".
 175   for (MachineBasicBlock *Pred : MBB->predecessors())
 176     MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred);
 177 }
 178
 179 void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
 180   VarInfo &VRInfo = getVarInfo(Reg);
 181
 182   if (VRInfo.AliveBlocks.empty())
 183     // If vr is not alive in any block, then defaults to dead.
 184     VRInfo.Kills.push_back(&MI);
 185 }
 186
 187 /// FindLastPartialDef - Return the last partial def of the specified register.
 188 /// Also returns the sub-registers that're defined by the instruction.
 189 MachineInstr *
 190 LiveVariables::FindLastPartialDef(Register Reg,
 191                                   SmallSet<unsigned, 4> &PartDefRegs) {
 192   unsigned LastDefReg = 0;
 193   unsigned LastDefDist = 0;
 194   MachineInstr *LastDef = nullptr;
 195   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 196     unsigned SubReg = *SubRegs;
 197     MachineInstr *Def = PhysRegDef[SubReg];
 198     if (!Def)
 199       continue;
 200     unsigned Dist = DistanceMap[Def];
 201     if (Dist > LastDefDist) {
 202       LastDefReg  = SubReg;
 203       LastDef     = Def;
 204       LastDefDist = Dist;
 205     }
 206   }
 207
 208   if (!LastDef)
 209     return nullptr;
 210
 211   PartDefRegs.insert(LastDefReg);
 212   for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
 213     MachineOperand &MO = LastDef->getOperand(i);
 214     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
 215       continue;
 216     Register DefReg = MO.getReg();
 217     if (TRI->isSubRegister(Reg, DefReg)) {
 218       for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
 219            SubRegs.isValid(); ++SubRegs)
 220         PartDefRegs.insert(*SubRegs);
 221     }
 222   }
 223   return LastDef;
 224 }
 225
 226 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
 227 /// implicit defs to a machine instruction if there was an earlier def of its
 228 /// super-register.
 229 void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
 230   MachineInstr *LastDef = PhysRegDef[Reg];
 231   // If there was a previous use or a "full" def all is well.
 232   if (!LastDef && !PhysRegUse[Reg]) {
 233     // Otherwise, the last sub-register def implicitly defines this register.
 234     // e.g.
 235     // AH =
 236     // AL = ... implicit-def EAX, implicit killed AH
 237     //    = AH
 238     // ...
 239     //    = EAX
 240     // All of the sub-registers must have been defined before the use of Reg!
 241     SmallSet<unsigned, 4> PartDefRegs;
 242     MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
 243     // If LastPartialDef is NULL, it must be using a livein register.
 244     if (LastPartialDef) {
 245       LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
 246                                                            true/*IsImp*/));
 247       PhysRegDef[Reg] = LastPartialDef;
 248       SmallSet<unsigned, 8> Processed;
 249       for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 250         unsigned SubReg = *SubRegs;
 251         if (Processed.count(SubReg))
 252           continue;
 253         if (PartDefRegs.count(SubReg))
 254           continue;
 255         // This part of Reg was defined before the last partial def. It's killed
 256         // here.
 257         LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
 258                                                              false/*IsDef*/,
 259                                                              true/*IsImp*/));
 260         PhysRegDef[SubReg] = LastPartialDef;
 261         for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
 262           Processed.insert(*SS);
 263       }
 264     }
 265   } else if (LastDef && !PhysRegUse[Reg] &&
 266              !LastDef->findRegisterDefOperand(Reg))
 267     // Last def defines the super register, add an implicit def of reg.
 268     LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
 269                                                   true/*IsImp*/));
 270
 271   // Remember this use.
 272   for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
 273        SubRegs.isValid(); ++SubRegs)
 274     PhysRegUse[*SubRegs] = &MI;
 275 }
 276
 277 /// FindLastRefOrPartRef - Return the last reference or partial reference of
 278 /// the specified register.
 279 MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
 280   MachineInstr *LastDef = PhysRegDef[Reg];
 281   MachineInstr *LastUse = PhysRegUse[Reg];
 282   if (!LastDef && !LastUse)
 283     return nullptr;
 284
 285   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
 286   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
 287   unsigned LastPartDefDist = 0;
 288   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 289     unsigned SubReg = *SubRegs;
 290     MachineInstr *Def = PhysRegDef[SubReg];
 291     if (Def && Def != LastDef) {
 292       // There was a def of this sub-register in between. This is a partial
 293       // def, keep track of the last one.
 294       unsigned Dist = DistanceMap[Def];
 295       if (Dist > LastPartDefDist)
 296         LastPartDefDist = Dist;
 297     } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
 298       unsigned Dist = DistanceMap[Use];
 299       if (Dist > LastRefOrPartRefDist) {
 300         LastRefOrPartRefDist = Dist;
 301         LastRefOrPartRef = Use;
 302       }
 303     }
 304   }
 305
 306   return LastRefOrPartRef;
 307 }
 308
 309 bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
 310   MachineInstr *LastDef = PhysRegDef[Reg];
 311   MachineInstr *LastUse = PhysRegUse[Reg];
 312   if (!LastDef && !LastUse)
 313     return false;
 314
 315   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
 316   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
 317   // The whole register is used.
 318   // AL =
 319   // AH =
 320   //
 321   //    = AX
 322   //    = AL, implicit killed AX
 323   // AX =
 324   //
 325   // Or whole register is defined, but not used at all.
 326   // dead AX =
 327   // ...
 328   // AX =
 329   //
 330   // Or whole register is defined, but only partly used.
 331   // dead AX = implicit-def AL
 332   //    = killed AL
 333   // AX =
 334   MachineInstr *LastPartDef = nullptr;
 335   unsigned LastPartDefDist = 0;
 336   SmallSet<unsigned, 8> PartUses;
 337   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 338     unsigned SubReg = *SubRegs;
 339     MachineInstr *Def = PhysRegDef[SubReg];
 340     if (Def && Def != LastDef) {
 341       // There was a def of this sub-register in between. This is a partial
 342       // def, keep track of the last one.
 343       unsigned Dist = DistanceMap[Def];
 344       if (Dist > LastPartDefDist) {
 345         LastPartDefDist = Dist;
 346         LastPartDef = Def;
 347       }
 348       continue;
 349     }
 350     if (MachineInstr *Use = PhysRegUse[SubReg]) {
 351       for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
 352            ++SS)
 353         PartUses.insert(*SS);
 354       unsigned Dist = DistanceMap[Use];
 355       if (Dist > LastRefOrPartRefDist) {
 356         LastRefOrPartRefDist = Dist;
 357         LastRefOrPartRef = Use;
 358       }
 359     }
 360   }
 361
 362   if (!PhysRegUse[Reg]) {
 363     // Partial uses. Mark register def dead and add implicit def of
 364     // sub-registers which are used.
 365     // dead EAX  = op  implicit-def AL
 366     // That is, EAX def is dead but AL def extends pass it.
 367     PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
 368     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 369       unsigned SubReg = *SubRegs;
 370       if (!PartUses.count(SubReg))
 371         continue;
 372       bool NeedDef = true;
 373       if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
 374         MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
 375         if (MO) {
 376           NeedDef = false;
 377           assert(!MO->isDead());
 378         }
 379       }
 380       if (NeedDef)
 381         PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
 382                                                  true/*IsDef*/, true/*IsImp*/));
 383       MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
 384       if (LastSubRef)
 385         LastSubRef->addRegisterKilled(SubReg, TRI, true);
 386       else {
 387         LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
 388         for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
 389              SS.isValid(); ++SS)
 390           PhysRegUse[*SS] = LastRefOrPartRef;
 391       }
 392       for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
 393         PartUses.erase(*SS);
 394     }
 395   } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
 396     if (LastPartDef)
 397       // The last partial def kills the register.
 398       LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
 399                                                 true/*IsImp*/, true/*IsKill*/));
 400     else {
 401       MachineOperand *MO =
 402         LastRefOrPartRef->findRegisterDefOperand(Reg, false, false, TRI);
 403       bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
 404       // If the last reference is the last def, then it's not used at all.
 405       // That is, unless we are currently processing the last reference itself.
 406       LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
 407       if (NeedEC) {
 408         // If we are adding a subreg def and the superreg def is marked early
 409         // clobber, add an early clobber marker to the subreg def.
 410         MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
 411         if (MO)
 412           MO->setIsEarlyClobber();
 413       }
 414     }
 415   } else
 416     LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
 417   return true;
 418 }
 419
 420 void LiveVariables::HandleRegMask(const MachineOperand &MO) {
 421   // Call HandlePhysRegKill() for all live registers clobbered by Mask.
 422   // Clobbered registers are always dead, sp there is no need to use
 423   // HandlePhysRegDef().
 424   for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
 425     // Skip dead regs.
 426     if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
 427       continue;
 428     // Skip mask-preserved regs.
 429     if (!MO.clobbersPhysReg(Reg))
 430       continue;
 431     // Kill the largest clobbered super-register.
 432     // This avoids needless implicit operands.
 433     unsigned Super = Reg;
 434     for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
 435       if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
 436         Super = *SR;
 437     HandlePhysRegKill(Super, nullptr);
 438   }
 439 }
 440
 441 void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,
 442                                      SmallVectorImpl<unsigned> &Defs) {
 443   // What parts of the register are previously defined?
 444   SmallSet<unsigned, 32> Live;
 445   if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
 446     for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
 447          SubRegs.isValid(); ++SubRegs)
 448       Live.insert(*SubRegs);
 449   } else {
 450     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 451       unsigned SubReg = *SubRegs;
 452       // If a register isn't itself defined, but all parts that make up of it
 453       // are defined, then consider it also defined.
 454       // e.g.
 455       // AL =
 456       // AH =
 457       //    = AX
 458       if (Live.count(SubReg))
 459         continue;
 460       if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
 461         for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
 462              SS.isValid(); ++SS)
 463           Live.insert(*SS);
 464       }
 465     }
 466   }
 467
 468   // Start from the largest piece, find the last time any part of the register
 469   // is referenced.
 470   HandlePhysRegKill(Reg, MI);
 471   // Only some of the sub-registers are used.
 472   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 473     unsigned SubReg = *SubRegs;
 474     if (!Live.count(SubReg))
 475       // Skip if this sub-register isn't defined.
 476       continue;
 477     HandlePhysRegKill(SubReg, MI);
 478   }
 479
 480   if (MI)
 481     Defs.push_back(Reg);  // Remember this def.
 482 }
 483
 484 void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
 485                                       SmallVectorImpl<unsigned> &Defs) {
 486   while (!Defs.empty()) {
 487     Register Reg = Defs.back();
 488     Defs.pop_back();
 489     for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
 490          SubRegs.isValid(); ++SubRegs) {
 491       unsigned SubReg = *SubRegs;
 492       PhysRegDef[SubReg] = &MI;
 493       PhysRegUse[SubReg]  = nullptr;
 494     }
 495   }
 496 }
 497
 498 void LiveVariables::runOnInstr(MachineInstr &MI,
 499                                SmallVectorImpl<unsigned> &Defs) {
 500   assert(!MI.isDebugOrPseudoInstr());
 501   // Process all of the operands of the instruction...
 502   unsigned NumOperandsToProcess = MI.getNumOperands();
 503
 504   // Unless it is a PHI node.  In this case, ONLY process the DEF, not any
 505   // of the uses.  They will be handled in other basic blocks.
 506   if (MI.isPHI())
 507     NumOperandsToProcess = 1;
 508
 509   // Clear kill and dead markers. LV will recompute them.
 510   SmallVector<unsigned, 4> UseRegs;
 511   SmallVector<unsigned, 4> DefRegs;
 512   SmallVector<unsigned, 1> RegMasks;
 513   for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
 514     MachineOperand &MO = MI.getOperand(i);
 515     if (MO.isRegMask()) {
 516       RegMasks.push_back(i);
 517       continue;
 518     }
 519     if (!MO.isReg() || MO.getReg() == 0)
 520       continue;
 521     Register MOReg = MO.getReg();
 522     if (MO.isUse()) {
 523       if (!(Register::isPhysicalRegister(MOReg) && MRI->isReserved(MOReg)))
 524         MO.setIsKill(false);
 525       if (MO.readsReg())
 526         UseRegs.push_back(MOReg);
 527     } else {
 528       assert(MO.isDef());
 529       // FIXME: We should not remove any dead flags. However the MIPS RDDSP
 530       // instruction needs it at the moment: http://llvm.org/PR27116.
 531       if (Register::isPhysicalRegister(MOReg) && !MRI->isReserved(MOReg))
 532         MO.setIsDead(false);
 533       DefRegs.push_back(MOReg);
 534     }
 535   }
 536
 537   MachineBasicBlock *MBB = MI.getParent();
 538   // Process all uses.
 539   for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
 540     unsigned MOReg = UseRegs[i];
 541     if (Register::isVirtualRegister(MOReg))
 542       HandleVirtRegUse(MOReg, MBB, MI);
 543     else if (!MRI->isReserved(MOReg))
 544       HandlePhysRegUse(MOReg, MI);
 545   }
 546
 547   // Process all masked registers. (Call clobbers).
 548   for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
 549     HandleRegMask(MI.getOperand(RegMasks[i]));
 550
 551   // Process all defs.
 552   for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
 553     unsigned MOReg = DefRegs[i];
 554     if (Register::isVirtualRegister(MOReg))
 555       HandleVirtRegDef(MOReg, MI);
 556     else if (!MRI->isReserved(MOReg))
 557       HandlePhysRegDef(MOReg, &MI, Defs);
 558   }
 559   UpdatePhysRegDefs(MI, Defs);
 560 }
 561
 562 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
 563   // Mark live-in registers as live-in.
 564   SmallVector<unsigned, 4> Defs;
 565   for (const auto &LI : MBB->liveins()) {
 566     assert(Register::isPhysicalRegister(LI.PhysReg) &&
 567            "Cannot have a live-in virtual register!");
 568     HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
 569   }
 570
 571   // Loop over all of the instructions, processing them.
 572   DistanceMap.clear();
 573   unsigned Dist = 0;
 574   for (MachineInstr &MI : *MBB) {
 575     if (MI.isDebugOrPseudoInstr())
 576       continue;
 577     DistanceMap.insert(std::make_pair(&MI, Dist++));
 578
 579     runOnInstr(MI, Defs);
 580   }
 581
 582   // Handle any virtual assignments from PHI nodes which might be at the
 583   // bottom of this basic block.  We check all of our successor blocks to see
 584   // if they have PHI nodes, and if so, we simulate an assignment at the end
 585   // of the current block.
 586   if (!PHIVarInfo[MBB->getNumber()].empty()) {
 587     SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
 588
 589     for (unsigned I : VarInfoVec)
 590       // Mark it alive only in the block we are representing.
 591       MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
 592                               MBB);
 593   }
 594
 595   // MachineCSE may CSE instructions which write to non-allocatable physical
 596   // registers across MBBs. Remember if any reserved register is liveout.
 597   SmallSet<unsigned, 4> LiveOuts;
 598   for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
 599     if (SuccMBB->isEHPad())
 600       continue;
 601     for (const auto &LI : SuccMBB->liveins()) {
 602       if (!TRI->isInAllocatableClass(LI.PhysReg))
 603         // Ignore other live-ins, e.g. those that are live into landing pads.
 604         LiveOuts.insert(LI.PhysReg);
 605     }
 606   }
 607
 608   // Loop over PhysRegDef / PhysRegUse, killing any registers that are
 609   // available at the end of the basic block.
 610   for (unsigned i = 0; i != NumRegs; ++i)
 611     if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
 612       HandlePhysRegDef(i, nullptr, Defs);
 613 }
 614
 615 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
 616   MF = &mf;
 617   MRI = &mf.getRegInfo();
 618   TRI = MF->getSubtarget().getRegisterInfo();
 619
 620   const unsigned NumRegs = TRI->getNumRegs();
 621   PhysRegDef.assign(NumRegs, nullptr);
 622   PhysRegUse.assign(NumRegs, nullptr);
 623   PHIVarInfo.resize(MF->getNumBlockIDs());
 624   PHIJoins.clear();
 625
 626   // FIXME: LiveIntervals will be updated to remove its dependence on
 627   // LiveVariables to improve compilation time and eliminate bizarre pass
 628   // dependencies. Until then, we can't change much in -O0.
 629   if (!MRI->isSSA())
 630     report_fatal_error("regalloc=... not currently supported with -O0");
 631
 632   analyzePHINodes(mf);
 633
 634   // Calculate live variable information in depth first order on the CFG of the
 635   // function.  This guarantees that we will see the definition of a virtual
 636   // register before its uses due to dominance properties of SSA (except for PHI
 637   // nodes, which are treated as a special case).
 638   MachineBasicBlock *Entry = &MF->front();
 639   df_iterator_default_set<MachineBasicBlock*,16> Visited;
 640
 641   for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
 642     runOnBlock(MBB, NumRegs);
 643
 644     PhysRegDef.assign(NumRegs, nullptr);
 645     PhysRegUse.assign(NumRegs, nullptr);
 646   }
 647
 648   // Convert and transfer the dead / killed information we have gathered into
 649   // VirtRegInfo onto MI's.
 650   for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
 651     const Register Reg = Register::index2VirtReg(i);
 652     for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
 653       if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
 654         VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
 655       else
 656         VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
 657   }
 658
 659   // Check to make sure there are no unreachable blocks in the MC CFG for the
 660   // function.  If so, it is due to a bug in the instruction selector or some
 661   // other part of the code generator if this happens.
 662 #ifndef NDEBUG
 663   for (const MachineBasicBlock &MBB : *MF)
 664     assert(Visited.contains(&MBB) && "unreachable basic block found");
 665 #endif
 666
 667   PhysRegDef.clear();
 668   PhysRegUse.clear();
 669   PHIVarInfo.clear();
 670
 671   return false;
 672 }
 673
 674 /// replaceKillInstruction - Update register kill info by replacing a kill
 675 /// instruction with a new one.
 676 void LiveVariables::replaceKillInstruction(Register Reg, MachineInstr &OldMI,
 677                                            MachineInstr &NewMI) {
 678   VarInfo &VI = getVarInfo(Reg);
 679   std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
 680 }
 681
 682 /// removeVirtualRegistersKilled - Remove all killed info for the specified
 683 /// instruction.
 684 void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
 685   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 686     MachineOperand &MO = MI.getOperand(i);
 687     if (MO.isReg() && MO.isKill()) {
 688       MO.setIsKill(false);
 689       Register Reg = MO.getReg();
 690       if (Register::isVirtualRegister(Reg)) {
 691         bool removed = getVarInfo(Reg).removeKill(MI);
 692         assert(removed && "kill not in register's VarInfo?");
 693         (void)removed;
 694       }
 695     }
 696   }
 697 }
 698
 699 /// analyzePHINodes - Gather information about the PHI nodes in here. In
 700 /// particular, we want to map the variable information of a virtual register
 701 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
 702 ///
 703 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
 704   for (const auto &MBB : Fn)
 705     for (const auto &BBI : MBB) {
 706       if (!BBI.isPHI())
 707         break;
 708       for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
 709         if (BBI.getOperand(i).readsReg())
 710           PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
 711             .push_back(BBI.getOperand(i).getReg());
 712     }
 713 }
 714
 715 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
 716                                       Register Reg, MachineRegisterInfo &MRI) {
 717   unsigned Num = MBB.getNumber();
 718
 719   // Reg is live-through.
 720   if (AliveBlocks.test(Num))
 721     return true;
 722
 723   // Registers defined in MBB cannot be live in.
 724   const MachineInstr *Def = MRI.getVRegDef(Reg);
 725   if (Def && Def->getParent() == &MBB)
 726     return false;
 727
 728  // Reg was not defined in MBB, was it killed here?
 729   return findKill(&MBB);
 730 }
 731
 732 bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) {
 733   LiveVariables::VarInfo &VI = getVarInfo(Reg);
 734
 735   SmallPtrSet<const MachineBasicBlock *, 8> Kills;
 736   for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
 737     Kills.insert(VI.Kills[i]->getParent());
 738
 739   // Loop over all of the successors of the basic block, checking to see if
 740   // the value is either live in the block, or if it is killed in the block.
 741   for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
 742     // Is it alive in this successor?
 743     unsigned SuccIdx = SuccMBB->getNumber();
 744     if (VI.AliveBlocks.test(SuccIdx))
 745       return true;
 746     // Or is it live because there is a use in a successor that kills it?
 747     if (Kills.count(SuccMBB))
 748       return true;
 749   }
 750
 751   return false;
 752 }
 753
 754 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
 755 /// variables that are live out of DomBB will be marked as passing live through
 756 /// BB.
 757 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
 758                                 MachineBasicBlock *DomBB,
 759                                 MachineBasicBlock *SuccBB) {
 760   const unsigned NumNew = BB->getNumber();
 761
 762   DenseSet<unsigned> Defs, Kills;
 763
 764   MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
 765   for (; BBI != BBE && BBI->isPHI(); ++BBI) {
 766     // Record the def of the PHI node.
 767     Defs.insert(BBI->getOperand(0).getReg());
 768
 769     // All registers used by PHI nodes in SuccBB must be live through BB.
 770     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
 771       if (BBI->getOperand(i+1).getMBB() == BB)
 772         getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
 773   }
 774
 775   // Record all vreg defs and kills of all instructions in SuccBB.
 776   for (; BBI != BBE; ++BBI) {
 777     for (const MachineOperand &Op : BBI->operands()) {
 778       if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
 779         if (Op.isDef())
 780           Defs.insert(Op.getReg());
 781         else if (Op.isKill())
 782           Kills.insert(Op.getReg());
 783       }
 784     }
 785   }
 786
 787   // Update info for all live variables
 788   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
 789     Register Reg = Register::index2VirtReg(i);
 790
 791     // If the Defs is defined in the successor it can't be live in BB.
 792     if (Defs.count(Reg))
 793       continue;
 794
 795     // If the register is either killed in or live through SuccBB it's also live
 796     // through BB.
 797     VarInfo &VI = getVarInfo(Reg);
 798     if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
 799       VI.AliveBlocks.set(NumNew);
 800   }
 801 }
 802
 803 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
 804 /// variables that are live out of DomBB will be marked as passing live through
 805 /// BB. LiveInSets[BB] is *not* updated (because it is not needed during
 806 /// PHIElimination).
 807 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
 808                                 MachineBasicBlock *DomBB,
 809                                 MachineBasicBlock *SuccBB,
 810                                 std::vector<SparseBitVector<>> &LiveInSets) {
 811   const unsigned NumNew = BB->getNumber();
 812
 813   SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
 814   for (unsigned R : BV) {
 815     Register VirtReg = Register::index2VirtReg(R);
 816     LiveVariables::VarInfo &VI = getVarInfo(VirtReg);
 817     VI.AliveBlocks.set(NumNew);
 818   }
 819   // All registers used by PHI nodes in SuccBB must be live through BB.
 820   for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
 821          BBE = SuccBB->end();
 822        BBI != BBE && BBI->isPHI(); ++BBI) {
 823     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
 824       if (BBI->getOperand(i + 1).getMBB() == BB &&
 825           BBI->getOperand(i).readsReg())
 826         getVarInfo(BBI->getOperand(i).getReg())
 827           .AliveBlocks.set(NumNew);
 828   }
 829 }