llvm/lib/CodeGen/MachineOperand.cpp

   1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file Methods common to all machine operands.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineOperand.h"
  14 #include "llvm/ADT/FoldingSet.h"
  15 #include "llvm/ADT/StringExtras.h"
  16 #include "llvm/Analysis/Loads.h"
  17 #include "llvm/Analysis/MemoryLocation.h"
  18 #include "llvm/CodeGen/MIRFormatter.h"
  19 #include "llvm/CodeGen/MIRPrinter.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/TargetInstrInfo.h"
  24 #include "llvm/CodeGen/TargetRegisterInfo.h"
  25 #include "llvm/Config/llvm-config.h"
  26 #include "llvm/IR/Constants.h"
  27 #include "llvm/IR/IRPrintingPasses.h"
  28 #include "llvm/IR/Instructions.h"
  29 #include "llvm/IR/ModuleSlotTracker.h"
  30 #include "llvm/MC/MCDwarf.h"
  31 #include "llvm/Target/TargetIntrinsicInfo.h"
  32 #include "llvm/Target/TargetMachine.h"
  33
  34 using namespace llvm;
  35
  36 static cl::opt<int>
  37     PrintRegMaskNumRegs("print-regmask-num-regs",
  38                         cl::desc("Number of registers to limit to when "
  39                                  "printing regmask operands in IR dumps. "
  40                                  "unlimited = -1"),
  41                         cl::init(32), cl::Hidden);
  42
  43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
  44   if (const MachineInstr *MI = MO.getParent())
  45     if (const MachineBasicBlock *MBB = MI->getParent())
  46       if (const MachineFunction *MF = MBB->getParent())
  47         return MF;
  48   return nullptr;
  49 }
  50 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
  51   return const_cast<MachineFunction *>(
  52       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
  53 }
  54
  55 void MachineOperand::setReg(Register Reg) {
  56   if (getReg() == Reg)
  57     return; // No change.
  58
  59   // Clear the IsRenamable bit to keep it conservatively correct.
  60   IsRenamable = false;
  61
  62   // Otherwise, we have to change the register.  If this operand is embedded
  63   // into a machine function, we need to update the old and new register's
  64   // use/def lists.
  65   if (MachineFunction *MF = getMFIfAvailable(*this)) {
  66     MachineRegisterInfo &MRI = MF->getRegInfo();
  67     MRI.removeRegOperandFromUseList(this);
  68     SmallContents.RegNo = Reg;
  69     MRI.addRegOperandToUseList(this);
  70     return;
  71   }
  72
  73   // Otherwise, just change the register, no problem.  :)
  74   SmallContents.RegNo = Reg;
  75 }
  76
  77 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
  78                                   const TargetRegisterInfo &TRI) {
  79   assert(Reg.isVirtual());
  80   if (SubIdx && getSubReg())
  81     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
  82   setReg(Reg);
  83   if (SubIdx)
  84     setSubReg(SubIdx);
  85 }
  86
  87 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
  88   assert(Register::isPhysicalRegister(Reg));
  89   if (getSubReg()) {
  90     Reg = TRI.getSubReg(Reg, getSubReg());
  91     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
  92     // That won't happen in legal code.
  93     setSubReg(0);
  94     if (isDef())
  95       setIsUndef(false);
  96   }
  97   setReg(Reg);
  98 }
  99
 100 /// Change a def to a use, or a use to a def.
 101 void MachineOperand::setIsDef(bool Val) {
 102   assert(isReg() && "Wrong MachineOperand accessor");
 103   assert((!Val || !isDebug()) && "Marking a debug operation as def");
 104   if (IsDef == Val)
 105     return;
 106   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
 107   // MRI may keep uses and defs in different list positions.
 108   if (MachineFunction *MF = getMFIfAvailable(*this)) {
 109     MachineRegisterInfo &MRI = MF->getRegInfo();
 110     MRI.removeRegOperandFromUseList(this);
 111     IsDef = Val;
 112     MRI.addRegOperandToUseList(this);
 113     return;
 114   }
 115   IsDef = Val;
 116 }
 117
 118 bool MachineOperand::isRenamable() const {
 119   assert(isReg() && "Wrong MachineOperand accessor");
 120   assert(Register::isPhysicalRegister(getReg()) &&
 121          "isRenamable should only be checked on physical registers");
 122   if (!IsRenamable)
 123     return false;
 124
 125   const MachineInstr *MI = getParent();
 126   if (!MI)
 127     return true;
 128
 129   if (isDef())
 130     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
 131
 132   assert(isUse() && "Reg is not def or use");
 133   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
 134 }
 135
 136 void MachineOperand::setIsRenamable(bool Val) {
 137   assert(isReg() && "Wrong MachineOperand accessor");
 138   assert(Register::isPhysicalRegister(getReg()) &&
 139          "setIsRenamable should only be called on physical registers");
 140   IsRenamable = Val;
 141 }
 142
 143 // If this operand is currently a register operand, and if this is in a
 144 // function, deregister the operand from the register's use/def list.
 145 void MachineOperand::removeRegFromUses() {
 146   if (!isReg() || !isOnRegUseList())
 147     return;
 148
 149   if (MachineFunction *MF = getMFIfAvailable(*this))
 150     MF->getRegInfo().removeRegOperandFromUseList(this);
 151 }
 152
 153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 154 /// the specified value.  If an operand is known to be an immediate already,
 155 /// the setImm method should be used.
 156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
 157   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 158
 159   removeRegFromUses();
 160
 161   OpKind = MO_Immediate;
 162   Contents.ImmVal = ImmVal;
 163   setTargetFlags(TargetFlags);
 164 }
 165
 166 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
 167                                          unsigned TargetFlags) {
 168   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 169
 170   removeRegFromUses();
 171
 172   OpKind = MO_FPImmediate;
 173   Contents.CFP = FPImm;
 174   setTargetFlags(TargetFlags);
 175 }
 176
 177 void MachineOperand::ChangeToES(const char *SymName,
 178                                 unsigned TargetFlags) {
 179   assert((!isReg() || !isTied()) &&
 180          "Cannot change a tied operand into an external symbol");
 181
 182   removeRegFromUses();
 183
 184   OpKind = MO_ExternalSymbol;
 185   Contents.OffsetedInfo.Val.SymbolName = SymName;
 186   setOffset(0); // Offset is always 0.
 187   setTargetFlags(TargetFlags);
 188 }
 189
 190 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
 191                                 unsigned TargetFlags) {
 192   assert((!isReg() || !isTied()) &&
 193          "Cannot change a tied operand into a global address");
 194
 195   removeRegFromUses();
 196
 197   OpKind = MO_GlobalAddress;
 198   Contents.OffsetedInfo.Val.GV = GV;
 199   setOffset(Offset);
 200   setTargetFlags(TargetFlags);
 201 }
 202
 203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
 204   assert((!isReg() || !isTied()) &&
 205          "Cannot change a tied operand into an MCSymbol");
 206
 207   removeRegFromUses();
 208
 209   OpKind = MO_MCSymbol;
 210   Contents.Sym = Sym;
 211   setTargetFlags(TargetFlags);
 212 }
 213
 214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
 215   assert((!isReg() || !isTied()) &&
 216          "Cannot change a tied operand into a FrameIndex");
 217
 218   removeRegFromUses();
 219
 220   OpKind = MO_FrameIndex;
 221   setIndex(Idx);
 222   setTargetFlags(TargetFlags);
 223 }
 224
 225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
 226                                          unsigned TargetFlags) {
 227   assert((!isReg() || !isTied()) &&
 228          "Cannot change a tied operand into a FrameIndex");
 229
 230   removeRegFromUses();
 231
 232   OpKind = MO_TargetIndex;
 233   setIndex(Idx);
 234   setOffset(Offset);
 235   setTargetFlags(TargetFlags);
 236 }
 237
 238 /// ChangeToRegister - Replace this operand with a new register operand of
 239 /// the specified value.  If an operand is known to be an register already,
 240 /// the setReg method should be used.
 241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
 242                                       bool isKill, bool isDead, bool isUndef,
 243                                       bool isDebug) {
 244   MachineRegisterInfo *RegInfo = nullptr;
 245   if (MachineFunction *MF = getMFIfAvailable(*this))
 246     RegInfo = &MF->getRegInfo();
 247   // If this operand is already a register operand, remove it from the
 248   // register's use/def lists.
 249   bool WasReg = isReg();
 250   if (RegInfo && WasReg)
 251     RegInfo->removeRegOperandFromUseList(this);
 252
 253   // Change this to a register and set the reg#.
 254   assert(!(isDead && !isDef) && "Dead flag on non-def");
 255   assert(!(isKill && isDef) && "Kill flag on def");
 256   OpKind = MO_Register;
 257   SmallContents.RegNo = Reg;
 258   SubReg_TargetFlags = 0;
 259   IsDef = isDef;
 260   IsImp = isImp;
 261   IsDeadOrKill = isKill | isDead;
 262   IsRenamable = false;
 263   IsUndef = isUndef;
 264   IsInternalRead = false;
 265   IsEarlyClobber = false;
 266   IsDebug = isDebug;
 267   // Ensure isOnRegUseList() returns false.
 268   Contents.Reg.Prev = nullptr;
 269   // Preserve the tie when the operand was already a register.
 270   if (!WasReg)
 271     TiedTo = 0;
 272
 273   // If this operand is embedded in a function, add the operand to the
 274   // register's use/def list.
 275   if (RegInfo)
 276     RegInfo->addRegOperandToUseList(this);
 277 }
 278
 279 /// isIdenticalTo - Return true if this operand is identical to the specified
 280 /// operand. Note that this should stay in sync with the hash_value overload
 281 /// below.
 282 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 283   if (getType() != Other.getType() ||
 284       getTargetFlags() != Other.getTargetFlags())
 285     return false;
 286
 287   switch (getType()) {
 288   case MachineOperand::MO_Register:
 289     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 290            getSubReg() == Other.getSubReg();
 291   case MachineOperand::MO_Immediate:
 292     return getImm() == Other.getImm();
 293   case MachineOperand::MO_CImmediate:
 294     return getCImm() == Other.getCImm();
 295   case MachineOperand::MO_FPImmediate:
 296     return getFPImm() == Other.getFPImm();
 297   case MachineOperand::MO_MachineBasicBlock:
 298     return getMBB() == Other.getMBB();
 299   case MachineOperand::MO_FrameIndex:
 300     return getIndex() == Other.getIndex();
 301   case MachineOperand::MO_ConstantPoolIndex:
 302   case MachineOperand::MO_TargetIndex:
 303     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 304   case MachineOperand::MO_JumpTableIndex:
 305     return getIndex() == Other.getIndex();
 306   case MachineOperand::MO_GlobalAddress:
 307     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 308   case MachineOperand::MO_ExternalSymbol:
 309     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
 310            getOffset() == Other.getOffset();
 311   case MachineOperand::MO_BlockAddress:
 312     return getBlockAddress() == Other.getBlockAddress() &&
 313            getOffset() == Other.getOffset();
 314   case MachineOperand::MO_RegisterMask:
 315   case MachineOperand::MO_RegisterLiveOut: {
 316     // Shallow compare of the two RegMasks
 317     const uint32_t *RegMask = getRegMask();
 318     const uint32_t *OtherRegMask = Other.getRegMask();
 319     if (RegMask == OtherRegMask)
 320       return true;
 321
 322     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 323       // Calculate the size of the RegMask
 324       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 325       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
 326
 327       // Deep compare of the two RegMasks
 328       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
 329     }
 330     // We don't know the size of the RegMask, so we can't deep compare the two
 331     // reg masks.
 332     return false;
 333   }
 334   case MachineOperand::MO_MCSymbol:
 335     return getMCSymbol() == Other.getMCSymbol();
 336   case MachineOperand::MO_CFIIndex:
 337     return getCFIIndex() == Other.getCFIIndex();
 338   case MachineOperand::MO_Metadata:
 339     return getMetadata() == Other.getMetadata();
 340   case MachineOperand::MO_IntrinsicID:
 341     return getIntrinsicID() == Other.getIntrinsicID();
 342   case MachineOperand::MO_Predicate:
 343     return getPredicate() == Other.getPredicate();
 344   case MachineOperand::MO_ShuffleMask:
 345     return getShuffleMask() == Other.getShuffleMask();
 346   }
 347   llvm_unreachable("Invalid machine operand type");
 348 }
 349
 350 // Note: this must stay exactly in sync with isIdenticalTo above.
 351 hash_code llvm::hash_value(const MachineOperand &MO) {
 352   switch (MO.getType()) {
 353   case MachineOperand::MO_Register:
 354     // Register operands don't have target flags.
 355     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
 356   case MachineOperand::MO_Immediate:
 357     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
 358   case MachineOperand::MO_CImmediate:
 359     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
 360   case MachineOperand::MO_FPImmediate:
 361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
 362   case MachineOperand::MO_MachineBasicBlock:
 363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
 364   case MachineOperand::MO_FrameIndex:
 365     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 366   case MachineOperand::MO_ConstantPoolIndex:
 367   case MachineOperand::MO_TargetIndex:
 368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
 369                         MO.getOffset());
 370   case MachineOperand::MO_JumpTableIndex:
 371     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 372   case MachineOperand::MO_ExternalSymbol:
 373     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
 374                         StringRef(MO.getSymbolName()));
 375   case MachineOperand::MO_GlobalAddress:
 376     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
 377                         MO.getOffset());
 378   case MachineOperand::MO_BlockAddress:
 379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
 380                         MO.getOffset());
 381   case MachineOperand::MO_RegisterMask:
 382   case MachineOperand::MO_RegisterLiveOut:
 383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
 384   case MachineOperand::MO_Metadata:
 385     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
 386   case MachineOperand::MO_MCSymbol:
 387     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
 388   case MachineOperand::MO_CFIIndex:
 389     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
 390   case MachineOperand::MO_IntrinsicID:
 391     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
 392   case MachineOperand::MO_Predicate:
 393     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
 394   case MachineOperand::MO_ShuffleMask:
 395     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
 396   }
 397   llvm_unreachable("Invalid machine operand type");
 398 }
 399
 400 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
 401 // it.
 402 static void tryToGetTargetInfo(const MachineOperand &MO,
 403                                const TargetRegisterInfo *&TRI,
 404                                const TargetIntrinsicInfo *&IntrinsicInfo) {
 405   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
 406     TRI = MF->getSubtarget().getRegisterInfo();
 407     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
 408   }
 409 }
 410
 411 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
 412   const auto *TII = MF.getSubtarget().getInstrInfo();
 413   assert(TII && "expected instruction info");
 414   auto Indices = TII->getSerializableTargetIndices();
 415   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
 416     return I.first == Index;
 417   });
 418   if (Found != Indices.end())
 419     return Found->second;
 420   return nullptr;
 421 }
 422
 423 const char *MachineOperand::getTargetIndexName() const {
 424   const MachineFunction *MF = getMFIfAvailable(*this);
 425   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
 426 }
 427
 428 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
 429   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
 430   for (const auto &I : Flags) {
 431     if (I.first == TF) {
 432       return I.second;
 433     }
 434   }
 435   return nullptr;
 436 }
 437
 438 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
 439                              const TargetRegisterInfo *TRI) {
 440   if (!TRI) {
 441     OS << "%dwarfreg." << DwarfReg;
 442     return;
 443   }
 444
 445   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
 446     OS << printReg(*Reg, TRI);
 447   else
 448     OS << "<badreg>";
 449 }
 450
 451 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
 452                                   ModuleSlotTracker &MST) {
 453   OS << "%ir-block.";
 454   if (BB.hasName()) {
 455     printLLVMNameWithoutPrefix(OS, BB.getName());
 456     return;
 457   }
 458   Optional<int> Slot;
 459   if (const Function *F = BB.getParent()) {
 460     if (F == MST.getCurrentFunction()) {
 461       Slot = MST.getLocalSlot(&BB);
 462     } else if (const Module *M = F->getParent()) {
 463       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
 464       CustomMST.incorporateFunction(*F);
 465       Slot = CustomMST.getLocalSlot(&BB);
 466     }
 467   }
 468   if (Slot)
 469     MachineOperand::printIRSlotNumber(OS, *Slot);
 470   else
 471     OS << "<unknown>";
 472 }
 473
 474 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
 475                            SyncScope::ID SSID,
 476                            SmallVectorImpl<StringRef> &SSNs) {
 477   switch (SSID) {
 478   case SyncScope::System:
 479     break;
 480   default:
 481     if (SSNs.empty())
 482       Context.getSyncScopeNames(SSNs);
 483
 484     OS << "syncscope(\"";
 485     printEscapedString(SSNs[SSID], OS);
 486     OS << "\") ";
 487     break;
 488   }
 489 }
 490
 491 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
 492                                         unsigned TMMOFlag) {
 493   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
 494   for (const auto &I : Flags) {
 495     if (I.first == TMMOFlag) {
 496       return I.second;
 497     }
 498   }
 499   return nullptr;
 500 }
 501
 502 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
 503                             const MachineFrameInfo *MFI) {
 504   StringRef Name;
 505   if (MFI) {
 506     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
 507     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
 508       if (Alloca->hasName())
 509         Name = Alloca->getName();
 510     if (IsFixed)
 511       FrameIndex -= MFI->getObjectIndexBegin();
 512   }
 513   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
 514 }
 515
 516 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
 517                                     const TargetRegisterInfo *TRI) {
 518   OS << "%subreg.";
 519   if (TRI)
 520     OS << TRI->getSubRegIndexName(Index);
 521   else
 522     OS << Index;
 523 }
 524
 525 void MachineOperand::printTargetFlags(raw_ostream &OS,
 526                                       const MachineOperand &Op) {
 527   if (!Op.getTargetFlags())
 528     return;
 529   const MachineFunction *MF = getMFIfAvailable(Op);
 530   if (!MF)
 531     return;
 532
 533   const auto *TII = MF->getSubtarget().getInstrInfo();
 534   assert(TII && "expected instruction info");
 535   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
 536   OS << "target-flags(";
 537   const bool HasDirectFlags = Flags.first;
 538   const bool HasBitmaskFlags = Flags.second;
 539   if (!HasDirectFlags && !HasBitmaskFlags) {
 540     OS << "<unknown>) ";
 541     return;
 542   }
 543   if (HasDirectFlags) {
 544     if (const auto *Name = getTargetFlagName(TII, Flags.first))
 545       OS << Name;
 546     else
 547       OS << "<unknown target flag>";
 548   }
 549   if (!HasBitmaskFlags) {
 550     OS << ") ";
 551     return;
 552   }
 553   bool IsCommaNeeded = HasDirectFlags;
 554   unsigned BitMask = Flags.second;
 555   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
 556   for (const auto &Mask : BitMasks) {
 557     // Check if the flag's bitmask has the bits of the current mask set.
 558     if ((BitMask & Mask.first) == Mask.first) {
 559       if (IsCommaNeeded)
 560         OS << ", ";
 561       IsCommaNeeded = true;
 562       OS << Mask.second;
 563       // Clear the bits which were serialized from the flag's bitmask.
 564       BitMask &= ~(Mask.first);
 565     }
 566   }
 567   if (BitMask) {
 568     // When the resulting flag's bitmask isn't zero, we know that we didn't
 569     // serialize all of the bit flags.
 570     if (IsCommaNeeded)
 571       OS << ", ";
 572     OS << "<unknown bitmask target flag>";
 573   }
 574   OS << ") ";
 575 }
 576
 577 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
 578   OS << "<mcsymbol " << Sym << ">";
 579 }
 580
 581 void MachineOperand::printStackObjectReference(raw_ostream &OS,
 582                                                unsigned FrameIndex,
 583                                                bool IsFixed, StringRef Name) {
 584   if (IsFixed) {
 585     OS << "%fixed-stack." << FrameIndex;
 586     return;
 587   }
 588
 589   OS << "%stack." << FrameIndex;
 590   if (!Name.empty())
 591     OS << '.' << Name;
 592 }
 593
 594 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
 595   if (Offset == 0)
 596     return;
 597   if (Offset < 0) {
 598     OS << " - " << -Offset;
 599     return;
 600   }
 601   OS << " + " << Offset;
 602 }
 603
 604 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
 605   if (Slot == -1)
 606     OS << "<badref>";
 607   else
 608     OS << Slot;
 609 }
 610
 611 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
 612                      const TargetRegisterInfo *TRI) {
 613   switch (CFI.getOperation()) {
 614   case MCCFIInstruction::OpSameValue:
 615     OS << "same_value ";
 616     if (MCSymbol *Label = CFI.getLabel())
 617       MachineOperand::printSymbol(OS, *Label);
 618     printCFIRegister(CFI.getRegister(), OS, TRI);
 619     break;
 620   case MCCFIInstruction::OpRememberState:
 621     OS << "remember_state ";
 622     if (MCSymbol *Label = CFI.getLabel())
 623       MachineOperand::printSymbol(OS, *Label);
 624     break;
 625   case MCCFIInstruction::OpRestoreState:
 626     OS << "restore_state ";
 627     if (MCSymbol *Label = CFI.getLabel())
 628       MachineOperand::printSymbol(OS, *Label);
 629     break;
 630   case MCCFIInstruction::OpOffset:
 631     OS << "offset ";
 632     if (MCSymbol *Label = CFI.getLabel())
 633       MachineOperand::printSymbol(OS, *Label);
 634     printCFIRegister(CFI.getRegister(), OS, TRI);
 635     OS << ", " << CFI.getOffset();
 636     break;
 637   case MCCFIInstruction::OpDefCfaRegister:
 638     OS << "def_cfa_register ";
 639     if (MCSymbol *Label = CFI.getLabel())
 640       MachineOperand::printSymbol(OS, *Label);
 641     printCFIRegister(CFI.getRegister(), OS, TRI);
 642     break;
 643   case MCCFIInstruction::OpDefCfaOffset:
 644     OS << "def_cfa_offset ";
 645     if (MCSymbol *Label = CFI.getLabel())
 646       MachineOperand::printSymbol(OS, *Label);
 647     OS << CFI.getOffset();
 648     break;
 649   case MCCFIInstruction::OpDefCfa:
 650     OS << "def_cfa ";
 651     if (MCSymbol *Label = CFI.getLabel())
 652       MachineOperand::printSymbol(OS, *Label);
 653     printCFIRegister(CFI.getRegister(), OS, TRI);
 654     OS << ", " << CFI.getOffset();
 655     break;
 656   case MCCFIInstruction::OpLLVMDefAspaceCfa:
 657     OS << "llvm_def_aspace_cfa ";
 658     if (MCSymbol *Label = CFI.getLabel())
 659       MachineOperand::printSymbol(OS, *Label);
 660     printCFIRegister(CFI.getRegister(), OS, TRI);
 661     OS << ", " << CFI.getOffset();
 662     OS << ", " << CFI.getAddressSpace();
 663     break;
 664   case MCCFIInstruction::OpRelOffset:
 665     OS << "rel_offset ";
 666     if (MCSymbol *Label = CFI.getLabel())
 667       MachineOperand::printSymbol(OS, *Label);
 668     printCFIRegister(CFI.getRegister(), OS, TRI);
 669     OS << ", " << CFI.getOffset();
 670     break;
 671   case MCCFIInstruction::OpAdjustCfaOffset:
 672     OS << "adjust_cfa_offset ";
 673     if (MCSymbol *Label = CFI.getLabel())
 674       MachineOperand::printSymbol(OS, *Label);
 675     OS << CFI.getOffset();
 676     break;
 677   case MCCFIInstruction::OpRestore:
 678     OS << "restore ";
 679     if (MCSymbol *Label = CFI.getLabel())
 680       MachineOperand::printSymbol(OS, *Label);
 681     printCFIRegister(CFI.getRegister(), OS, TRI);
 682     break;
 683   case MCCFIInstruction::OpEscape: {
 684     OS << "escape ";
 685     if (MCSymbol *Label = CFI.getLabel())
 686       MachineOperand::printSymbol(OS, *Label);
 687     if (!CFI.getValues().empty()) {
 688       size_t e = CFI.getValues().size() - 1;
 689       for (size_t i = 0; i < e; ++i)
 690         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
 691       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
 692     }
 693     break;
 694   }
 695   case MCCFIInstruction::OpUndefined:
 696     OS << "undefined ";
 697     if (MCSymbol *Label = CFI.getLabel())
 698       MachineOperand::printSymbol(OS, *Label);
 699     printCFIRegister(CFI.getRegister(), OS, TRI);
 700     break;
 701   case MCCFIInstruction::OpRegister:
 702     OS << "register ";
 703     if (MCSymbol *Label = CFI.getLabel())
 704       MachineOperand::printSymbol(OS, *Label);
 705     printCFIRegister(CFI.getRegister(), OS, TRI);
 706     OS << ", ";
 707     printCFIRegister(CFI.getRegister2(), OS, TRI);
 708     break;
 709   case MCCFIInstruction::OpWindowSave:
 710     OS << "window_save ";
 711     if (MCSymbol *Label = CFI.getLabel())
 712       MachineOperand::printSymbol(OS, *Label);
 713     break;
 714   case MCCFIInstruction::OpNegateRAState:
 715     OS << "negate_ra_sign_state ";
 716     if (MCSymbol *Label = CFI.getLabel())
 717       MachineOperand::printSymbol(OS, *Label);
 718     break;
 719   default:
 720     // TODO: Print the other CFI Operations.
 721     OS << "<unserializable cfi directive>";
 722     break;
 723   }
 724 }
 725
 726 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
 727                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 728   print(OS, LLT{}, TRI, IntrinsicInfo);
 729 }
 730
 731 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
 732                            const TargetRegisterInfo *TRI,
 733                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 734   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
 735   ModuleSlotTracker DummyMST(nullptr);
 736   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
 737         /*IsStandalone=*/true,
 738         /*ShouldPrintRegisterTies=*/true,
 739         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 740 }
 741
 742 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
 743                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
 744                            bool IsStandalone, bool ShouldPrintRegisterTies,
 745                            unsigned TiedOperandIdx,
 746                            const TargetRegisterInfo *TRI,
 747                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 748   printTargetFlags(OS, *this);
 749   switch (getType()) {
 750   case MachineOperand::MO_Register: {
 751     Register Reg = getReg();
 752     if (isImplicit())
 753       OS << (isDef() ? "implicit-def " : "implicit ");
 754     else if (PrintDef && isDef())
 755       // Print the 'def' flag only when the operand is defined after '='.
 756       OS << "def ";
 757     if (isInternalRead())
 758       OS << "internal ";
 759     if (isDead())
 760       OS << "dead ";
 761     if (isKill())
 762       OS << "killed ";
 763     if (isUndef())
 764       OS << "undef ";
 765     if (isEarlyClobber())
 766       OS << "early-clobber ";
 767     if (Register::isPhysicalRegister(getReg()) && isRenamable())
 768       OS << "renamable ";
 769     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
 770     // simply infer it when parsing and do not need to print it.
 771
 772     const MachineRegisterInfo *MRI = nullptr;
 773     if (Register::isVirtualRegister(Reg)) {
 774       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 775         MRI = &MF->getRegInfo();
 776       }
 777     }
 778
 779     OS << printReg(Reg, TRI, 0, MRI);
 780     // Print the sub register.
 781     if (unsigned SubReg = getSubReg()) {
 782       if (TRI)
 783         OS << '.' << TRI->getSubRegIndexName(SubReg);
 784       else
 785         OS << ".subreg" << SubReg;
 786     }
 787     // Print the register class / bank.
 788     if (Register::isVirtualRegister(Reg)) {
 789       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 790         const MachineRegisterInfo &MRI = MF->getRegInfo();
 791         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
 792           OS << ':';
 793           OS << printRegClassOrBank(Reg, MRI, TRI);
 794         }
 795       }
 796     }
 797     // Print ties.
 798     if (ShouldPrintRegisterTies && isTied() && !isDef())
 799       OS << "(tied-def " << TiedOperandIdx << ")";
 800     // Print types.
 801     if (TypeToPrint.isValid())
 802       OS << '(' << TypeToPrint << ')';
 803     break;
 804   }
 805   case MachineOperand::MO_Immediate: {
 806     const MIRFormatter *Formatter = nullptr;
 807     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 808       const auto *TII = MF->getSubtarget().getInstrInfo();
 809       assert(TII && "expected instruction info");
 810       Formatter = TII->getMIRFormatter();
 811     }
 812     if (Formatter)
 813       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
 814     else
 815       OS << getImm();
 816     break;
 817   }
 818   case MachineOperand::MO_CImmediate:
 819     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 820     break;
 821   case MachineOperand::MO_FPImmediate:
 822     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 823     break;
 824   case MachineOperand::MO_MachineBasicBlock:
 825     OS << printMBBReference(*getMBB());
 826     break;
 827   case MachineOperand::MO_FrameIndex: {
 828     int FrameIndex = getIndex();
 829     bool IsFixed = false;
 830     const MachineFrameInfo *MFI = nullptr;
 831     if (const MachineFunction *MF = getMFIfAvailable(*this))
 832       MFI = &MF->getFrameInfo();
 833     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
 834     break;
 835   }
 836   case MachineOperand::MO_ConstantPoolIndex:
 837     OS << "%const." << getIndex();
 838     printOperandOffset(OS, getOffset());
 839     break;
 840   case MachineOperand::MO_TargetIndex: {
 841     OS << "target-index(";
 842     const char *Name = "<unknown>";
 843     if (const MachineFunction *MF = getMFIfAvailable(*this))
 844       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
 845         Name = TargetIndexName;
 846     OS << Name << ')';
 847     printOperandOffset(OS, getOffset());
 848     break;
 849   }
 850   case MachineOperand::MO_JumpTableIndex:
 851     OS << printJumpTableEntryReference(getIndex());
 852     break;
 853   case MachineOperand::MO_GlobalAddress:
 854     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
 855     printOperandOffset(OS, getOffset());
 856     break;
 857   case MachineOperand::MO_ExternalSymbol: {
 858     StringRef Name = getSymbolName();
 859     OS << '&';
 860     if (Name.empty()) {
 861       OS << "\"\"";
 862     } else {
 863       printLLVMNameWithoutPrefix(OS, Name);
 864     }
 865     printOperandOffset(OS, getOffset());
 866     break;
 867   }
 868   case MachineOperand::MO_BlockAddress: {
 869     OS << "blockaddress(";
 870     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
 871                                                      MST);
 872     OS << ", ";
 873     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
 874     OS << ')';
 875     MachineOperand::printOperandOffset(OS, getOffset());
 876     break;
 877   }
 878   case MachineOperand::MO_RegisterMask: {
 879     OS << "<regmask";
 880     if (TRI) {
 881       unsigned NumRegsInMask = 0;
 882       unsigned NumRegsEmitted = 0;
 883       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
 884         unsigned MaskWord = i / 32;
 885         unsigned MaskBit = i % 32;
 886         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
 887           if (PrintRegMaskNumRegs < 0 ||
 888               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
 889             OS << " " << printReg(i, TRI);
 890             NumRegsEmitted++;
 891           }
 892           NumRegsInMask++;
 893         }
 894       }
 895       if (NumRegsEmitted != NumRegsInMask)
 896         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
 897     } else {
 898       OS << " ...";
 899     }
 900     OS << ">";
 901     break;
 902   }
 903   case MachineOperand::MO_RegisterLiveOut: {
 904     const uint32_t *RegMask = getRegLiveOut();
 905     OS << "liveout(";
 906     if (!TRI) {
 907       OS << "<unknown>";
 908     } else {
 909       bool IsCommaNeeded = false;
 910       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
 911         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
 912           if (IsCommaNeeded)
 913             OS << ", ";
 914           OS << printReg(Reg, TRI);
 915           IsCommaNeeded = true;
 916         }
 917       }
 918     }
 919     OS << ")";
 920     break;
 921   }
 922   case MachineOperand::MO_Metadata:
 923     getMetadata()->printAsOperand(OS, MST);
 924     break;
 925   case MachineOperand::MO_MCSymbol:
 926     printSymbol(OS, *getMCSymbol());
 927     break;
 928   case MachineOperand::MO_CFIIndex: {
 929     if (const MachineFunction *MF = getMFIfAvailable(*this))
 930       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
 931     else
 932       OS << "<cfi directive>";
 933     break;
 934   }
 935   case MachineOperand::MO_IntrinsicID: {
 936     Intrinsic::ID ID = getIntrinsicID();
 937     if (ID < Intrinsic::num_intrinsics)
 938       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
 939     else if (IntrinsicInfo)
 940       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
 941     else
 942       OS << "intrinsic(" << ID << ')';
 943     break;
 944   }
 945   case MachineOperand::MO_Predicate: {
 946     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
 947     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
 948        << CmpInst::getPredicateName(Pred) << ')';
 949     break;
 950   }
 951   case MachineOperand::MO_ShuffleMask:
 952     OS << "shufflemask(";
 953     ArrayRef<int> Mask = getShuffleMask();
 954     StringRef Separator;
 955     for (int Elt : Mask) {
 956       if (Elt == -1)
 957         OS << Separator << "undef";
 958       else
 959         OS << Separator << Elt;
 960       Separator = ", ";
 961     }
 962
 963     OS << ')';
 964     break;
 965   }
 966 }
 967
 968 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 969 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
 970 #endif
 971
 972 //===----------------------------------------------------------------------===//
 973 // MachineMemOperand Implementation
 974 //===----------------------------------------------------------------------===//
 975
 976 /// getAddrSpace - Return the LLVM IR address space number that this pointer
 977 /// points into.
 978 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
 979
 980 /// isDereferenceable - Return true if V is always dereferenceable for
 981 /// Offset + Size byte.
 982 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
 983                                            const DataLayout &DL) const {
 984   if (!V.is<const Value *>())
 985     return false;
 986
 987   const Value *BasePtr = V.get<const Value *>();
 988   if (BasePtr == nullptr)
 989     return false;
 990
 991   return isDereferenceableAndAlignedPointer(
 992       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
 993 }
 994
 995 /// getConstantPool - Return a MachinePointerInfo record that refers to the
 996 /// constant pool.
 997 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
 998   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
 999 }
1000
1001 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1002 /// the specified FrameIndex.
1003 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1004                                                      int FI, int64_t Offset) {
1005   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1006 }
1007
1008 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1009   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1010 }
1011
1012 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1013   return MachinePointerInfo(MF.getPSVManager().getGOT());
1014 }
1015
1016 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1017                                                 int64_t Offset, uint8_t ID) {
1018   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1019 }
1020
1021 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1022   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1023 }
1024
1025 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1026                                      LLT type, Align a, const AAMDNodes &AAInfo,
1027                                      const MDNode *Ranges, SyncScope::ID SSID,
1028                                      AtomicOrdering Ordering,
1029                                      AtomicOrdering FailureOrdering)
1030     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1031       AAInfo(AAInfo), Ranges(Ranges) {
1032   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1033           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1034          "invalid pointer value");
1035   assert((isLoad() || isStore()) && "Not a load/store!");
1036
1037   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1038   assert(getSyncScopeID() == SSID && "Value truncated");
1039   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1040   assert(getSuccessOrdering() == Ordering && "Value truncated");
1041   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1042   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1043 }
1044
1045 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1046                                      uint64_t s, Align a,
1047                                      const AAMDNodes &AAInfo,
1048                                      const MDNode *Ranges, SyncScope::ID SSID,
1049                                      AtomicOrdering Ordering,
1050                                      AtomicOrdering FailureOrdering)
1051     : MachineMemOperand(ptrinfo, f,
1052                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1053                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1054
1055 /// Profile - Gather unique data for the object.
1056 ///
1057 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1058   ID.AddInteger(getOffset());
1059   ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1060   ID.AddPointer(getOpaqueValue());
1061   ID.AddInteger(getFlags());
1062   ID.AddInteger(getBaseAlign().value());
1063 }
1064
1065 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1066   // The Value and Offset may differ due to CSE. But the flags and size
1067   // should be the same.
1068   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1069   assert(MMO->getSize() == getSize() && "Size mismatch!");
1070
1071   if (MMO->getBaseAlign() >= getBaseAlign()) {
1072     // Update the alignment value.
1073     BaseAlign = MMO->getBaseAlign();
1074     // Also update the base and offset, because the new alignment may
1075     // not be applicable with the old ones.
1076     PtrInfo = MMO->PtrInfo;
1077   }
1078 }
1079
1080 /// getAlign - Return the minimum known alignment in bytes of the
1081 /// actual memory reference.
1082 Align MachineMemOperand::getAlign() const {
1083   return commonAlignment(getBaseAlign(), getOffset());
1084 }
1085
1086 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1087                               SmallVectorImpl<StringRef> &SSNs,
1088                               const LLVMContext &Context,
1089                               const MachineFrameInfo *MFI,
1090                               const TargetInstrInfo *TII) const {
1091   OS << '(';
1092   if (isVolatile())
1093     OS << "volatile ";
1094   if (isNonTemporal())
1095     OS << "non-temporal ";
1096   if (isDereferenceable())
1097     OS << "dereferenceable ";
1098   if (isInvariant())
1099     OS << "invariant ";
1100   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1101     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1102        << "\" ";
1103   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1104     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1105        << "\" ";
1106   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1107     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1108        << "\" ";
1109
1110   assert((isLoad() || isStore()) &&
1111          "machine memory operand must be a load or store (or both)");
1112   if (isLoad())
1113     OS << "load ";
1114   if (isStore())
1115     OS << "store ";
1116
1117   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1118
1119   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1120     OS << toIRString(getSuccessOrdering()) << ' ';
1121   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1122     OS << toIRString(getFailureOrdering()) << ' ';
1123
1124   if (getMemoryType().isValid())
1125     OS << '(' << getMemoryType() << ')';
1126   else
1127     OS << "unknown-size";
1128
1129   if (const Value *Val = getValue()) {
1130     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1131     MIRFormatter::printIRValue(OS, *Val, MST);
1132   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1133     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1134     assert(PVal && "Expected a pseudo source value");
1135     switch (PVal->kind()) {
1136     case PseudoSourceValue::Stack:
1137       OS << "stack";
1138       break;
1139     case PseudoSourceValue::GOT:
1140       OS << "got";
1141       break;
1142     case PseudoSourceValue::JumpTable:
1143       OS << "jump-table";
1144       break;
1145     case PseudoSourceValue::ConstantPool:
1146       OS << "constant-pool";
1147       break;
1148     case PseudoSourceValue::FixedStack: {
1149       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1150       bool IsFixed = true;
1151       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1152       break;
1153     }
1154     case PseudoSourceValue::GlobalValueCallEntry:
1155       OS << "call-entry ";
1156       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1157           OS, /*PrintType=*/false, MST);
1158       break;
1159     case PseudoSourceValue::ExternalSymbolCallEntry:
1160       OS << "call-entry &";
1161       printLLVMNameWithoutPrefix(
1162           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1163       break;
1164     default: {
1165       const MIRFormatter *Formatter = TII->getMIRFormatter();
1166       // FIXME: This is not necessarily the correct MIR serialization format for
1167       // a custom pseudo source value, but at least it allows
1168       // MIR printing to work on a target with custom pseudo source
1169       // values.
1170       OS << "custom \"";
1171       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1172       OS << '\"';
1173       break;
1174     }
1175     }
1176   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1177     OS << ((isLoad() && isStore()) ? " on "
1178            : isLoad()              ? " from "
1179                                    : " into ")
1180        << "unknown-address";
1181   }
1182   MachineOperand::printOperandOffset(OS, getOffset());
1183   if (getSize() > 0 && getAlign() != getSize())
1184     OS << ", align " << getAlign().value();
1185   if (getAlign() != getBaseAlign())
1186     OS << ", basealign " << getBaseAlign().value();
1187   auto AAInfo = getAAInfo();
1188   if (AAInfo.TBAA) {
1189     OS << ", !tbaa ";
1190     AAInfo.TBAA->printAsOperand(OS, MST);
1191   }
1192   if (AAInfo.Scope) {
1193     OS << ", !alias.scope ";
1194     AAInfo.Scope->printAsOperand(OS, MST);
1195   }
1196   if (AAInfo.NoAlias) {
1197     OS << ", !noalias ";
1198     AAInfo.NoAlias->printAsOperand(OS, MST);
1199   }
1200   if (getRanges()) {
1201     OS << ", !range ";
1202     getRanges()->printAsOperand(OS, MST);
1203   }
1204   // FIXME: Implement addrspace printing/parsing in MIR.
1205   // For now, print this even though parsing it is not available in MIR.
1206   if (unsigned AS = getAddrSpace())
1207     OS << ", addrspace " << AS;
1208
1209   OS << ')';
1210 }