1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This implements the TargetLoweringBase class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/ISDOpcodes.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RuntimeLibcalls.h"
33 #include "llvm/CodeGen/StackMaps.h"
34 #include "llvm/CodeGen/TargetLowering.h"
35 #include "llvm/CodeGen/TargetOpcodes.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/ValueTypes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MachineValueType.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Transforms/Utils/SizeOpts.h"
69 static cl::opt
<bool> JumpIsExpensiveOverride(
70 "jump-is-expensive", cl::init(false),
71 cl::desc("Do not create extra branches to split comparison logic."),
74 static cl::opt
<unsigned> MinimumJumpTableEntries
75 ("min-jump-table-entries", cl::init(4), cl::Hidden
,
76 cl::desc("Set minimum number of entries to use a jump table."));
78 static cl::opt
<unsigned> MaximumJumpTableSize
79 ("max-jump-table-size", cl::init(UINT_MAX
), cl::Hidden
,
80 cl::desc("Set maximum size of jump tables."));
82 /// Minimum jump table density for normal functions.
83 static cl::opt
<unsigned>
84 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden
,
85 cl::desc("Minimum density for building a jump table in "
86 "a normal function"));
88 /// Minimum jump table density for -Os or -Oz functions.
89 static cl::opt
<unsigned> OptsizeJumpTableDensity(
90 "optsize-jump-table-density", cl::init(40), cl::Hidden
,
91 cl::desc("Minimum density for building a jump table in "
92 "an optsize function"));
94 // FIXME: This option is only to test if the strict fp operation processed
95 // correctly by preventing mutating strict fp operation to normal fp operation
96 // during development. When the backend supports strict float operation, this
97 // option will be meaningless.
98 static cl::opt
<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
99 cl::desc("Don't mutate strict-float node to a legalize node"),
100 cl::init(false), cl::Hidden
);
102 static bool darwinHasSinCos(const Triple
&TT
) {
103 assert(TT
.isOSDarwin() && "should be called with darwin triple");
104 // Don't bother with 32 bit x86.
105 if (TT
.getArch() == Triple::x86
)
107 // Macos < 10.9 has no sincos_stret.
109 return !TT
.isMacOSXVersionLT(10, 9) && TT
.isArch64Bit();
110 // iOS < 7.0 has no sincos_stret.
112 return !TT
.isOSVersionLT(7, 0);
113 // Any other darwin such as WatchOS/TvOS is new enough.
117 void TargetLoweringBase::InitLibcalls(const Triple
&TT
) {
118 #define HANDLE_LIBCALL(code, name) \
119 setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122 // Initialize calling conventions to their default.
123 for (int LC
= 0; LC
< RTLIB::UNKNOWN_LIBCALL
; ++LC
)
124 setLibcallCallingConv((RTLIB::Libcall
)LC
, CallingConv::C
);
126 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
128 setLibcallName(RTLIB::ADD_F128
, "__addkf3");
129 setLibcallName(RTLIB::SUB_F128
, "__subkf3");
130 setLibcallName(RTLIB::MUL_F128
, "__mulkf3");
131 setLibcallName(RTLIB::DIV_F128
, "__divkf3");
132 setLibcallName(RTLIB::POWI_F128
, "__powikf2");
133 setLibcallName(RTLIB::FPEXT_F32_F128
, "__extendsfkf2");
134 setLibcallName(RTLIB::FPEXT_F64_F128
, "__extenddfkf2");
135 setLibcallName(RTLIB::FPROUND_F128_F32
, "__trunckfsf2");
136 setLibcallName(RTLIB::FPROUND_F128_F64
, "__trunckfdf2");
137 setLibcallName(RTLIB::FPTOSINT_F128_I32
, "__fixkfsi");
138 setLibcallName(RTLIB::FPTOSINT_F128_I64
, "__fixkfdi");
139 setLibcallName(RTLIB::FPTOSINT_F128_I128
, "__fixkfti");
140 setLibcallName(RTLIB::FPTOUINT_F128_I32
, "__fixunskfsi");
141 setLibcallName(RTLIB::FPTOUINT_F128_I64
, "__fixunskfdi");
142 setLibcallName(RTLIB::FPTOUINT_F128_I128
, "__fixunskfti");
143 setLibcallName(RTLIB::SINTTOFP_I32_F128
, "__floatsikf");
144 setLibcallName(RTLIB::SINTTOFP_I64_F128
, "__floatdikf");
145 setLibcallName(RTLIB::SINTTOFP_I128_F128
, "__floattikf");
146 setLibcallName(RTLIB::UINTTOFP_I32_F128
, "__floatunsikf");
147 setLibcallName(RTLIB::UINTTOFP_I64_F128
, "__floatundikf");
148 setLibcallName(RTLIB::UINTTOFP_I128_F128
, "__floatuntikf");
149 setLibcallName(RTLIB::OEQ_F128
, "__eqkf2");
150 setLibcallName(RTLIB::UNE_F128
, "__nekf2");
151 setLibcallName(RTLIB::OGE_F128
, "__gekf2");
152 setLibcallName(RTLIB::OLT_F128
, "__ltkf2");
153 setLibcallName(RTLIB::OLE_F128
, "__lekf2");
154 setLibcallName(RTLIB::OGT_F128
, "__gtkf2");
155 setLibcallName(RTLIB::UO_F128
, "__unordkf2");
158 // A few names are different on particular architectures or environments.
159 if (TT
.isOSDarwin()) {
160 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
161 // of the gnueabi-style __gnu_*_ieee.
162 // FIXME: What about other targets?
163 setLibcallName(RTLIB::FPEXT_F16_F32
, "__extendhfsf2");
164 setLibcallName(RTLIB::FPROUND_F32_F16
, "__truncsfhf2");
166 // Some darwins have an optimized __bzero/bzero function.
167 switch (TT
.getArch()) {
170 if (TT
.isMacOSX() && !TT
.isMacOSXVersionLT(10, 6))
171 setLibcallName(RTLIB::BZERO
, "__bzero");
173 case Triple::aarch64
:
174 case Triple::aarch64_32
:
175 setLibcallName(RTLIB::BZERO
, "bzero");
181 if (darwinHasSinCos(TT
)) {
182 setLibcallName(RTLIB::SINCOS_STRET_F32
, "__sincosf_stret");
183 setLibcallName(RTLIB::SINCOS_STRET_F64
, "__sincos_stret");
184 if (TT
.isWatchABI()) {
185 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32
,
186 CallingConv::ARM_AAPCS_VFP
);
187 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64
,
188 CallingConv::ARM_AAPCS_VFP
);
192 setLibcallName(RTLIB::FPEXT_F16_F32
, "__gnu_h2f_ieee");
193 setLibcallName(RTLIB::FPROUND_F32_F16
, "__gnu_f2h_ieee");
196 if (TT
.isGNUEnvironment() || TT
.isOSFuchsia() ||
197 (TT
.isAndroid() && !TT
.isAndroidVersionLT(9))) {
198 setLibcallName(RTLIB::SINCOS_F32
, "sincosf");
199 setLibcallName(RTLIB::SINCOS_F64
, "sincos");
200 setLibcallName(RTLIB::SINCOS_F80
, "sincosl");
201 setLibcallName(RTLIB::SINCOS_F128
, "sincosl");
202 setLibcallName(RTLIB::SINCOS_PPCF128
, "sincosl");
206 setLibcallName(RTLIB::SINCOS_F32
, "sincosf");
207 setLibcallName(RTLIB::SINCOS_F64
, "sincos");
210 if (TT
.isOSOpenBSD()) {
211 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL
, nullptr);
215 /// GetFPLibCall - Helper to return the right libcall for the given floating
216 /// point type, or UNKNOWN_LIBCALL if there is none.
217 RTLIB::Libcall
RTLIB::getFPLibCall(EVT VT
,
218 RTLIB::Libcall Call_F32
,
219 RTLIB::Libcall Call_F64
,
220 RTLIB::Libcall Call_F80
,
221 RTLIB::Libcall Call_F128
,
222 RTLIB::Libcall Call_PPCF128
) {
224 VT
== MVT::f32
? Call_F32
:
225 VT
== MVT::f64
? Call_F64
:
226 VT
== MVT::f80
? Call_F80
:
227 VT
== MVT::f128
? Call_F128
:
228 VT
== MVT::ppcf128
? Call_PPCF128
:
229 RTLIB::UNKNOWN_LIBCALL
;
232 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
233 /// UNKNOWN_LIBCALL if there is none.
234 RTLIB::Libcall
RTLIB::getFPEXT(EVT OpVT
, EVT RetVT
) {
235 if (OpVT
== MVT::f16
) {
236 if (RetVT
== MVT::f32
)
237 return FPEXT_F16_F32
;
238 if (RetVT
== MVT::f64
)
239 return FPEXT_F16_F64
;
240 if (RetVT
== MVT::f80
)
241 return FPEXT_F16_F80
;
242 if (RetVT
== MVT::f128
)
243 return FPEXT_F16_F128
;
244 } else if (OpVT
== MVT::f32
) {
245 if (RetVT
== MVT::f64
)
246 return FPEXT_F32_F64
;
247 if (RetVT
== MVT::f128
)
248 return FPEXT_F32_F128
;
249 if (RetVT
== MVT::ppcf128
)
250 return FPEXT_F32_PPCF128
;
251 } else if (OpVT
== MVT::f64
) {
252 if (RetVT
== MVT::f128
)
253 return FPEXT_F64_F128
;
254 else if (RetVT
== MVT::ppcf128
)
255 return FPEXT_F64_PPCF128
;
256 } else if (OpVT
== MVT::f80
) {
257 if (RetVT
== MVT::f128
)
258 return FPEXT_F80_F128
;
261 return UNKNOWN_LIBCALL
;
264 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
265 /// UNKNOWN_LIBCALL if there is none.
266 RTLIB::Libcall
RTLIB::getFPROUND(EVT OpVT
, EVT RetVT
) {
267 if (RetVT
== MVT::f16
) {
268 if (OpVT
== MVT::f32
)
269 return FPROUND_F32_F16
;
270 if (OpVT
== MVT::f64
)
271 return FPROUND_F64_F16
;
272 if (OpVT
== MVT::f80
)
273 return FPROUND_F80_F16
;
274 if (OpVT
== MVT::f128
)
275 return FPROUND_F128_F16
;
276 if (OpVT
== MVT::ppcf128
)
277 return FPROUND_PPCF128_F16
;
278 } else if (RetVT
== MVT::f32
) {
279 if (OpVT
== MVT::f64
)
280 return FPROUND_F64_F32
;
281 if (OpVT
== MVT::f80
)
282 return FPROUND_F80_F32
;
283 if (OpVT
== MVT::f128
)
284 return FPROUND_F128_F32
;
285 if (OpVT
== MVT::ppcf128
)
286 return FPROUND_PPCF128_F32
;
287 } else if (RetVT
== MVT::f64
) {
288 if (OpVT
== MVT::f80
)
289 return FPROUND_F80_F64
;
290 if (OpVT
== MVT::f128
)
291 return FPROUND_F128_F64
;
292 if (OpVT
== MVT::ppcf128
)
293 return FPROUND_PPCF128_F64
;
294 } else if (RetVT
== MVT::f80
) {
295 if (OpVT
== MVT::f128
)
296 return FPROUND_F128_F80
;
299 return UNKNOWN_LIBCALL
;
302 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
303 /// UNKNOWN_LIBCALL if there is none.
304 RTLIB::Libcall
RTLIB::getFPTOSINT(EVT OpVT
, EVT RetVT
) {
305 if (OpVT
== MVT::f16
) {
306 if (RetVT
== MVT::i32
)
307 return FPTOSINT_F16_I32
;
308 if (RetVT
== MVT::i64
)
309 return FPTOSINT_F16_I64
;
310 if (RetVT
== MVT::i128
)
311 return FPTOSINT_F16_I128
;
312 } else if (OpVT
== MVT::f32
) {
313 if (RetVT
== MVT::i32
)
314 return FPTOSINT_F32_I32
;
315 if (RetVT
== MVT::i64
)
316 return FPTOSINT_F32_I64
;
317 if (RetVT
== MVT::i128
)
318 return FPTOSINT_F32_I128
;
319 } else if (OpVT
== MVT::f64
) {
320 if (RetVT
== MVT::i32
)
321 return FPTOSINT_F64_I32
;
322 if (RetVT
== MVT::i64
)
323 return FPTOSINT_F64_I64
;
324 if (RetVT
== MVT::i128
)
325 return FPTOSINT_F64_I128
;
326 } else if (OpVT
== MVT::f80
) {
327 if (RetVT
== MVT::i32
)
328 return FPTOSINT_F80_I32
;
329 if (RetVT
== MVT::i64
)
330 return FPTOSINT_F80_I64
;
331 if (RetVT
== MVT::i128
)
332 return FPTOSINT_F80_I128
;
333 } else if (OpVT
== MVT::f128
) {
334 if (RetVT
== MVT::i32
)
335 return FPTOSINT_F128_I32
;
336 if (RetVT
== MVT::i64
)
337 return FPTOSINT_F128_I64
;
338 if (RetVT
== MVT::i128
)
339 return FPTOSINT_F128_I128
;
340 } else if (OpVT
== MVT::ppcf128
) {
341 if (RetVT
== MVT::i32
)
342 return FPTOSINT_PPCF128_I32
;
343 if (RetVT
== MVT::i64
)
344 return FPTOSINT_PPCF128_I64
;
345 if (RetVT
== MVT::i128
)
346 return FPTOSINT_PPCF128_I128
;
348 return UNKNOWN_LIBCALL
;
351 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
352 /// UNKNOWN_LIBCALL if there is none.
353 RTLIB::Libcall
RTLIB::getFPTOUINT(EVT OpVT
, EVT RetVT
) {
354 if (OpVT
== MVT::f16
) {
355 if (RetVT
== MVT::i32
)
356 return FPTOUINT_F16_I32
;
357 if (RetVT
== MVT::i64
)
358 return FPTOUINT_F16_I64
;
359 if (RetVT
== MVT::i128
)
360 return FPTOUINT_F16_I128
;
361 } else if (OpVT
== MVT::f32
) {
362 if (RetVT
== MVT::i32
)
363 return FPTOUINT_F32_I32
;
364 if (RetVT
== MVT::i64
)
365 return FPTOUINT_F32_I64
;
366 if (RetVT
== MVT::i128
)
367 return FPTOUINT_F32_I128
;
368 } else if (OpVT
== MVT::f64
) {
369 if (RetVT
== MVT::i32
)
370 return FPTOUINT_F64_I32
;
371 if (RetVT
== MVT::i64
)
372 return FPTOUINT_F64_I64
;
373 if (RetVT
== MVT::i128
)
374 return FPTOUINT_F64_I128
;
375 } else if (OpVT
== MVT::f80
) {
376 if (RetVT
== MVT::i32
)
377 return FPTOUINT_F80_I32
;
378 if (RetVT
== MVT::i64
)
379 return FPTOUINT_F80_I64
;
380 if (RetVT
== MVT::i128
)
381 return FPTOUINT_F80_I128
;
382 } else if (OpVT
== MVT::f128
) {
383 if (RetVT
== MVT::i32
)
384 return FPTOUINT_F128_I32
;
385 if (RetVT
== MVT::i64
)
386 return FPTOUINT_F128_I64
;
387 if (RetVT
== MVT::i128
)
388 return FPTOUINT_F128_I128
;
389 } else if (OpVT
== MVT::ppcf128
) {
390 if (RetVT
== MVT::i32
)
391 return FPTOUINT_PPCF128_I32
;
392 if (RetVT
== MVT::i64
)
393 return FPTOUINT_PPCF128_I64
;
394 if (RetVT
== MVT::i128
)
395 return FPTOUINT_PPCF128_I128
;
397 return UNKNOWN_LIBCALL
;
400 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
401 /// UNKNOWN_LIBCALL if there is none.
402 RTLIB::Libcall
RTLIB::getSINTTOFP(EVT OpVT
, EVT RetVT
) {
403 if (OpVT
== MVT::i32
) {
404 if (RetVT
== MVT::f16
)
405 return SINTTOFP_I32_F16
;
406 if (RetVT
== MVT::f32
)
407 return SINTTOFP_I32_F32
;
408 if (RetVT
== MVT::f64
)
409 return SINTTOFP_I32_F64
;
410 if (RetVT
== MVT::f80
)
411 return SINTTOFP_I32_F80
;
412 if (RetVT
== MVT::f128
)
413 return SINTTOFP_I32_F128
;
414 if (RetVT
== MVT::ppcf128
)
415 return SINTTOFP_I32_PPCF128
;
416 } else if (OpVT
== MVT::i64
) {
417 if (RetVT
== MVT::f16
)
418 return SINTTOFP_I64_F16
;
419 if (RetVT
== MVT::f32
)
420 return SINTTOFP_I64_F32
;
421 if (RetVT
== MVT::f64
)
422 return SINTTOFP_I64_F64
;
423 if (RetVT
== MVT::f80
)
424 return SINTTOFP_I64_F80
;
425 if (RetVT
== MVT::f128
)
426 return SINTTOFP_I64_F128
;
427 if (RetVT
== MVT::ppcf128
)
428 return SINTTOFP_I64_PPCF128
;
429 } else if (OpVT
== MVT::i128
) {
430 if (RetVT
== MVT::f16
)
431 return SINTTOFP_I128_F16
;
432 if (RetVT
== MVT::f32
)
433 return SINTTOFP_I128_F32
;
434 if (RetVT
== MVT::f64
)
435 return SINTTOFP_I128_F64
;
436 if (RetVT
== MVT::f80
)
437 return SINTTOFP_I128_F80
;
438 if (RetVT
== MVT::f128
)
439 return SINTTOFP_I128_F128
;
440 if (RetVT
== MVT::ppcf128
)
441 return SINTTOFP_I128_PPCF128
;
443 return UNKNOWN_LIBCALL
;
446 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
447 /// UNKNOWN_LIBCALL if there is none.
448 RTLIB::Libcall
RTLIB::getUINTTOFP(EVT OpVT
, EVT RetVT
) {
449 if (OpVT
== MVT::i32
) {
450 if (RetVT
== MVT::f16
)
451 return UINTTOFP_I32_F16
;
452 if (RetVT
== MVT::f32
)
453 return UINTTOFP_I32_F32
;
454 if (RetVT
== MVT::f64
)
455 return UINTTOFP_I32_F64
;
456 if (RetVT
== MVT::f80
)
457 return UINTTOFP_I32_F80
;
458 if (RetVT
== MVT::f128
)
459 return UINTTOFP_I32_F128
;
460 if (RetVT
== MVT::ppcf128
)
461 return UINTTOFP_I32_PPCF128
;
462 } else if (OpVT
== MVT::i64
) {
463 if (RetVT
== MVT::f16
)
464 return UINTTOFP_I64_F16
;
465 if (RetVT
== MVT::f32
)
466 return UINTTOFP_I64_F32
;
467 if (RetVT
== MVT::f64
)
468 return UINTTOFP_I64_F64
;
469 if (RetVT
== MVT::f80
)
470 return UINTTOFP_I64_F80
;
471 if (RetVT
== MVT::f128
)
472 return UINTTOFP_I64_F128
;
473 if (RetVT
== MVT::ppcf128
)
474 return UINTTOFP_I64_PPCF128
;
475 } else if (OpVT
== MVT::i128
) {
476 if (RetVT
== MVT::f16
)
477 return UINTTOFP_I128_F16
;
478 if (RetVT
== MVT::f32
)
479 return UINTTOFP_I128_F32
;
480 if (RetVT
== MVT::f64
)
481 return UINTTOFP_I128_F64
;
482 if (RetVT
== MVT::f80
)
483 return UINTTOFP_I128_F80
;
484 if (RetVT
== MVT::f128
)
485 return UINTTOFP_I128_F128
;
486 if (RetVT
== MVT::ppcf128
)
487 return UINTTOFP_I128_PPCF128
;
489 return UNKNOWN_LIBCALL
;
492 RTLIB::Libcall
RTLIB::getPOWI(EVT RetVT
) {
493 return getFPLibCall(RetVT
, POWI_F32
, POWI_F64
, POWI_F80
, POWI_F128
,
497 RTLIB::Libcall
RTLIB::getOUTLINE_ATOMIC(unsigned Opc
, AtomicOrdering Order
,
499 unsigned ModeN
, ModelN
;
500 switch (VT
.SimpleTy
) {
517 return UNKNOWN_LIBCALL
;
521 case AtomicOrdering::Monotonic
:
524 case AtomicOrdering::Acquire
:
527 case AtomicOrdering::Release
:
530 case AtomicOrdering::AcquireRelease
:
531 case AtomicOrdering::SequentiallyConsistent
:
535 return UNKNOWN_LIBCALL
;
538 #define LCALLS(A, B) \
539 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
541 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
543 case ISD::ATOMIC_CMP_SWAP
: {
544 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS
)};
545 return LC
[ModeN
][ModelN
];
547 case ISD::ATOMIC_SWAP
: {
548 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP
)};
549 return LC
[ModeN
][ModelN
];
551 case ISD::ATOMIC_LOAD_ADD
: {
552 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD
)};
553 return LC
[ModeN
][ModelN
];
555 case ISD::ATOMIC_LOAD_OR
: {
556 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET
)};
557 return LC
[ModeN
][ModelN
];
559 case ISD::ATOMIC_LOAD_CLR
: {
560 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR
)};
561 return LC
[ModeN
][ModelN
];
563 case ISD::ATOMIC_LOAD_XOR
: {
564 const Libcall LC
[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR
)};
565 return LC
[ModeN
][ModelN
];
568 return UNKNOWN_LIBCALL
;
574 RTLIB::Libcall
RTLIB::getSYNC(unsigned Opc
, MVT VT
) {
575 #define OP_TO_LIBCALL(Name, Enum) \
577 switch (VT.SimpleTy) { \
579 return UNKNOWN_LIBCALL; \
593 OP_TO_LIBCALL(ISD::ATOMIC_SWAP
, SYNC_LOCK_TEST_AND_SET
)
594 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP
, SYNC_VAL_COMPARE_AND_SWAP
)
595 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD
, SYNC_FETCH_AND_ADD
)
596 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB
, SYNC_FETCH_AND_SUB
)
597 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND
, SYNC_FETCH_AND_AND
)
598 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR
, SYNC_FETCH_AND_OR
)
599 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR
, SYNC_FETCH_AND_XOR
)
600 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND
, SYNC_FETCH_AND_NAND
)
601 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX
, SYNC_FETCH_AND_MAX
)
602 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX
, SYNC_FETCH_AND_UMAX
)
603 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN
, SYNC_FETCH_AND_MIN
)
604 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN
, SYNC_FETCH_AND_UMIN
)
609 return UNKNOWN_LIBCALL
;
612 RTLIB::Libcall
RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize
) {
613 switch (ElementSize
) {
615 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1
;
617 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2
;
619 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4
;
621 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8
;
623 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16
;
625 return UNKNOWN_LIBCALL
;
629 RTLIB::Libcall
RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize
) {
630 switch (ElementSize
) {
632 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1
;
634 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2
;
636 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4
;
638 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8
;
640 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16
;
642 return UNKNOWN_LIBCALL
;
646 RTLIB::Libcall
RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize
) {
647 switch (ElementSize
) {
649 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1
;
651 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2
;
653 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4
;
655 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8
;
657 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16
;
659 return UNKNOWN_LIBCALL
;
663 /// InitCmpLibcallCCs - Set default comparison libcall CC.
664 static void InitCmpLibcallCCs(ISD::CondCode
*CCs
) {
665 memset(CCs
, ISD::SETCC_INVALID
, sizeof(ISD::CondCode
)*RTLIB::UNKNOWN_LIBCALL
);
666 CCs
[RTLIB::OEQ_F32
] = ISD::SETEQ
;
667 CCs
[RTLIB::OEQ_F64
] = ISD::SETEQ
;
668 CCs
[RTLIB::OEQ_F128
] = ISD::SETEQ
;
669 CCs
[RTLIB::OEQ_PPCF128
] = ISD::SETEQ
;
670 CCs
[RTLIB::UNE_F32
] = ISD::SETNE
;
671 CCs
[RTLIB::UNE_F64
] = ISD::SETNE
;
672 CCs
[RTLIB::UNE_F128
] = ISD::SETNE
;
673 CCs
[RTLIB::UNE_PPCF128
] = ISD::SETNE
;
674 CCs
[RTLIB::OGE_F32
] = ISD::SETGE
;
675 CCs
[RTLIB::OGE_F64
] = ISD::SETGE
;
676 CCs
[RTLIB::OGE_F128
] = ISD::SETGE
;
677 CCs
[RTLIB::OGE_PPCF128
] = ISD::SETGE
;
678 CCs
[RTLIB::OLT_F32
] = ISD::SETLT
;
679 CCs
[RTLIB::OLT_F64
] = ISD::SETLT
;
680 CCs
[RTLIB::OLT_F128
] = ISD::SETLT
;
681 CCs
[RTLIB::OLT_PPCF128
] = ISD::SETLT
;
682 CCs
[RTLIB::OLE_F32
] = ISD::SETLE
;
683 CCs
[RTLIB::OLE_F64
] = ISD::SETLE
;
684 CCs
[RTLIB::OLE_F128
] = ISD::SETLE
;
685 CCs
[RTLIB::OLE_PPCF128
] = ISD::SETLE
;
686 CCs
[RTLIB::OGT_F32
] = ISD::SETGT
;
687 CCs
[RTLIB::OGT_F64
] = ISD::SETGT
;
688 CCs
[RTLIB::OGT_F128
] = ISD::SETGT
;
689 CCs
[RTLIB::OGT_PPCF128
] = ISD::SETGT
;
690 CCs
[RTLIB::UO_F32
] = ISD::SETNE
;
691 CCs
[RTLIB::UO_F64
] = ISD::SETNE
;
692 CCs
[RTLIB::UO_F128
] = ISD::SETNE
;
693 CCs
[RTLIB::UO_PPCF128
] = ISD::SETNE
;
696 /// NOTE: The TargetMachine owns TLOF.
697 TargetLoweringBase::TargetLoweringBase(const TargetMachine
&tm
) : TM(tm
) {
700 // Perform these initializations only once.
701 MaxStoresPerMemset
= MaxStoresPerMemcpy
= MaxStoresPerMemmove
=
702 MaxLoadsPerMemcmp
= 8;
703 MaxGluedStoresPerMemcpy
= 0;
704 MaxStoresPerMemsetOptSize
= MaxStoresPerMemcpyOptSize
=
705 MaxStoresPerMemmoveOptSize
= MaxLoadsPerMemcmpOptSize
= 4;
706 HasMultipleConditionRegisters
= false;
707 HasExtractBitsInsn
= false;
708 JumpIsExpensive
= JumpIsExpensiveOverride
;
709 PredictableSelectIsExpensive
= false;
710 EnableExtLdPromotion
= false;
711 StackPointerRegisterToSaveRestore
= 0;
712 BooleanContents
= UndefinedBooleanContent
;
713 BooleanFloatContents
= UndefinedBooleanContent
;
714 BooleanVectorContents
= UndefinedBooleanContent
;
715 SchedPreferenceInfo
= Sched::ILP
;
716 GatherAllAliasesMaxDepth
= 18;
717 IsStrictFPEnabled
= DisableStrictNodeMutation
;
718 // TODO: the default will be switched to 0 in the next commit, along
719 // with the Target-specific changes necessary.
720 MaxAtomicSizeInBitsSupported
= 1024;
722 MinCmpXchgSizeInBits
= 0;
723 SupportsUnalignedAtomics
= false;
725 std::fill(std::begin(LibcallRoutineNames
), std::end(LibcallRoutineNames
), nullptr);
727 InitLibcalls(TM
.getTargetTriple());
728 InitCmpLibcallCCs(CmpLibcallCCs
);
731 void TargetLoweringBase::initActions() {
732 // All operations default to being supported.
733 memset(OpActions
, 0, sizeof(OpActions
));
734 memset(LoadExtActions
, 0, sizeof(LoadExtActions
));
735 memset(TruncStoreActions
, 0, sizeof(TruncStoreActions
));
736 memset(IndexedModeActions
, 0, sizeof(IndexedModeActions
));
737 memset(CondCodeActions
, 0, sizeof(CondCodeActions
));
738 std::fill(std::begin(RegClassForVT
), std::end(RegClassForVT
), nullptr);
739 std::fill(std::begin(TargetDAGCombineArray
),
740 std::end(TargetDAGCombineArray
), 0);
742 for (MVT VT
: MVT::fp_valuetypes()) {
743 MVT IntVT
= MVT::getIntegerVT(VT
.getFixedSizeInBits());
744 if (IntVT
.isValid()) {
745 setOperationAction(ISD::ATOMIC_SWAP
, VT
, Promote
);
746 AddPromotedToType(ISD::ATOMIC_SWAP
, VT
, IntVT
);
750 // Set default actions for various operations.
751 for (MVT VT
: MVT::all_valuetypes()) {
752 // Default all indexed load / store to expand.
753 for (unsigned IM
= (unsigned)ISD::PRE_INC
;
754 IM
!= (unsigned)ISD::LAST_INDEXED_MODE
; ++IM
) {
755 setIndexedLoadAction(IM
, VT
, Expand
);
756 setIndexedStoreAction(IM
, VT
, Expand
);
757 setIndexedMaskedLoadAction(IM
, VT
, Expand
);
758 setIndexedMaskedStoreAction(IM
, VT
, Expand
);
761 // Most backends expect to see the node which just returns the value loaded.
762 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
, VT
, Expand
);
764 // These operations default to expand.
765 setOperationAction(ISD::FGETSIGN
, VT
, Expand
);
766 setOperationAction(ISD::ISNAN
, VT
, Expand
);
767 setOperationAction(ISD::CONCAT_VECTORS
, VT
, Expand
);
768 setOperationAction(ISD::FMINNUM
, VT
, Expand
);
769 setOperationAction(ISD::FMAXNUM
, VT
, Expand
);
770 setOperationAction(ISD::FMINNUM_IEEE
, VT
, Expand
);
771 setOperationAction(ISD::FMAXNUM_IEEE
, VT
, Expand
);
772 setOperationAction(ISD::FMINIMUM
, VT
, Expand
);
773 setOperationAction(ISD::FMAXIMUM
, VT
, Expand
);
774 setOperationAction(ISD::FMAD
, VT
, Expand
);
775 setOperationAction(ISD::SMIN
, VT
, Expand
);
776 setOperationAction(ISD::SMAX
, VT
, Expand
);
777 setOperationAction(ISD::UMIN
, VT
, Expand
);
778 setOperationAction(ISD::UMAX
, VT
, Expand
);
779 setOperationAction(ISD::ABS
, VT
, Expand
);
780 setOperationAction(ISD::FSHL
, VT
, Expand
);
781 setOperationAction(ISD::FSHR
, VT
, Expand
);
782 setOperationAction(ISD::SADDSAT
, VT
, Expand
);
783 setOperationAction(ISD::UADDSAT
, VT
, Expand
);
784 setOperationAction(ISD::SSUBSAT
, VT
, Expand
);
785 setOperationAction(ISD::USUBSAT
, VT
, Expand
);
786 setOperationAction(ISD::SSHLSAT
, VT
, Expand
);
787 setOperationAction(ISD::USHLSAT
, VT
, Expand
);
788 setOperationAction(ISD::SMULFIX
, VT
, Expand
);
789 setOperationAction(ISD::SMULFIXSAT
, VT
, Expand
);
790 setOperationAction(ISD::UMULFIX
, VT
, Expand
);
791 setOperationAction(ISD::UMULFIXSAT
, VT
, Expand
);
792 setOperationAction(ISD::SDIVFIX
, VT
, Expand
);
793 setOperationAction(ISD::SDIVFIXSAT
, VT
, Expand
);
794 setOperationAction(ISD::UDIVFIX
, VT
, Expand
);
795 setOperationAction(ISD::UDIVFIXSAT
, VT
, Expand
);
796 setOperationAction(ISD::FP_TO_SINT_SAT
, VT
, Expand
);
797 setOperationAction(ISD::FP_TO_UINT_SAT
, VT
, Expand
);
799 // Overflow operations default to expand
800 setOperationAction(ISD::SADDO
, VT
, Expand
);
801 setOperationAction(ISD::SSUBO
, VT
, Expand
);
802 setOperationAction(ISD::UADDO
, VT
, Expand
);
803 setOperationAction(ISD::USUBO
, VT
, Expand
);
804 setOperationAction(ISD::SMULO
, VT
, Expand
);
805 setOperationAction(ISD::UMULO
, VT
, Expand
);
807 // ADDCARRY operations default to expand
808 setOperationAction(ISD::ADDCARRY
, VT
, Expand
);
809 setOperationAction(ISD::SUBCARRY
, VT
, Expand
);
810 setOperationAction(ISD::SETCCCARRY
, VT
, Expand
);
811 setOperationAction(ISD::SADDO_CARRY
, VT
, Expand
);
812 setOperationAction(ISD::SSUBO_CARRY
, VT
, Expand
);
814 // ADDC/ADDE/SUBC/SUBE default to expand.
815 setOperationAction(ISD::ADDC
, VT
, Expand
);
816 setOperationAction(ISD::ADDE
, VT
, Expand
);
817 setOperationAction(ISD::SUBC
, VT
, Expand
);
818 setOperationAction(ISD::SUBE
, VT
, Expand
);
820 // Absolute difference
821 setOperationAction(ISD::ABDS
, VT
, Expand
);
822 setOperationAction(ISD::ABDU
, VT
, Expand
);
824 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
825 setOperationAction(ISD::CTLZ_ZERO_UNDEF
, VT
, Expand
);
826 setOperationAction(ISD::CTTZ_ZERO_UNDEF
, VT
, Expand
);
828 setOperationAction(ISD::BITREVERSE
, VT
, Expand
);
829 setOperationAction(ISD::PARITY
, VT
, Expand
);
831 // These library functions default to expand.
832 setOperationAction(ISD::FROUND
, VT
, Expand
);
833 setOperationAction(ISD::FROUNDEVEN
, VT
, Expand
);
834 setOperationAction(ISD::FPOWI
, VT
, Expand
);
836 // These operations default to expand for vector types.
838 setOperationAction(ISD::FCOPYSIGN
, VT
, Expand
);
839 setOperationAction(ISD::SIGN_EXTEND_INREG
, VT
, Expand
);
840 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG
, VT
, Expand
);
841 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG
, VT
, Expand
);
842 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG
, VT
, Expand
);
843 setOperationAction(ISD::SPLAT_VECTOR
, VT
, Expand
);
846 // Constrained floating-point operations default to expand.
847 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
848 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
849 #include "llvm/IR/ConstrainedOps.def"
851 // For most targets @llvm.get.dynamic.area.offset just returns 0.
852 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET
, VT
, Expand
);
854 // Vector reduction default to expand.
855 setOperationAction(ISD::VECREDUCE_FADD
, VT
, Expand
);
856 setOperationAction(ISD::VECREDUCE_FMUL
, VT
, Expand
);
857 setOperationAction(ISD::VECREDUCE_ADD
, VT
, Expand
);
858 setOperationAction(ISD::VECREDUCE_MUL
, VT
, Expand
);
859 setOperationAction(ISD::VECREDUCE_AND
, VT
, Expand
);
860 setOperationAction(ISD::VECREDUCE_OR
, VT
, Expand
);
861 setOperationAction(ISD::VECREDUCE_XOR
, VT
, Expand
);
862 setOperationAction(ISD::VECREDUCE_SMAX
, VT
, Expand
);
863 setOperationAction(ISD::VECREDUCE_SMIN
, VT
, Expand
);
864 setOperationAction(ISD::VECREDUCE_UMAX
, VT
, Expand
);
865 setOperationAction(ISD::VECREDUCE_UMIN
, VT
, Expand
);
866 setOperationAction(ISD::VECREDUCE_FMAX
, VT
, Expand
);
867 setOperationAction(ISD::VECREDUCE_FMIN
, VT
, Expand
);
868 setOperationAction(ISD::VECREDUCE_SEQ_FADD
, VT
, Expand
);
869 setOperationAction(ISD::VECREDUCE_SEQ_FMUL
, VT
, Expand
);
871 // Named vector shuffles default to expand.
872 setOperationAction(ISD::VECTOR_SPLICE
, VT
, Expand
);
875 // Most targets ignore the @llvm.prefetch intrinsic.
876 setOperationAction(ISD::PREFETCH
, MVT::Other
, Expand
);
878 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
879 setOperationAction(ISD::READCYCLECOUNTER
, MVT::i64
, Expand
);
881 // ConstantFP nodes default to expand. Targets can either change this to
882 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
883 // to optimize expansions for certain constants.
884 setOperationAction(ISD::ConstantFP
, MVT::f16
, Expand
);
885 setOperationAction(ISD::ConstantFP
, MVT::f32
, Expand
);
886 setOperationAction(ISD::ConstantFP
, MVT::f64
, Expand
);
887 setOperationAction(ISD::ConstantFP
, MVT::f80
, Expand
);
888 setOperationAction(ISD::ConstantFP
, MVT::f128
, Expand
);
890 // These library functions default to expand.
891 for (MVT VT
: {MVT::f32
, MVT::f64
, MVT::f128
}) {
892 setOperationAction(ISD::FCBRT
, VT
, Expand
);
893 setOperationAction(ISD::FLOG
, VT
, Expand
);
894 setOperationAction(ISD::FLOG2
, VT
, Expand
);
895 setOperationAction(ISD::FLOG10
, VT
, Expand
);
896 setOperationAction(ISD::FEXP
, VT
, Expand
);
897 setOperationAction(ISD::FEXP2
, VT
, Expand
);
898 setOperationAction(ISD::FFLOOR
, VT
, Expand
);
899 setOperationAction(ISD::FNEARBYINT
, VT
, Expand
);
900 setOperationAction(ISD::FCEIL
, VT
, Expand
);
901 setOperationAction(ISD::FRINT
, VT
, Expand
);
902 setOperationAction(ISD::FTRUNC
, VT
, Expand
);
903 setOperationAction(ISD::FROUND
, VT
, Expand
);
904 setOperationAction(ISD::FROUNDEVEN
, VT
, Expand
);
905 setOperationAction(ISD::LROUND
, VT
, Expand
);
906 setOperationAction(ISD::LLROUND
, VT
, Expand
);
907 setOperationAction(ISD::LRINT
, VT
, Expand
);
908 setOperationAction(ISD::LLRINT
, VT
, Expand
);
911 // Default ISD::TRAP to expand (which turns it into abort).
912 setOperationAction(ISD::TRAP
, MVT::Other
, Expand
);
914 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
915 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
916 setOperationAction(ISD::DEBUGTRAP
, MVT::Other
, Expand
);
918 setOperationAction(ISD::UBSANTRAP
, MVT::Other
, Expand
);
921 MVT
TargetLoweringBase::getScalarShiftAmountTy(const DataLayout
&DL
,
923 return MVT::getIntegerVT(DL
.getPointerSizeInBits(0));
926 EVT
TargetLoweringBase::getShiftAmountTy(EVT LHSTy
, const DataLayout
&DL
,
927 bool LegalTypes
) const {
928 assert(LHSTy
.isInteger() && "Shift amount is not an integer type!");
929 if (LHSTy
.isVector())
931 return LegalTypes
? getScalarShiftAmountTy(DL
, LHSTy
)
935 bool TargetLoweringBase::canOpTrap(unsigned Op
, EVT VT
) const {
936 assert(isTypeLegal(VT
));
948 bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS
,
949 unsigned DestAS
) const {
950 return TM
.isNoopAddrSpaceCast(SrcAS
, DestAS
);
953 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive
) {
954 // If the command-line option was specified, ignore this request.
955 if (!JumpIsExpensiveOverride
.getNumOccurrences())
956 JumpIsExpensive
= isExpensive
;
959 TargetLoweringBase::LegalizeKind
960 TargetLoweringBase::getTypeConversion(LLVMContext
&Context
, EVT VT
) const {
961 // If this is a simple type, use the ComputeRegisterProp mechanism.
963 MVT SVT
= VT
.getSimpleVT();
964 assert((unsigned)SVT
.SimpleTy
< array_lengthof(TransformToType
));
965 MVT NVT
= TransformToType
[SVT
.SimpleTy
];
966 LegalizeTypeAction LA
= ValueTypeActions
.getTypeAction(SVT
);
968 assert((LA
== TypeLegal
|| LA
== TypeSoftenFloat
||
969 LA
== TypeSoftPromoteHalf
||
971 ValueTypeActions
.getTypeAction(NVT
) != TypePromoteInteger
)) &&
972 "Promote may not follow Expand or Promote");
974 if (LA
== TypeSplitVector
)
975 return LegalizeKind(LA
, EVT(SVT
).getHalfNumVectorElementsVT(Context
));
976 if (LA
== TypeScalarizeVector
)
977 return LegalizeKind(LA
, SVT
.getVectorElementType());
978 return LegalizeKind(LA
, NVT
);
981 // Handle Extended Scalar Types.
982 if (!VT
.isVector()) {
983 assert(VT
.isInteger() && "Float types must be simple");
984 unsigned BitSize
= VT
.getSizeInBits();
985 // First promote to a power-of-two size, then expand if necessary.
986 if (BitSize
< 8 || !isPowerOf2_32(BitSize
)) {
987 EVT NVT
= VT
.getRoundIntegerType(Context
);
988 assert(NVT
!= VT
&& "Unable to round integer VT");
989 LegalizeKind NextStep
= getTypeConversion(Context
, NVT
);
990 // Avoid multi-step promotion.
991 if (NextStep
.first
== TypePromoteInteger
)
993 // Return rounded integer type.
994 return LegalizeKind(TypePromoteInteger
, NVT
);
997 return LegalizeKind(TypeExpandInteger
,
998 EVT::getIntegerVT(Context
, VT
.getSizeInBits() / 2));
1001 // Handle vector types.
1002 ElementCount NumElts
= VT
.getVectorElementCount();
1003 EVT EltVT
= VT
.getVectorElementType();
1005 // Vectors with only one element are always scalarized.
1006 if (NumElts
.isScalar())
1007 return LegalizeKind(TypeScalarizeVector
, EltVT
);
1009 // Try to widen vector elements until the element type is a power of two and
1010 // promote it to a legal type later on, for example:
1011 // <3 x i8> -> <4 x i8> -> <4 x i32>
1012 if (EltVT
.isInteger()) {
1013 // Vectors with a number of elements that is not a power of two are always
1014 // widened, for example <3 x i8> -> <4 x i8>.
1015 if (!VT
.isPow2VectorType()) {
1016 NumElts
= NumElts
.coefficientNextPowerOf2();
1017 EVT NVT
= EVT::getVectorVT(Context
, EltVT
, NumElts
);
1018 return LegalizeKind(TypeWidenVector
, NVT
);
1021 // Examine the element type.
1022 LegalizeKind LK
= getTypeConversion(Context
, EltVT
);
1024 // If type is to be expanded, split the vector.
1025 // <4 x i140> -> <2 x i140>
1026 if (LK
.first
== TypeExpandInteger
) {
1027 if (VT
.getVectorElementCount().isScalable())
1028 return LegalizeKind(TypeScalarizeScalableVector
, EltVT
);
1029 return LegalizeKind(TypeSplitVector
,
1030 VT
.getHalfNumVectorElementsVT(Context
));
1033 // Promote the integer element types until a legal vector type is found
1034 // or until the element integer type is too big. If a legal type was not
1035 // found, fallback to the usual mechanism of widening/splitting the
1037 EVT OldEltVT
= EltVT
;
1039 // Increase the bitwidth of the element to the next pow-of-two
1040 // (which is greater than 8 bits).
1041 EltVT
= EVT::getIntegerVT(Context
, 1 + EltVT
.getSizeInBits())
1042 .getRoundIntegerType(Context
);
1044 // Stop trying when getting a non-simple element type.
1045 // Note that vector elements may be greater than legal vector element
1046 // types. Example: X86 XMM registers hold 64bit element on 32bit
1048 if (!EltVT
.isSimple())
1051 // Build a new vector type and check if it is legal.
1052 MVT NVT
= MVT::getVectorVT(EltVT
.getSimpleVT(), NumElts
);
1053 // Found a legal promoted vector type.
1054 if (NVT
!= MVT() && ValueTypeActions
.getTypeAction(NVT
) == TypeLegal
)
1055 return LegalizeKind(TypePromoteInteger
,
1056 EVT::getVectorVT(Context
, EltVT
, NumElts
));
1059 // Reset the type to the unexpanded type if we did not find a legal vector
1060 // type with a promoted vector element type.
1064 // Try to widen the vector until a legal type is found.
1065 // If there is no wider legal type, split the vector.
1067 // Round up to the next power of 2.
1068 NumElts
= NumElts
.coefficientNextPowerOf2();
1070 // If there is no simple vector type with this many elements then there
1071 // cannot be a larger legal vector type. Note that this assumes that
1072 // there are no skipped intermediate vector types in the simple types.
1073 if (!EltVT
.isSimple())
1075 MVT LargerVector
= MVT::getVectorVT(EltVT
.getSimpleVT(), NumElts
);
1076 if (LargerVector
== MVT())
1079 // If this type is legal then widen the vector.
1080 if (ValueTypeActions
.getTypeAction(LargerVector
) == TypeLegal
)
1081 return LegalizeKind(TypeWidenVector
, LargerVector
);
1084 // Widen odd vectors to next power of two.
1085 if (!VT
.isPow2VectorType()) {
1086 EVT NVT
= VT
.getPow2VectorType(Context
);
1087 return LegalizeKind(TypeWidenVector
, NVT
);
1090 if (VT
.getVectorElementCount() == ElementCount::getScalable(1))
1091 return LegalizeKind(TypeScalarizeScalableVector
, EltVT
);
1093 // Vectors with illegal element types are expanded.
1094 EVT NVT
= EVT::getVectorVT(Context
, EltVT
,
1095 VT
.getVectorElementCount().divideCoefficientBy(2));
1096 return LegalizeKind(TypeSplitVector
, NVT
);
1099 static unsigned getVectorTypeBreakdownMVT(MVT VT
, MVT
&IntermediateVT
,
1100 unsigned &NumIntermediates
,
1102 TargetLoweringBase
*TLI
) {
1103 // Figure out the right, legal destination reg to copy into.
1104 ElementCount EC
= VT
.getVectorElementCount();
1105 MVT EltTy
= VT
.getVectorElementType();
1107 unsigned NumVectorRegs
= 1;
1109 // Scalable vectors cannot be scalarized, so splitting or widening is
1111 if (VT
.isScalableVector() && !isPowerOf2_32(EC
.getKnownMinValue()))
1113 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1115 // FIXME: We don't support non-power-of-2-sized vectors for now.
1116 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1117 if (!isPowerOf2_32(EC
.getKnownMinValue())) {
1118 // Split EC to unit size (scalable property is preserved).
1119 NumVectorRegs
= EC
.getKnownMinValue();
1120 EC
= ElementCount::getFixed(1);
1123 // Divide the input until we get to a supported size. This will
1124 // always end up with an EC that represent a scalar or a scalable
1126 while (EC
.getKnownMinValue() > 1 &&
1127 !TLI
->isTypeLegal(MVT::getVectorVT(EltTy
, EC
))) {
1128 EC
= EC
.divideCoefficientBy(2);
1129 NumVectorRegs
<<= 1;
1132 NumIntermediates
= NumVectorRegs
;
1134 MVT NewVT
= MVT::getVectorVT(EltTy
, EC
);
1135 if (!TLI
->isTypeLegal(NewVT
))
1137 IntermediateVT
= NewVT
;
1139 unsigned LaneSizeInBits
= NewVT
.getScalarSizeInBits();
1141 // Convert sizes such as i33 to i64.
1142 if (!isPowerOf2_32(LaneSizeInBits
))
1143 LaneSizeInBits
= NextPowerOf2(LaneSizeInBits
);
1145 MVT DestVT
= TLI
->getRegisterType(NewVT
);
1146 RegisterVT
= DestVT
;
1147 if (EVT(DestVT
).bitsLT(NewVT
)) // Value is expanded, e.g. i64 -> i16.
1148 return NumVectorRegs
* (LaneSizeInBits
/ DestVT
.getScalarSizeInBits());
1150 // Otherwise, promotion or legal types use the same number of registers as
1151 // the vector decimated to the appropriate level.
1152 return NumVectorRegs
;
1155 /// isLegalRC - Return true if the value types that can be represented by the
1156 /// specified register class are all legal.
1157 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo
&TRI
,
1158 const TargetRegisterClass
&RC
) const {
1159 for (auto I
= TRI
.legalclasstypes_begin(RC
); *I
!= MVT::Other
; ++I
)
1160 if (isTypeLegal(*I
))
1165 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1166 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1168 TargetLoweringBase::emitPatchPoint(MachineInstr
&InitialMI
,
1169 MachineBasicBlock
*MBB
) const {
1170 MachineInstr
*MI
= &InitialMI
;
1171 MachineFunction
&MF
= *MI
->getMF();
1172 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
1174 // We're handling multiple types of operands here:
1175 // PATCHPOINT MetaArgs - live-in, read only, direct
1176 // STATEPOINT Deopt Spill - live-through, read only, indirect
1177 // STATEPOINT Deopt Alloca - live-through, read only, direct
1178 // (We're currently conservative and mark the deopt slots read/write in
1180 // STATEPOINT GC Spill - live-through, read/write, indirect
1181 // STATEPOINT GC Alloca - live-through, read/write, direct
1182 // The live-in vs live-through is handled already (the live through ones are
1183 // all stack slots), but we need to handle the different type of stackmap
1184 // operands and memory effects here.
1186 if (!llvm::any_of(MI
->operands(),
1187 [](MachineOperand
&Operand
) { return Operand
.isFI(); }))
1190 MachineInstrBuilder MIB
= BuildMI(MF
, MI
->getDebugLoc(), MI
->getDesc());
1192 // Inherit previous memory operands.
1193 MIB
.cloneMemRefs(*MI
);
1195 for (unsigned i
= 0; i
< MI
->getNumOperands(); ++i
) {
1196 MachineOperand
&MO
= MI
->getOperand(i
);
1198 // Index of Def operand this Use it tied to.
1199 // Since Defs are coming before Uses, if Use is tied, then
1200 // index of Def must be smaller that index of that Use.
1201 // Also, Defs preserve their position in new MI.
1202 unsigned TiedTo
= i
;
1203 if (MO
.isReg() && MO
.isTied())
1204 TiedTo
= MI
->findTiedOperandIdx(i
);
1207 MIB
->tieOperands(TiedTo
, MIB
->getNumOperands() - 1);
1211 // foldMemoryOperand builds a new MI after replacing a single FI operand
1212 // with the canonical set of five x86 addressing-mode operands.
1213 int FI
= MO
.getIndex();
1215 // Add frame index operands recognized by stackmaps.cpp
1216 if (MFI
.isStatepointSpillSlotObjectIndex(FI
)) {
1217 // indirect-mem-ref tag, size, #FI, offset.
1218 // Used for spills inserted by StatepointLowering. This codepath is not
1219 // used for patchpoints/stackmaps at all, for these spilling is done via
1220 // foldMemoryOperand callback only.
1221 assert(MI
->getOpcode() == TargetOpcode::STATEPOINT
&& "sanity");
1222 MIB
.addImm(StackMaps::IndirectMemRefOp
);
1223 MIB
.addImm(MFI
.getObjectSize(FI
));
1227 // direct-mem-ref tag, #FI, offset.
1228 // Used by patchpoint, and direct alloca arguments to statepoints
1229 MIB
.addImm(StackMaps::DirectMemRefOp
);
1234 assert(MIB
->mayLoad() && "Folded a stackmap use to a non-load!");
1236 // Add a new memory operand for this FI.
1237 assert(MFI
.getObjectOffset(FI
) != -1);
1239 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1240 // PATCHPOINT should be updated to do the same. (TODO)
1241 if (MI
->getOpcode() != TargetOpcode::STATEPOINT
) {
1242 auto Flags
= MachineMemOperand::MOLoad
;
1243 MachineMemOperand
*MMO
= MF
.getMachineMemOperand(
1244 MachinePointerInfo::getFixedStack(MF
, FI
), Flags
,
1245 MF
.getDataLayout().getPointerSize(), MFI
.getObjectAlign(FI
));
1246 MIB
->addMemOperand(MF
, MMO
);
1249 MBB
->insert(MachineBasicBlock::iterator(MI
), MIB
);
1250 MI
->eraseFromParent();
1254 /// findRepresentativeClass - Return the largest legal super-reg register class
1255 /// of the register class for the specified type and its associated "cost".
1256 // This function is in TargetLowering because it uses RegClassForVT which would
1257 // need to be moved to TargetRegisterInfo and would necessitate moving
1258 // isTypeLegal over as well - a massive change that would just require
1259 // TargetLowering having a TargetRegisterInfo class member that it would use.
1260 std::pair
<const TargetRegisterClass
*, uint8_t>
1261 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo
*TRI
,
1263 const TargetRegisterClass
*RC
= RegClassForVT
[VT
.SimpleTy
];
1265 return std::make_pair(RC
, 0);
1267 // Compute the set of all super-register classes.
1268 BitVector
SuperRegRC(TRI
->getNumRegClasses());
1269 for (SuperRegClassIterator
RCI(RC
, TRI
); RCI
.isValid(); ++RCI
)
1270 SuperRegRC
.setBitsInMask(RCI
.getMask());
1272 // Find the first legal register class with the largest spill size.
1273 const TargetRegisterClass
*BestRC
= RC
;
1274 for (unsigned i
: SuperRegRC
.set_bits()) {
1275 const TargetRegisterClass
*SuperRC
= TRI
->getRegClass(i
);
1276 // We want the largest possible spill size.
1277 if (TRI
->getSpillSize(*SuperRC
) <= TRI
->getSpillSize(*BestRC
))
1279 if (!isLegalRC(*TRI
, *SuperRC
))
1283 return std::make_pair(BestRC
, 1);
1286 /// computeRegisterProperties - Once all of the register classes are added,
1287 /// this allows us to compute derived properties we expose.
1288 void TargetLoweringBase::computeRegisterProperties(
1289 const TargetRegisterInfo
*TRI
) {
1290 static_assert(MVT::VALUETYPE_SIZE
<= MVT::MAX_ALLOWED_VALUETYPE
,
1291 "Too many value types for ValueTypeActions to hold!");
1293 // Everything defaults to needing one register.
1294 for (unsigned i
= 0; i
!= MVT::VALUETYPE_SIZE
; ++i
) {
1295 NumRegistersForVT
[i
] = 1;
1296 RegisterTypeForVT
[i
] = TransformToType
[i
] = (MVT::SimpleValueType
)i
;
1298 // ...except isVoid, which doesn't need any registers.
1299 NumRegistersForVT
[MVT::isVoid
] = 0;
1301 // Find the largest integer register class.
1302 unsigned LargestIntReg
= MVT::LAST_INTEGER_VALUETYPE
;
1303 for (; RegClassForVT
[LargestIntReg
] == nullptr; --LargestIntReg
)
1304 assert(LargestIntReg
!= MVT::i1
&& "No integer registers defined!");
1306 // Every integer value type larger than this largest register takes twice as
1307 // many registers to represent as the previous ValueType.
1308 for (unsigned ExpandedReg
= LargestIntReg
+ 1;
1309 ExpandedReg
<= MVT::LAST_INTEGER_VALUETYPE
; ++ExpandedReg
) {
1310 NumRegistersForVT
[ExpandedReg
] = 2*NumRegistersForVT
[ExpandedReg
-1];
1311 RegisterTypeForVT
[ExpandedReg
] = (MVT::SimpleValueType
)LargestIntReg
;
1312 TransformToType
[ExpandedReg
] = (MVT::SimpleValueType
)(ExpandedReg
- 1);
1313 ValueTypeActions
.setTypeAction((MVT::SimpleValueType
)ExpandedReg
,
1317 // Inspect all of the ValueType's smaller than the largest integer
1318 // register to see which ones need promotion.
1319 unsigned LegalIntReg
= LargestIntReg
;
1320 for (unsigned IntReg
= LargestIntReg
- 1;
1321 IntReg
>= (unsigned)MVT::i1
; --IntReg
) {
1322 MVT IVT
= (MVT::SimpleValueType
)IntReg
;
1323 if (isTypeLegal(IVT
)) {
1324 LegalIntReg
= IntReg
;
1326 RegisterTypeForVT
[IntReg
] = TransformToType
[IntReg
] =
1327 (MVT::SimpleValueType
)LegalIntReg
;
1328 ValueTypeActions
.setTypeAction(IVT
, TypePromoteInteger
);
1332 // ppcf128 type is really two f64's.
1333 if (!isTypeLegal(MVT::ppcf128
)) {
1334 if (isTypeLegal(MVT::f64
)) {
1335 NumRegistersForVT
[MVT::ppcf128
] = 2*NumRegistersForVT
[MVT::f64
];
1336 RegisterTypeForVT
[MVT::ppcf128
] = MVT::f64
;
1337 TransformToType
[MVT::ppcf128
] = MVT::f64
;
1338 ValueTypeActions
.setTypeAction(MVT::ppcf128
, TypeExpandFloat
);
1340 NumRegistersForVT
[MVT::ppcf128
] = NumRegistersForVT
[MVT::i128
];
1341 RegisterTypeForVT
[MVT::ppcf128
] = RegisterTypeForVT
[MVT::i128
];
1342 TransformToType
[MVT::ppcf128
] = MVT::i128
;
1343 ValueTypeActions
.setTypeAction(MVT::ppcf128
, TypeSoftenFloat
);
1347 // Decide how to handle f128. If the target does not have native f128 support,
1348 // expand it to i128 and we will be generating soft float library calls.
1349 if (!isTypeLegal(MVT::f128
)) {
1350 NumRegistersForVT
[MVT::f128
] = NumRegistersForVT
[MVT::i128
];
1351 RegisterTypeForVT
[MVT::f128
] = RegisterTypeForVT
[MVT::i128
];
1352 TransformToType
[MVT::f128
] = MVT::i128
;
1353 ValueTypeActions
.setTypeAction(MVT::f128
, TypeSoftenFloat
);
1356 // Decide how to handle f64. If the target does not have native f64 support,
1357 // expand it to i64 and we will be generating soft float library calls.
1358 if (!isTypeLegal(MVT::f64
)) {
1359 NumRegistersForVT
[MVT::f64
] = NumRegistersForVT
[MVT::i64
];
1360 RegisterTypeForVT
[MVT::f64
] = RegisterTypeForVT
[MVT::i64
];
1361 TransformToType
[MVT::f64
] = MVT::i64
;
1362 ValueTypeActions
.setTypeAction(MVT::f64
, TypeSoftenFloat
);
1365 // Decide how to handle f32. If the target does not have native f32 support,
1366 // expand it to i32 and we will be generating soft float library calls.
1367 if (!isTypeLegal(MVT::f32
)) {
1368 NumRegistersForVT
[MVT::f32
] = NumRegistersForVT
[MVT::i32
];
1369 RegisterTypeForVT
[MVT::f32
] = RegisterTypeForVT
[MVT::i32
];
1370 TransformToType
[MVT::f32
] = MVT::i32
;
1371 ValueTypeActions
.setTypeAction(MVT::f32
, TypeSoftenFloat
);
1374 // Decide how to handle f16. If the target does not have native f16 support,
1375 // promote it to f32, because there are no f16 library calls (except for
1377 if (!isTypeLegal(MVT::f16
)) {
1378 // Allow targets to control how we legalize half.
1379 if (softPromoteHalfType()) {
1380 NumRegistersForVT
[MVT::f16
] = NumRegistersForVT
[MVT::i16
];
1381 RegisterTypeForVT
[MVT::f16
] = RegisterTypeForVT
[MVT::i16
];
1382 TransformToType
[MVT::f16
] = MVT::f32
;
1383 ValueTypeActions
.setTypeAction(MVT::f16
, TypeSoftPromoteHalf
);
1385 NumRegistersForVT
[MVT::f16
] = NumRegistersForVT
[MVT::f32
];
1386 RegisterTypeForVT
[MVT::f16
] = RegisterTypeForVT
[MVT::f32
];
1387 TransformToType
[MVT::f16
] = MVT::f32
;
1388 ValueTypeActions
.setTypeAction(MVT::f16
, TypePromoteFloat
);
1392 // Loop over all of the vector value types to see which need transformations.
1393 for (unsigned i
= MVT::FIRST_VECTOR_VALUETYPE
;
1394 i
<= (unsigned)MVT::LAST_VECTOR_VALUETYPE
; ++i
) {
1395 MVT VT
= (MVT::SimpleValueType
) i
;
1396 if (isTypeLegal(VT
))
1399 MVT EltVT
= VT
.getVectorElementType();
1400 ElementCount EC
= VT
.getVectorElementCount();
1401 bool IsLegalWiderType
= false;
1402 bool IsScalable
= VT
.isScalableVector();
1403 LegalizeTypeAction PreferredAction
= getPreferredVectorAction(VT
);
1404 switch (PreferredAction
) {
1405 case TypePromoteInteger
: {
1406 MVT::SimpleValueType EndVT
= IsScalable
?
1407 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
:
1408 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
;
1409 // Try to promote the elements of integer vectors. If no legal
1410 // promotion was found, fall through to the widen-vector method.
1411 for (unsigned nVT
= i
+ 1;
1412 (MVT::SimpleValueType
)nVT
<= EndVT
; ++nVT
) {
1413 MVT SVT
= (MVT::SimpleValueType
) nVT
;
1414 // Promote vectors of integers to vectors with the same number
1415 // of elements, with a wider element type.
1416 if (SVT
.getScalarSizeInBits() > EltVT
.getFixedSizeInBits() &&
1417 SVT
.getVectorElementCount() == EC
&& isTypeLegal(SVT
)) {
1418 TransformToType
[i
] = SVT
;
1419 RegisterTypeForVT
[i
] = SVT
;
1420 NumRegistersForVT
[i
] = 1;
1421 ValueTypeActions
.setTypeAction(VT
, TypePromoteInteger
);
1422 IsLegalWiderType
= true;
1426 if (IsLegalWiderType
)
1431 case TypeWidenVector
:
1432 if (isPowerOf2_32(EC
.getKnownMinValue())) {
1433 // Try to widen the vector.
1434 for (unsigned nVT
= i
+ 1; nVT
<= MVT::LAST_VECTOR_VALUETYPE
; ++nVT
) {
1435 MVT SVT
= (MVT::SimpleValueType
) nVT
;
1436 if (SVT
.getVectorElementType() == EltVT
&&
1437 SVT
.isScalableVector() == IsScalable
&&
1438 SVT
.getVectorElementCount().getKnownMinValue() >
1439 EC
.getKnownMinValue() &&
1441 TransformToType
[i
] = SVT
;
1442 RegisterTypeForVT
[i
] = SVT
;
1443 NumRegistersForVT
[i
] = 1;
1444 ValueTypeActions
.setTypeAction(VT
, TypeWidenVector
);
1445 IsLegalWiderType
= true;
1449 if (IsLegalWiderType
)
1452 // Only widen to the next power of 2 to keep consistency with EVT.
1453 MVT NVT
= VT
.getPow2VectorType();
1454 if (isTypeLegal(NVT
)) {
1455 TransformToType
[i
] = NVT
;
1456 ValueTypeActions
.setTypeAction(VT
, TypeWidenVector
);
1457 RegisterTypeForVT
[i
] = NVT
;
1458 NumRegistersForVT
[i
] = 1;
1464 case TypeSplitVector
:
1465 case TypeScalarizeVector
: {
1468 unsigned NumIntermediates
;
1469 unsigned NumRegisters
= getVectorTypeBreakdownMVT(VT
, IntermediateVT
,
1470 NumIntermediates
, RegisterVT
, this);
1471 NumRegistersForVT
[i
] = NumRegisters
;
1472 assert(NumRegistersForVT
[i
] == NumRegisters
&&
1473 "NumRegistersForVT size cannot represent NumRegisters!");
1474 RegisterTypeForVT
[i
] = RegisterVT
;
1476 MVT NVT
= VT
.getPow2VectorType();
1478 // Type is already a power of 2. The default action is to split.
1479 TransformToType
[i
] = MVT::Other
;
1480 if (PreferredAction
== TypeScalarizeVector
)
1481 ValueTypeActions
.setTypeAction(VT
, TypeScalarizeVector
);
1482 else if (PreferredAction
== TypeSplitVector
)
1483 ValueTypeActions
.setTypeAction(VT
, TypeSplitVector
);
1484 else if (EC
.getKnownMinValue() > 1)
1485 ValueTypeActions
.setTypeAction(VT
, TypeSplitVector
);
1487 ValueTypeActions
.setTypeAction(VT
, EC
.isScalable()
1488 ? TypeScalarizeScalableVector
1489 : TypeScalarizeVector
);
1491 TransformToType
[i
] = NVT
;
1492 ValueTypeActions
.setTypeAction(VT
, TypeWidenVector
);
1497 llvm_unreachable("Unknown vector legalization action!");
1501 // Determine the 'representative' register class for each value type.
1502 // An representative register class is the largest (meaning one which is
1503 // not a sub-register class / subreg register class) legal register class for
1504 // a group of value types. For example, on i386, i8, i16, and i32
1505 // representative would be GR32; while on x86_64 it's GR64.
1506 for (unsigned i
= 0; i
!= MVT::VALUETYPE_SIZE
; ++i
) {
1507 const TargetRegisterClass
* RRC
;
1509 std::tie(RRC
, Cost
) = findRepresentativeClass(TRI
, (MVT::SimpleValueType
)i
);
1510 RepRegClassForVT
[i
] = RRC
;
1511 RepRegClassCostForVT
[i
] = Cost
;
1515 EVT
TargetLoweringBase::getSetCCResultType(const DataLayout
&DL
, LLVMContext
&,
1517 assert(!VT
.isVector() && "No default SetCC type for vectors!");
1518 return getPointerTy(DL
).SimpleTy
;
1521 MVT::SimpleValueType
TargetLoweringBase::getCmpLibcallReturnType() const {
1522 return MVT::i32
; // return the default value
1525 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1526 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1527 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1528 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1530 /// This method returns the number of registers needed, and the VT for each
1531 /// register. It also returns the VT and quantity of the intermediate values
1532 /// before they are promoted/expanded.
1533 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext
&Context
,
1534 EVT VT
, EVT
&IntermediateVT
,
1535 unsigned &NumIntermediates
,
1536 MVT
&RegisterVT
) const {
1537 ElementCount EltCnt
= VT
.getVectorElementCount();
1539 // If there is a wider vector type with the same element type as this one,
1540 // or a promoted vector type that has the same number of elements which
1541 // are wider, then we should convert to that legal vector type.
1542 // This handles things like <2 x float> -> <4 x float> and
1543 // <4 x i1> -> <4 x i32>.
1544 LegalizeTypeAction TA
= getTypeAction(Context
, VT
);
1545 if (!EltCnt
.isScalar() &&
1546 (TA
== TypeWidenVector
|| TA
== TypePromoteInteger
)) {
1547 EVT RegisterEVT
= getTypeToTransformTo(Context
, VT
);
1548 if (isTypeLegal(RegisterEVT
)) {
1549 IntermediateVT
= RegisterEVT
;
1550 RegisterVT
= RegisterEVT
.getSimpleVT();
1551 NumIntermediates
= 1;
1556 // Figure out the right, legal destination reg to copy into.
1557 EVT EltTy
= VT
.getVectorElementType();
1559 unsigned NumVectorRegs
= 1;
1561 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1562 // types like done elsewhere in SelectionDAG.
1563 if (EltCnt
.isScalable()) {
1567 // Iterate until we've found a legal (part) type to hold VT.
1568 LK
= getTypeConversion(Context
, PartVT
);
1570 } while (LK
.first
!= TypeLegal
);
1572 if (!PartVT
.isVector()) {
1574 "Don't know how to legalize this scalable vector type");
1578 divideCeil(VT
.getVectorElementCount().getKnownMinValue(),
1579 PartVT
.getVectorElementCount().getKnownMinValue());
1580 IntermediateVT
= PartVT
;
1581 RegisterVT
= getRegisterType(Context
, IntermediateVT
);
1582 return NumIntermediates
;
1585 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1586 // we could break down into LHS/RHS like LegalizeDAG does.
1587 if (!isPowerOf2_32(EltCnt
.getKnownMinValue())) {
1588 NumVectorRegs
= EltCnt
.getKnownMinValue();
1589 EltCnt
= ElementCount::getFixed(1);
1592 // Divide the input until we get to a supported size. This will always
1593 // end with a scalar if the target doesn't support vectors.
1594 while (EltCnt
.getKnownMinValue() > 1 &&
1595 !isTypeLegal(EVT::getVectorVT(Context
, EltTy
, EltCnt
))) {
1596 EltCnt
= EltCnt
.divideCoefficientBy(2);
1597 NumVectorRegs
<<= 1;
1600 NumIntermediates
= NumVectorRegs
;
1602 EVT NewVT
= EVT::getVectorVT(Context
, EltTy
, EltCnt
);
1603 if (!isTypeLegal(NewVT
))
1605 IntermediateVT
= NewVT
;
1607 MVT DestVT
= getRegisterType(Context
, NewVT
);
1608 RegisterVT
= DestVT
;
1610 if (EVT(DestVT
).bitsLT(NewVT
)) { // Value is expanded, e.g. i64 -> i16.
1611 TypeSize NewVTSize
= NewVT
.getSizeInBits();
1612 // Convert sizes such as i33 to i64.
1613 if (!isPowerOf2_32(NewVTSize
.getKnownMinSize()))
1614 NewVTSize
= NewVTSize
.coefficientNextPowerOf2();
1615 return NumVectorRegs
*(NewVTSize
/DestVT
.getSizeInBits());
1618 // Otherwise, promotion or legal types use the same number of registers as
1619 // the vector decimated to the appropriate level.
1620 return NumVectorRegs
;
1623 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst
*SI
,
1626 ProfileSummaryInfo
*PSI
,
1627 BlockFrequencyInfo
*BFI
) const {
1628 // FIXME: This function check the maximum table size and density, but the
1629 // minimum size is not checked. It would be nice if the minimum size is
1630 // also combined within this function. Currently, the minimum size check is
1631 // performed in findJumpTable() in SelectionDAGBuiler and
1632 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1633 const bool OptForSize
=
1634 SI
->getParent()->getParent()->hasOptSize() ||
1635 llvm::shouldOptimizeForSize(SI
->getParent(), PSI
, BFI
);
1636 const unsigned MinDensity
= getMinimumJumpTableDensity(OptForSize
);
1637 const unsigned MaxJumpTableSize
= getMaximumJumpTableSize();
1639 // Check whether the number of cases is small enough and
1640 // the range is dense enough for a jump table.
1641 return (OptForSize
|| Range
<= MaxJumpTableSize
) &&
1642 (NumCases
* 100 >= Range
* MinDensity
);
1645 /// Get the EVTs and ArgFlags collections that represent the legalized return
1646 /// type of the given function. This does not require a DAG or a return value,
1647 /// and is suitable for use before any DAGs for the function are constructed.
1648 /// TODO: Move this out of TargetLowering.cpp.
1649 void llvm::GetReturnInfo(CallingConv::ID CC
, Type
*ReturnType
,
1651 SmallVectorImpl
<ISD::OutputArg
> &Outs
,
1652 const TargetLowering
&TLI
, const DataLayout
&DL
) {
1653 SmallVector
<EVT
, 4> ValueVTs
;
1654 ComputeValueVTs(TLI
, DL
, ReturnType
, ValueVTs
);
1655 unsigned NumValues
= ValueVTs
.size();
1656 if (NumValues
== 0) return;
1658 for (unsigned j
= 0, f
= NumValues
; j
!= f
; ++j
) {
1659 EVT VT
= ValueVTs
[j
];
1660 ISD::NodeType ExtendKind
= ISD::ANY_EXTEND
;
1662 if (attr
.hasRetAttr(Attribute::SExt
))
1663 ExtendKind
= ISD::SIGN_EXTEND
;
1664 else if (attr
.hasRetAttr(Attribute::ZExt
))
1665 ExtendKind
= ISD::ZERO_EXTEND
;
1667 // FIXME: C calling convention requires the return type to be promoted to
1668 // at least 32-bit. But this is not necessary for non-C calling
1669 // conventions. The frontend should mark functions whose return values
1670 // require promoting with signext or zeroext attributes.
1671 if (ExtendKind
!= ISD::ANY_EXTEND
&& VT
.isInteger()) {
1672 MVT MinVT
= TLI
.getRegisterType(ReturnType
->getContext(), MVT::i32
);
1673 if (VT
.bitsLT(MinVT
))
1678 TLI
.getNumRegistersForCallingConv(ReturnType
->getContext(), CC
, VT
);
1680 TLI
.getRegisterTypeForCallingConv(ReturnType
->getContext(), CC
, VT
);
1682 // 'inreg' on function refers to return value
1683 ISD::ArgFlagsTy Flags
= ISD::ArgFlagsTy();
1684 if (attr
.hasRetAttr(Attribute::InReg
))
1687 // Propagate extension type if any
1688 if (attr
.hasRetAttr(Attribute::SExt
))
1690 else if (attr
.hasRetAttr(Attribute::ZExt
))
1693 for (unsigned i
= 0; i
< NumParts
; ++i
)
1694 Outs
.push_back(ISD::OutputArg(Flags
, PartVT
, VT
, /*isfixed=*/true, 0, 0));
1698 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1699 /// function arguments in the caller parameter area. This is the actual
1700 /// alignment, not its logarithm.
1701 unsigned TargetLoweringBase::getByValTypeAlignment(Type
*Ty
,
1702 const DataLayout
&DL
) const {
1703 return DL
.getABITypeAlign(Ty
).value();
1706 bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1707 LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
, unsigned AddrSpace
,
1708 Align Alignment
, MachineMemOperand::Flags Flags
, bool *Fast
) const {
1709 // Check if the specified alignment is sufficient based on the data layout.
1710 // TODO: While using the data layout works in practice, a better solution
1711 // would be to implement this check directly (make this a virtual function).
1712 // For example, the ABI alignment may change based on software platform while
1713 // this function should only be affected by hardware implementation.
1714 Type
*Ty
= VT
.getTypeForEVT(Context
);
1715 if (VT
.isZeroSized() || Alignment
>= DL
.getABITypeAlign(Ty
)) {
1716 // Assume that an access that meets the ABI-specified alignment is fast.
1717 if (Fast
!= nullptr)
1722 // This is a misaligned access.
1723 return allowsMisalignedMemoryAccesses(VT
, AddrSpace
, Alignment
, Flags
, Fast
);
1726 bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1727 LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
,
1728 const MachineMemOperand
&MMO
, bool *Fast
) const {
1729 return allowsMemoryAccessForAlignment(Context
, DL
, VT
, MMO
.getAddrSpace(),
1730 MMO
.getAlign(), MMO
.getFlags(), Fast
);
1733 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext
&Context
,
1734 const DataLayout
&DL
, EVT VT
,
1735 unsigned AddrSpace
, Align Alignment
,
1736 MachineMemOperand::Flags Flags
,
1738 return allowsMemoryAccessForAlignment(Context
, DL
, VT
, AddrSpace
, Alignment
,
1742 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext
&Context
,
1743 const DataLayout
&DL
, EVT VT
,
1744 const MachineMemOperand
&MMO
,
1746 return allowsMemoryAccess(Context
, DL
, VT
, MMO
.getAddrSpace(), MMO
.getAlign(),
1747 MMO
.getFlags(), Fast
);
1750 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext
&Context
,
1751 const DataLayout
&DL
, LLT Ty
,
1752 const MachineMemOperand
&MMO
,
1754 EVT VT
= getApproximateEVTForLLT(Ty
, DL
, Context
);
1755 return allowsMemoryAccess(Context
, DL
, VT
, MMO
.getAddrSpace(), MMO
.getAlign(),
1756 MMO
.getFlags(), Fast
);
1759 //===----------------------------------------------------------------------===//
1760 // TargetTransformInfo Helpers
1761 //===----------------------------------------------------------------------===//
1763 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode
) const {
1764 enum InstructionOpcodes
{
1765 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1766 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1767 #include "llvm/IR/Instruction.def"
1769 switch (static_cast<InstructionOpcodes
>(Opcode
)) {
1772 case Switch
: return 0;
1773 case IndirectBr
: return 0;
1774 case Invoke
: return 0;
1775 case CallBr
: return 0;
1776 case Resume
: return 0;
1777 case Unreachable
: return 0;
1778 case CleanupRet
: return 0;
1779 case CatchRet
: return 0;
1780 case CatchPad
: return 0;
1781 case CatchSwitch
: return 0;
1782 case CleanupPad
: return 0;
1783 case FNeg
: return ISD::FNEG
;
1784 case Add
: return ISD::ADD
;
1785 case FAdd
: return ISD::FADD
;
1786 case Sub
: return ISD::SUB
;
1787 case FSub
: return ISD::FSUB
;
1788 case Mul
: return ISD::MUL
;
1789 case FMul
: return ISD::FMUL
;
1790 case UDiv
: return ISD::UDIV
;
1791 case SDiv
: return ISD::SDIV
;
1792 case FDiv
: return ISD::FDIV
;
1793 case URem
: return ISD::UREM
;
1794 case SRem
: return ISD::SREM
;
1795 case FRem
: return ISD::FREM
;
1796 case Shl
: return ISD::SHL
;
1797 case LShr
: return ISD::SRL
;
1798 case AShr
: return ISD::SRA
;
1799 case And
: return ISD::AND
;
1800 case Or
: return ISD::OR
;
1801 case Xor
: return ISD::XOR
;
1802 case Alloca
: return 0;
1803 case Load
: return ISD::LOAD
;
1804 case Store
: return ISD::STORE
;
1805 case GetElementPtr
: return 0;
1806 case Fence
: return 0;
1807 case AtomicCmpXchg
: return 0;
1808 case AtomicRMW
: return 0;
1809 case Trunc
: return ISD::TRUNCATE
;
1810 case ZExt
: return ISD::ZERO_EXTEND
;
1811 case SExt
: return ISD::SIGN_EXTEND
;
1812 case FPToUI
: return ISD::FP_TO_UINT
;
1813 case FPToSI
: return ISD::FP_TO_SINT
;
1814 case UIToFP
: return ISD::UINT_TO_FP
;
1815 case SIToFP
: return ISD::SINT_TO_FP
;
1816 case FPTrunc
: return ISD::FP_ROUND
;
1817 case FPExt
: return ISD::FP_EXTEND
;
1818 case PtrToInt
: return ISD::BITCAST
;
1819 case IntToPtr
: return ISD::BITCAST
;
1820 case BitCast
: return ISD::BITCAST
;
1821 case AddrSpaceCast
: return ISD::ADDRSPACECAST
;
1822 case ICmp
: return ISD::SETCC
;
1823 case FCmp
: return ISD::SETCC
;
1825 case Call
: return 0;
1826 case Select
: return ISD::SELECT
;
1827 case UserOp1
: return 0;
1828 case UserOp2
: return 0;
1829 case VAArg
: return 0;
1830 case ExtractElement
: return ISD::EXTRACT_VECTOR_ELT
;
1831 case InsertElement
: return ISD::INSERT_VECTOR_ELT
;
1832 case ShuffleVector
: return ISD::VECTOR_SHUFFLE
;
1833 case ExtractValue
: return ISD::MERGE_VALUES
;
1834 case InsertValue
: return ISD::MERGE_VALUES
;
1835 case LandingPad
: return 0;
1836 case Freeze
: return ISD::FREEZE
;
1839 llvm_unreachable("Unknown instruction type encountered!");
1842 std::pair
<InstructionCost
, MVT
>
1843 TargetLoweringBase::getTypeLegalizationCost(const DataLayout
&DL
,
1845 LLVMContext
&C
= Ty
->getContext();
1846 EVT MTy
= getValueType(DL
, Ty
);
1848 InstructionCost Cost
= 1;
1849 // We keep legalizing the type until we find a legal kind. We assume that
1850 // the only operation that costs anything is the split. After splitting
1851 // we need to handle two types.
1853 LegalizeKind LK
= getTypeConversion(C
, MTy
);
1855 if (LK
.first
== TypeScalarizeScalableVector
)
1856 return std::make_pair(InstructionCost::getInvalid(), MVT::getVT(Ty
));
1858 if (LK
.first
== TypeLegal
)
1859 return std::make_pair(Cost
, MTy
.getSimpleVT());
1861 if (LK
.first
== TypeSplitVector
|| LK
.first
== TypeExpandInteger
)
1864 // Do not loop with f128 type.
1865 if (MTy
== LK
.second
)
1866 return std::make_pair(Cost
, MTy
.getSimpleVT());
1868 // Keep legalizing the type.
1874 TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase
&IRB
,
1875 bool UseTLS
) const {
1876 // compiler-rt provides a variable with a magic name. Targets that do not
1877 // link with compiler-rt may also provide such a variable.
1878 Module
*M
= IRB
.GetInsertBlock()->getParent()->getParent();
1879 const char *UnsafeStackPtrVar
= "__safestack_unsafe_stack_ptr";
1880 auto UnsafeStackPtr
=
1881 dyn_cast_or_null
<GlobalVariable
>(M
->getNamedValue(UnsafeStackPtrVar
));
1883 Type
*StackPtrTy
= Type::getInt8PtrTy(M
->getContext());
1885 if (!UnsafeStackPtr
) {
1886 auto TLSModel
= UseTLS
?
1887 GlobalValue::InitialExecTLSModel
:
1888 GlobalValue::NotThreadLocal
;
1889 // The global variable is not defined yet, define it ourselves.
1890 // We use the initial-exec TLS model because we do not support the
1891 // variable living anywhere other than in the main executable.
1892 UnsafeStackPtr
= new GlobalVariable(
1893 *M
, StackPtrTy
, false, GlobalValue::ExternalLinkage
, nullptr,
1894 UnsafeStackPtrVar
, nullptr, TLSModel
);
1896 // The variable exists, check its type and attributes.
1897 if (UnsafeStackPtr
->getValueType() != StackPtrTy
)
1898 report_fatal_error(Twine(UnsafeStackPtrVar
) + " must have void* type");
1899 if (UseTLS
!= UnsafeStackPtr
->isThreadLocal())
1900 report_fatal_error(Twine(UnsafeStackPtrVar
) + " must " +
1901 (UseTLS
? "" : "not ") + "be thread-local");
1903 return UnsafeStackPtr
;
1907 TargetLoweringBase::getSafeStackPointerLocation(IRBuilderBase
&IRB
) const {
1908 if (!TM
.getTargetTriple().isAndroid())
1909 return getDefaultSafeStackPointerLocation(IRB
, true);
1911 // Android provides a libc function to retrieve the address of the current
1912 // thread's unsafe stack pointer.
1913 Module
*M
= IRB
.GetInsertBlock()->getParent()->getParent();
1914 Type
*StackPtrTy
= Type::getInt8PtrTy(M
->getContext());
1915 FunctionCallee Fn
= M
->getOrInsertFunction("__safestack_pointer_address",
1916 StackPtrTy
->getPointerTo(0));
1917 return IRB
.CreateCall(Fn
);
1920 //===----------------------------------------------------------------------===//
1921 // Loop Strength Reduction hooks
1922 //===----------------------------------------------------------------------===//
1924 /// isLegalAddressingMode - Return true if the addressing mode represented
1925 /// by AM is legal for this target, for a load/store of the specified type.
1926 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout
&DL
,
1927 const AddrMode
&AM
, Type
*Ty
,
1928 unsigned AS
, Instruction
*I
) const {
1929 // The default implementation of this implements a conservative RISCy, r+r and
1932 // Allows a sign-extended 16-bit immediate field.
1933 if (AM
.BaseOffs
<= -(1LL << 16) || AM
.BaseOffs
>= (1LL << 16)-1)
1936 // No global is ever allowed as a base.
1940 // Only support r+r,
1942 case 0: // "r+i" or just "i", depending on HasBaseReg.
1945 if (AM
.HasBaseReg
&& AM
.BaseOffs
) // "r+r+i" is not allowed.
1947 // Otherwise we have r+r or r+i.
1950 if (AM
.HasBaseReg
|| AM
.BaseOffs
) // 2*r+r or 2*r+i is not allowed.
1952 // Allow 2*r as r+r.
1954 default: // Don't allow n * r
1961 //===----------------------------------------------------------------------===//
1963 //===----------------------------------------------------------------------===//
1965 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1966 // so that SelectionDAG handle SSP.
1967 Value
*TargetLoweringBase::getIRStackGuard(IRBuilderBase
&IRB
) const {
1968 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1969 Module
&M
= *IRB
.GetInsertBlock()->getParent()->getParent();
1970 PointerType
*PtrTy
= Type::getInt8PtrTy(M
.getContext());
1971 Constant
*C
= M
.getOrInsertGlobal("__guard_local", PtrTy
);
1972 if (GlobalVariable
*G
= dyn_cast_or_null
<GlobalVariable
>(C
))
1973 G
->setVisibility(GlobalValue::HiddenVisibility
);
1979 // Currently only support "standard" __stack_chk_guard.
1980 // TODO: add LOAD_STACK_GUARD support.
1981 void TargetLoweringBase::insertSSPDeclarations(Module
&M
) const {
1982 if (!M
.getNamedValue("__stack_chk_guard")) {
1983 auto *GV
= new GlobalVariable(M
, Type::getInt8PtrTy(M
.getContext()), false,
1984 GlobalVariable::ExternalLinkage
, nullptr,
1985 "__stack_chk_guard");
1986 if (TM
.getRelocationModel() == Reloc::Static
&&
1987 !TM
.getTargetTriple().isWindowsGNUEnvironment())
1988 GV
->setDSOLocal(true);
1992 // Currently only support "standard" __stack_chk_guard.
1993 // TODO: add LOAD_STACK_GUARD support.
1994 Value
*TargetLoweringBase::getSDagStackGuard(const Module
&M
) const {
1995 return M
.getNamedValue("__stack_chk_guard");
1998 Function
*TargetLoweringBase::getSSPStackGuardCheck(const Module
&M
) const {
2002 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2003 return MinimumJumpTableEntries
;
2006 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val
) {
2007 MinimumJumpTableEntries
= Val
;
2010 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize
) const {
2011 return OptForSize
? OptsizeJumpTableDensity
: JumpTableDensity
;
2014 unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2015 return MaximumJumpTableSize
;
2018 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val
) {
2019 MaximumJumpTableSize
= Val
;
2022 bool TargetLoweringBase::isJumpTableRelative() const {
2023 return getTargetMachine().isPositionIndependent();
2026 Align
TargetLoweringBase::getPrefLoopAlignment(MachineLoop
*ML
) const {
2027 if (TM
.Options
.LoopAlignment
)
2028 return Align(TM
.Options
.LoopAlignment
);
2029 return PrefLoopAlignment
;
2032 //===----------------------------------------------------------------------===//
2033 // Reciprocal Estimates
2034 //===----------------------------------------------------------------------===//
2036 /// Get the reciprocal estimate attribute string for a function that will
2037 /// override the target defaults.
2038 static StringRef
getRecipEstimateForFunc(MachineFunction
&MF
) {
2039 const Function
&F
= MF
.getFunction();
2040 return F
.getFnAttribute("reciprocal-estimates").getValueAsString();
2043 /// Construct a string for the given reciprocal operation of the given type.
2044 /// This string should match the corresponding option to the front-end's
2045 /// "-mrecip" flag assuming those strings have been passed through in an
2046 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2047 static std::string
getReciprocalOpName(bool IsSqrt
, EVT VT
) {
2048 std::string Name
= VT
.isVector() ? "vec-" : "";
2050 Name
+= IsSqrt
? "sqrt" : "div";
2052 // TODO: Handle "half" or other float types?
2053 if (VT
.getScalarType() == MVT::f64
) {
2056 assert(VT
.getScalarType() == MVT::f32
&&
2057 "Unexpected FP type for reciprocal estimate");
2064 /// Return the character position and value (a single numeric character) of a
2065 /// customized refinement operation in the input string if it exists. Return
2066 /// false if there is no customized refinement step count.
2067 static bool parseRefinementStep(StringRef In
, size_t &Position
,
2069 const char RefStepToken
= ':';
2070 Position
= In
.find(RefStepToken
);
2071 if (Position
== StringRef::npos
)
2074 StringRef RefStepString
= In
.substr(Position
+ 1);
2075 // Allow exactly one numeric character for the additional refinement
2077 if (RefStepString
.size() == 1) {
2078 char RefStepChar
= RefStepString
[0];
2079 if (isDigit(RefStepChar
)) {
2080 Value
= RefStepChar
- '0';
2084 report_fatal_error("Invalid refinement step for -recip.");
2087 /// For the input attribute string, return one of the ReciprocalEstimate enum
2088 /// status values (enabled, disabled, or not specified) for this operation on
2089 /// the specified data type.
2090 static int getOpEnabled(bool IsSqrt
, EVT VT
, StringRef Override
) {
2091 if (Override
.empty())
2092 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2094 SmallVector
<StringRef
, 4> OverrideVector
;
2095 Override
.split(OverrideVector
, ',');
2096 unsigned NumArgs
= OverrideVector
.size();
2098 // Check if "all", "none", or "default" was specified.
2100 // Look for an optional setting of the number of refinement steps needed
2101 // for this type of reciprocal operation.
2104 if (parseRefinementStep(Override
, RefPos
, RefSteps
)) {
2105 // Split the string for further processing.
2106 Override
= Override
.substr(0, RefPos
);
2109 // All reciprocal types are enabled.
2110 if (Override
== "all")
2111 return TargetLoweringBase::ReciprocalEstimate::Enabled
;
2113 // All reciprocal types are disabled.
2114 if (Override
== "none")
2115 return TargetLoweringBase::ReciprocalEstimate::Disabled
;
2117 // Target defaults for enablement are used.
2118 if (Override
== "default")
2119 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2122 // The attribute string may omit the size suffix ('f'/'d').
2123 std::string VTName
= getReciprocalOpName(IsSqrt
, VT
);
2124 std::string VTNameNoSize
= VTName
;
2125 VTNameNoSize
.pop_back();
2126 static const char DisabledPrefix
= '!';
2128 for (StringRef RecipType
: OverrideVector
) {
2131 if (parseRefinementStep(RecipType
, RefPos
, RefSteps
))
2132 RecipType
= RecipType
.substr(0, RefPos
);
2134 // Ignore the disablement token for string matching.
2135 bool IsDisabled
= RecipType
[0] == DisabledPrefix
;
2137 RecipType
= RecipType
.substr(1);
2139 if (RecipType
.equals(VTName
) || RecipType
.equals(VTNameNoSize
))
2140 return IsDisabled
? TargetLoweringBase::ReciprocalEstimate::Disabled
2141 : TargetLoweringBase::ReciprocalEstimate::Enabled
;
2144 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2147 /// For the input attribute string, return the customized refinement step count
2148 /// for this operation on the specified data type. If the step count does not
2149 /// exist, return the ReciprocalEstimate enum value for unspecified.
2150 static int getOpRefinementSteps(bool IsSqrt
, EVT VT
, StringRef Override
) {
2151 if (Override
.empty())
2152 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2154 SmallVector
<StringRef
, 4> OverrideVector
;
2155 Override
.split(OverrideVector
, ',');
2156 unsigned NumArgs
= OverrideVector
.size();
2158 // Check if "all", "default", or "none" was specified.
2160 // Look for an optional setting of the number of refinement steps needed
2161 // for this type of reciprocal operation.
2164 if (!parseRefinementStep(Override
, RefPos
, RefSteps
))
2165 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2167 // Split the string for further processing.
2168 Override
= Override
.substr(0, RefPos
);
2169 assert(Override
!= "none" &&
2170 "Disabled reciprocals, but specifed refinement steps?");
2172 // If this is a general override, return the specified number of steps.
2173 if (Override
== "all" || Override
== "default")
2177 // The attribute string may omit the size suffix ('f'/'d').
2178 std::string VTName
= getReciprocalOpName(IsSqrt
, VT
);
2179 std::string VTNameNoSize
= VTName
;
2180 VTNameNoSize
.pop_back();
2182 for (StringRef RecipType
: OverrideVector
) {
2185 if (!parseRefinementStep(RecipType
, RefPos
, RefSteps
))
2188 RecipType
= RecipType
.substr(0, RefPos
);
2189 if (RecipType
.equals(VTName
) || RecipType
.equals(VTNameNoSize
))
2193 return TargetLoweringBase::ReciprocalEstimate::Unspecified
;
2196 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT
,
2197 MachineFunction
&MF
) const {
2198 return getOpEnabled(true, VT
, getRecipEstimateForFunc(MF
));
2201 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT
,
2202 MachineFunction
&MF
) const {
2203 return getOpEnabled(false, VT
, getRecipEstimateForFunc(MF
));
2206 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT
,
2207 MachineFunction
&MF
) const {
2208 return getOpRefinementSteps(true, VT
, getRecipEstimateForFunc(MF
));
2211 int TargetLoweringBase::getDivRefinementSteps(EVT VT
,
2212 MachineFunction
&MF
) const {
2213 return getOpRefinementSteps(false, VT
, getRecipEstimateForFunc(MF
));
2216 void TargetLoweringBase::finalizeLowering(MachineFunction
&MF
) const {
2217 MF
.getRegInfo().freezeReservedRegs(MF
);
2220 MachineMemOperand::Flags
2221 TargetLoweringBase::getLoadMemOperandFlags(const LoadInst
&LI
,
2222 const DataLayout
&DL
) const {
2223 MachineMemOperand::Flags Flags
= MachineMemOperand::MOLoad
;
2224 if (LI
.isVolatile())
2225 Flags
|= MachineMemOperand::MOVolatile
;
2227 if (LI
.hasMetadata(LLVMContext::MD_nontemporal
))
2228 Flags
|= MachineMemOperand::MONonTemporal
;
2230 if (LI
.hasMetadata(LLVMContext::MD_invariant_load
))
2231 Flags
|= MachineMemOperand::MOInvariant
;
2233 if (isDereferenceablePointer(LI
.getPointerOperand(), LI
.getType(), DL
))
2234 Flags
|= MachineMemOperand::MODereferenceable
;
2236 Flags
|= getTargetMMOFlags(LI
);
2240 MachineMemOperand::Flags
2241 TargetLoweringBase::getStoreMemOperandFlags(const StoreInst
&SI
,
2242 const DataLayout
&DL
) const {
2243 MachineMemOperand::Flags Flags
= MachineMemOperand::MOStore
;
2245 if (SI
.isVolatile())
2246 Flags
|= MachineMemOperand::MOVolatile
;
2248 if (SI
.hasMetadata(LLVMContext::MD_nontemporal
))
2249 Flags
|= MachineMemOperand::MONonTemporal
;
2251 // FIXME: Not preserving dereferenceable
2252 Flags
|= getTargetMMOFlags(SI
);
2256 MachineMemOperand::Flags
2257 TargetLoweringBase::getAtomicMemOperandFlags(const Instruction
&AI
,
2258 const DataLayout
&DL
) const {
2259 auto Flags
= MachineMemOperand::MOLoad
| MachineMemOperand::MOStore
;
2261 if (const AtomicRMWInst
*RMW
= dyn_cast
<AtomicRMWInst
>(&AI
)) {
2262 if (RMW
->isVolatile())
2263 Flags
|= MachineMemOperand::MOVolatile
;
2264 } else if (const AtomicCmpXchgInst
*CmpX
= dyn_cast
<AtomicCmpXchgInst
>(&AI
)) {
2265 if (CmpX
->isVolatile())
2266 Flags
|= MachineMemOperand::MOVolatile
;
2268 llvm_unreachable("not an atomic instruction");
2270 // FIXME: Not preserving dereferenceable
2271 Flags
|= getTargetMMOFlags(AI
);
2275 Instruction
*TargetLoweringBase::emitLeadingFence(IRBuilderBase
&Builder
,
2277 AtomicOrdering Ord
) const {
2278 if (isReleaseOrStronger(Ord
) && Inst
->hasAtomicStore())
2279 return Builder
.CreateFence(Ord
);
2284 Instruction
*TargetLoweringBase::emitTrailingFence(IRBuilderBase
&Builder
,
2286 AtomicOrdering Ord
) const {
2287 if (isAcquireOrStronger(Ord
))
2288 return Builder
.CreateFence(Ord
);
2293 //===----------------------------------------------------------------------===//
2295 //===----------------------------------------------------------------------===//
2297 bool TargetLoweringBase::shouldLocalize(const MachineInstr
&MI
,
2298 const TargetTransformInfo
*TTI
) const {
2299 auto &MF
= *MI
.getMF();
2300 auto &MRI
= MF
.getRegInfo();
2301 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2302 // this helper function computes the maximum number of uses we should consider
2303 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2304 // break even in terms of code size when the original MI has 2 users vs
2305 // choosing to potentially spill. Any more than 2 users we we have a net code
2306 // size increase. This doesn't take into account register pressure though.
2307 auto maxUses
= [](unsigned RematCost
) {
2308 // A cost of 1 means remats are basically free.
2314 // Remat is too expensive, only sink if there's one user.
2317 llvm_unreachable("Unexpected remat cost");
2320 // Helper to walk through uses and terminate if we've reached a limit. Saves
2321 // us spending time traversing uses if all we want to know is if it's >= min.
2322 auto isUsesAtMost
= [&](unsigned Reg
, unsigned MaxUses
) {
2323 unsigned NumUses
= 0;
2324 auto UI
= MRI
.use_instr_nodbg_begin(Reg
), UE
= MRI
.use_instr_nodbg_end();
2325 for (; UI
!= UE
&& NumUses
< MaxUses
; ++UI
) {
2328 // If we haven't reached the end yet then there are more than MaxUses users.
2332 switch (MI
.getOpcode()) {
2335 // Constants-like instructions should be close to their users.
2336 // We don't want long live-ranges for them.
2337 case TargetOpcode::G_CONSTANT
:
2338 case TargetOpcode::G_FCONSTANT
:
2339 case TargetOpcode::G_FRAME_INDEX
:
2340 case TargetOpcode::G_INTTOPTR
:
2342 case TargetOpcode::G_GLOBAL_VALUE
: {
2343 unsigned RematCost
= TTI
->getGISelRematGlobalCost();
2344 Register Reg
= MI
.getOperand(0).getReg();
2345 unsigned MaxUses
= maxUses(RematCost
);
2346 if (MaxUses
== UINT_MAX
)
2347 return true; // Remats are "free" so always localize.
2348 bool B
= isUsesAtMost(Reg
, MaxUses
);