llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing.
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // AArch64 Subtarget features.
  20 //
  21
  22 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  23                                        "Enable ARMv8 FP">;
  24
  25 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  26   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  27
  28 def FeatureSM4 : SubtargetFeature<
  29     "sm4", "HasSM4", "true",
  30     "Enable SM3 and SM4 support", [FeatureNEON]>;
  31
  32 def FeatureSHA2 : SubtargetFeature<
  33     "sha2", "HasSHA2", "true",
  34     "Enable SHA1 and SHA256 support", [FeatureNEON]>;
  35
  36 def FeatureSHA3 : SubtargetFeature<
  37     "sha3", "HasSHA3", "true",
  38     "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
  39
  40 def FeatureAES : SubtargetFeature<
  41     "aes", "HasAES", "true",
  42     "Enable AES support", [FeatureNEON]>;
  43
  44 // Crypto has been split up and any combination is now valid (see the
  45 // crypto definitions above). Also, crypto is now context sensitive:
  46 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
  47 // Therefore, we rely on Clang, the user interacing tool, to pass on the
  48 // appropriate crypto options. But here in the backend, crypto has very little
  49 // meaning anymore. We kept the Crypto definition here for backward
  50 // compatibility, and now imply features SHA2 and AES, which was the
  51 // "traditional" meaning of Crypto.
  52 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  53   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
  54
  55 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  56   "Enable ARMv8 CRC-32 checksum instructions">;
  57
  58 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  59   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  60
  61 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  62   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  63
  64 def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
  65   "Enable out of line atomics to support LSE instructions">;
  66
  67 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  68   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  69
  70 def FeaturePAN : SubtargetFeature<
  71     "pan", "HasPAN", "true",
  72     "Enables ARM v8.1 Privileged Access-Never extension">;
  73
  74 def FeatureLOR : SubtargetFeature<
  75     "lor", "HasLOR", "true",
  76     "Enables ARM v8.1 Limited Ordering Regions extension">;
  77
  78 def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
  79     "true", "Enable RW operand CONTEXTIDR_EL2" >;
  80
  81 def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
  82     "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
  83
  84 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  85   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  86
  87 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  88   "Full FP16", [FeatureFPARMv8]>;
  89
  90 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
  91   "Enable FP16 FML instructions", [FeatureFullFP16]>;
  92
  93 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  94   "Enable Statistical Profiling extension">;
  95
  96 def FeaturePAN_RWV : SubtargetFeature<
  97     "pan-rwv", "HasPAN_RWV", "true",
  98     "Enable v8.2 PAN s1e1R and s1e1W Variants",
  99     [FeaturePAN]>;
 100
 101 // UAO PState
 102 def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
 103     "Enable v8.2 UAO PState">;
 104
 105 def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
 106     "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
 107
 108 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
 109   "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
 110
 111 // This flag is currently still labeled as Experimental, but when fully
 112 // implemented this should tell the compiler to use the zeroing pseudos to
 113 // benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
 114 // lanes are known to be zero. The pseudos will then be expanded using the
 115 // MOVPRFX instruction to zero the inactive lanes. This feature should only be
 116 // enabled if MOVPRFX instructions are known to merge with the destructive
 117 // operations they prefix.
 118 //
 119 // This feature could similarly be extended to support cheap merging of _any_
 120 // value into the inactive lanes using the MOVPRFX instruction that uses
 121 // merging-predication.
 122 def FeatureExperimentalZeroingPseudos
 123     : SubtargetFeature<"use-experimental-zeroing-pseudos",
 124                        "UseExperimentalZeroingPseudos", "true",
 125                        "Hint to the compiler that the MOVPRFX instruction is "
 126                        "merged with destructive operations",
 127                        []>;
 128
 129 def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
 130   "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
 131
 132 def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
 133   "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
 134
 135 def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
 136   "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
 137
 138 def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
 139   "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
 140
 141 def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
 142   "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
 143
 144 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
 145                                         "Has zero-cycle register moves">;
 146
 147 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
 148                                         "Has zero-cycle zeroing instructions for generic registers">;
 149
 150 def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
 151                                         "Has no zero-cycle zeroing instructions for FP registers">;
 152
 153 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 154                                         "Has zero-cycle zeroing instructions",
 155                                         [FeatureZCZeroingGP]>;
 156
 157 /// ... but the floating-point version doesn't quite work in rare cases on older
 158 /// CPUs.
 159 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
 160     "HasZeroCycleZeroingFPWorkaround", "true",
 161     "The zero-cycle floating-point zeroing instruction has a bug">;
 162
 163 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 164                                           "StrictAlign", "true",
 165                                           "Disallow all unaligned memory "
 166                                           "access">;
 167
 168 foreach i = {1-7,9-15,18,20-28,30} in
 169     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
 170                                              "Reserve X"#i#", making it unavailable "
 171                                              "as a GPR">;
 172
 173 foreach i = {8-15,18} in
 174     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
 175          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 176
 177 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
 178     "true",
 179     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 180
 181 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
 182     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
 183     "Prefer likely predicted branches over selects">;
 184
 185 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
 186     "CustomAsCheapAsMove", "true",
 187     "Use custom handling of cheap instructions">;
 188
 189 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
 190     "ExynosAsCheapAsMove", "true",
 191     "Use Exynos specific handling of cheap instructions",
 192     [FeatureCustomCheapAsMoveHandling]>;
 193
 194 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 195     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 196
 197 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
 198     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
 199
 200 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 201     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
 202
 203 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
 204     "true", "STR of Q register with register offset is slow">;
 205
 206 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
 207     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
 208     "true", "Use alternative pattern for sextload convert to f32">;
 209
 210 def FeatureArithmeticBccFusion : SubtargetFeature<
 211     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 212     "CPU fuses arithmetic+bcc operations">;
 213
 214 def FeatureArithmeticCbzFusion : SubtargetFeature<
 215     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 216     "CPU fuses arithmetic + cbz/cbnz operations">;
 217
 218 def FeatureCmpBccFusion : SubtargetFeature<
 219     "cmp-bcc-fusion", "HasCmpBccFusion", "true",
 220     "CPU fuses cmp+bcc operations">;
 221
 222 def FeatureFuseAddress : SubtargetFeature<
 223     "fuse-address", "HasFuseAddress", "true",
 224     "CPU fuses address generation and memory operations">;
 225
 226 def FeatureFuseAES : SubtargetFeature<
 227     "fuse-aes", "HasFuseAES", "true",
 228     "CPU fuses AES crypto operations">;
 229
 230 def FeatureFuseArithmeticLogic : SubtargetFeature<
 231     "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
 232     "CPU fuses arithmetic and logic operations">;
 233
 234 def FeatureFuseCCSelect : SubtargetFeature<
 235     "fuse-csel", "HasFuseCCSelect", "true",
 236     "CPU fuses conditional select operations">;
 237
 238 def FeatureFuseCryptoEOR : SubtargetFeature<
 239     "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
 240     "CPU fuses AES/PMULL and EOR operations">;
 241
 242 def FeatureFuseLiterals : SubtargetFeature<
 243     "fuse-literals", "HasFuseLiterals", "true",
 244     "CPU fuses literal generation operations">;
 245
 246 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 247     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 248     "Disable latency scheduling heuristic">;
 249
 250 def FeatureForce32BitJumpTables
 251    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
 252                       "Force jump table entries to be 32-bits wide except at MinSize">;
 253
 254 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
 255                                    "Enable support for RCPC extension">;
 256
 257 def FeatureUseRSqrt : SubtargetFeature<
 258     "use-reciprocal-square-root", "UseRSqrt", "true",
 259     "Use the reciprocal square root approximation">;
 260
 261 def FeatureDotProd : SubtargetFeature<
 262     "dotprod", "HasDotProd", "true",
 263     "Enable dot product support">;
 264
 265 def FeaturePAuth : SubtargetFeature<
 266     "pauth", "HasPAuth", "true",
 267     "Enable v8.3-A Pointer Authentication extension">;
 268
 269 def FeatureJS : SubtargetFeature<
 270     "jsconv", "HasJS", "true",
 271     "Enable v8.3-A JavaScript FP conversion instructions",
 272     [FeatureFPARMv8]>;
 273
 274 def FeatureCCIDX : SubtargetFeature<
 275     "ccidx", "HasCCIDX", "true",
 276     "Enable v8.3-A Extend of the CCSIDR number of sets">;
 277
 278 def FeatureComplxNum : SubtargetFeature<
 279     "complxnum", "HasComplxNum", "true",
 280     "Enable v8.3-A Floating-point complex number support",
 281     [FeatureNEON]>;
 282
 283 def FeatureNV : SubtargetFeature<
 284     "nv", "HasNV", "true",
 285     "Enable v8.4-A Nested Virtualization Enchancement">;
 286
 287 def FeatureMPAM : SubtargetFeature<
 288     "mpam", "HasMPAM", "true",
 289     "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
 290
 291 def FeatureDIT : SubtargetFeature<
 292     "dit", "HasDIT", "true",
 293     "Enable v8.4-A Data Independent Timing instructions">;
 294
 295 def FeatureTRACEV8_4 : SubtargetFeature<
 296     "tracev8.4", "HasTRACEV8_4", "true",
 297     "Enable v8.4-A Trace extension">;
 298
 299 def FeatureAM : SubtargetFeature<
 300     "am", "HasAM", "true",
 301     "Enable v8.4-A Activity Monitors extension">;
 302
 303 def FeatureAMVS : SubtargetFeature<
 304     "amvs", "HasAMVS", "true",
 305     "Enable v8.6-A Activity Monitors Virtualization support",
 306     [FeatureAM]>;
 307
 308 def FeatureSEL2 : SubtargetFeature<
 309     "sel2", "HasSEL2", "true",
 310     "Enable v8.4-A Secure Exception Level 2 extension">;
 311
 312 def FeaturePMU : SubtargetFeature<
 313     "pmu", "HasPMU", "true",
 314     "Enable v8.4-A PMU extension">;
 315
 316 def FeatureTLB_RMI : SubtargetFeature<
 317     "tlb-rmi", "HasTLB_RMI", "true",
 318     "Enable v8.4-A TLB Range and Maintenance Instructions">;
 319
 320 def FeatureFlagM : SubtargetFeature<
 321     "flagm", "HasFlagM", "true",
 322     "Enable v8.4-A Flag Manipulation Instructions">;
 323
 324 // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
 325 def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
 326     "Enable v8.4-A RCPC instructions with Immediate Offsets",
 327     [FeatureRCPC]>;
 328
 329 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 330                                         "NegativeImmediates", "false",
 331                                         "Convert immediates and instructions "
 332                                         "to their negated or complemented "
 333                                         "equivalent when the immediate does "
 334                                         "not fit in the encoding.">;
 335
 336 def FeatureLSLFast : SubtargetFeature<
 337     "lsl-fast", "HasLSLFast", "true",
 338     "CPU has a fastpath logical shift of up to 3 places">;
 339
 340 def FeatureAggressiveFMA :
 341   SubtargetFeature<"aggressive-fma",
 342                    "HasAggressiveFMA",
 343                    "true",
 344                    "Enable Aggressive FMA for floating-point.">;
 345
 346 def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
 347   "Enable alternative NZCV format for floating point comparisons">;
 348
 349 def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
 350   "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
 351   "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
 352
 353 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
 354   "true", "Enable architectural speculation restriction" >;
 355
 356 def FeatureSB : SubtargetFeature<"sb", "HasSB",
 357   "true", "Enable v8.5 Speculation Barrier" >;
 358
 359 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
 360   "true", "Enable Speculative Store Bypass Safe bit" >;
 361
 362 def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
 363   "Enable v8.5a execution and data prediction invalidation instructions" >;
 364
 365 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
 366     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
 367
 368 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
 369     "true", "Enable Branch Target Identification" >;
 370
 371 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
 372     "true", "Enable Random Number generation instructions" >;
 373
 374 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
 375     "true", "Enable Memory Tagging Extension" >;
 376
 377 def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
 378     "true", "Enable Trace Buffer Extension">;
 379
 380 def FeatureETE : SubtargetFeature<"ete", "HasETE",
 381     "true", "Enable Embedded Trace Extension",
 382     [FeatureTRBE]>;
 383
 384 def FeatureTME : SubtargetFeature<"tme", "HasTME",
 385     "true", "Enable Transactional Memory Extension" >;
 386
 387 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
 388     "AllowTaggedGlobals",
 389     "true", "Use an instruction sequence for taking the address of a global "
 390     "that allows a memory tag in the upper address bits">;
 391
 392 def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
 393     "true", "Enable BFloat16 Extension" >;
 394
 395 def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
 396     "true", "Enable Matrix Multiply Int8 Extension">;
 397
 398 def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
 399     "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
 400
 401 def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
 402     "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
 403
 404 def FeatureXS : SubtargetFeature<"xs", "HasXS",
 405     "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
 406
 407 def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
 408     "true", "Enable Armv8.7-A WFET and WFIT instruction">;
 409
 410 def FeatureHCX : SubtargetFeature<
 411     "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
 412
 413 def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
 414     "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
 415
 416 def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
 417     "true", "Enable Branch Record Buffer Extension">;
 418
 419 def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
 420     "true", "Enable extra register in the Statistical Profiling Extension">;
 421
 422 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
 423     "true", "Enable fine grained virtualization traps extension">;
 424
 425 def FeatureEnhancedCounterVirtualization :
 426       SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
 427       "true", "Enable enhanced counter virtualization extension">;
 428
 429 def FeatureRME : SubtargetFeature<"rme", "HasRME",
 430     "true", "Enable Realm Management Extension">;
 431
 432 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode
 433 // defined by SME.
 434 def FeatureStreamingSVE : SubtargetFeature<"streaming-sve",
 435                                            "HasStreamingSVE", "true",
 436   "Enable subset of SVE(2) instructions for Streaming SVE execution mode">;
 437 def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
 438   "Enable Scalable Matrix Extension (SME)", [FeatureStreamingSVE, FeatureBF16]>;
 439
 440 def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
 441   "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
 442
 443 def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
 444   "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;
 445
 446 //===----------------------------------------------------------------------===//
 447 // Architectures.
 448 //
 449
 450 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 451   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
 452   FeaturePAN, FeatureLOR, FeatureVH]>;
 453
 454 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 455   "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
 456   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 457
 458 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 459   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
 460   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 461
 462 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 463   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
 464   FeatureNV, FeatureMPAM, FeatureDIT,
 465   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
 466   FeatureFlagM, FeatureRCPC_IMMO]>;
 467
 468 def HasV8_5aOps : SubtargetFeature<
 469   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
 470   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
 471    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
 472    FeatureBranchTargetId]>;
 473
 474 def HasV8_6aOps : SubtargetFeature<
 475   "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
 476   [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
 477    FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
 478
 479 def HasV8_7aOps : SubtargetFeature<
 480   "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
 481   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 482
 483 def HasV8_0rOps : SubtargetFeature<
 484   "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
 485   [//v8.1
 486   FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
 487   //v8.2
 488   FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4,
 489   FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,
 490   //v8.3
 491   FeatureComplxNum, FeatureCCIDX, FeatureJS,
 492   FeaturePAuth, FeatureRCPC,
 493   //v8.4
 494   FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
 495   FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
 496   //v8.5
 497   FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
 498
 499 //===----------------------------------------------------------------------===//
 500 // Register File Description
 501 //===----------------------------------------------------------------------===//
 502
 503 include "AArch64RegisterInfo.td"
 504 include "AArch64RegisterBanks.td"
 505 include "AArch64CallingConvention.td"
 506
 507 //===----------------------------------------------------------------------===//
 508 // Instruction Descriptions
 509 //===----------------------------------------------------------------------===//
 510
 511 include "AArch64Schedule.td"
 512 include "AArch64InstrInfo.td"
 513 include "AArch64SchedPredicates.td"
 514 include "AArch64SchedPredExynos.td"
 515 include "AArch64Combine.td"
 516
 517 def AArch64InstrInfo : InstrInfo;
 518
 519 //===----------------------------------------------------------------------===//
 520 // Named operands for MRS/MSR/TLBI/...
 521 //===----------------------------------------------------------------------===//
 522
 523 include "AArch64SystemOperands.td"
 524
 525 //===----------------------------------------------------------------------===//
 526 // Access to privileged registers
 527 //===----------------------------------------------------------------------===//
 528
 529 foreach i = 1-3 in
 530 def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
 531   "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
 532
 533 //===----------------------------------------------------------------------===//
 534 // Control codegen mitigation against Straight Line Speculation vulnerability.
 535 //===----------------------------------------------------------------------===//
 536
 537 def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
 538   "HardenSlsRetBr", "true",
 539   "Harden against straight line speculation across RET and BR instructions">;
 540 def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
 541   "HardenSlsBlr", "true",
 542   "Harden against straight line speculation across BLR instructions">;
 543 def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
 544   "HardenSlsNoComdat", "true",
 545   "Generate thunk code for SLS mitigation in the normal text section">;
 546
 547 //===----------------------------------------------------------------------===//
 548 // AArch64 Processors supported.
 549 //
 550
 551 //===----------------------------------------------------------------------===//
 552 // Unsupported features to disable for scheduling models
 553 //===----------------------------------------------------------------------===//
 554
 555 class AArch64Unsupported { list<Predicate> F; }
 556
 557 def SVEUnsupported : AArch64Unsupported {
 558   let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
 559            HasSVE2BitPerm, HasSVEorStreamingSVE, HasSVE2orStreamingSVE];
 560 }
 561
 562 def PAUnsupported : AArch64Unsupported {
 563   let F = [HasPAuth];
 564 }
 565
 566 def SMEUnsupported : AArch64Unsupported {
 567   let F = [HasSME, HasSMEF64, HasSMEI64];
 568 }
 569
 570 include "AArch64SchedA53.td"
 571 include "AArch64SchedA55.td"
 572 include "AArch64SchedA57.td"
 573 include "AArch64SchedCyclone.td"
 574 include "AArch64SchedFalkor.td"
 575 include "AArch64SchedKryo.td"
 576 include "AArch64SchedExynosM3.td"
 577 include "AArch64SchedExynosM4.td"
 578 include "AArch64SchedExynosM5.td"
 579 include "AArch64SchedThunderX.td"
 580 include "AArch64SchedThunderX2T99.td"
 581 include "AArch64SchedA64FX.td"
 582 include "AArch64SchedThunderX3T110.td"
 583 include "AArch64SchedTSV110.td"
 584
 585 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 586                                    "Cortex-A35 ARM processors", [
 587                                    FeatureCRC,
 588                                    FeatureCrypto,
 589                                    FeatureFPARMv8,
 590                                    FeatureNEON,
 591                                    FeaturePerfMon
 592                                    ]>;
 593
 594 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 595                                    "Cortex-A53 ARM processors", [
 596                                    FeatureBalanceFPOps,
 597                                    FeatureCRC,
 598                                    FeatureCrypto,
 599                                    FeatureCustomCheapAsMoveHandling,
 600                                    FeatureFPARMv8,
 601                                    FeatureFuseAES,
 602                                    FeatureNEON,
 603                                    FeaturePerfMon,
 604                                    FeaturePostRAScheduler,
 605                                    ]>;
 606
 607 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 608                                    "Cortex-A55 ARM processors", [
 609                                    HasV8_2aOps,
 610                                    FeatureCrypto,
 611                                    FeatureFPARMv8,
 612                                    FeatureFuseAES,
 613                                    FeatureNEON,
 614                                    FeatureFullFP16,
 615                                    FeatureDotProd,
 616                                    FeatureRCPC,
 617                                    FeaturePerfMon,
 618                                    FeaturePostRAScheduler,
 619                                    ]>;
 620
 621 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 622                                    "Cortex-A57 ARM processors", [
 623                                    FeatureBalanceFPOps,
 624                                    FeatureCRC,
 625                                    FeatureCrypto,
 626                                    FeatureCustomCheapAsMoveHandling,
 627                                    FeatureFPARMv8,
 628                                    FeatureFuseAES,
 629                                    FeatureFuseLiterals,
 630                                    FeatureNEON,
 631                                    FeaturePerfMon,
 632                                    FeaturePostRAScheduler,
 633                                    FeaturePredictableSelectIsExpensive
 634                                    ]>;
 635
 636 def ProcA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
 637                                    "Cortex-A65 ARM processors", [
 638                                    HasV8_2aOps,
 639                                    FeatureCrypto,
 640                                    FeatureDotProd,
 641                                    FeatureFPARMv8,
 642                                    FeatureFullFP16,
 643                                    FeatureFuseAddress,
 644                                    FeatureFuseAES,
 645                                    FeatureFuseLiterals,
 646                                    FeatureNEON,
 647                                    FeatureRAS,
 648                                    FeatureRCPC,
 649                                    FeatureSSBS,
 650                                    ]>;
 651
 652 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 653                                    "Cortex-A72 ARM processors", [
 654                                    FeatureCRC,
 655                                    FeatureCrypto,
 656                                    FeatureFPARMv8,
 657                                    FeatureFuseAES,
 658                                    FeatureFuseLiterals,
 659                                    FeatureNEON,
 660                                    FeaturePerfMon
 661                                    ]>;
 662
 663 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 664                                    "Cortex-A73 ARM processors", [
 665                                    FeatureCRC,
 666                                    FeatureCrypto,
 667                                    FeatureFPARMv8,
 668                                    FeatureFuseAES,
 669                                    FeatureNEON,
 670                                    FeaturePerfMon
 671                                    ]>;
 672
 673 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 674                                    "Cortex-A75 ARM processors", [
 675                                    HasV8_2aOps,
 676                                    FeatureCrypto,
 677                                    FeatureFPARMv8,
 678                                    FeatureFuseAES,
 679                                    FeatureNEON,
 680                                    FeatureFullFP16,
 681                                    FeatureDotProd,
 682                                    FeatureRCPC,
 683                                    FeaturePerfMon
 684                                    ]>;
 685
 686 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 687                                    "Cortex-A76 ARM processors", [
 688                                     HasV8_2aOps,
 689                                     FeatureFPARMv8,
 690                                     FeatureFuseAES,
 691                                     FeatureNEON,
 692                                     FeatureRCPC,
 693                                     FeatureCrypto,
 694                                     FeatureFullFP16,
 695                                     FeatureDotProd,
 696                                     FeatureSSBS
 697                                     ]>;
 698
 699 def ProcA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
 700                                    "Cortex-A77 ARM processors", [
 701                                     HasV8_2aOps,
 702                                     FeatureCmpBccFusion,
 703                                     FeatureFPARMv8,
 704                                     FeatureFuseAES,
 705                                     FeatureNEON, FeatureRCPC,
 706                                     FeatureCrypto,
 707                                     FeatureFullFP16,
 708                                     FeatureDotProd
 709                                     ]>;
 710
 711 def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
 712                                "CortexA78",
 713                                "Cortex-A78 ARM processors", [
 714                                HasV8_2aOps,
 715                                FeatureCmpBccFusion,
 716                                FeatureCrypto,
 717                                FeatureFPARMv8,
 718                                FeatureFuseAES,
 719                                FeatureNEON,
 720                                FeatureRCPC,
 721                                FeaturePerfMon,
 722                                FeaturePostRAScheduler,
 723                                FeatureSPE,
 724                                FeatureFullFP16,
 725                                FeatureSSBS,
 726                                FeatureDotProd]>;
 727
 728 def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
 729                                 "CortexA78C",
 730                                 "Cortex-A78C ARM processors", [
 731                                 HasV8_2aOps,
 732                                 FeatureCmpBccFusion,
 733                                 FeatureCrypto,
 734                                 FeatureDotProd,
 735                                 FeatureFlagM,
 736                                 FeatureFP16FML,
 737                                 FeatureFPARMv8,
 738                                 FeatureFullFP16,
 739                                 FeatureFuseAES,
 740                                 FeatureNEON,
 741                                 FeaturePAuth,
 742                                 FeaturePerfMon,
 743                                 FeaturePostRAScheduler,
 744                                 FeatureRCPC,
 745                                 FeatureSPE,
 746                                 FeatureSSBS]>;
 747
 748 def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
 749                                "CortexR82",
 750                                "Cortex-R82 ARM Processors", [
 751                                FeaturePostRAScheduler,
 752                                // All other features are implied by v8_0r ops:
 753                                HasV8_0rOps,
 754                                ]>;
 755
 756 def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
 757                                   "Cortex-X1 ARM processors", [
 758                                   HasV8_2aOps,
 759                                   FeatureCmpBccFusion,
 760                                   FeatureCrypto,
 761                                   FeatureFPARMv8,
 762                                   FeatureFuseAES,
 763                                   FeatureNEON,
 764                                   FeatureRCPC,
 765                                   FeaturePerfMon,
 766                                   FeaturePostRAScheduler,
 767                                   FeatureSPE,
 768                                   FeatureFullFP16,
 769                                   FeatureDotProd]>;
 770
 771 def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
 772                                  "Fujitsu A64FX processors", [
 773                                   HasV8_2aOps,
 774                                   FeatureFPARMv8,
 775                                   FeatureNEON,
 776                                   FeatureSHA2,
 777                                   FeaturePerfMon,
 778                                   FeatureFullFP16,
 779                                   FeatureSVE,
 780                                   FeaturePostRAScheduler,
 781                                   FeatureComplxNum,
 782                                   FeatureAggressiveFMA,
 783                                   FeatureArithmeticBccFusion,
 784                                   FeaturePredictableSelectIsExpensive
 785                                   ]>;
 786
 787 def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
 788                                   "Nvidia Carmel processors", [
 789                                    HasV8_2aOps,
 790                                    FeatureNEON,
 791                                    FeatureCrypto,
 792                                    FeatureFullFP16
 793                                    ]>;
 794
 795 // Note that cyclone does not fuse AES instructions, but newer apple chips do
 796 // perform the fusion and cyclone is used by default when targetting apple OSes.
 797 def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
 798                                    "Apple A7 (the CPU formerly known as Cyclone)", [
 799                                    FeatureAlternateSExtLoadCVTF32Pattern,
 800                                    FeatureArithmeticBccFusion,
 801                                    FeatureArithmeticCbzFusion,
 802                                    FeatureCrypto,
 803                                    FeatureDisableLatencySchedHeuristic,
 804                                    FeatureFPARMv8,
 805                                    FeatureFuseAES,
 806                                    FeatureFuseCryptoEOR,
 807                                    FeatureNEON,
 808                                    FeaturePerfMon,
 809                                    FeatureZCRegMove,
 810                                    FeatureZCZeroing,
 811                                    FeatureZCZeroingFPWorkaround
 812                                    ]>;
 813
 814 def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
 815                                     "Apple A10", [
 816                                     FeatureAlternateSExtLoadCVTF32Pattern,
 817                                     FeatureArithmeticBccFusion,
 818                                     FeatureArithmeticCbzFusion,
 819                                     FeatureCrypto,
 820                                     FeatureDisableLatencySchedHeuristic,
 821                                     FeatureFPARMv8,
 822                                     FeatureFuseAES,
 823                                     FeatureFuseCryptoEOR,
 824                                     FeatureNEON,
 825                                     FeaturePerfMon,
 826                                     FeatureZCRegMove,
 827                                     FeatureZCZeroing,
 828                                     FeatureCRC,
 829                                     FeatureRDM,
 830                                     FeaturePAN,
 831                                     FeatureLOR,
 832                                     FeatureVH,
 833                                     ]>;
 834
 835 def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
 836                                     "Apple A11", [
 837                                     FeatureAlternateSExtLoadCVTF32Pattern,
 838                                     FeatureArithmeticBccFusion,
 839                                     FeatureArithmeticCbzFusion,
 840                                     FeatureCrypto,
 841                                     FeatureDisableLatencySchedHeuristic,
 842                                     FeatureFPARMv8,
 843                                     FeatureFuseAES,
 844                                     FeatureFuseCryptoEOR,
 845                                     FeatureNEON,
 846                                     FeaturePerfMon,
 847                                     FeatureZCRegMove,
 848                                     FeatureZCZeroing,
 849                                     FeatureFullFP16,
 850                                     HasV8_2aOps
 851                                     ]>;
 852
 853 def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
 854                                     "Apple A12", [
 855                                     FeatureAlternateSExtLoadCVTF32Pattern,
 856                                     FeatureArithmeticBccFusion,
 857                                     FeatureArithmeticCbzFusion,
 858                                     FeatureCrypto,
 859                                     FeatureDisableLatencySchedHeuristic,
 860                                     FeatureFPARMv8,
 861                                     FeatureFuseAES,
 862                                     FeatureFuseCryptoEOR,
 863                                     FeatureNEON,
 864                                     FeaturePerfMon,
 865                                     FeatureZCRegMove,
 866                                     FeatureZCZeroing,
 867                                     FeatureFullFP16,
 868                                     HasV8_3aOps
 869                                     ]>;
 870
 871 def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
 872                                      "Apple A13", [
 873                                      FeatureAlternateSExtLoadCVTF32Pattern,
 874                                      FeatureArithmeticBccFusion,
 875                                      FeatureArithmeticCbzFusion,
 876                                      FeatureCrypto,
 877                                      FeatureDisableLatencySchedHeuristic,
 878                                      FeatureFPARMv8,
 879                                      FeatureFuseAES,
 880                                      FeatureFuseCryptoEOR,
 881                                      FeatureNEON,
 882                                      FeaturePerfMon,
 883                                      FeatureZCRegMove,
 884                                      FeatureZCZeroing,
 885                                      FeatureFullFP16,
 886                                      FeatureFP16FML,
 887                                      FeatureSHA3,
 888                                      HasV8_4aOps
 889                                      ]>;
 890
 891 def ProcAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
 892                                      "Apple A14", [
 893                                      FeatureAggressiveFMA,
 894                                      FeatureAlternateSExtLoadCVTF32Pattern,
 895                                      FeatureAltFPCmp,
 896                                      FeatureArithmeticBccFusion,
 897                                      FeatureArithmeticCbzFusion,
 898                                      FeatureCrypto,
 899                                      FeatureDisableLatencySchedHeuristic,
 900                                      FeatureFPARMv8,
 901                                      FeatureFRInt3264,
 902                                      FeatureFuseAddress,
 903                                      FeatureFuseAES,
 904                                      FeatureFuseArithmeticLogic,
 905                                      FeatureFuseCCSelect,
 906                                      FeatureFuseCryptoEOR,
 907                                      FeatureFuseLiterals,
 908                                      FeatureNEON,
 909                                      FeaturePerfMon,
 910                                      FeatureSpecRestrict,
 911                                      FeatureSSBS,
 912                                      FeatureSB,
 913                                      FeaturePredRes,
 914                                      FeatureCacheDeepPersist,
 915                                      FeatureZCRegMove,
 916                                      FeatureZCZeroing,
 917                                      FeatureFullFP16,
 918                                      FeatureFP16FML,
 919                                      FeatureSHA3,
 920                                      HasV8_4aOps
 921                                      ]>;
 922
 923 def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
 924                                     "Samsung Exynos-M3 processors",
 925                                     [FeatureCRC,
 926                                      FeatureCrypto,
 927                                      FeatureExynosCheapAsMoveHandling,
 928                                      FeatureForce32BitJumpTables,
 929                                      FeatureFuseAddress,
 930                                      FeatureFuseAES,
 931                                      FeatureFuseCCSelect,
 932                                      FeatureFuseLiterals,
 933                                      FeatureLSLFast,
 934                                      FeaturePerfMon,
 935                                      FeaturePostRAScheduler,
 936                                      FeaturePredictableSelectIsExpensive]>;
 937
 938 def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
 939                                     "Samsung Exynos-M4 processors",
 940                                     [HasV8_2aOps,
 941                                      FeatureArithmeticBccFusion,
 942                                      FeatureArithmeticCbzFusion,
 943                                      FeatureCrypto,
 944                                      FeatureDotProd,
 945                                      FeatureExynosCheapAsMoveHandling,
 946                                      FeatureForce32BitJumpTables,
 947                                      FeatureFullFP16,
 948                                      FeatureFuseAddress,
 949                                      FeatureFuseAES,
 950                                      FeatureFuseArithmeticLogic,
 951                                      FeatureFuseCCSelect,
 952                                      FeatureFuseLiterals,
 953                                      FeatureLSLFast,
 954                                      FeaturePerfMon,
 955                                      FeaturePostRAScheduler,
 956                                      FeatureZCZeroing]>;
 957
 958 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 959                                    "Qualcomm Kryo processors", [
 960                                    FeatureCRC,
 961                                    FeatureCrypto,
 962                                    FeatureCustomCheapAsMoveHandling,
 963                                    FeatureFPARMv8,
 964                                    FeatureNEON,
 965                                    FeaturePerfMon,
 966                                    FeaturePostRAScheduler,
 967                                    FeaturePredictableSelectIsExpensive,
 968                                    FeatureZCZeroing,
 969                                    FeatureLSLFast
 970                                    ]>;
 971
 972 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 973                                    "Qualcomm Falkor processors", [
 974                                    FeatureCRC,
 975                                    FeatureCrypto,
 976                                    FeatureCustomCheapAsMoveHandling,
 977                                    FeatureFPARMv8,
 978                                    FeatureNEON,
 979                                    FeaturePerfMon,
 980                                    FeaturePostRAScheduler,
 981                                    FeaturePredictableSelectIsExpensive,
 982                                    FeatureRDM,
 983                                    FeatureZCZeroing,
 984                                    FeatureLSLFast,
 985                                    FeatureSlowSTRQro
 986                                    ]>;
 987
 988 def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
 989                                       "NeoverseE1",
 990                                       "Neoverse E1 ARM processors", [
 991                                       HasV8_2aOps,
 992                                       FeatureCrypto,
 993                                       FeatureDotProd,
 994                                       FeatureFPARMv8,
 995                                       FeatureFullFP16,
 996                                       FeatureNEON,
 997                                       FeatureRCPC,
 998                                       FeatureSSBS,
 999                                       FeaturePostRAScheduler,
1000                                       FeatureFuseAES,
1001                                       ]>;
1002
1003 def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
1004                                       "NeoverseN1",
1005                                       "Neoverse N1 ARM processors", [
1006                                       HasV8_2aOps,
1007                                       FeatureCrypto,
1008                                       FeatureDotProd,
1009                                       FeatureFPARMv8,
1010                                       FeatureFullFP16,
1011                                       FeatureNEON,
1012                                       FeatureRCPC,
1013                                       FeatureSPE,
1014                                       FeatureSSBS,
1015                                       FeaturePostRAScheduler,
1016                                       FeatureFuseAES,
1017                                       ]>;
1018
1019 def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
1020                                       "NeoverseN2",
1021                                       "Neoverse N2 ARM processors", [
1022                                       HasV8_5aOps,
1023                                       FeatureBF16,
1024                                       FeatureETE,
1025                                       FeatureMatMulInt8,
1026                                       FeatureMTE,
1027                                       FeatureSVE2,
1028                                       FeatureSVE2BitPerm,
1029                                       FeatureTRBE,
1030                                       FeaturePostRAScheduler,
1031                                       FeatureCrypto,
1032                                       FeatureFuseAES,
1033                                       ]>;
1034
1035 def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
1036                                       "NeoverseV1",
1037                                       "Neoverse V1 ARM processors", [
1038                                       HasV8_4aOps,
1039                                       FeatureBF16,
1040                                       FeatureCacheDeepPersist,
1041                                       FeatureCrypto,
1042                                       FeatureFPARMv8,
1043                                       FeatureFP16FML,
1044                                       FeatureFullFP16,
1045                                       FeatureFuseAES,
1046                                       FeatureMatMulInt8,
1047                                       FeatureNEON,
1048                                       FeaturePerfMon,
1049                                       FeaturePostRAScheduler,
1050                                       FeatureRandGen,
1051                                       FeatureSPE,
1052                                       FeatureSSBS,
1053                                       FeatureSVE]>;
1054
1055 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
1056                                    "Qualcomm Saphira processors", [
1057                                    FeatureCrypto,
1058                                    FeatureCustomCheapAsMoveHandling,
1059                                    FeatureFPARMv8,
1060                                    FeatureNEON,
1061                                    FeatureSPE,
1062                                    FeaturePerfMon,
1063                                    FeaturePostRAScheduler,
1064                                    FeaturePredictableSelectIsExpensive,
1065                                    FeatureZCZeroing,
1066                                    FeatureLSLFast,
1067                                    HasV8_4aOps]>;
1068
1069 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
1070                                          "ThunderX2T99",
1071                                          "Cavium ThunderX2 processors", [
1072                                           FeatureAggressiveFMA,
1073                                           FeatureCRC,
1074                                           FeatureCrypto,
1075                                           FeatureFPARMv8,
1076                                           FeatureArithmeticBccFusion,
1077                                           FeatureNEON,
1078                                           FeaturePostRAScheduler,
1079                                           FeaturePredictableSelectIsExpensive,
1080                                           FeatureLSE,
1081                                           HasV8_1aOps]>;
1082
1083 def ProcThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
1084                                          "ThunderX3T110",
1085                                          "Marvell ThunderX3 processors", [
1086                                           FeatureAggressiveFMA,
1087                                           FeatureCRC,
1088                                           FeatureCrypto,
1089                                           FeatureFPARMv8,
1090                                           FeatureArithmeticBccFusion,
1091                                           FeatureNEON,
1092                                           FeaturePostRAScheduler,
1093                                           FeaturePredictableSelectIsExpensive,
1094                                           FeatureLSE,
1095                                           FeaturePAuth,
1096                                           FeatureBalanceFPOps,
1097                                           FeaturePerfMon,
1098                                           FeatureStrictAlign,
1099                                           HasV8_3aOps]>;
1100
1101 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
1102                                     "Cavium ThunderX processors", [
1103                                     FeatureCRC,
1104                                     FeatureCrypto,
1105                                     FeatureFPARMv8,
1106                                     FeaturePerfMon,
1107                                     FeaturePostRAScheduler,
1108                                     FeaturePredictableSelectIsExpensive,
1109                                     FeatureNEON]>;
1110
1111 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
1112                                        "ThunderXT88",
1113                                        "Cavium ThunderX processors", [
1114                                        FeatureCRC,
1115                                        FeatureCrypto,
1116                                        FeatureFPARMv8,
1117                                        FeaturePerfMon,
1118                                        FeaturePostRAScheduler,
1119                                        FeaturePredictableSelectIsExpensive,
1120                                        FeatureNEON]>;
1121
1122 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
1123                                        "ThunderXT81",
1124                                        "Cavium ThunderX processors", [
1125                                        FeatureCRC,
1126                                        FeatureCrypto,
1127                                        FeatureFPARMv8,
1128                                        FeaturePerfMon,
1129                                        FeaturePostRAScheduler,
1130                                        FeaturePredictableSelectIsExpensive,
1131                                        FeatureNEON]>;
1132
1133 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
1134                                        "ThunderXT83",
1135                                        "Cavium ThunderX processors", [
1136                                        FeatureCRC,
1137                                        FeatureCrypto,
1138                                        FeatureFPARMv8,
1139                                        FeaturePerfMon,
1140                                        FeaturePostRAScheduler,
1141                                        FeaturePredictableSelectIsExpensive,
1142                                        FeatureNEON]>;
1143
1144 def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
1145                                   "HiSilicon TS-V110 processors", [
1146                                   HasV8_2aOps,
1147                                   FeatureCrypto,
1148                                   FeatureCustomCheapAsMoveHandling,
1149                                   FeatureFPARMv8,
1150                                   FeatureFuseAES,
1151                                   FeatureNEON,
1152                                   FeaturePerfMon,
1153                                   FeaturePostRAScheduler,
1154                                   FeatureSPE,
1155                                   FeatureFullFP16,
1156                                   FeatureFP16FML,
1157                                   FeatureDotProd]>;
1158
1159 def : ProcessorModel<"generic", NoSchedModel, [
1160                      FeatureFPARMv8,
1161                      FeatureFuseAES,
1162                      FeatureNEON,
1163                      FeaturePerfMon,
1164                      FeaturePostRAScheduler,
1165 // ETE and TRBE are future architecture extensions. We temporarily enable them
1166 // by default for users targeting generic AArch64, until it is decided in which
1167 // armv8.x-a architecture revision they will end up. The extensions do not
1168 // affect code generated by the compiler and can be used only by explicitly
1169 // mentioning the new system register names in assembly.
1170                      FeatureETE
1171                      ]>;
1172
1173 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
1174 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
1175 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
1176 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
1177 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
1178 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
1179 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
1180 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
1181 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
1182 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
1183 def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
1184 def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
1185 def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
1186 def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
1187 def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>;
1188 def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
1189 def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
1190 def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
1191 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
1192 def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
1193 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
1194 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
1195 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
1196 def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
1197 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
1198 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
1199 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
1200 // Cavium ThunderX/ThunderX T8X  Processors
1201 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
1202 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
1203 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
1204 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
1205 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1206 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
1207 // Marvell ThunderX3T110 Processors.
1208 def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>;
1209 def : ProcessorModel<"tsv110", TSV110Model, [ProcTSV110]>;
1210
1211 // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1212 def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>;
1213
1214 // iPhone and iPad CPUs
1215 def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>;
1216 def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>;
1217 def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>;
1218 def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>;
1219 def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>;
1220 def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>;
1221 def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>;
1222 def : ProcessorModel<"apple-a14", CycloneModel, [ProcAppleA14]>;
1223
1224 // Mac CPUs
1225 def : ProcessorModel<"apple-m1", CycloneModel, [ProcAppleA14]>;
1226
1227 // watch CPUs.
1228 def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>;
1229 def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>;
1230
1231 // Alias for the latest Apple processor model supported by LLVM.
1232 def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA14]>;
1233
1234 // Fujitsu A64FX
1235 def : ProcessorModel<"a64fx", A64FXModel, [ProcA64FX]>;
1236
1237 // Nvidia Carmel
1238 def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>;
1239
1240 //===----------------------------------------------------------------------===//
1241 // Assembly parser
1242 //===----------------------------------------------------------------------===//
1243
1244 def GenericAsmParserVariant : AsmParserVariant {
1245   int Variant = 0;
1246   string Name = "generic";
1247   string BreakCharacters = ".";
1248   string TokenizingCharacters = "[]*!/";
1249 }
1250
1251 def AppleAsmParserVariant : AsmParserVariant {
1252   int Variant = 1;
1253   string Name = "apple-neon";
1254   string BreakCharacters = ".";
1255   string TokenizingCharacters = "[]*!/";
1256 }
1257
1258 //===----------------------------------------------------------------------===//
1259 // Assembly printer
1260 //===----------------------------------------------------------------------===//
1261 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
1262 // AsmWriter bits get associated with the correct class.
1263 def GenericAsmWriter : AsmWriter {
1264   string AsmWriterClassName  = "InstPrinter";
1265   int PassSubtarget = 1;
1266   int Variant = 0;
1267   bit isMCAsmWriter = 1;
1268 }
1269
1270 def AppleAsmWriter : AsmWriter {
1271   let AsmWriterClassName = "AppleInstPrinter";
1272   int PassSubtarget = 1;
1273   int Variant = 1;
1274   int isMCAsmWriter = 1;
1275 }
1276
1277 //===----------------------------------------------------------------------===//
1278 // Target Declaration
1279 //===----------------------------------------------------------------------===//
1280
1281 def AArch64 : Target {
1282   let InstructionSet = AArch64InstrInfo;
1283   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1284   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1285   let AllowRegisterRenaming = 1;
1286 }
1287
1288 //===----------------------------------------------------------------------===//
1289 // Pfm Counters
1290 //===----------------------------------------------------------------------===//
1291
1292 include "AArch64PfmCounters.td"