llvm/lib/Target/AArch64/AArch64RegisterInfo.h

   1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the AArch64 implementation of the MRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
  14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
  15
  16 #define GET_REGINFO_HEADER
  17 #include "AArch64GenRegisterInfo.inc"
  18
  19 namespace llvm {
  20
  21 class MachineFunction;
  22 class RegScavenger;
  23 class TargetRegisterClass;
  24 class Triple;
  25
  26 class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
  27   const Triple &TT;
  28
  29 public:
  30   AArch64RegisterInfo(const Triple &TT);
  31
  32   // FIXME: This should be tablegen'd like getDwarfRegNum is
  33   int getSEHRegNum(unsigned i) const {
  34     return getEncodingValue(i);
  35   }
  36
  37   bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
  38   bool isAnyArgRegReserved(const MachineFunction &MF) const;
  39   void emitReservedArgRegCallError(const MachineFunction &MF) const;
  40
  41   void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
  42   void UpdateCustomCallPreservedMask(MachineFunction &MF,
  43                                      const uint32_t **Mask) const;
  44
  45   static bool hasSVEArgsOrReturn(const MachineFunction *MF);
  46
  47   /// Code Generation virtual methods...
  48   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  49   const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
  50   const MCPhysReg *
  51   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
  52   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
  53                                        CallingConv::ID) const override;
  54   const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
  55                                              CallingConv::ID) const;
  56
  57   unsigned getCSRFirstUseCost() const override {
  58     // The cost will be compared against BlockFrequency where entry has the
  59     // value of 1 << 14. A value of 5 will choose to spill or split really
  60     // cold path instead of using a callee-saved register.
  61     return 5;
  62   }
  63
  64   const TargetRegisterClass *
  65   getSubClassWithSubReg(const TargetRegisterClass *RC,
  66                         unsigned Idx) const override;
  67
  68   // Calls involved in thread-local variable lookup save more registers than
  69   // normal calls, so they need a different mask to represent this.
  70   const uint32_t *getTLSCallPreservedMask() const;
  71
  72   // Funclets on ARM64 Windows don't preserve any registers.
  73   const uint32_t *getNoPreservedMask() const override;
  74
  75   // Unwinders may not preserve all Neon and SVE registers.
  76   const uint32_t *
  77   getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
  78
  79   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
  80   /// case that 'returned' is on an i64 first argument if the calling convention
  81   /// is one that can (partially) model this attribute with a preserved mask
  82   /// (i.e. it is a calling convention that uses the same register for the first
  83   /// i64 argument and an i64 return value)
  84   ///
  85   /// Should return NULL in the case that the calling convention does not have
  86   /// this property
  87   const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
  88                                              CallingConv::ID) const;
  89
  90   /// Stack probing calls preserve different CSRs to the normal CC.
  91   const uint32_t *getWindowsStackProbePreservedMask() const;
  92
  93   BitVector getReservedRegs(const MachineFunction &MF) const override;
  94   bool isAsmClobberable(const MachineFunction &MF,
  95                        MCRegister PhysReg) const override;
  96   bool isConstantPhysReg(MCRegister PhysReg) const override;
  97   const TargetRegisterClass *
  98   getPointerRegClass(const MachineFunction &MF,
  99                      unsigned Kind = 0) const override;
 100   const TargetRegisterClass *
 101   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 102
 103   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 104   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 105   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 106
 107   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
 108   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
 109                           int64_t Offset) const override;
 110   Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
 111                                         int64_t Offset) const override;
 112   void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
 113                          int64_t Offset) const override;
 114   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 115                            unsigned FIOperandNum,
 116                            RegScavenger *RS = nullptr) const override;
 117   bool cannotEliminateFrame(const MachineFunction &MF) const;
 118
 119   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
 120   bool hasBasePointer(const MachineFunction &MF) const;
 121   unsigned getBaseRegister() const;
 122
 123   // Debug information queries.
 124   Register getFrameRegister(const MachineFunction &MF) const override;
 125
 126   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
 127                                MachineFunction &MF) const override;
 128
 129   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
 130   bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
 131
 132   /// SrcRC and DstRC will be morphed into NewRC if this returns true
 133   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
 134                       unsigned SubReg, const TargetRegisterClass *DstRC,
 135                       unsigned DstSubReg, const TargetRegisterClass *NewRC,
 136                       LiveIntervals &LIS) const override;
 137
 138   void getOffsetOpcodes(const StackOffset &Offset,
 139                         SmallVectorImpl<uint64_t> &Ops) const override;
 140 };
 141
 142 } // end namespace llvm
 143
 144 #endif