llvm/lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===------------------------------------------------------------===//
   8
   9 include "llvm/TableGen/SearchableTable.td"
  10 include "llvm/Target/Target.td"
  11 include "AMDGPUFeatures.td"
  12
  13 def p0 : PtrValueType<i64, 0>;
  14 def p1 : PtrValueType<i64, 1>;
  15 def p2 : PtrValueType<i32, 2>;
  16 def p3 : PtrValueType<i32, 3>;
  17 def p4 : PtrValueType<i64, 4>;
  18 def p5 : PtrValueType<i32, 5>;
  19 def p6 : PtrValueType<i32, 6>;
  20
  21
  22 class BoolToList<bit Value> {
  23   list<int> ret = !if(Value, [1]<int>, []<int>);
  24 }
  25
  26 //===------------------------------------------------------------===//
  27 // Subtarget Features (device properties)
  28 //===------------------------------------------------------------===//
  29
  30 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  31   "FastFMAF32",
  32   "true",
  33   "Assuming f32 fma is at least as fast as mul + add"
  34 >;
  35
  36 def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
  37   "FastDenormalF32",
  38   "true",
  39   "Enabling denormals does not cause f32 instructions to run at f64 rates"
  40 >;
  41
  42 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  43   "MIMG_R128",
  44   "true",
  45   "Support 128-bit texture resources"
  46 >;
  47
  48 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  49   "HalfRate64Ops",
  50   "true",
  51   "Most fp64 instructions are half rate instead of quarter"
  52 >;
  53
  54 def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
  55   "FullRate64Ops",
  56   "true",
  57   "Most fp64 instructions are full rate"
  58 >;
  59
  60 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  61   "FlatAddressSpace",
  62   "true",
  63   "Support flat address space"
  64 >;
  65
  66 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  67   "FlatInstOffsets",
  68   "true",
  69   "Flat instructions have immediate offset addressing mode"
  70 >;
  71
  72 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  73   "FlatGlobalInsts",
  74   "true",
  75   "Have global_* flat memory instructions"
  76 >;
  77
  78 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  79   "FlatScratchInsts",
  80   "true",
  81   "Have scratch_* flat memory instructions"
  82 >;
  83
  84 def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
  85   "ScalarFlatScratchInsts",
  86   "true",
  87   "Have s_scratch_* flat memory instructions"
  88 >;
  89
  90 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  91   "AddNoCarryInsts",
  92   "true",
  93   "Have VALU add/sub instructions without carry out"
  94 >;
  95
  96 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  97   "UnalignedBufferAccess",
  98   "true",
  99   "Hardware supports unaligned global loads and stores"
 100 >;
 101
 102 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
 103   "TrapHandler",
 104   "true",
 105   "Trap handler support"
 106 >;
 107
 108 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
 109   "UnalignedScratchAccess",
 110   "true",
 111   "Support unaligned scratch loads and stores"
 112 >;
 113
 114 def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
 115   "UnalignedDSAccess",
 116   "true",
 117   "Hardware supports unaligned local and region loads and stores"
 118 >;
 119
 120 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
 121   "HasApertureRegs",
 122   "true",
 123   "Has Memory Aperture Base and Size Registers"
 124 >;
 125
 126 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
 127   "HasMadMixInsts",
 128   "true",
 129   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
 130 >;
 131
 132 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
 133   "HasFmaMixInsts",
 134   "true",
 135   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 136 >;
 137
 138 def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
 139   "SupportsXNACK",
 140   "true",
 141   "Hardware supports XNACK"
 142 >;
 143
 144 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 145 // XNACK. The current default kernel driver setting is:
 146 // - graphics ring: XNACK disabled
 147 // - compute ring: XNACK enabled
 148 //
 149 // If XNACK is enabled, the VMEM latency can be worse.
 150 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 151 def FeatureXNACK : SubtargetFeature<"xnack",
 152   "EnableXNACK",
 153   "true",
 154   "Enable XNACK support"
 155 >;
 156
 157 def FeatureTgSplit : SubtargetFeature<"tgsplit",
 158   "EnableTgSplit",
 159   "true",
 160   "Enable threadgroup split execution"
 161 >;
 162
 163 def FeatureCuMode : SubtargetFeature<"cumode",
 164   "EnableCuMode",
 165   "true",
 166   "Enable CU wavefront execution mode"
 167 >;
 168
 169 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 170   "SGPRInitBug",
 171   "true",
 172   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 173 >;
 174
 175 def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
 176   "LDSMisalignedBug",
 177   "true",
 178   "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
 179 >;
 180
 181 def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
 182   "HasMFMAInlineLiteralBug",
 183   "true",
 184   "MFMA cannot use inline literal as SrcC"
 185 >;
 186
 187 def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
 188   "HasVcmpxPermlaneHazard",
 189   "true",
 190   "TODO: describe me"
 191 >;
 192
 193 def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
 194   "HasVMEMtoScalarWriteHazard",
 195   "true",
 196   "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
 197 >;
 198
 199 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
 200   "HasSMEMtoVectorWriteHazard",
 201   "true",
 202   "s_load_dword followed by v_cmp page faults"
 203 >;
 204
 205 def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
 206   "HasInstFwdPrefetchBug",
 207   "true",
 208   "S_INST_PREFETCH instruction causes shader to hang"
 209 >;
 210
 211 def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
 212   "HasVcmpxExecWARHazard",
 213   "true",
 214   "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
 215 >;
 216
 217 def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
 218   "HasLdsBranchVmemWARHazard",
 219   "true",
 220   "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
 221 >;
 222
 223 def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
 224   "HasNSAtoVMEMBug",
 225   "true",
 226   "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
 227 >;
 228
 229 def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
 230   "HasNSAClauseBug",
 231   "true",
 232   "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
 233 >;
 234
 235 def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
 236   "HasFlatSegmentOffsetBug",
 237   "true",
 238   "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
 239 >;
 240
 241 def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
 242   "NegativeScratchOffsetBug",
 243   "true",
 244   "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
 245 >;
 246
 247 def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
 248   "NegativeUnalignedScratchOffsetBug",
 249   "true",
 250   "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
 251 >;
 252
 253 def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
 254   "HasOffset3fBug",
 255   "true",
 256   "Branch offset of 3f hardware bug"
 257 >;
 258
 259 def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
 260   "HasImageStoreD16Bug",
 261   "true",
 262   "Image Store D16 hardware bug"
 263 >;
 264
 265 def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
 266   "HasImageGather4D16Bug",
 267   "true",
 268   "Image Gather4 D16 hardware bug"
 269 >;
 270
 271 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 272   "ldsbankcount"#Value,
 273   "LDSBankCount",
 274   !cast<string>(Value),
 275   "The number of LDS banks per compute unit."
 276 >;
 277
 278 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 279 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 280
 281 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 282   "GCN3Encoding",
 283   "true",
 284   "Encoding format for VI"
 285 >;
 286
 287 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 288   "CIInsts",
 289   "true",
 290   "Additional instructions for CI+"
 291 >;
 292
 293 def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
 294   "GFX8Insts",
 295   "true",
 296   "Additional instructions for GFX8+"
 297 >;
 298
 299 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 300   "GFX9Insts",
 301   "true",
 302   "Additional instructions for GFX9+"
 303 >;
 304
 305 def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
 306   "GFX90AInsts",
 307   "true",
 308   "Additional instructions for GFX90A+"
 309 >;
 310
 311 def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
 312   "GFX10Insts",
 313   "true",
 314   "Additional instructions for GFX10+"
 315 >;
 316
 317 def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
 318   "GFX10_3Insts",
 319   "true",
 320   "Additional instructions for GFX10.3"
 321 >;
 322
 323 def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
 324   "GFX7GFX8GFX9Insts",
 325   "true",
 326   "Instructions shared in GFX7, GFX8, GFX9"
 327 >;
 328
 329 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 330   "HasSMemRealTime",
 331   "true",
 332   "Has s_memrealtime instruction"
 333 >;
 334
 335 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 336   "HasInv2PiInlineImm",
 337   "true",
 338   "Has 1 / (2 * pi) as inline immediate"
 339 >;
 340
 341 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 342   "Has16BitInsts",
 343   "true",
 344   "Has i16/f16 instructions"
 345 >;
 346
 347 def FeatureVOP3P : SubtargetFeature<"vop3p",
 348   "HasVOP3PInsts",
 349   "true",
 350   "Has VOP3P packed instructions"
 351 >;
 352
 353 def FeatureMovrel : SubtargetFeature<"movrel",
 354   "HasMovrel",
 355   "true",
 356   "Has v_movrel*_b32 instructions"
 357 >;
 358
 359 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 360   "HasVGPRIndexMode",
 361   "true",
 362   "Has VGPR mode register indexing"
 363 >;
 364
 365 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 366   "HasScalarStores",
 367   "true",
 368   "Has store scalar memory instructions"
 369 >;
 370
 371 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 372   "HasScalarAtomics",
 373   "true",
 374   "Has atomic scalar memory instructions"
 375 >;
 376
 377 def FeatureSDWA : SubtargetFeature<"sdwa",
 378   "HasSDWA",
 379   "true",
 380   "Support SDWA (Sub-DWORD Addressing) extension"
 381 >;
 382
 383 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 384   "HasSDWAOmod",
 385   "true",
 386   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 387 >;
 388
 389 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 390   "HasSDWAScalar",
 391   "true",
 392   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 393 >;
 394
 395 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 396   "HasSDWASdst",
 397   "true",
 398   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 399 >;
 400
 401 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 402   "HasSDWAMac",
 403   "true",
 404   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 405 >;
 406
 407 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 408   "HasSDWAOutModsVOPC",
 409   "true",
 410   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 411 >;
 412
 413 def FeatureDPP : SubtargetFeature<"dpp",
 414   "HasDPP",
 415   "true",
 416   "Support DPP (Data Parallel Primitives) extension"
 417 >;
 418
 419 // DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
 420 def FeatureDPP8 : SubtargetFeature<"dpp8",
 421   "HasDPP8",
 422   "true",
 423   "Support DPP8 (Data Parallel Primitives) extension"
 424 >;
 425
 426 def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
 427   "Has64BitDPP",
 428   "true",
 429   "Support DPP (Data Parallel Primitives) extension"
 430 >;
 431
 432 def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
 433   "HasPackedFP32Ops",
 434   "true",
 435   "Support packed fp32 instructions"
 436 >;
 437
 438 def FeatureR128A16 : SubtargetFeature<"r128-a16",
 439   "HasR128A16",
 440   "true",
 441   "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
 442 >;
 443
 444 def FeatureGFX10A16 : SubtargetFeature<"a16",
 445   "HasGFX10A16",
 446   "true",
 447   "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
 448 >;
 449
 450 def FeatureG16 : SubtargetFeature<"g16",
 451   "HasG16",
 452   "true",
 453   "Support G16 for 16-bit gradient image operands"
 454 >;
 455
 456 def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
 457   "HasNSAEncoding",
 458   "true",
 459   "Support NSA encoding for image instructions"
 460 >;
 461
 462 def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
 463   "HasExtendedImageInsts",
 464   "true",
 465   "Support mips != 0, lod != 0, gather4, and get_lod"
 466 >;
 467
 468 def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
 469   "GFX10_AEncoding",
 470   "true",
 471   "Has BVH ray tracing instructions"
 472 >;
 473
 474 def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
 475   "GFX10_BEncoding",
 476   "true",
 477   "Encoding format GFX10_B"
 478 >;
 479
 480 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 481   "HasIntClamp",
 482   "true",
 483   "Support clamp for integer destination"
 484 >;
 485
 486 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 487   "HasUnpackedD16VMem",
 488   "true",
 489   "Has unpacked d16 vmem instructions"
 490 >;
 491
 492 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 493   "HasDLInsts",
 494   "true",
 495   "Has v_fmac_f32 and v_xnor_b32 instructions"
 496 >;
 497
 498 def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
 499   "HasDot1Insts",
 500   "true",
 501   "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
 502 >;
 503
 504 def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
 505   "HasDot2Insts",
 506   "true",
 507   "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
 508 >;
 509
 510 def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
 511   "HasDot3Insts",
 512   "true",
 513   "Has v_dot8c_i32_i4 instruction"
 514 >;
 515
 516 def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
 517   "HasDot4Insts",
 518   "true",
 519   "Has v_dot2c_i32_i16 instruction"
 520 >;
 521
 522 def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
 523   "HasDot5Insts",
 524   "true",
 525   "Has v_dot2c_f32_f16 instruction"
 526 >;
 527
 528 def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
 529   "HasDot6Insts",
 530   "true",
 531   "Has v_dot4c_i32_i8 instruction"
 532 >;
 533
 534 def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
 535   "HasDot7Insts",
 536   "true",
 537   "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
 538 >;
 539
 540 def FeatureMAIInsts : SubtargetFeature<"mai-insts",
 541   "HasMAIInsts",
 542   "true",
 543   "Has mAI instructions"
 544 >;
 545
 546 def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
 547   "HasPkFmacF16Inst",
 548   "true",
 549   "Has v_pk_fmac_f16 instruction"
 550 >;
 551
 552 def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
 553   "HasAtomicFaddInsts",
 554   "true",
 555   "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
 556   "global_atomic_pk_add_f16 instructions",
 557   [FeatureFlatGlobalInsts]
 558 >;
 559
 560 def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
 561   "SupportsSRAMECC",
 562   "true",
 563   "Hardware supports SRAMECC"
 564 >;
 565
 566 def FeatureSRAMECC : SubtargetFeature<"sramecc",
 567   "EnableSRAMECC",
 568   "true",
 569   "Enable SRAMECC"
 570 >;
 571
 572 def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
 573   "HasNoSdstCMPX",
 574   "true",
 575   "V_CMPX does not write VCC/SGPR in addition to EXEC"
 576 >;
 577
 578 def FeatureVscnt : SubtargetFeature<"vscnt",
 579   "HasVscnt",
 580   "true",
 581   "Has separate store vscnt counter"
 582 >;
 583
 584 def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
 585   "HasGetWaveIdInst",
 586   "true",
 587   "Has s_get_waveid_in_workgroup instruction"
 588 >;
 589
 590 def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
 591   "HasSMemTimeInst",
 592   "true",
 593   "Has s_memtime instruction"
 594 >;
 595
 596 def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
 597   "HasShaderCyclesRegister",
 598   "true",
 599   "Has SHADER_CYCLES hardware register"
 600 >;
 601
 602 def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
 603   "HasMadMacF32Insts",
 604   "true",
 605   "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
 606 >;
 607
 608 def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
 609   "HasDsSrc2Insts",
 610   "true",
 611   "Has ds_*_src2 instructions"
 612 >;
 613
 614 def FeatureRegisterBanking : SubtargetFeature<"register-banking",
 615   "HasRegisterBanking",
 616   "true",
 617   "Has register banking"
 618 >;
 619
 620 def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
 621   "HasVOP3Literal",
 622   "true",
 623   "Can use one literal in VOP3"
 624 >;
 625
 626 def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
 627   "HasNoDataDepHazard",
 628   "true",
 629   "Does not need SW waitstates"
 630 >;
 631
 632 class SubtargetFeatureNSAMaxSize <int Value> : SubtargetFeature <
 633   "nsa-max-size-"#Value,
 634   "NSAMaxSize",
 635   !cast<string>(Value),
 636   "The maximum non-sequential address size in VGPRs."
 637 >;
 638
 639 def FeatureNSAMaxSize5 : SubtargetFeatureNSAMaxSize<5>;
 640 def FeatureNSAMaxSize13 : SubtargetFeatureNSAMaxSize<13>;
 641
 642 //===------------------------------------------------------------===//
 643 // Subtarget Features (options and debugging)
 644 //===------------------------------------------------------------===//
 645
 646 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 647   "max-private-element-size-"#size,
 648   "MaxPrivateElementSize",
 649   !cast<string>(size),
 650   "Maximum private access size may be "#size
 651 >;
 652
 653 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 654 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 655 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 656
 657 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 658   "DumpCode",
 659   "true",
 660   "Dump MachineInstrs in the CodeEmitter"
 661 >;
 662
 663 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 664   "DumpCode",
 665   "true",
 666   "Dump MachineInstrs in the CodeEmitter"
 667 >;
 668
 669 // XXX - This should probably be removed once enabled by default
 670 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 671   "EnableLoadStoreOpt",
 672   "true",
 673   "Enable SI load/store optimizer pass"
 674 >;
 675
 676 // Performance debugging feature. Allow using DS instruction immediate
 677 // offsets even if the base pointer can't be proven to be base. On SI,
 678 // base pointer values that won't give the same result as a 16-bit add
 679 // are not safe to fold, but this will override the conservative test
 680 // for the base pointer.
 681 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 682   "unsafe-ds-offset-folding",
 683   "EnableUnsafeDSOffsetFolding",
 684   "true",
 685   "Force using DS instruction immediate offsets on SI"
 686 >;
 687
 688 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 689   "EnableSIScheduler",
 690   "true",
 691   "Enable SI Machine Scheduler"
 692 >;
 693
 694 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 695   "EnableDS128",
 696   "true",
 697   "Use ds_{read|write}_b128"
 698 >;
 699
 700 // Sparse texture support requires that all result registers are zeroed when
 701 // PRTStrictNull is set to true. This feature is turned on for all architectures
 702 // but is enabled as a feature in case there are situations where PRTStrictNull
 703 // is disabled by the driver.
 704 def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
 705   "EnablePRTStrictNull",
 706   "true",
 707   "Enable zeroing of result registers for sparse texture fetches"
 708 >;
 709
 710 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 711 // all OS-es on VI and newer hardware to avoid assertion failures due
 712 // to missing ADDR64 variants of MUBUF instructions.
 713 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 714 // instructions.
 715
 716 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 717   "FlatForGlobal",
 718   "true",
 719   "Force to generate flat instruction for global"
 720 >;
 721
 722 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 723   "auto-waitcnt-before-barrier",
 724   "AutoWaitcntBeforeBarrier",
 725   "true",
 726   "Hardware automatically inserts waitcnt before barrier"
 727 >;
 728
 729 def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
 730   "HasTrigReducedRange",
 731   "true",
 732   "Requires use of fract on arguments to trig instructions"
 733 >;
 734
 735 // Alignment enforcement is controlled by a configuration register:
 736 // SH_MEM_CONFIG.alignment_mode
 737 def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
 738   "UnalignedAccessMode",
 739   "true",
 740   "Enable unaligned global, local and region loads and stores if the hardware"
 741   " supports it"
 742 >;
 743
 744 def FeaturePackedTID : SubtargetFeature<"packed-tid",
 745   "HasPackedTID",
 746   "true",
 747   "Workitem IDs are packed into v0 at kernel launch"
 748 >;
 749
 750 def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
 751   "HasArchitectedFlatScratch",
 752   "true",
 753   "Flat Scratch register is a readonly SPI initialized architected register"
 754 >;
 755
 756 // Dummy feature used to disable assembler instructions.
 757 def FeatureDisable : SubtargetFeature<"",
 758   "FeatureDisable","true",
 759   "Dummy feature to disable assembler instructions"
 760 >;
 761
 762 class GCNSubtargetFeatureGeneration <string Value,
 763                                      string FeatureName,
 764                                      list<SubtargetFeature> Implies> :
 765         SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
 766
 767 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 768     "southern-islands",
 769   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 770   FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 771   FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
 772   FeatureTrigReducedRange, FeatureExtendedImageInsts
 773   ]
 774 >;
 775
 776 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 777     "sea-islands",
 778   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 779   FeatureWavefrontSize64, FeatureFlatAddressSpace,
 780   FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
 781   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 782   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
 783   ]
 784 >;
 785
 786 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 787   "volcanic-islands",
 788   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 789    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 790    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 791    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 792    FeatureScalarStores, FeatureInv2PiInlineImm,
 793    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 794    FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
 795    FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
 796    FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
 797    FeatureUnalignedBufferAccess
 798   ]
 799 >;
 800
 801 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 802   "gfx9",
 803   [FeatureFP64, FeatureLocalMemorySize65536,
 804    FeatureWavefrontSize64, FeatureFlatAddressSpace,
 805    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
 806    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 807    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 808    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 809    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 810    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 811    FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
 812    FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
 813    FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
 814    FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
 815    FeatureNegativeScratchOffsetBug
 816   ]
 817 >;
 818
 819 def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
 820   "gfx10",
 821   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 822    FeatureFlatAddressSpace,
 823    FeatureCIInsts, Feature16BitInsts,
 824    FeatureSMemRealTime, FeatureInv2PiInlineImm,
 825    FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
 826    FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 827    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 828    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 829    FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
 830    FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
 831    FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
 832    FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
 833    FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
 834    FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
 835   ]
 836 >;
 837
 838 class FeatureSet<list<SubtargetFeature> Features_> {
 839   list<SubtargetFeature> Features = Features_;
 840 }
 841
 842 def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
 843    FeatureFastFMAF32,
 844    HalfRate64Ops,
 845    FeatureLDSBankCount32]>;
 846
 847 def FeatureISAVersion6_0_1 : FeatureSet<
 848   [FeatureSouthernIslands,
 849    FeatureLDSBankCount32]>;
 850
 851 def FeatureISAVersion6_0_2 : FeatureSet<
 852   [FeatureSouthernIslands,
 853    FeatureLDSBankCount32]>;
 854
 855 def FeatureISAVersion7_0_0 : FeatureSet<
 856   [FeatureSeaIslands,
 857    FeatureLDSBankCount32]>;
 858
 859 def FeatureISAVersion7_0_1 : FeatureSet<
 860   [FeatureSeaIslands,
 861    HalfRate64Ops,
 862    FeatureLDSBankCount32,
 863    FeatureFastFMAF32]>;
 864
 865 def FeatureISAVersion7_0_2 : FeatureSet<
 866   [FeatureSeaIslands,
 867    FeatureLDSBankCount16,
 868    FeatureFastFMAF32]>;
 869
 870 def FeatureISAVersion7_0_3 : FeatureSet<
 871   [FeatureSeaIslands,
 872    FeatureLDSBankCount16]>;
 873
 874 def FeatureISAVersion7_0_4 : FeatureSet<
 875   [FeatureSeaIslands,
 876    FeatureLDSBankCount32]>;
 877
 878 def FeatureISAVersion7_0_5 : FeatureSet<
 879   [FeatureSeaIslands,
 880    FeatureLDSBankCount16]>;
 881
 882 def FeatureISAVersion8_0_1 : FeatureSet<
 883   [FeatureVolcanicIslands,
 884    FeatureFastFMAF32,
 885    HalfRate64Ops,
 886    FeatureLDSBankCount32,
 887    FeatureSupportsXNACK,
 888    FeatureUnpackedD16VMem]>;
 889
 890 def FeatureISAVersion8_0_2 : FeatureSet<
 891   [FeatureVolcanicIslands,
 892    FeatureLDSBankCount32,
 893    FeatureSGPRInitBug,
 894    FeatureUnpackedD16VMem]>;
 895
 896 def FeatureISAVersion8_0_3 : FeatureSet<
 897   [FeatureVolcanicIslands,
 898    FeatureLDSBankCount32,
 899    FeatureUnpackedD16VMem]>;
 900
 901 def FeatureISAVersion8_0_5 : FeatureSet<
 902   [FeatureVolcanicIslands,
 903    FeatureLDSBankCount32,
 904    FeatureSGPRInitBug,
 905    FeatureUnpackedD16VMem]>;
 906
 907 def FeatureISAVersion8_1_0 : FeatureSet<
 908   [FeatureVolcanicIslands,
 909    FeatureLDSBankCount16,
 910    FeatureSupportsXNACK,
 911    FeatureImageStoreD16Bug,
 912    FeatureImageGather4D16Bug]>;
 913
 914 def FeatureISAVersion9_0_0 : FeatureSet<
 915   [FeatureGFX9,
 916    FeatureMadMixInsts,
 917    FeatureLDSBankCount32,
 918    FeatureDsSrc2Insts,
 919    FeatureExtendedImageInsts,
 920    FeatureMadMacF32Insts,
 921    FeatureImageGather4D16Bug]>;
 922
 923 def FeatureISAVersion9_0_2 : FeatureSet<
 924   [FeatureGFX9,
 925    FeatureMadMixInsts,
 926    FeatureLDSBankCount32,
 927    FeatureDsSrc2Insts,
 928    FeatureExtendedImageInsts,
 929    FeatureMadMacF32Insts,
 930    FeatureImageGather4D16Bug]>;
 931
 932 def FeatureISAVersion9_0_4 : FeatureSet<
 933   [FeatureGFX9,
 934    FeatureLDSBankCount32,
 935    FeatureDsSrc2Insts,
 936    FeatureExtendedImageInsts,
 937    FeatureMadMacF32Insts,
 938    FeatureFmaMixInsts,
 939    FeatureImageGather4D16Bug]>;
 940
 941 def FeatureISAVersion9_0_6 : FeatureSet<
 942   [FeatureGFX9,
 943    HalfRate64Ops,
 944    FeatureFmaMixInsts,
 945    FeatureLDSBankCount32,
 946    FeatureDsSrc2Insts,
 947    FeatureExtendedImageInsts,
 948    FeatureMadMacF32Insts,
 949    FeatureDLInsts,
 950    FeatureDot1Insts,
 951    FeatureDot2Insts,
 952    FeatureDot7Insts,
 953    FeatureSupportsSRAMECC,
 954    FeatureImageGather4D16Bug]>;
 955
 956 def FeatureISAVersion9_0_8 : FeatureSet<
 957   [FeatureGFX9,
 958    HalfRate64Ops,
 959    FeatureFmaMixInsts,
 960    FeatureLDSBankCount32,
 961    FeatureDsSrc2Insts,
 962    FeatureExtendedImageInsts,
 963    FeatureMadMacF32Insts,
 964    FeatureDLInsts,
 965    FeatureDot1Insts,
 966    FeatureDot2Insts,
 967    FeatureDot3Insts,
 968    FeatureDot4Insts,
 969    FeatureDot5Insts,
 970    FeatureDot6Insts,
 971    FeatureDot7Insts,
 972    FeatureMAIInsts,
 973    FeaturePkFmacF16Inst,
 974    FeatureAtomicFaddInsts,
 975    FeatureSupportsSRAMECC,
 976    FeatureMFMAInlineLiteralBug,
 977    FeatureImageGather4D16Bug]>;
 978
 979 def FeatureISAVersion9_0_9 : FeatureSet<
 980   [FeatureGFX9,
 981    FeatureMadMixInsts,
 982    FeatureLDSBankCount32,
 983    FeatureDsSrc2Insts,
 984    FeatureExtendedImageInsts,
 985    FeatureMadMacF32Insts,
 986    FeatureImageGather4D16Bug]>;
 987
 988 def FeatureISAVersion9_0_A : FeatureSet<
 989   [FeatureGFX9,
 990    FeatureGFX90AInsts,
 991    FeatureFmaMixInsts,
 992    FeatureLDSBankCount32,
 993    FeatureDLInsts,
 994    FeatureDot1Insts,
 995    FeatureDot2Insts,
 996    FeatureDot3Insts,
 997    FeatureDot4Insts,
 998    FeatureDot5Insts,
 999    FeatureDot6Insts,
1000    FeatureDot7Insts,
1001    Feature64BitDPP,
1002    FeaturePackedFP32Ops,
1003    FeatureMAIInsts,
1004    FeaturePkFmacF16Inst,
1005    FeatureAtomicFaddInsts,
1006    FeatureMadMacF32Insts,
1007    FeatureSupportsSRAMECC,
1008    FeaturePackedTID,
1009    FullRate64Ops]>;
1010
1011 def FeatureISAVersion9_0_C : FeatureSet<
1012   [FeatureGFX9,
1013    FeatureMadMixInsts,
1014    FeatureLDSBankCount32,
1015    FeatureDsSrc2Insts,
1016    FeatureExtendedImageInsts,
1017    FeatureMadMacF32Insts,
1018    FeatureImageGather4D16Bug]>;
1019
1020 // TODO: Organize more features into groups.
1021 def FeatureGroup {
1022   // Bugs present on gfx10.1.
1023   list<SubtargetFeature> GFX10_1_Bugs = [
1024     FeatureVcmpxPermlaneHazard,
1025     FeatureVMEMtoScalarWriteHazard,
1026     FeatureSMEMtoVectorWriteHazard,
1027     FeatureInstFwdPrefetchBug,
1028     FeatureVcmpxExecWARHazard,
1029     FeatureLdsBranchVmemWARHazard,
1030     FeatureNSAtoVMEMBug,
1031     FeatureNSAClauseBug,
1032     FeatureOffset3fBug,
1033     FeatureFlatSegmentOffsetBug,
1034     FeatureNegativeUnalignedScratchOffsetBug
1035    ];
1036 }
1037
1038 def FeatureISAVersion10_1_0 : FeatureSet<
1039   !listconcat(FeatureGroup.GFX10_1_Bugs,
1040     [FeatureGFX10,
1041      FeatureLDSBankCount32,
1042      FeatureDLInsts,
1043      FeatureNSAEncoding,
1044      FeatureNSAMaxSize5,
1045      FeatureWavefrontSize32,
1046      FeatureScalarStores,
1047      FeatureScalarAtomics,
1048      FeatureScalarFlatScratchInsts,
1049      FeatureGetWaveIdInst,
1050      FeatureMadMacF32Insts,
1051      FeatureDsSrc2Insts,
1052      FeatureLdsMisalignedBug,
1053      FeatureSupportsXNACK])>;
1054
1055 def FeatureISAVersion10_1_1 : FeatureSet<
1056   !listconcat(FeatureGroup.GFX10_1_Bugs,
1057     [FeatureGFX10,
1058      FeatureLDSBankCount32,
1059      FeatureDLInsts,
1060      FeatureDot1Insts,
1061      FeatureDot2Insts,
1062      FeatureDot5Insts,
1063      FeatureDot6Insts,
1064      FeatureDot7Insts,
1065      FeatureNSAEncoding,
1066      FeatureNSAMaxSize5,
1067      FeatureWavefrontSize32,
1068      FeatureScalarStores,
1069      FeatureScalarAtomics,
1070      FeatureScalarFlatScratchInsts,
1071      FeatureGetWaveIdInst,
1072      FeatureMadMacF32Insts,
1073      FeatureDsSrc2Insts,
1074      FeatureLdsMisalignedBug,
1075      FeatureSupportsXNACK])>;
1076
1077 def FeatureISAVersion10_1_2 : FeatureSet<
1078   !listconcat(FeatureGroup.GFX10_1_Bugs,
1079     [FeatureGFX10,
1080      FeatureLDSBankCount32,
1081      FeatureDLInsts,
1082      FeatureDot1Insts,
1083      FeatureDot2Insts,
1084      FeatureDot5Insts,
1085      FeatureDot6Insts,
1086      FeatureDot7Insts,
1087      FeatureNSAEncoding,
1088      FeatureNSAMaxSize5,
1089      FeatureWavefrontSize32,
1090      FeatureScalarStores,
1091      FeatureScalarAtomics,
1092      FeatureScalarFlatScratchInsts,
1093      FeatureGetWaveIdInst,
1094      FeatureMadMacF32Insts,
1095      FeatureDsSrc2Insts,
1096      FeatureLdsMisalignedBug,
1097      FeatureSupportsXNACK])>;
1098
1099 def FeatureISAVersion10_1_3 : FeatureSet<
1100   !listconcat(FeatureGroup.GFX10_1_Bugs,
1101     [FeatureGFX10,
1102      FeatureGFX10_AEncoding,
1103      FeatureLDSBankCount32,
1104      FeatureDLInsts,
1105      FeatureNSAEncoding,
1106      FeatureNSAMaxSize5,
1107      FeatureWavefrontSize32,
1108      FeatureScalarStores,
1109      FeatureScalarAtomics,
1110      FeatureScalarFlatScratchInsts,
1111      FeatureGetWaveIdInst,
1112      FeatureMadMacF32Insts,
1113      FeatureDsSrc2Insts,
1114      FeatureLdsMisalignedBug,
1115      FeatureSupportsXNACK])>;
1116
1117 def FeatureISAVersion10_3_0 : FeatureSet<
1118   [FeatureGFX10,
1119    FeatureGFX10_AEncoding,
1120    FeatureGFX10_BEncoding,
1121    FeatureGFX10_3Insts,
1122    FeatureLDSBankCount32,
1123    FeatureDLInsts,
1124    FeatureDot1Insts,
1125    FeatureDot2Insts,
1126    FeatureDot5Insts,
1127    FeatureDot6Insts,
1128    FeatureDot7Insts,
1129    FeatureNSAEncoding,
1130    FeatureNSAMaxSize13,
1131    FeatureWavefrontSize32,
1132    FeatureShaderCyclesRegister]>;
1133
1134 //===----------------------------------------------------------------------===//
1135
1136 def AMDGPUInstrInfo : InstrInfo {
1137   let guessInstructionProperties = 1;
1138   let noNamedPositionallyEncodedOperands = 1;
1139 }
1140
1141 def AMDGPUAsmParser : AsmParser {
1142   // Some of the R600 registers have the same name, so this crashes.
1143   // For example T0_XYZW and T0_XY both have the asm name T0.
1144   let ShouldEmitMatchRegisterName = 0;
1145 }
1146
1147 def AMDGPUAsmWriter : AsmWriter {
1148   int PassSubtarget = 1;
1149 }
1150
1151 def AMDGPUAsmVariants {
1152   string Default = "Default";
1153   int Default_ID = 0;
1154   string VOP3 = "VOP3";
1155   int VOP3_ID = 1;
1156   string SDWA = "SDWA";
1157   int SDWA_ID = 2;
1158   string SDWA9 = "SDWA9";
1159   int SDWA9_ID = 3;
1160   string DPP = "DPP";
1161   int DPP_ID = 4;
1162   string Disable = "Disable";
1163   int Disable_ID = 5;
1164 }
1165
1166 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1167   let Variant = AMDGPUAsmVariants.Default_ID;
1168   let Name = AMDGPUAsmVariants.Default;
1169 }
1170
1171 def VOP3AsmParserVariant : AsmParserVariant {
1172   let Variant = AMDGPUAsmVariants.VOP3_ID;
1173   let Name = AMDGPUAsmVariants.VOP3;
1174 }
1175
1176 def SDWAAsmParserVariant : AsmParserVariant {
1177   let Variant = AMDGPUAsmVariants.SDWA_ID;
1178   let Name = AMDGPUAsmVariants.SDWA;
1179 }
1180
1181 def SDWA9AsmParserVariant : AsmParserVariant {
1182   let Variant = AMDGPUAsmVariants.SDWA9_ID;
1183   let Name = AMDGPUAsmVariants.SDWA9;
1184 }
1185
1186
1187 def DPPAsmParserVariant : AsmParserVariant {
1188   let Variant = AMDGPUAsmVariants.DPP_ID;
1189   let Name = AMDGPUAsmVariants.DPP;
1190 }
1191
1192 def AMDGPU : Target {
1193   // Pull in Instruction Info:
1194   let InstructionSet = AMDGPUInstrInfo;
1195   let AssemblyParsers = [AMDGPUAsmParser];
1196   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1197                                 VOP3AsmParserVariant,
1198                                 SDWAAsmParserVariant,
1199                                 SDWA9AsmParserVariant,
1200                                 DPPAsmParserVariant];
1201   let AssemblyWriters = [AMDGPUAsmWriter];
1202   let AllowRegisterRenaming = 1;
1203 }
1204
1205 // Dummy Instruction itineraries for pseudo instructions
1206 def ALU_NULL : FuncUnit;
1207 def NullALU : InstrItinClass;
1208
1209 //===----------------------------------------------------------------------===//
1210 // Predicate helper class
1211 //===----------------------------------------------------------------------===//
1212
1213 def isGFX6 :
1214   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1215   AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1216
1217 def isGFX6GFX7 :
1218   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1219             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1220   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1221
1222 def isGFX6GFX7GFX10 :
1223   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1224             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1225             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1226   AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1227
1228 def isGFX7Only :
1229   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1230   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1231
1232 def isGFX7GFX10 :
1233   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1234             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1235   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1236
1237 def isGFX7GFX8GFX9 :
1238   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1239             "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1240             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1241   AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1242
1243 def isGFX6GFX7GFX8GFX9 :
1244   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1245             "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1246             "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1247             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1248   AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1249
1250 def isGFX6GFX7GFX8GFX9NotGFX90A :
1251   Predicate<"!Subtarget->hasGFX90AInsts() &&"
1252             "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1253             " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1254             " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1255             " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1256   AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1257
1258 def isGFX7Plus :
1259   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1260   AssemblerPredicate<(all_of FeatureCIInsts)>;
1261
1262 def isGFX8Plus :
1263   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1264   AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1265
1266 def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1267                            "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1268   AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1269
1270 def isGFX9Plus :
1271   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1272   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1273
1274 def isGFX9Only : Predicate <
1275   "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1276   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1277
1278 def isGCN3ExcludingGFX90A :
1279   Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1280   AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1281
1282 def isGFX90APlus :
1283   Predicate<"Subtarget->hasGFX90AInsts()">,
1284   AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1285
1286 def isNotGFX90APlus :
1287   Predicate<"!Subtarget->hasGFX90AInsts()">,
1288   AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1289
1290 def isGFX8GFX9NotGFX90A :
1291   Predicate<"!Subtarget->hasGFX90AInsts() &&"
1292             "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1293             " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1294   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1295
1296 def isGFX90AOnly :
1297   Predicate<"Subtarget->hasGFX90AInsts()">,
1298   AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1299
1300 def isGFX908orGFX90A :
1301   Predicate<"Subtarget->hasMAIInsts()">,
1302   AssemblerPredicate<(all_of FeatureMAIInsts)>;
1303
1304 def isGFX8GFX9 :
1305   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1306             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1307   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1308
1309 def isGFX10Plus :
1310   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1311   AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1312
1313 def isGFX10Before1030 :
1314   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1315             "!Subtarget->hasGFX10_3Insts()">,
1316   AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1317
1318 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1319   AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1320
1321 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1322   AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1323 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1324   AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1325 def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1326   AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1327 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1328   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1329
1330 def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1331   AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1332
1333 def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1334   AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1335
1336 def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1337   AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1338
1339 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1340   AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1341 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1342   AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1343
1344 def D16PreservesUnusedBits :
1345   Predicate<"Subtarget->d16PreservesUnusedBits()">,
1346   AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1347
1348 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1349 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1350
1351 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1352   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1353
1354 def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1355   AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1356
1357 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1358   AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1359
1360 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1361
1362 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1363   AssemblerPredicate<(all_of Feature16BitInsts)>;
1364 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1365   AssemblerPredicate<(all_of FeatureVOP3P)>;
1366
1367 def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1368 def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1369
1370 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1371   AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1372
1373 def HasSDWA9 :
1374   Predicate<"Subtarget->hasSDWA()">,
1375   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1376
1377 def HasSDWA10 :
1378   Predicate<"Subtarget->hasSDWA()">,
1379   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1380
1381 def HasDPP : Predicate<"Subtarget->hasDPP()">,
1382   AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1383
1384 def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1385   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1386
1387 def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1388   AssemblerPredicate<(all_of Feature64BitDPP)>;
1389
1390 def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1391   AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1392
1393 def HasFmaakFmamkF32Insts :
1394   Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1395   AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1396
1397 def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1398   AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1399
1400 def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1401   AssemblerPredicate<(all_of FeatureR128A16)>;
1402
1403 def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1404   AssemblerPredicate<(all_of FeatureGFX10A16)>;
1405
1406 def HasG16 : Predicate<"Subtarget->hasG16()">,
1407   AssemblerPredicate<(all_of FeatureG16)>;
1408
1409 def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1410   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1411
1412 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1413   AssemblerPredicate<(all_of FeatureIntClamp)>;
1414
1415 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1416   AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1417
1418 def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1419   AssemblerPredicate<(all_of FeatureScalarStores)>;
1420
1421 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1422   AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1423
1424 def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1425   AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1426
1427 def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1428   AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1429
1430 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1431 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1432 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1433                       AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1434 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1435                 AssemblerPredicate<(all_of FeatureMovrel)>;
1436
1437 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1438   AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1439
1440 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1441   AssemblerPredicate<(all_of FeatureDLInsts)>;
1442
1443 def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1444   AssemblerPredicate<(all_of FeatureDot1Insts)>;
1445
1446 def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1447   AssemblerPredicate<(all_of FeatureDot2Insts)>;
1448
1449 def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1450   AssemblerPredicate<(all_of FeatureDot3Insts)>;
1451
1452 def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1453   AssemblerPredicate<(all_of FeatureDot4Insts)>;
1454
1455 def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1456   AssemblerPredicate<(all_of FeatureDot5Insts)>;
1457
1458 def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1459   AssemblerPredicate<(all_of FeatureDot6Insts)>;
1460
1461 def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1462   AssemblerPredicate<(all_of FeatureDot7Insts)>;
1463
1464 def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1465   AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1466
1467 def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1468   AssemblerPredicate<(all_of FeatureMAIInsts)>;
1469
1470 def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1471   AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1472
1473 def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1474   AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1475
1476 def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1477   AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1478
1479 def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1480   AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1481
1482 def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1483   AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1484
1485 def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1486   AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1487
1488 def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1489   AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1490
1491 def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1492   AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1493
1494 def EnableLateCFGStructurize : Predicate<
1495   "EnableLateStructurizeCFG">;
1496
1497 def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1498
1499 def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1500
1501 def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1502   AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1503
1504 // Include AMDGPU TD files
1505 include "SISchedule.td"
1506 include "GCNProcessors.td"
1507 include "AMDGPUInstrInfo.td"
1508 include "SIRegisterInfo.td"
1509 include "AMDGPURegisterBanks.td"
1510 include "AMDGPUInstructions.td"
1511 include "SIInstrInfo.td"
1512 include "AMDGPUCallingConv.td"
1513 include "AMDGPUSearchableTables.td"