[ORC] Add std::tuple support to SimplePackedSerialization.
[llvm-project.git] / llvm / lib / Target / AMDGPU / CMakeLists.txt
blob78f4f8fa874f159ff39cef99e124c509301be7ff
1 add_llvm_component_group(AMDGPU)
3 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
5 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
6 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
7 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
8 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
9 tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
10 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
11 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
12 tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
13 tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
14 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
15 tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
16 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
18 set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
19 tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
20 tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
21               -combiners="AMDGPUPreLegalizerCombinerHelper")
22 tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
23               -combiners="AMDGPUPostLegalizerCombinerHelper")
24 tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
25               -combiners="AMDGPURegBankCombinerHelper")
27 set(LLVM_TARGET_DEFINITIONS R600.td)
28 tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
29 tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
30 tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
31 tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
32 tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
33 tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
34 tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
35 tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
37 add_public_tablegen_target(AMDGPUCommonTableGen)
39 set(LLVM_TARGET_DEFINITIONS InstCombineTables.td)
40 tablegen(LLVM InstCombineTables.inc -gen-searchable-tables)
41 add_public_tablegen_target(InstCombineTableGen)
43 add_llvm_target(AMDGPUCodeGen
44   AMDGPUAliasAnalysis.cpp
45   AMDGPUAlwaysInlinePass.cpp
46   AMDGPUAnnotateKernelFeatures.cpp
47   AMDGPUAttributor.cpp
48   AMDGPUAnnotateUniformValues.cpp
49   AMDGPUArgumentUsageInfo.cpp
50   AMDGPUAsmPrinter.cpp
51   AMDGPUAtomicOptimizer.cpp
52   AMDGPUCallLowering.cpp
53   AMDGPUCodeGenPrepare.cpp
54   AMDGPUExportClustering.cpp
55   AMDGPUFixFunctionBitcasts.cpp
56   AMDGPUCtorDtorLowering.cpp
57   AMDGPUFrameLowering.cpp
58   AMDGPUHSAMetadataStreamer.cpp
59   AMDGPUInstCombineIntrinsic.cpp
60   AMDGPUInstrInfo.cpp
61   AMDGPUInstructionSelector.cpp
62   AMDGPUISelDAGToDAG.cpp
63   AMDGPUISelLowering.cpp
64   AMDGPUGlobalISelUtils.cpp
65   AMDGPULateCodeGenPrepare.cpp
66   AMDGPULegalizerInfo.cpp
67   AMDGPULibCalls.cpp
68   AMDGPULibFunc.cpp
69   AMDGPULowerIntrinsics.cpp
70   AMDGPULowerKernelArguments.cpp
71   AMDGPULowerKernelAttributes.cpp
72   AMDGPULowerModuleLDSPass.cpp
73   AMDGPUMachineCFGStructurizer.cpp
74   AMDGPUMachineFunction.cpp
75   AMDGPUMachineModuleInfo.cpp
76   AMDGPUMacroFusion.cpp
77   AMDGPUMCInstLower.cpp
78   AMDGPUMIRFormatter.cpp
79   AMDGPUOpenCLEnqueuedBlockLowering.cpp
80   AMDGPUPostLegalizerCombiner.cpp
81   AMDGPUPreLegalizerCombiner.cpp
82   AMDGPUPromoteAlloca.cpp
83   AMDGPUPropagateAttributes.cpp
84   AMDGPURegBankCombiner.cpp
85   AMDGPURegisterBankInfo.cpp
86   AMDGPUReplaceLDSUseWithPointer.cpp
87   AMDGPURewriteOutArguments.cpp
88   AMDGPUSubtarget.cpp
89   AMDGPUTargetMachine.cpp
90   AMDGPUTargetObjectFile.cpp
91   AMDGPUTargetTransformInfo.cpp
92   AMDGPUUnifyDivergentExitNodes.cpp
93   AMDGPUUnifyMetadata.cpp
94   AMDGPUPerfHintAnalysis.cpp
95   AMDILCFGStructurizer.cpp
96   AMDGPUPrintfRuntimeBinding.cpp
97   AMDGPUResourceUsageAnalysis.cpp
98   GCNHazardRecognizer.cpp
99   GCNIterativeScheduler.cpp
100   GCNMinRegStrategy.cpp
101   GCNRegPressure.cpp
102   GCNSchedStrategy.cpp
103   R600AsmPrinter.cpp
104   R600ClauseMergePass.cpp
105   R600ControlFlowFinalizer.cpp
106   R600EmitClauseMarkers.cpp
107   R600ExpandSpecialInstrs.cpp
108   R600FrameLowering.cpp
109   R600InstrInfo.cpp
110   R600ISelLowering.cpp
111   R600MachineFunctionInfo.cpp
112   R600MachineScheduler.cpp
113   R600OpenCLImageTypeLoweringPass.cpp
114   R600OptimizeVectorRegisters.cpp
115   R600Packetizer.cpp
116   R600RegisterInfo.cpp
117   SIAnnotateControlFlow.cpp
118   SIFixSGPRCopies.cpp
119   SIFixVGPRCopies.cpp
120   SIPreAllocateWWMRegs.cpp
121   SIFoldOperands.cpp
122   SIFormMemoryClauses.cpp
123   SIFrameLowering.cpp
124   SIInsertHardClauses.cpp
125   SILateBranchLowering.cpp
126   SIInsertWaitcnts.cpp
127   SIInstrInfo.cpp
128   SIISelLowering.cpp
129   SILoadStoreOptimizer.cpp
130   SILowerControlFlow.cpp
131   SILowerI1Copies.cpp
132   SILowerSGPRSpills.cpp
133   SIMachineFunctionInfo.cpp
134   SIMachineScheduler.cpp
135   SIMemoryLegalizer.cpp
136   SIOptimizeExecMasking.cpp
137   SIOptimizeExecMaskingPreRA.cpp
138   SIOptimizeVGPRLiveRange.cpp
139   SIPeepholeSDWA.cpp
140   SIPostRABundler.cpp
141   SIPreEmitPeephole.cpp
142   SIProgramInfo.cpp
143   SIRegisterInfo.cpp
144   SIShrinkInstructions.cpp
145   SIWholeQuadMode.cpp
146   GCNILPSched.cpp
147   GCNNSAReassign.cpp
148   GCNDPPCombine.cpp
149   GCNPreRAOptimizations.cpp
150   SIModeRegister.cpp
152   LINK_COMPONENTS
153   Analysis
154   AsmPrinter
155   CodeGen
156   Core
157   IPO
158   MC
159   Passes
160   AMDGPUDesc
161   AMDGPUInfo
162   AMDGPUUtils
163   Scalar
164   SelectionDAG
165   Support
166   Target
167   TransformUtils
168   Vectorize
169   GlobalISel
170   BinaryFormat
171   MIRParser
173   ADD_TO_COMPONENT
174   AMDGPU
175   )
177 add_subdirectory(AsmParser)
178 add_subdirectory(Disassembler)
179 add_subdirectory(MCA)
180 add_subdirectory(MCTargetDesc)
181 add_subdirectory(TargetInfo)
182 add_subdirectory(Utils)