llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

   1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 ///
  11 /// This file contains declaration for AMDGPU ISA disassembler
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
  16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
  17
  18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/Support/DataExtractor.h"
  21 #include <memory>
  22
  23 namespace llvm {
  24
  25 class MCInst;
  26 class MCOperand;
  27 class MCSubtargetInfo;
  28 class Twine;
  29
  30 //===----------------------------------------------------------------------===//
  31 // AMDGPUDisassembler
  32 //===----------------------------------------------------------------------===//
  33
  34 class AMDGPUDisassembler : public MCDisassembler {
  35 private:
  36   std::unique_ptr<MCInstrInfo const> const MCII;
  37   const MCRegisterInfo &MRI;
  38   const unsigned TargetMaxInstBytes;
  39   mutable ArrayRef<uint8_t> Bytes;
  40   mutable uint32_t Literal;
  41   mutable bool HasLiteral;
  42
  43 public:
  44   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  45                      MCInstrInfo const *MCII);
  46   ~AMDGPUDisassembler() override = default;
  47
  48   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
  49                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  50                               raw_ostream &CS) const override;
  51
  52   const char* getRegClassName(unsigned RegClassID) const;
  53
  54   MCOperand createRegOperand(unsigned int RegId) const;
  55   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
  56   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
  57
  58   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
  59
  60   DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
  61                              uint64_t Address) const;
  62
  63   Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
  64                                        ArrayRef<uint8_t> Bytes,
  65                                        uint64_t Address,
  66                                        raw_ostream &CStream) const override;
  67
  68   DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef<uint8_t> Bytes,
  69                                       uint64_t KdAddress) const;
  70
  71   DecodeStatus
  72   decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
  73                                   ArrayRef<uint8_t> Bytes,
  74                                   raw_string_ostream &KdStream) const;
  75
  76   /// Decode as directives that handle COMPUTE_PGM_RSRC1.
  77   /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
  78   /// \param KdStream       - Stream to write the disassembled directives to.
  79   // NOLINTNEXTLINE(readability-identifier-naming)
  80   DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
  81                                        raw_string_ostream &KdStream) const;
  82
  83   /// Decode as directives that handle COMPUTE_PGM_RSRC2.
  84   /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
  85   /// \param KdStream       - Stream to write the disassembled directives to.
  86   // NOLINTNEXTLINE(readability-identifier-naming)
  87   DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
  88                                        raw_string_ostream &KdStream) const;
  89
  90   DecodeStatus convertSDWAInst(MCInst &MI) const;
  91   DecodeStatus convertDPP8Inst(MCInst &MI) const;
  92   DecodeStatus convertMIMGInst(MCInst &MI) const;
  93
  94   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
  95   MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
  96
  97   MCOperand decodeOperand_VS_32(unsigned Val) const;
  98   MCOperand decodeOperand_VS_64(unsigned Val) const;
  99   MCOperand decodeOperand_VS_128(unsigned Val) const;
 100   MCOperand decodeOperand_VSrc16(unsigned Val) const;
 101   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
 102   MCOperand decodeOperand_VSrcV232(unsigned Val) const;
 103
 104   MCOperand decodeOperand_VReg_64(unsigned Val) const;
 105   MCOperand decodeOperand_VReg_96(unsigned Val) const;
 106   MCOperand decodeOperand_VReg_128(unsigned Val) const;
 107   MCOperand decodeOperand_VReg_256(unsigned Val) const;
 108   MCOperand decodeOperand_VReg_512(unsigned Val) const;
 109   MCOperand decodeOperand_VReg_1024(unsigned Val) const;
 110
 111   MCOperand decodeOperand_SReg_32(unsigned Val) const;
 112   MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
 113   MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
 114   MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
 115   MCOperand decodeOperand_SReg_64(unsigned Val) const;
 116   MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
 117   MCOperand decodeOperand_SReg_128(unsigned Val) const;
 118   MCOperand decodeOperand_SReg_256(unsigned Val) const;
 119   MCOperand decodeOperand_SReg_512(unsigned Val) const;
 120
 121   MCOperand decodeOperand_AGPR_32(unsigned Val) const;
 122   MCOperand decodeOperand_AReg_64(unsigned Val) const;
 123   MCOperand decodeOperand_AReg_128(unsigned Val) const;
 124   MCOperand decodeOperand_AReg_256(unsigned Val) const;
 125   MCOperand decodeOperand_AReg_512(unsigned Val) const;
 126   MCOperand decodeOperand_AReg_1024(unsigned Val) const;
 127   MCOperand decodeOperand_AV_32(unsigned Val) const;
 128   MCOperand decodeOperand_AV_64(unsigned Val) const;
 129
 130   enum OpWidthTy {
 131     OPW32,
 132     OPW64,
 133     OPW96,
 134     OPW128,
 135     OPW160,
 136     OPW256,
 137     OPW512,
 138     OPW1024,
 139     OPW16,
 140     OPWV216,
 141     OPWV232,
 142     OPW_LAST_,
 143     OPW_FIRST_ = OPW32
 144   };
 145
 146   unsigned getVgprClassId(const OpWidthTy Width) const;
 147   unsigned getAgprClassId(const OpWidthTy Width) const;
 148   unsigned getSgprClassId(const OpWidthTy Width) const;
 149   unsigned getTtmpClassId(const OpWidthTy Width) const;
 150
 151   static MCOperand decodeIntImmed(unsigned Imm);
 152   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
 153   MCOperand decodeLiteralConstant() const;
 154
 155   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
 156   MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
 157   MCOperand decodeSpecialReg32(unsigned Val) const;
 158   MCOperand decodeSpecialReg64(unsigned Val) const;
 159
 160   MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
 161   MCOperand decodeSDWASrc16(unsigned Val) const;
 162   MCOperand decodeSDWASrc32(unsigned Val) const;
 163   MCOperand decodeSDWAVopcDst(unsigned Val) const;
 164
 165   MCOperand decodeBoolReg(unsigned Val) const;
 166
 167   int getTTmpIdx(unsigned Val) const;
 168
 169   const MCInstrInfo *getMCII() const { return MCII.get(); }
 170
 171   bool isVI() const;
 172   bool isGFX9() const;
 173   bool isGFX90A() const;
 174   bool isGFX9Plus() const;
 175   bool isGFX10() const;
 176   bool isGFX10Plus() const;
 177
 178   bool hasArchitectedFlatScratch() const;
 179 };
 180
 181 //===----------------------------------------------------------------------===//
 182 // AMDGPUSymbolizer
 183 //===----------------------------------------------------------------------===//
 184
 185 class AMDGPUSymbolizer : public MCSymbolizer {
 186 private:
 187   void *DisInfo;
 188   std::vector<uint64_t> ReferencedAddresses;
 189
 190 public:
 191   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
 192                    void *disInfo)
 193                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
 194
 195   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
 196                                 int64_t Value, uint64_t Address,
 197                                 bool IsBranch, uint64_t Offset,
 198                                 uint64_t InstSize) override;
 199
 200   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
 201                                        int64_t Value,
 202                                        uint64_t Address) override;
 203
 204   ArrayRef<uint64_t> getReferencedAddresses() const override {
 205     return ReferencedAddresses;
 206   }
 207 };
 208
 209 } // end namespace llvm
 210
 211 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H