llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

   1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 // \file
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "AMDGPUInstPrinter.h"
  11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  12 #include "SIDefines.h"
  13 #include "SIRegisterInfo.h"
  14 #include "Utils/AMDGPUAsmUtils.h"
  15 #include "Utils/AMDGPUBaseInfo.h"
  16 #include "llvm/MC/MCExpr.h"
  17 #include "llvm/MC/MCInst.h"
  18 #include "llvm/MC/MCInstrDesc.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/CommandLine.h"
  22 #include "llvm/Support/TargetParser.h"
  23
  24 using namespace llvm;
  25 using namespace llvm::AMDGPU;
  26
  27 static cl::opt<bool> Keep16BitSuffixes(
  28   "amdgpu-keep-16-bit-reg-suffixes",
  29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
  30   cl::init(false),
  31   cl::ReallyHidden);
  32
  33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
  34   // FIXME: The current implementation of
  35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
  36   // as an integer or we provide a name which represents a physical register.
  37   // For CFI instructions we really want to emit a name for the DWARF register
  38   // instead, because there may be multiple DWARF registers corresponding to a
  39   // single physical register. One case where this problem manifests is with
  40   // wave32/wave64 where using the physical register name is ambiguous: if we
  41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
  42   // size which we need to encode the register in the final DWARF. Ideally we
  43   // would extend MC to support parsing DWARF register names so we could do
  44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
  45   // non-pretty DWARF register names in assembly text.
  46   OS << RegNo;
  47 }
  48
  49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
  50                                   StringRef Annot, const MCSubtargetInfo &STI,
  51                                   raw_ostream &OS) {
  52   OS.flush();
  53   printInstruction(MI, Address, STI, OS);
  54   printAnnotation(OS, Annot);
  55 }
  56
  57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
  58                                           const MCSubtargetInfo &STI,
  59                                           raw_ostream &O) {
  60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
  61 }
  62
  63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
  64                                           raw_ostream &O) {
  65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
  66 }
  67
  68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
  69                                            const MCSubtargetInfo &STI,
  70                                            raw_ostream &O) {
  71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
  72   // with ignored high bits. Print as 32-bit anyway in that case.
  73   int64_t Imm = MI->getOperand(OpNo).getImm();
  74   if (isInt<16>(Imm) || isUInt<16>(Imm))
  75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
  76   else
  77     printU32ImmOperand(MI, OpNo, STI, O);
  78 }
  79
  80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
  81                                              raw_ostream &O) {
  82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
  83 }
  84
  85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
  86                                              raw_ostream &O) {
  87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
  88 }
  89
  90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
  91                                               raw_ostream &O) {
  92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
  93 }
  94
  95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
  96                                            const MCSubtargetInfo &STI,
  97                                            raw_ostream &O) {
  98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
  99 }
 100
 101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
 102                                       raw_ostream &O, StringRef BitName) {
 103   if (MI->getOperand(OpNo).getImm()) {
 104     O << ' ' << BitName;
 105   }
 106 }
 107
 108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
 109                                    raw_ostream &O) {
 110   printNamedBit(MI, OpNo, O, "offen");
 111 }
 112
 113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
 114                                    raw_ostream &O) {
 115   printNamedBit(MI, OpNo, O, "idxen");
 116 }
 117
 118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
 119                                     raw_ostream &O) {
 120   printNamedBit(MI, OpNo, O, "addr64");
 121 }
 122
 123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
 124                                         raw_ostream &O) {
 125   if (MI->getOperand(OpNo).getImm()) {
 126     O << " offset:";
 127     printU16ImmDecOperand(MI, OpNo, O);
 128   }
 129 }
 130
 131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
 132                                     const MCSubtargetInfo &STI,
 133                                     raw_ostream &O) {
 134   uint16_t Imm = MI->getOperand(OpNo).getImm();
 135   if (Imm != 0) {
 136     O << " offset:";
 137     printU16ImmDecOperand(MI, OpNo, O);
 138   }
 139 }
 140
 141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
 142                                         const MCSubtargetInfo &STI,
 143                                         raw_ostream &O) {
 144   uint16_t Imm = MI->getOperand(OpNo).getImm();
 145   if (Imm != 0) {
 146     O << " offset:";
 147
 148     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
 149     bool IsFlatSeg = !(Desc.TSFlags &
 150                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
 151
 152     if (IsFlatSeg) { // Unsigned offset
 153       printU16ImmDecOperand(MI, OpNo, O);
 154     } else {         // Signed offset
 155       if (AMDGPU::isGFX10Plus(STI)) {
 156         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
 157       } else {
 158         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
 159       }
 160     }
 161   }
 162 }
 163
 164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
 165                                      const MCSubtargetInfo &STI,
 166                                      raw_ostream &O) {
 167   if (MI->getOperand(OpNo).getImm()) {
 168     O << " offset0:";
 169     printU8ImmDecOperand(MI, OpNo, O);
 170   }
 171 }
 172
 173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
 174                                      const MCSubtargetInfo &STI,
 175                                      raw_ostream &O) {
 176   if (MI->getOperand(OpNo).getImm()) {
 177     O << " offset1:";
 178     printU8ImmDecOperand(MI, OpNo, O);
 179   }
 180 }
 181
 182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
 183                                         const MCSubtargetInfo &STI,
 184                                         raw_ostream &O) {
 185   printU32ImmOperand(MI, OpNo, STI, O);
 186 }
 187
 188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
 189                                         const MCSubtargetInfo &STI,
 190                                         raw_ostream &O) {
 191   O << formatHex(MI->getOperand(OpNo).getImm());
 192 }
 193
 194 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
 195                                                const MCSubtargetInfo &STI,
 196                                                raw_ostream &O) {
 197   printU32ImmOperand(MI, OpNo, STI, O);
 198 }
 199
 200 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
 201                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 202   printNamedBit(MI, OpNo, O, "gds");
 203 }
 204
 205 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
 206                                   const MCSubtargetInfo &STI, raw_ostream &O) {
 207   auto Imm = MI->getOperand(OpNo).getImm();
 208   if (Imm & CPol::GLC)
 209     O << " glc";
 210   if (Imm & CPol::SLC)
 211     O << " slc";
 212   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
 213     O << " dlc";
 214   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
 215     O << " scc";
 216   if (Imm & ~CPol::ALL)
 217     O << " /* unexpected cache policy bit */";
 218 }
 219
 220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
 221                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 222 }
 223
 224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
 225                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 226   printNamedBit(MI, OpNo, O, "tfe");
 227 }
 228
 229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
 230                                    const MCSubtargetInfo &STI, raw_ostream &O) {
 231   if (MI->getOperand(OpNo).getImm()) {
 232     O << " dmask:";
 233     printU16ImmOperand(MI, OpNo, STI, O);
 234   }
 235 }
 236
 237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
 238                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 239   unsigned Dim = MI->getOperand(OpNo).getImm();
 240   O << " dim:SQ_RSRC_IMG_";
 241
 242   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
 243   if (DimInfo)
 244     O << DimInfo->AsmSuffix;
 245   else
 246     O << Dim;
 247 }
 248
 249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
 250                                    const MCSubtargetInfo &STI, raw_ostream &O) {
 251   printNamedBit(MI, OpNo, O, "unorm");
 252 }
 253
 254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
 255                                 const MCSubtargetInfo &STI, raw_ostream &O) {
 256   printNamedBit(MI, OpNo, O, "da");
 257 }
 258
 259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
 260                                   const MCSubtargetInfo &STI, raw_ostream &O) {
 261   if (STI.hasFeature(AMDGPU::FeatureR128A16))
 262     printNamedBit(MI, OpNo, O, "a16");
 263   else
 264     printNamedBit(MI, OpNo, O, "r128");
 265 }
 266
 267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
 268                                   const MCSubtargetInfo &STI, raw_ostream &O) {
 269   printNamedBit(MI, OpNo, O, "a16");
 270 }
 271
 272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
 273                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 274   printNamedBit(MI, OpNo, O, "lwe");
 275 }
 276
 277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
 278                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 279   printNamedBit(MI, OpNo, O, "d16");
 280 }
 281
 282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
 283                                       const MCSubtargetInfo &STI,
 284                                       raw_ostream &O) {
 285   printNamedBit(MI, OpNo, O, "compr");
 286 }
 287
 288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
 289                                    const MCSubtargetInfo &STI,
 290                                    raw_ostream &O) {
 291   printNamedBit(MI, OpNo, O, "vm");
 292 }
 293
 294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
 295                                     const MCSubtargetInfo &STI,
 296                                     raw_ostream &O) {
 297 }
 298
 299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
 300                                             const MCSubtargetInfo &STI,
 301                                             raw_ostream &O) {
 302   using namespace llvm::AMDGPU::MTBUFFormat;
 303
 304   int OpNo =
 305     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
 306   assert(OpNo != -1);
 307
 308   unsigned Val = MI->getOperand(OpNo).getImm();
 309   if (AMDGPU::isGFX10Plus(STI)) {
 310     if (Val == UFMT_DEFAULT)
 311       return;
 312     if (isValidUnifiedFormat(Val)) {
 313       O << " format:[" << getUnifiedFormatName(Val) << ']';
 314     } else {
 315       O << " format:" << Val;
 316     }
 317   } else {
 318     if (Val == DFMT_NFMT_DEFAULT)
 319       return;
 320     if (isValidDfmtNfmt(Val, STI)) {
 321       unsigned Dfmt;
 322       unsigned Nfmt;
 323       decodeDfmtNfmt(Val, Dfmt, Nfmt);
 324       O << " format:[";
 325       if (Dfmt != DFMT_DEFAULT) {
 326         O << getDfmtName(Dfmt);
 327         if (Nfmt != NFMT_DEFAULT) {
 328           O << ',';
 329         }
 330       }
 331       if (Nfmt != NFMT_DEFAULT) {
 332         O << getNfmtName(Nfmt, STI);
 333       }
 334       O << ']';
 335     } else {
 336       O << " format:" << Val;
 337     }
 338   }
 339 }
 340
 341 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
 342                                         const MCRegisterInfo &MRI) {
 343 #if !defined(NDEBUG)
 344   switch (RegNo) {
 345   case AMDGPU::FP_REG:
 346   case AMDGPU::SP_REG:
 347   case AMDGPU::PRIVATE_RSRC_REG:
 348     llvm_unreachable("pseudo-register should not ever be emitted");
 349   case AMDGPU::SCC:
 350     llvm_unreachable("pseudo scc should not ever be emitted");
 351   default:
 352     break;
 353   }
 354 #endif
 355
 356   StringRef RegName(getRegisterName(RegNo));
 357   if (!Keep16BitSuffixes)
 358     if (!RegName.consume_back(".l"))
 359       RegName.consume_back(".h");
 360
 361   O << RegName;
 362 }
 363
 364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
 365                                     const MCSubtargetInfo &STI,
 366                                     raw_ostream &O) {
 367   auto Opcode = MI->getOpcode();
 368   auto Flags = MII.get(Opcode).TSFlags;
 369
 370   if (OpNo == 0) {
 371     if (Flags & SIInstrFlags::VOP3) {
 372       if (!getVOP3IsSingle(Opcode))
 373         O << "_e64";
 374     } else if (Flags & SIInstrFlags::DPP) {
 375       O << "_dpp";
 376     } else if (Flags & SIInstrFlags::SDWA) {
 377       O << "_sdwa";
 378     } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
 379                ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
 380       O << "_e32";
 381     }
 382     O << " ";
 383   }
 384
 385   printOperand(MI, OpNo, STI, O);
 386
 387   // Print default vcc/vcc_lo operand.
 388   switch (Opcode) {
 389   default: break;
 390
 391   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
 392   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
 393   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
 394   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
 395   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
 396   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
 397   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
 398   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
 399   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
 400   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
 401   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
 402   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
 403     printDefaultVccOperand(1, STI, O);
 404     break;
 405   }
 406 }
 407
 408 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
 409                                        const MCSubtargetInfo &STI, raw_ostream &O) {
 410   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
 411     O << " ";
 412   else
 413     O << "_e32 ";
 414
 415   printOperand(MI, OpNo, STI, O);
 416 }
 417
 418 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
 419                                             const MCSubtargetInfo &STI,
 420                                             raw_ostream &O) {
 421   int16_t SImm = static_cast<int16_t>(Imm);
 422   if (isInlinableIntLiteral(SImm)) {
 423     O << SImm;
 424   } else {
 425     uint64_t Imm16 = static_cast<uint16_t>(Imm);
 426     O << formatHex(Imm16);
 427   }
 428 }
 429
 430 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
 431                                          const MCSubtargetInfo &STI,
 432                                          raw_ostream &O) {
 433   int16_t SImm = static_cast<int16_t>(Imm);
 434   if (isInlinableIntLiteral(SImm)) {
 435     O << SImm;
 436     return;
 437   }
 438
 439   if (Imm == 0x3C00)
 440     O<< "1.0";
 441   else if (Imm == 0xBC00)
 442     O<< "-1.0";
 443   else if (Imm == 0x3800)
 444     O<< "0.5";
 445   else if (Imm == 0xB800)
 446     O<< "-0.5";
 447   else if (Imm == 0x4000)
 448     O<< "2.0";
 449   else if (Imm == 0xC000)
 450     O<< "-2.0";
 451   else if (Imm == 0x4400)
 452     O<< "4.0";
 453   else if (Imm == 0xC400)
 454     O<< "-4.0";
 455   else if (Imm == 0x3118 &&
 456            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
 457     O << "0.15915494";
 458   } else {
 459     uint64_t Imm16 = static_cast<uint16_t>(Imm);
 460     O << formatHex(Imm16);
 461   }
 462 }
 463
 464 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
 465                                            const MCSubtargetInfo &STI,
 466                                            raw_ostream &O) {
 467   uint16_t Lo16 = static_cast<uint16_t>(Imm);
 468   printImmediate16(Lo16, STI, O);
 469 }
 470
 471 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
 472                                          const MCSubtargetInfo &STI,
 473                                          raw_ostream &O) {
 474   int32_t SImm = static_cast<int32_t>(Imm);
 475   if (SImm >= -16 && SImm <= 64) {
 476     O << SImm;
 477     return;
 478   }
 479
 480   if (Imm == FloatToBits(0.0f))
 481     O << "0.0";
 482   else if (Imm == FloatToBits(1.0f))
 483     O << "1.0";
 484   else if (Imm == FloatToBits(-1.0f))
 485     O << "-1.0";
 486   else if (Imm == FloatToBits(0.5f))
 487     O << "0.5";
 488   else if (Imm == FloatToBits(-0.5f))
 489     O << "-0.5";
 490   else if (Imm == FloatToBits(2.0f))
 491     O << "2.0";
 492   else if (Imm == FloatToBits(-2.0f))
 493     O << "-2.0";
 494   else if (Imm == FloatToBits(4.0f))
 495     O << "4.0";
 496   else if (Imm == FloatToBits(-4.0f))
 497     O << "-4.0";
 498   else if (Imm == 0x3e22f983 &&
 499            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
 500     O << "0.15915494";
 501   else
 502     O << formatHex(static_cast<uint64_t>(Imm));
 503 }
 504
 505 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
 506                                          const MCSubtargetInfo &STI,
 507                                          raw_ostream &O) {
 508   int64_t SImm = static_cast<int64_t>(Imm);
 509   if (SImm >= -16 && SImm <= 64) {
 510     O << SImm;
 511     return;
 512   }
 513
 514   if (Imm == DoubleToBits(0.0))
 515     O << "0.0";
 516   else if (Imm == DoubleToBits(1.0))
 517     O << "1.0";
 518   else if (Imm == DoubleToBits(-1.0))
 519     O << "-1.0";
 520   else if (Imm == DoubleToBits(0.5))
 521     O << "0.5";
 522   else if (Imm == DoubleToBits(-0.5))
 523     O << "-0.5";
 524   else if (Imm == DoubleToBits(2.0))
 525     O << "2.0";
 526   else if (Imm == DoubleToBits(-2.0))
 527     O << "-2.0";
 528   else if (Imm == DoubleToBits(4.0))
 529     O << "4.0";
 530   else if (Imm == DoubleToBits(-4.0))
 531     O << "-4.0";
 532   else if (Imm == 0x3fc45f306dc9c882 &&
 533            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
 534     O << "0.15915494309189532";
 535   else {
 536     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
 537
 538     // In rare situations, we will have a 32-bit literal in a 64-bit
 539     // operand. This is technically allowed for the encoding of s_mov_b64.
 540     O << formatHex(static_cast<uint64_t>(Imm));
 541   }
 542 }
 543
 544 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
 545                                   const MCSubtargetInfo &STI,
 546                                   raw_ostream &O) {
 547   unsigned Imm = MI->getOperand(OpNo).getImm();
 548   if (!Imm)
 549     return;
 550
 551   O << " blgp:" << Imm;
 552 }
 553
 554 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
 555                                   const MCSubtargetInfo &STI,
 556                                   raw_ostream &O) {
 557   unsigned Imm = MI->getOperand(OpNo).getImm();
 558   if (!Imm)
 559     return;
 560
 561   O << " cbsz:" << Imm;
 562 }
 563
 564 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
 565                                   const MCSubtargetInfo &STI,
 566                                   raw_ostream &O) {
 567   unsigned Imm = MI->getOperand(OpNo).getImm();
 568   if (!Imm)
 569     return;
 570
 571   O << " abid:" << Imm;
 572 }
 573
 574 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
 575                                                const MCSubtargetInfo &STI,
 576                                                raw_ostream &O) {
 577   if (OpNo > 0)
 578     O << ", ";
 579   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
 580                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
 581   if (OpNo == 0)
 582     O << ", ";
 583 }
 584
 585 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 586                                      const MCSubtargetInfo &STI,
 587                                      raw_ostream &O) {
 588   // Print default vcc/vcc_lo operand of VOPC.
 589   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
 590   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
 591       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
 592        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
 593     printDefaultVccOperand(OpNo, STI, O);
 594
 595   if (OpNo >= MI->getNumOperands()) {
 596     O << "/*Missing OP" << OpNo << "*/";
 597     return;
 598   }
 599
 600   const MCOperand &Op = MI->getOperand(OpNo);
 601   if (Op.isReg()) {
 602     printRegOperand(Op.getReg(), O, MRI);
 603   } else if (Op.isImm()) {
 604     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
 605     switch (OpTy) {
 606     case AMDGPU::OPERAND_REG_IMM_INT32:
 607     case AMDGPU::OPERAND_REG_IMM_FP32:
 608     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
 609     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
 610     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
 611     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
 612     case AMDGPU::OPERAND_REG_IMM_V2INT32:
 613     case AMDGPU::OPERAND_REG_IMM_V2FP32:
 614     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
 615     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
 616     case MCOI::OPERAND_IMMEDIATE:
 617       printImmediate32(Op.getImm(), STI, O);
 618       break;
 619     case AMDGPU::OPERAND_REG_IMM_INT64:
 620     case AMDGPU::OPERAND_REG_IMM_FP64:
 621     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
 622     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
 623     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
 624       printImmediate64(Op.getImm(), STI, O);
 625       break;
 626     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
 627     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
 628     case AMDGPU::OPERAND_REG_IMM_INT16:
 629       printImmediateInt16(Op.getImm(), STI, O);
 630       break;
 631     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
 632     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
 633     case AMDGPU::OPERAND_REG_IMM_FP16:
 634       printImmediate16(Op.getImm(), STI, O);
 635       break;
 636     case AMDGPU::OPERAND_REG_IMM_V2INT16:
 637     case AMDGPU::OPERAND_REG_IMM_V2FP16:
 638       if (!isUInt<16>(Op.getImm()) &&
 639           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
 640         printImmediate32(Op.getImm(), STI, O);
 641         break;
 642       }
 643
 644       //  Deal with 16-bit FP inline immediates not working.
 645       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
 646         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
 647         break;
 648       }
 649       LLVM_FALLTHROUGH;
 650     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
 651     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
 652       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
 653       break;
 654     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
 655     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
 656       printImmediateV216(Op.getImm(), STI, O);
 657       break;
 658     case MCOI::OPERAND_UNKNOWN:
 659     case MCOI::OPERAND_PCREL:
 660       O << formatDec(Op.getImm());
 661       break;
 662     case MCOI::OPERAND_REGISTER:
 663       // FIXME: This should be removed and handled somewhere else. Seems to come
 664       // from a disassembler bug.
 665       O << "/*invalid immediate*/";
 666       break;
 667     default:
 668       // We hit this for the immediate instruction bits that don't yet have a
 669       // custom printer.
 670       llvm_unreachable("unexpected immediate operand type");
 671     }
 672   } else if (Op.isDFPImm()) {
 673     double Value = bit_cast<double>(Op.getDFPImm());
 674     // We special case 0.0 because otherwise it will be printed as an integer.
 675     if (Value == 0.0)
 676       O << "0.0";
 677     else {
 678       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
 679       int RCID = Desc.OpInfo[OpNo].RegClass;
 680       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
 681       if (RCBits == 32)
 682         printImmediate32(FloatToBits(Value), STI, O);
 683       else if (RCBits == 64)
 684         printImmediate64(DoubleToBits(Value), STI, O);
 685       else
 686         llvm_unreachable("Invalid register class size");
 687     }
 688   } else if (Op.isExpr()) {
 689     const MCExpr *Exp = Op.getExpr();
 690     Exp->print(O, &MAI);
 691   } else {
 692     O << "/*INV_OP*/";
 693   }
 694
 695   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
 696   switch (MI->getOpcode()) {
 697   default: break;
 698
 699   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
 700   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
 701   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
 702   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
 703   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
 704   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
 705   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
 706   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
 707   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
 708   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
 709   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
 710   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
 711
 712   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
 713   case AMDGPU::V_CNDMASK_B32_e32_vi:
 714     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
 715                                                 AMDGPU::OpName::src1))
 716       printDefaultVccOperand(OpNo, STI, O);
 717     break;
 718   }
 719
 720   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
 721     int SOffsetIdx =
 722       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
 723     assert(SOffsetIdx != -1);
 724     if ((int)OpNo == SOffsetIdx)
 725       printSymbolicFormat(MI, STI, O);
 726   }
 727 }
 728
 729 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
 730                                                    unsigned OpNo,
 731                                                    const MCSubtargetInfo &STI,
 732                                                    raw_ostream &O) {
 733   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
 734
 735   // Use 'neg(...)' instead of '-' to avoid ambiguity.
 736   // This is important for integer literals because
 737   // -1 is not the same value as neg(1).
 738   bool NegMnemo = false;
 739
 740   if (InputModifiers & SISrcMods::NEG) {
 741     if (OpNo + 1 < MI->getNumOperands() &&
 742         (InputModifiers & SISrcMods::ABS) == 0) {
 743       const MCOperand &Op = MI->getOperand(OpNo + 1);
 744       NegMnemo = Op.isImm() || Op.isDFPImm();
 745     }
 746     if (NegMnemo) {
 747       O << "neg(";
 748     } else {
 749       O << '-';
 750     }
 751   }
 752
 753   if (InputModifiers & SISrcMods::ABS)
 754     O << '|';
 755   printOperand(MI, OpNo + 1, STI, O);
 756   if (InputModifiers & SISrcMods::ABS)
 757     O << '|';
 758
 759   if (NegMnemo) {
 760     O << ')';
 761   }
 762 }
 763
 764 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
 765                                                     unsigned OpNo,
 766                                                     const MCSubtargetInfo &STI,
 767                                                     raw_ostream &O) {
 768   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
 769   if (InputModifiers & SISrcMods::SEXT)
 770     O << "sext(";
 771   printOperand(MI, OpNo + 1, STI, O);
 772   if (InputModifiers & SISrcMods::SEXT)
 773     O << ')';
 774
 775   // Print default vcc/vcc_lo operand of VOP2b.
 776   switch (MI->getOpcode()) {
 777   default: break;
 778
 779   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
 780   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
 781   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
 782   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
 783     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
 784                                                     AMDGPU::OpName::src1))
 785       printDefaultVccOperand(OpNo, STI, O);
 786     break;
 787   }
 788 }
 789
 790 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
 791                                   const MCSubtargetInfo &STI,
 792                                   raw_ostream &O) {
 793   if (!AMDGPU::isGFX10Plus(STI))
 794     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
 795
 796   unsigned Imm = MI->getOperand(OpNo).getImm();
 797   O << "dpp8:[" << formatDec(Imm & 0x7);
 798   for (size_t i = 1; i < 8; ++i) {
 799     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
 800   }
 801   O << ']';
 802 }
 803
 804 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
 805                                      const MCSubtargetInfo &STI,
 806                                      raw_ostream &O) {
 807   using namespace AMDGPU::DPP;
 808
 809   unsigned Imm = MI->getOperand(OpNo).getImm();
 810   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
 811   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
 812                                            AMDGPU::OpName::src0);
 813
 814   if (Src0Idx >= 0 &&
 815       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
 816       !AMDGPU::isLegal64BitDPPControl(Imm)) {
 817     O << " /* 64 bit dpp only supports row_newbcast */";
 818     return;
 819   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
 820     O << "quad_perm:[";
 821     O << formatDec(Imm & 0x3)         << ',';
 822     O << formatDec((Imm & 0xc)  >> 2) << ',';
 823     O << formatDec((Imm & 0x30) >> 4) << ',';
 824     O << formatDec((Imm & 0xc0) >> 6) << ']';
 825   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
 826              (Imm <= DppCtrl::ROW_SHL_LAST)) {
 827     O << "row_shl:";
 828     printU4ImmDecOperand(MI, OpNo, O);
 829   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
 830              (Imm <= DppCtrl::ROW_SHR_LAST)) {
 831     O << "row_shr:";
 832     printU4ImmDecOperand(MI, OpNo, O);
 833   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
 834              (Imm <= DppCtrl::ROW_ROR_LAST)) {
 835     O << "row_ror:";
 836     printU4ImmDecOperand(MI, OpNo, O);
 837   } else if (Imm == DppCtrl::WAVE_SHL1) {
 838     if (AMDGPU::isGFX10Plus(STI)) {
 839       O << "/* wave_shl is not supported starting from GFX10 */";
 840       return;
 841     }
 842     O << "wave_shl:1";
 843   } else if (Imm == DppCtrl::WAVE_ROL1) {
 844     if (AMDGPU::isGFX10Plus(STI)) {
 845       O << "/* wave_rol is not supported starting from GFX10 */";
 846       return;
 847     }
 848     O << "wave_rol:1";
 849   } else if (Imm == DppCtrl::WAVE_SHR1) {
 850     if (AMDGPU::isGFX10Plus(STI)) {
 851       O << "/* wave_shr is not supported starting from GFX10 */";
 852       return;
 853     }
 854     O << "wave_shr:1";
 855   } else if (Imm == DppCtrl::WAVE_ROR1) {
 856     if (AMDGPU::isGFX10Plus(STI)) {
 857       O << "/* wave_ror is not supported starting from GFX10 */";
 858       return;
 859     }
 860     O << "wave_ror:1";
 861   } else if (Imm == DppCtrl::ROW_MIRROR) {
 862     O << "row_mirror";
 863   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
 864     O << "row_half_mirror";
 865   } else if (Imm == DppCtrl::BCAST15) {
 866     if (AMDGPU::isGFX10Plus(STI)) {
 867       O << "/* row_bcast is not supported starting from GFX10 */";
 868       return;
 869     }
 870     O << "row_bcast:15";
 871   } else if (Imm == DppCtrl::BCAST31) {
 872     if (AMDGPU::isGFX10Plus(STI)) {
 873       O << "/* row_bcast is not supported starting from GFX10 */";
 874       return;
 875     }
 876     O << "row_bcast:31";
 877   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
 878              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
 879     if (AMDGPU::isGFX90A(STI)) {
 880       O << "row_newbcast:";
 881     } else if (AMDGPU::isGFX10Plus(STI)) {
 882       O << "row_share:";
 883     } else {
 884       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
 885            "than GFX90A/GFX10 */";
 886       return;
 887     }
 888     printU4ImmDecOperand(MI, OpNo, O);
 889   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
 890              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
 891     if (!AMDGPU::isGFX10Plus(STI)) {
 892       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
 893       return;
 894     }
 895     O << "row_xmask:";
 896     printU4ImmDecOperand(MI, OpNo, O);
 897   } else {
 898     O << "/* Invalid dpp_ctrl value */";
 899   }
 900 }
 901
 902 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
 903                                      const MCSubtargetInfo &STI,
 904                                      raw_ostream &O) {
 905   O << " row_mask:";
 906   printU4ImmOperand(MI, OpNo, STI, O);
 907 }
 908
 909 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
 910                                       const MCSubtargetInfo &STI,
 911                                       raw_ostream &O) {
 912   O << " bank_mask:";
 913   printU4ImmOperand(MI, OpNo, STI, O);
 914 }
 915
 916 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
 917                                        const MCSubtargetInfo &STI,
 918                                        raw_ostream &O) {
 919   unsigned Imm = MI->getOperand(OpNo).getImm();
 920   if (Imm) {
 921     O << " bound_ctrl:1";
 922   }
 923 }
 924
 925 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
 926                                 const MCSubtargetInfo &STI,
 927                                 raw_ostream &O) {
 928   using namespace llvm::AMDGPU::DPP;
 929   unsigned Imm = MI->getOperand(OpNo).getImm();
 930   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
 931     O << " fi:1";
 932   }
 933 }
 934
 935 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
 936                                      raw_ostream &O) {
 937   using namespace llvm::AMDGPU::SDWA;
 938
 939   unsigned Imm = MI->getOperand(OpNo).getImm();
 940   switch (Imm) {
 941   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
 942   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
 943   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
 944   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
 945   case SdwaSel::WORD_0: O << "WORD_0"; break;
 946   case SdwaSel::WORD_1: O << "WORD_1"; break;
 947   case SdwaSel::DWORD: O << "DWORD"; break;
 948   default: llvm_unreachable("Invalid SDWA data select operand");
 949   }
 950 }
 951
 952 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
 953                                         const MCSubtargetInfo &STI,
 954                                         raw_ostream &O) {
 955   O << "dst_sel:";
 956   printSDWASel(MI, OpNo, O);
 957 }
 958
 959 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
 960                                          const MCSubtargetInfo &STI,
 961                                          raw_ostream &O) {
 962   O << "src0_sel:";
 963   printSDWASel(MI, OpNo, O);
 964 }
 965
 966 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
 967                                          const MCSubtargetInfo &STI,
 968                                          raw_ostream &O) {
 969   O << "src1_sel:";
 970   printSDWASel(MI, OpNo, O);
 971 }
 972
 973 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
 974                                            const MCSubtargetInfo &STI,
 975                                            raw_ostream &O) {
 976   using namespace llvm::AMDGPU::SDWA;
 977
 978   O << "dst_unused:";
 979   unsigned Imm = MI->getOperand(OpNo).getImm();
 980   switch (Imm) {
 981   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
 982   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
 983   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
 984   default: llvm_unreachable("Invalid SDWA dest_unused operand");
 985   }
 986 }
 987
 988 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
 989                                      const MCSubtargetInfo &STI, raw_ostream &O,
 990                                      unsigned N) {
 991   unsigned Opc = MI->getOpcode();
 992   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
 993   unsigned En = MI->getOperand(EnIdx).getImm();
 994
 995   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
 996
 997   // If compr is set, print as src0, src0, src1, src1
 998   if (MI->getOperand(ComprIdx).getImm())
 999     OpNo = OpNo - N + N / 2;
1000
1001   if (En & (1 << N))
1002     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1003   else
1004     O << "off";
1005 }
1006
1007 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1008                                      const MCSubtargetInfo &STI,
1009                                      raw_ostream &O) {
1010   printExpSrcN(MI, OpNo, STI, O, 0);
1011 }
1012
1013 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1014                                      const MCSubtargetInfo &STI,
1015                                      raw_ostream &O) {
1016   printExpSrcN(MI, OpNo, STI, O, 1);
1017 }
1018
1019 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1020                                      const MCSubtargetInfo &STI,
1021                                      raw_ostream &O) {
1022   printExpSrcN(MI, OpNo, STI, O, 2);
1023 }
1024
1025 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1026                                      const MCSubtargetInfo &STI,
1027                                      raw_ostream &O) {
1028   printExpSrcN(MI, OpNo, STI, O, 3);
1029 }
1030
1031 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1032                                     const MCSubtargetInfo &STI,
1033                                     raw_ostream &O) {
1034   using namespace llvm::AMDGPU::Exp;
1035
1036   // This is really a 6 bit field.
1037   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1038
1039   int Index;
1040   StringRef TgtName;
1041   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1042     O << ' ' << TgtName;
1043     if (Index >= 0)
1044       O << Index;
1045   } else {
1046     O << " invalid_target_" << Id;
1047   }
1048 }
1049
1050 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1051                                bool IsPacked, bool HasDstSel) {
1052   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1053
1054   for (int I = 0; I < NumOps; ++I) {
1055     if (!!(Ops[I] & Mod) != DefaultValue)
1056       return false;
1057   }
1058
1059   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1060     return false;
1061
1062   return true;
1063 }
1064
1065 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1066                                             StringRef Name,
1067                                             unsigned Mod,
1068                                             raw_ostream &O) {
1069   unsigned Opc = MI->getOpcode();
1070   int NumOps = 0;
1071   int Ops[3];
1072
1073   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1074                       AMDGPU::OpName::src1_modifiers,
1075                       AMDGPU::OpName::src2_modifiers }) {
1076     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1077     if (Idx == -1)
1078       break;
1079
1080     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1081   }
1082
1083   const bool HasDstSel =
1084     NumOps > 0 &&
1085     Mod == SISrcMods::OP_SEL_0 &&
1086     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1087
1088   const bool IsPacked =
1089     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1090
1091   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1092     return;
1093
1094   O << Name;
1095   for (int I = 0; I < NumOps; ++I) {
1096     if (I != 0)
1097       O << ',';
1098
1099     O << !!(Ops[I] & Mod);
1100   }
1101
1102   if (HasDstSel) {
1103     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1104   }
1105
1106   O << ']';
1107 }
1108
1109 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1110                                    const MCSubtargetInfo &STI,
1111                                    raw_ostream &O) {
1112   unsigned Opc = MI->getOpcode();
1113   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1114       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1115     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1116     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1117     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1118     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1119     if (FI || BC)
1120       O << " op_sel:[" << FI << ',' << BC << ']';
1121     return;
1122   }
1123
1124   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1125 }
1126
1127 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1128                                      const MCSubtargetInfo &STI,
1129                                      raw_ostream &O) {
1130   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1131 }
1132
1133 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1134                                    const MCSubtargetInfo &STI,
1135                                    raw_ostream &O) {
1136   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1137 }
1138
1139 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1140                                    const MCSubtargetInfo &STI,
1141                                    raw_ostream &O) {
1142   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1143 }
1144
1145 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1146                                         const MCSubtargetInfo &STI,
1147                                         raw_ostream &O) {
1148   unsigned Imm = MI->getOperand(OpNum).getImm();
1149   switch (Imm) {
1150   case 0:
1151     O << "p10";
1152     break;
1153   case 1:
1154     O << "p20";
1155     break;
1156   case 2:
1157     O << "p0";
1158     break;
1159   default:
1160     O << "invalid_param_" << Imm;
1161   }
1162 }
1163
1164 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1165                                         const MCSubtargetInfo &STI,
1166                                         raw_ostream &O) {
1167   unsigned Attr = MI->getOperand(OpNum).getImm();
1168   O << "attr" << Attr;
1169 }
1170
1171 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1172                                         const MCSubtargetInfo &STI,
1173                                         raw_ostream &O) {
1174   unsigned Chan = MI->getOperand(OpNum).getImm();
1175   O << '.' << "xyzw"[Chan & 0x3];
1176 }
1177
1178 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1179                                            const MCSubtargetInfo &STI,
1180                                            raw_ostream &O) {
1181   using namespace llvm::AMDGPU::VGPRIndexMode;
1182   unsigned Val = MI->getOperand(OpNo).getImm();
1183
1184   if ((Val & ~ENABLE_MASK) != 0) {
1185     O << formatHex(static_cast<uint64_t>(Val));
1186   } else {
1187     O << "gpr_idx(";
1188     bool NeedComma = false;
1189     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1190       if (Val & (1 << ModeId)) {
1191         if (NeedComma)
1192           O << ',';
1193         O << IdSymbolic[ModeId];
1194         NeedComma = true;
1195       }
1196     }
1197     O << ')';
1198   }
1199 }
1200
1201 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1202                                         const MCSubtargetInfo &STI,
1203                                         raw_ostream &O) {
1204   printOperand(MI, OpNo, STI, O);
1205   O  << ", ";
1206   printOperand(MI, OpNo + 1, STI, O);
1207 }
1208
1209 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1210                                    raw_ostream &O, StringRef Asm,
1211                                    StringRef Default) {
1212   const MCOperand &Op = MI->getOperand(OpNo);
1213   assert(Op.isImm());
1214   if (Op.getImm() == 1) {
1215     O << Asm;
1216   } else {
1217     O << Default;
1218   }
1219 }
1220
1221 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1222                                    raw_ostream &O, char Asm) {
1223   const MCOperand &Op = MI->getOperand(OpNo);
1224   assert(Op.isImm());
1225   if (Op.getImm() == 1)
1226     O << Asm;
1227 }
1228
1229 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1230                                   const MCSubtargetInfo &STI,
1231                                   raw_ostream &O) {
1232   printNamedBit(MI, OpNo, O, "high");
1233 }
1234
1235 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1236                                      const MCSubtargetInfo &STI,
1237                                      raw_ostream &O) {
1238   printNamedBit(MI, OpNo, O, "clamp");
1239 }
1240
1241 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1242                                     const MCSubtargetInfo &STI,
1243                                     raw_ostream &O) {
1244   int Imm = MI->getOperand(OpNo).getImm();
1245   if (Imm == SIOutMods::MUL2)
1246     O << " mul:2";
1247   else if (Imm == SIOutMods::MUL4)
1248     O << " mul:4";
1249   else if (Imm == SIOutMods::DIV2)
1250     O << " div:2";
1251 }
1252
1253 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1254                                      const MCSubtargetInfo &STI,
1255                                      raw_ostream &O) {
1256   using namespace llvm::AMDGPU::SendMsg;
1257
1258   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1259
1260   uint16_t MsgId;
1261   uint16_t OpId;
1262   uint16_t StreamId;
1263   decodeMsg(Imm16, MsgId, OpId, StreamId);
1264
1265   if (isValidMsgId(MsgId, STI) &&
1266       isValidMsgOp(MsgId, OpId, STI) &&
1267       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1268     O << "sendmsg(" << getMsgName(MsgId);
1269     if (msgRequiresOp(MsgId)) {
1270       O << ", " << getMsgOpName(MsgId, OpId);
1271       if (msgSupportsStream(MsgId, OpId)) {
1272         O << ", " << StreamId;
1273       }
1274     }
1275     O << ')';
1276   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1277     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1278   } else {
1279     O << Imm16; // Unknown imm16 code.
1280   }
1281 }
1282
1283 static void printSwizzleBitmask(const uint16_t AndMask,
1284                                 const uint16_t OrMask,
1285                                 const uint16_t XorMask,
1286                                 raw_ostream &O) {
1287   using namespace llvm::AMDGPU::Swizzle;
1288
1289   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1290   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1291
1292   O << "\"";
1293
1294   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1295     uint16_t p0 = Probe0 & Mask;
1296     uint16_t p1 = Probe1 & Mask;
1297
1298     if (p0 == p1) {
1299       if (p0 == 0) {
1300         O << "0";
1301       } else {
1302         O << "1";
1303       }
1304     } else {
1305       if (p0 == 0) {
1306         O << "p";
1307       } else {
1308         O << "i";
1309       }
1310     }
1311   }
1312
1313   O << "\"";
1314 }
1315
1316 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1317                                      const MCSubtargetInfo &STI,
1318                                      raw_ostream &O) {
1319   using namespace llvm::AMDGPU::Swizzle;
1320
1321   uint16_t Imm = MI->getOperand(OpNo).getImm();
1322   if (Imm == 0) {
1323     return;
1324   }
1325
1326   O << " offset:";
1327
1328   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1329
1330     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1331     for (unsigned I = 0; I < LANE_NUM; ++I) {
1332       O << ",";
1333       O << formatDec(Imm & LANE_MASK);
1334       Imm >>= LANE_SHIFT;
1335     }
1336     O << ")";
1337
1338   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1339
1340     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1341     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1342     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1343
1344     if (AndMask == BITMASK_MAX &&
1345         OrMask == 0 &&
1346         countPopulation(XorMask) == 1) {
1347
1348       O << "swizzle(" << IdSymbolic[ID_SWAP];
1349       O << ",";
1350       O << formatDec(XorMask);
1351       O << ")";
1352
1353     } else if (AndMask == BITMASK_MAX &&
1354                OrMask == 0 && XorMask > 0 &&
1355                isPowerOf2_64(XorMask + 1)) {
1356
1357       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1358       O << ",";
1359       O << formatDec(XorMask + 1);
1360       O << ")";
1361
1362     } else {
1363
1364       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1365       if (GroupSize > 1 &&
1366           isPowerOf2_64(GroupSize) &&
1367           OrMask < GroupSize &&
1368           XorMask == 0) {
1369
1370         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1371         O << ",";
1372         O << formatDec(GroupSize);
1373         O << ",";
1374         O << formatDec(OrMask);
1375         O << ")";
1376
1377       } else {
1378         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1379         O << ",";
1380         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1381         O << ")";
1382       }
1383     }
1384   } else {
1385     printU16ImmDecOperand(MI, OpNo, O);
1386   }
1387 }
1388
1389 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1390                                       const MCSubtargetInfo &STI,
1391                                       raw_ostream &O) {
1392   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1393
1394   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1395   unsigned Vmcnt, Expcnt, Lgkmcnt;
1396   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1397
1398   bool NeedSpace = false;
1399
1400   if (Vmcnt != getVmcntBitMask(ISA)) {
1401     O << "vmcnt(" << Vmcnt << ')';
1402     NeedSpace = true;
1403   }
1404
1405   if (Expcnt != getExpcntBitMask(ISA)) {
1406     if (NeedSpace)
1407       O << ' ';
1408     O << "expcnt(" << Expcnt << ')';
1409     NeedSpace = true;
1410   }
1411
1412   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1413     if (NeedSpace)
1414       O << ' ';
1415     O << "lgkmcnt(" << Lgkmcnt << ')';
1416   }
1417 }
1418
1419 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1420                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1421   unsigned Id;
1422   unsigned Offset;
1423   unsigned Width;
1424
1425   using namespace llvm::AMDGPU::Hwreg;
1426   unsigned Val = MI->getOperand(OpNo).getImm();
1427   decodeHwreg(Val, Id, Offset, Width);
1428   StringRef HwRegName = getHwreg(Id, STI);
1429
1430   O << "hwreg(";
1431   if (!HwRegName.empty()) {
1432     O << HwRegName;
1433   } else {
1434     O << Id;
1435   }
1436   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1437     O << ", " << Offset << ", " << Width;
1438   }
1439   O << ')';
1440 }
1441
1442 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1443                                     const MCSubtargetInfo &STI,
1444                                     raw_ostream &O) {
1445   uint16_t Imm = MI->getOperand(OpNo).getImm();
1446   if (Imm == 0) {
1447     return;
1448   }
1449
1450   O << ' ' << formatDec(Imm);
1451 }
1452
1453 #include "AMDGPUGenAsmWriter.inc"
1454
1455 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1456                                 StringRef Annot, const MCSubtargetInfo &STI,
1457                                 raw_ostream &O) {
1458   O.flush();
1459   printInstruction(MI, Address, O);
1460   printAnnotation(O, Annot);
1461 }
1462
1463 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1464                                raw_ostream &O) {
1465   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1466 }
1467
1468 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1469                                        raw_ostream &O) {
1470   int BankSwizzle = MI->getOperand(OpNo).getImm();
1471   switch (BankSwizzle) {
1472   case 1:
1473     O << "BS:VEC_021/SCL_122";
1474     break;
1475   case 2:
1476     O << "BS:VEC_120/SCL_212";
1477     break;
1478   case 3:
1479     O << "BS:VEC_102/SCL_221";
1480     break;
1481   case 4:
1482     O << "BS:VEC_201";
1483     break;
1484   case 5:
1485     O << "BS:VEC_210";
1486     break;
1487   default:
1488     break;
1489   }
1490 }
1491
1492 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1493                                  raw_ostream &O) {
1494   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1495 }
1496
1497 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1498                                 raw_ostream &O) {
1499   unsigned CT = MI->getOperand(OpNo).getImm();
1500   switch (CT) {
1501   case 0:
1502     O << 'U';
1503     break;
1504   case 1:
1505     O << 'N';
1506     break;
1507   default:
1508     break;
1509   }
1510 }
1511
1512 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1513                                   raw_ostream &O) {
1514   int KCacheMode = MI->getOperand(OpNo).getImm();
1515   if (KCacheMode > 0) {
1516     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1517     O << "CB" << KCacheBank << ':';
1518     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1519     int LineSize = (KCacheMode == 1) ? 16 : 32;
1520     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1521   }
1522 }
1523
1524 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1525                                 raw_ostream &O) {
1526   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1527 }
1528
1529 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1530                                    raw_ostream &O) {
1531   const MCOperand &Op = MI->getOperand(OpNo);
1532   assert(Op.isImm() || Op.isExpr());
1533   if (Op.isImm()) {
1534     int64_t Imm = Op.getImm();
1535     O << Imm << '(' << BitsToFloat(Imm) << ')';
1536   }
1537   if (Op.isExpr()) {
1538     Op.getExpr()->print(O << '@', &MAI);
1539   }
1540 }
1541
1542 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1543                                raw_ostream &O) {
1544   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1545 }
1546
1547 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1548                                 raw_ostream &O) {
1549   switch (MI->getOperand(OpNo).getImm()) {
1550   default: break;
1551   case 1:
1552     O << " * 2.0";
1553     break;
1554   case 2:
1555     O << " * 4.0";
1556     break;
1557   case 3:
1558     O << " / 2.0";
1559     break;
1560   }
1561 }
1562
1563 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1564                                       raw_ostream &O) {
1565   printOperand(MI, OpNo, O);
1566   O  << ", ";
1567   printOperand(MI, OpNo + 1, O);
1568 }
1569
1570 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1571                                    raw_ostream &O) {
1572   if (OpNo >= MI->getNumOperands()) {
1573     O << "/*Missing OP" << OpNo << "*/";
1574     return;
1575   }
1576
1577   const MCOperand &Op = MI->getOperand(OpNo);
1578   if (Op.isReg()) {
1579     switch (Op.getReg()) {
1580     // This is the default predicate state, so we don't need to print it.
1581     case R600::PRED_SEL_OFF:
1582       break;
1583
1584     default:
1585       O << getRegisterName(Op.getReg());
1586       break;
1587     }
1588   } else if (Op.isImm()) {
1589       O << Op.getImm();
1590   } else if (Op.isDFPImm()) {
1591     // We special case 0.0 because otherwise it will be printed as an integer.
1592     if (Op.getDFPImm() == 0.0)
1593       O << "0.0";
1594     else {
1595       O << bit_cast<double>(Op.getDFPImm());
1596     }
1597   } else if (Op.isExpr()) {
1598     const MCExpr *Exp = Op.getExpr();
1599     Exp->print(O, &MAI);
1600   } else {
1601     O << "/*INV_OP*/";
1602   }
1603 }
1604
1605 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1606                                raw_ostream &O) {
1607   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1608 }
1609
1610 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1611                                   raw_ostream &O) {
1612   unsigned Sel = MI->getOperand(OpNo).getImm();
1613   switch (Sel) {
1614   case 0:
1615     O << 'X';
1616     break;
1617   case 1:
1618     O << 'Y';
1619     break;
1620   case 2:
1621     O << 'Z';
1622     break;
1623   case 3:
1624     O << 'W';
1625     break;
1626   case 4:
1627     O << '0';
1628     break;
1629   case 5:
1630     O << '1';
1631     break;
1632   case 7:
1633     O << '_';
1634     break;
1635   default:
1636     break;
1637   }
1638 }
1639
1640 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1641                                           raw_ostream &O) {
1642   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1643 }
1644
1645 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1646                                       raw_ostream &O) {
1647   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1648 }
1649
1650 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1651                                  raw_ostream &O) {
1652   const MCOperand &Op = MI->getOperand(OpNo);
1653   if (Op.getImm() == 0) {
1654     O << " (MASKED)";
1655   }
1656 }
1657
1658 #include "R600GenAsmWriter.inc"