llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

   1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// This file provides AMDGPU specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPUMCTargetDesc.h"
  15 #include "AMDGPUELFStreamer.h"
  16 #include "AMDGPUInstPrinter.h"
  17 #include "AMDGPUMCAsmInfo.h"
  18 #include "AMDGPUTargetStreamer.h"
  19 #include "SIDefines.h"
  20 #include "TargetInfo/AMDGPUTargetInfo.h"
  21 #include "llvm/MC/MCAsmBackend.h"
  22 #include "llvm/MC/MCCodeEmitter.h"
  23 #include "llvm/MC/MCELFStreamer.h"
  24 #include "llvm/MC/MCInstPrinter.h"
  25 #include "llvm/MC/MCInstrAnalysis.h"
  26 #include "llvm/MC/MCInstrDesc.h"
  27 #include "llvm/MC/MCInstrInfo.h"
  28 #include "llvm/MC/MCObjectWriter.h"
  29 #include "llvm/MC/MCRegister.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/MC/MCSubtargetInfo.h"
  32 #include "llvm/Support/TargetRegistry.h"
  33
  34 using namespace llvm;
  35
  36 #define GET_INSTRINFO_MC_DESC
  37 #include "AMDGPUGenInstrInfo.inc"
  38
  39 #define GET_SUBTARGETINFO_MC_DESC
  40 #include "AMDGPUGenSubtargetInfo.inc"
  41
  42 #define NoSchedModel NoSchedModelR600
  43 #define GET_SUBTARGETINFO_MC_DESC
  44 #include "R600GenSubtargetInfo.inc"
  45 #undef NoSchedModelR600
  46
  47 #define GET_REGINFO_MC_DESC
  48 #include "AMDGPUGenRegisterInfo.inc"
  49
  50 #define GET_REGINFO_MC_DESC
  51 #include "R600GenRegisterInfo.inc"
  52
  53 static MCInstrInfo *createAMDGPUMCInstrInfo() {
  54   MCInstrInfo *X = new MCInstrInfo();
  55   InitAMDGPUMCInstrInfo(X);
  56   return X;
  57 }
  58
  59 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
  60   MCRegisterInfo *X = new MCRegisterInfo();
  61   if (TT.getArch() == Triple::r600)
  62     InitR600MCRegisterInfo(X, 0);
  63   else
  64     InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
  65   return X;
  66 }
  67
  68 MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) {
  69   MCRegisterInfo *X = new MCRegisterInfo();
  70   InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour);
  71   return X;
  72 }
  73
  74 static MCSubtargetInfo *
  75 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
  76   if (TT.getArch() == Triple::r600)
  77     return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
  78   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
  79 }
  80
  81 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
  82                                                 unsigned SyntaxVariant,
  83                                                 const MCAsmInfo &MAI,
  84                                                 const MCInstrInfo &MII,
  85                                                 const MCRegisterInfo &MRI) {
  86   if (T.getArch() == Triple::r600)
  87     return new R600InstPrinter(MAI, MII, MRI);
  88   else
  89     return new AMDGPUInstPrinter(MAI, MII, MRI);
  90 }
  91
  92 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
  93                                                       formatted_raw_ostream &OS,
  94                                                       MCInstPrinter *InstPrint,
  95                                                       bool isVerboseAsm) {
  96   return new AMDGPUTargetAsmStreamer(S, OS);
  97 }
  98
  99 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
 100                                                    MCStreamer &S,
 101                                                    const MCSubtargetInfo &STI) {
 102   return new AMDGPUTargetELFStreamer(S, STI);
 103 }
 104
 105 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
 106                                     std::unique_ptr<MCAsmBackend> &&MAB,
 107                                     std::unique_ptr<MCObjectWriter> &&OW,
 108                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
 109                                     bool RelaxAll) {
 110   return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
 111                                  std::move(Emitter), RelaxAll);
 112 }
 113
 114 namespace {
 115
 116 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
 117 public:
 118   explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
 119       : MCInstrAnalysis(Info) {}
 120
 121   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
 122                       uint64_t &Target) const override {
 123     if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
 124         Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
 125             MCOI::OPERAND_PCREL)
 126       return false;
 127
 128     int64_t Imm = Inst.getOperand(0).getImm();
 129     // Our branches take a simm16, but we need two extra bits to account for
 130     // the factor of 4.
 131     APInt SignedOffset(18, Imm * 4, true);
 132     Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
 133     return true;
 134   }
 135 };
 136
 137 } // end anonymous namespace
 138
 139 static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) {
 140   return new AMDGPUMCInstrAnalysis(Info);
 141 }
 142
 143 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() {
 144
 145   TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
 146   TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
 147   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
 148     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
 149
 150     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
 151     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
 152     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
 153     TargetRegistry::RegisterMCInstrAnalysis(*T, createAMDGPUMCInstrAnalysis);
 154     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
 155     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
 156   }
 157
 158   // R600 specific registration
 159   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
 160                                         createR600MCCodeEmitter);
 161   TargetRegistry::RegisterObjectTargetStreamer(
 162       getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
 163
 164   // GCN specific registration
 165   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
 166                                         createSIMCCodeEmitter);
 167
 168   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
 169                                             createAMDGPUAsmTargetStreamer);
 170   TargetRegistry::RegisterObjectTargetStreamer(
 171       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
 172 }