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1 //===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 // MIMG-specific encoding families to distinguish between semantically
10 // equivalent machine instructions with different encoding.
11 //
12 // - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8)
13 // - MIMGEncGfx8: encoding introduced with gfx8 for atomics
14 // - MIMGEncGfx90a: encoding for gfx90a for atomics
15 // - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding
16 // - MIMGEncGfx10NSA: gfx10 NSA encoding
17 class MIMGEncoding;
19 def MIMGEncGfx6 : MIMGEncoding;
20 def MIMGEncGfx8 : MIMGEncoding;
21 def MIMGEncGfx90a : MIMGEncoding;
22 def MIMGEncGfx10Default : MIMGEncoding;
23 def MIMGEncGfx10NSA : MIMGEncoding;
25 def MIMGEncoding : GenericEnum {
26 let FilterClass = "MIMGEncoding";
27 }
29 // Represent an ISA-level opcode, independent of the encoding and the
30 // vdata/vaddr size.
31 class MIMGBaseOpcode : PredicateControl {
32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
33 bit Store = 0;
34 bit Atomic = 0;
35 bit AtomicX2 = 0; // (f)cmpswap
36 bit Sampler = 0;
37 bit Gather4 = 0;
38 bits<8> NumExtraArgs = 0;
39 bit Gradients = 0;
40 bit G16 = 0;
41 bit Coordinates = 1;
42 bit LodOrClampOrMip = 0;
43 bit HasD16 = 0;
44 bit IsAtomicRet = 0;
45 bit MSAA = 0;
46 bit BVH = 0;
47 }
49 def MIMGBaseOpcode : GenericEnum {
50 let FilterClass = "MIMGBaseOpcode";
51 }
53 def MIMGBaseOpcodesTable : GenericTable {
54 let FilterClass = "MIMGBaseOpcode";
55 let CppTypeName = "MIMGBaseOpcodeInfo";
56 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
57 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates",
58 "LodOrClampOrMip", "HasD16", "MSAA", "BVH"];
59 string TypeOf_BaseOpcode = "MIMGBaseOpcode";
61 let PrimaryKey = ["BaseOpcode"];
62 let PrimaryKeyName = "getMIMGBaseOpcodeInfo";
63 }
65 def MIMGDim : GenericEnum {
66 let FilterClass = "AMDGPUDimProps";
67 }
69 def MIMGDimInfoTable : GenericTable {
70 let FilterClass = "AMDGPUDimProps";
71 let CppTypeName = "MIMGDimInfo";
72 let Fields = ["Dim", "NumCoords", "NumGradients", "MSAA", "DA", "Encoding", "AsmSuffix"];
73 string TypeOf_Dim = "MIMGDim";
75 let PrimaryKey = ["Dim"];
76 let PrimaryKeyName = "getMIMGDimInfo";
77 }
79 def getMIMGDimInfoByEncoding : SearchIndex {
80 let Table = MIMGDimInfoTable;
81 let Key = ["Encoding"];
82 }
84 def getMIMGDimInfoByAsmSuffix : SearchIndex {
85 let Table = MIMGDimInfoTable;
86 let Key = ["AsmSuffix"];
87 }
89 def MIMG {
90 int NOP = -1;
91 }
93 class mimgopc <int base, int vi = base, int si = base> {
94 field bits<8> BASE = base; // Opcode for all but atomics
95 field bits<8> VI = vi; // VI is only used for atomic instructions
96 field bits<8> SI = si; // SI is only used for atomic instructions
97 bit HAS_BASE = !ne(base, MIMG.NOP);
98 bit HAS_VI = !ne(vi, MIMG.NOP);
99 bit HAS_SI = !ne(si, MIMG.NOP);
100 }
102 class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> {
103 MIMGBaseOpcode L = l;
104 MIMGBaseOpcode LZ = lz;
105 }
107 def MIMGLZMappingTable : GenericTable {
108 let FilterClass = "MIMGLZMapping";
109 let CppTypeName = "MIMGLZMappingInfo";
110 let Fields = ["L", "LZ"];
111 string TypeOf_L = "MIMGBaseOpcode";
112 string TypeOf_LZ = "MIMGBaseOpcode";
114 let PrimaryKey = ["L"];
115 let PrimaryKeyName = "getMIMGLZMappingInfo";
116 }
118 class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> {
119 MIMGBaseOpcode MIP = mip;
120 MIMGBaseOpcode NONMIP = nonmip;
121 }
123 def MIMGMIPMappingTable : GenericTable {
124 let FilterClass = "MIMGMIPMapping";
125 let CppTypeName = "MIMGMIPMappingInfo";
126 let Fields = ["MIP", "NONMIP"];
127 string TypeOf_MIP = "MIMGBaseOpcode";
128 string TypeOf_NONMIP = "MIMGBaseOpcode";
130 let PrimaryKey = ["MIP"];
131 let PrimaryKeyName = "getMIMGMIPMappingInfo";
132 }
134 class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> {
135 MIMGBaseOpcode G = g;
136 MIMGBaseOpcode G16 = g16;
137 }
139 def MIMGG16MappingTable : GenericTable {
140 let FilterClass = "MIMGG16Mapping";
141 let CppTypeName = "MIMGG16MappingInfo";
142 let Fields = ["G", "G16"];
143 string TypeOf_G = "MIMGBaseOpcode";
144 string TypeOf_G16 = "MIMGBaseOpcode";
146 let PrimaryKey = ["G"];
147 let PrimaryKeyName = "getMIMGG16MappingInfo";
148 }
150 class MIMG_Base <dag outs, string dns = "">
151 : InstSI <outs, (ins), "", []> {
153 let VM_CNT = 1;
154 let EXP_CNT = 1;
155 let MIMG = 1;
156 let Uses = [EXEC];
157 let mayLoad = 1;
158 let mayStore = 0;
159 let SchedRW = [WriteVMEM];
160 let UseNamedOperandTable = 1;
161 let hasSideEffects = 0; // XXX ????
163 let DecoderNamespace = dns;
164 let isAsmParserOnly = !eq(dns, "");
165 }
167 class MIMG <dag outs, string dns = "">
168 : MIMG_Base <outs, dns> {
170 let hasPostISelHook = 1;
171 let AsmMatchConverter = "cvtMIMG";
173 Instruction Opcode = !cast<Instruction>(NAME);
174 MIMGBaseOpcode BaseOpcode;
175 MIMGEncoding MIMGEncoding;
176 bits<8> VDataDwords;
177 bits<8> VAddrDwords;
178 }
180 def MIMGInfoTable : GenericTable {
181 let FilterClass = "MIMG";
182 let CppTypeName = "MIMGInfo";
183 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
184 string TypeOf_BaseOpcode = "MIMGBaseOpcode";
185 string TypeOf_MIMGEncoding = "MIMGEncoding";
187 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
188 let PrimaryKeyName = "getMIMGOpcodeHelper";
189 }
191 def getMIMGInfo : SearchIndex {
192 let Table = MIMGInfoTable;
193 let Key = ["Opcode"];
194 }
196 // This class used to use !foldl to memoize the AddrAsmNames list.
197 // It turned out that that was much slower than using !filter.
198 class MIMGNSAHelper<int num_addrs> {
199 list<string> AddrAsmNames =
200 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11],
201 !lt(i, num_addrs)), "vaddr" # i);
202 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames);
203 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]";
205 int NSA = !if(!le(num_addrs, 1), ?,
206 !if(!le(num_addrs, 5), 1,
207 !if(!le(num_addrs, 9), 2,
208 !if(!le(num_addrs, 13), 3, ?))));
209 }
211 // Base class of all pre-gfx10 MIMG instructions.
212 class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
213 : MIMG<outs, dns>, MIMGe_gfx6789<op> {
214 let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A;
215 let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A;
217 let MIMGEncoding = MIMGEncGfx6;
219 let d16 = !if(BaseOpcode.HasD16, ?, 0);
220 }
222 class MIMG_gfx90a<bits<8> op, dag outs, string dns = "">
223 : MIMG<outs, dns>, MIMGe_gfx90a<op> {
224 let SubtargetPredicate = isGFX90APlus;
225 let AssemblerPredicate = isGFX90APlus;
227 let MIMGEncoding = MIMGEncGfx90a;
229 let d16 = !if(BaseOpcode.HasD16, ?, 0);
230 }
232 // Base class of all non-NSA gfx10 MIMG instructions.
233 class MIMG_gfx10<int op, dag outs, string dns = "">
234 : MIMG<outs, dns>, MIMGe_gfx10<op> {
235 let SubtargetPredicate = isGFX10Plus;
236 let AssemblerPredicate = isGFX10Plus;
238 let MIMGEncoding = MIMGEncGfx10Default;
240 let d16 = !if(BaseOpcode.HasD16, ?, 0);
241 let nsa = 0;
242 }
244 // Base class for all NSA MIMG instructions.
245 // Note that 1-dword addresses always use non-NSA variants.
246 class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns="">
247 : MIMG<outs, dns>, MIMGe_gfx10<op> {
248 let SubtargetPredicate = isGFX10Plus;
249 let AssemblerPredicate = isGFX10Plus;
251 let MIMGEncoding = MIMGEncGfx10NSA;
253 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>;
254 dag AddrIns = nsah.AddrIns;
255 string AddrAsm = nsah.AddrAsm;
257 let d16 = !if(BaseOpcode.HasD16, ?, 0);
258 let nsa = nsah.NSA;
259 }
261 class MIMG_NoSampler_Helper <mimgopc op, string asm,
262 RegisterClass dst_rc,
263 RegisterClass addr_rc,
264 string dns="">
265 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> {
266 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
267 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
268 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
269 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
270 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
271 #!if(BaseOpcode.HasD16, "$d16", "");
272 }
274 class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
275 RegisterClass dst_rc,
276 RegisterClass addr_rc,
277 string dns="">
278 : MIMG_gfx90a <op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
279 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
280 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
281 R128A16:$r128, LWE:$lwe, DA:$da),
282 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
283 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"
284 #!if(BaseOpcode.HasD16, "$d16", "");
285 }
287 class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
288 RegisterClass DataRC, RegisterClass AddrRC,
289 string dns="">
290 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> {
291 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
292 Dim:$dim, UNorm:$unorm, CPol:$cpol,
293 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
294 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
295 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
296 #!if(BaseOpcode.HasD16, "$d16", "");
297 }
299 class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
300 RegisterClass DataRC, int num_addrs,
301 string dns="">
302 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> {
303 let InOperandList = !con(AddrIns,
304 (ins SReg_256:$srsrc, DMask:$dmask,
305 Dim:$dim, UNorm:$unorm, CPol:$cpol,
306 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
307 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
308 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
309 #!if(BaseOpcode.HasD16, "$d16", "");
310 }
312 multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
313 RegisterClass dst_rc,
314 bit enableDisasm,
315 bit ExtendedImageInst = 1> {
316 let ssamp = 0 in {
317 let VAddrDwords = 1 in {
318 if op.HAS_BASE then {
319 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
320 !if(enableDisasm, "AMDGPU", "")>;
321 if !not(ExtendedImageInst) then
322 def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
323 !if(enableDisasm, "GFX90A", "")>;
324 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
325 !if(enableDisasm, "AMDGPU", "")>;
326 }
327 }
329 let VAddrDwords = 2 in {
330 if op.HAS_BASE then {
331 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
332 if !not(ExtendedImageInst) then
333 def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>;
334 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
335 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
336 }
337 }
339 let VAddrDwords = 3 in {
340 if op.HAS_BASE then {
341 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
342 if !not(ExtendedImageInst) then
343 def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>;
344 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
345 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
346 }
347 }
349 let VAddrDwords = 4 in {
350 if op.HAS_BASE then {
351 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
352 if !not(ExtendedImageInst) then
353 def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>;
354 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
355 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
356 !if(enableDisasm, "AMDGPU", "")>;
357 }
358 }
359 }
360 }
362 multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0,
363 bit isResInfo = 0,
364 bit msaa = 0> {
365 def "" : MIMGBaseOpcode {
366 let Coordinates = !not(isResInfo);
367 let LodOrClampOrMip = mip;
368 let HasD16 = has_d16;
369 let MSAA = msaa;
370 }
372 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
373 mayLoad = !not(isResInfo) in {
374 let VDataDwords = 1 in
375 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>;
376 let VDataDwords = 2 in
377 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>;
378 let VDataDwords = 3 in
379 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>;
380 let VDataDwords = 4 in
381 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>;
382 let VDataDwords = 5 in
383 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>;
384 }
385 }
387 class MIMG_Store_Helper <mimgopc op, string asm,
388 RegisterClass data_rc,
389 RegisterClass addr_rc,
390 string dns = "">
391 : MIMG_gfx6789<op.BASE, (outs), dns> {
392 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
393 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
394 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
395 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
396 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
397 #!if(BaseOpcode.HasD16, "$d16", "");
398 }
400 class MIMG_Store_Helper_gfx90a <mimgopc op, string asm,
401 RegisterClass data_rc,
402 RegisterClass addr_rc,
403 string dns = "">
404 : MIMG_gfx90a<op.BASE, (outs), dns> {
405 let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata,
406 addr_rc:$vaddr, SReg_256:$srsrc,
407 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
408 R128A16:$r128, LWE:$lwe, DA:$da),
409 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
410 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"
411 #!if(BaseOpcode.HasD16, "$d16", "");
412 }
414 class MIMG_Store_gfx10<mimgopc op, string opcode,
415 RegisterClass DataRC, RegisterClass AddrRC,
416 string dns="">
417 : MIMG_gfx10<op.BASE, (outs), dns> {
418 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
419 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
420 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
421 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
422 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
423 #!if(BaseOpcode.HasD16, "$d16", "");
424 }
426 class MIMG_Store_nsa_gfx10<mimgopc op, string opcode,
427 RegisterClass DataRC, int num_addrs,
428 string dns="">
429 : MIMG_nsa_gfx10<op.BASE, (outs), num_addrs, dns> {
430 let InOperandList = !con((ins DataRC:$vdata),
431 AddrIns,
432 (ins SReg_256:$srsrc, DMask:$dmask,
433 Dim:$dim, UNorm:$unorm, CPol:$cpol,
434 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
435 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
436 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
437 #!if(BaseOpcode.HasD16, "$d16", "");
438 }
440 multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
441 RegisterClass data_rc,
442 bit enableDisasm> {
443 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0,
444 DisableWQM = 1, ssamp = 0 in {
445 let VAddrDwords = 1 in {
446 if op.HAS_BASE then {
447 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
448 !if(enableDisasm, "AMDGPU", "")>;
449 def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
450 !if(enableDisasm, "GFX90A", "")>;
451 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
452 !if(enableDisasm, "AMDGPU", "")>;
453 }
454 }
455 let VAddrDwords = 2 in {
456 if op.HAS_BASE then {
457 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>;
458 def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>;
459 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>;
460 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>;
461 }
462 }
463 let VAddrDwords = 3 in {
464 if op.HAS_BASE then {
465 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>;
466 def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>;
467 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>;
468 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>;
469 }
470 }
471 let VAddrDwords = 4 in {
472 if op.HAS_BASE then {
473 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>;
474 def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>;
475 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
476 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
477 !if(enableDisasm, "AMDGPU", "")>;
478 }
479 }
480 }
481 }
483 multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> {
484 def "" : MIMGBaseOpcode {
485 let Store = 1;
486 let LodOrClampOrMip = mip;
487 let HasD16 = has_d16;
488 }
490 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
491 let VDataDwords = 1 in
492 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
493 let VDataDwords = 2 in
494 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>;
495 let VDataDwords = 3 in
496 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>;
497 let VDataDwords = 4 in
498 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>;
499 let VDataDwords = 5 in
500 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>;
501 }
502 }
504 class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
505 RegisterClass addr_rc, string dns="">
506 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
507 let Constraints = "$vdst = $vdata";
508 let AsmMatchConverter = "cvtMIMGAtomic";
510 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
511 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
512 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
513 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
514 }
516 class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
517 RegisterClass addr_rc, string dns="">
518 : MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
519 let Constraints = "$vdst = $vdata";
520 let AsmMatchConverter = "cvtMIMGAtomic";
522 let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata,
523 addr_rc:$vaddr, SReg_256:$srsrc,
524 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
525 R128A16:$r128, LWE:$lwe, DA:$da);
526 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
527 }
529 class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc,
530 RegisterClass addr_rc, bit enableDasm = 0>
531 : MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc,
532 !if(enableDasm, "GFX6GFX7", "")> {
533 let AssemblerPredicate = isGFX6GFX7;
534 }
536 class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc,
537 RegisterClass addr_rc, bit enableDasm = 0>
538 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
539 let AssemblerPredicate = isGFX8GFX9NotGFX90A;
540 let MIMGEncoding = MIMGEncGfx8;
541 }
543 class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc,
544 RegisterClass addr_rc, bit enableDasm = 0>
545 : MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> {
546 let AssemblerPredicate = isGFX90APlus;
547 let MIMGEncoding = MIMGEncGfx90a;
548 }
550 class MIMG_Atomic_gfx10<mimgopc op, string opcode,
551 RegisterClass DataRC, RegisterClass AddrRC,
552 bit enableDisasm = 0>
553 : MIMG_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst),
554 !if(enableDisasm, "AMDGPU", "")> {
555 let Constraints = "$vdst = $vdata";
556 let AsmMatchConverter = "cvtMIMGAtomic";
558 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
559 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
560 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe);
561 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
562 }
564 class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
565 RegisterClass DataRC, int num_addrs,
566 bit enableDisasm = 0>
567 : MIMG_nsa_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), num_addrs,
568 !if(enableDisasm, "AMDGPU", "")> {
569 let Constraints = "$vdst = $vdata";
570 let AsmMatchConverter = "cvtMIMGAtomic";
572 let InOperandList = !con((ins DataRC:$vdata),
573 AddrIns,
574 (ins SReg_256:$srsrc, DMask:$dmask,
575 Dim:$dim, UNorm:$unorm, CPol:$cpol,
576 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe));
577 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
578 }
580 multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
581 RegisterClass data_rc,
582 bit enableDasm = 0,
583 bit isFP = 0> {
584 let hasSideEffects = 1, // FIXME: remove this
585 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1,
586 ssamp = 0, FPAtomic = isFP in {
587 let VAddrDwords = 1 in {
588 if op.HAS_SI then {
589 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
590 }
591 if op.HAS_VI then {
592 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
593 def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>;
594 }
595 if op.HAS_BASE then {
596 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>;
597 }
598 }
599 let VAddrDwords = 2 in {
600 if op.HAS_SI then {
601 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
602 }
603 if op.HAS_VI then {
604 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
605 def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>;
606 }
607 if op.HAS_BASE then {
608 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>;
609 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>;
610 }
611 }
612 let VAddrDwords = 3 in {
613 if op.HAS_SI then {
614 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
615 }
616 if op.HAS_VI then {
617 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
618 def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>;
619 }
620 if op.HAS_BASE then {
621 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>;
622 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>;
623 }
624 }
625 let VAddrDwords = 4 in {
626 if op.HAS_SI then {
627 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
628 }
629 if op.HAS_VI then {
630 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
631 def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>;
632 }
633 if op.HAS_BASE then {
634 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>;
635 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>;
636 }
637 }
638 }
639 }
641 multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics
642 let IsAtomicRet = 1 in {
643 def "" : MIMGBaseOpcode {
644 let Atomic = 1;
645 let AtomicX2 = isCmpSwap;
646 }
648 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
649 // _V* variants have different dst size, but the size is encoded implicitly,
650 // using dmask and tfe. Only 32-bit variant is registered with disassembler.
651 // Other variants are reconstructed by disassembler using dmask and tfe.
652 let VDataDwords = !if(isCmpSwap, 2, 1) in
653 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>;
654 let VDataDwords = !if(isCmpSwap, 4, 2) in
655 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>;
656 }
657 } // End IsAtomicRet = 1
658 }
660 class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
661 RegisterClass src_rc, string dns="">
662 : MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> {
663 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
664 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
665 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
666 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
667 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da"
668 #!if(BaseOpcode.HasD16, "$d16", "");
669 }
671 class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc,
672 RegisterClass src_rc, string dns="">
673 : MIMG_gfx90a<op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
674 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
675 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
676 R128A16:$r128, LWE:$lwe, DA:$da),
677 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
678 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$lwe$da"
679 #!if(BaseOpcode.HasD16, "$d16", "");
680 }
682 class MIMG_Sampler_gfx10<mimgopc op, string opcode,
683 RegisterClass DataRC, RegisterClass AddrRC,
684 string dns="">
685 : MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> {
686 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp,
687 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
688 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
689 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
690 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
691 #"$cpol$r128$a16$tfe$lwe"
692 #!if(BaseOpcode.HasD16, "$d16", "");
693 }
695 class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode,
696 RegisterClass DataRC, int num_addrs,
697 string dns="">
698 : MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> {
699 let InOperandList = !con(AddrIns,
700 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask,
701 Dim:$dim, UNorm:$unorm, CPol:$cpol,
702 R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
703 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
704 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm"
705 #"$cpol$r128$a16$tfe$lwe"
706 #!if(BaseOpcode.HasD16, "$d16", "");
707 }
709 class MIMGAddrSize<int dw, bit enable_disasm> {
710 int NumWords = dw;
712 RegisterClass RegClass = !if(!le(NumWords, 0), ?,
713 !if(!eq(NumWords, 1), VGPR_32,
714 !if(!eq(NumWords, 2), VReg_64,
715 !if(!eq(NumWords, 3), VReg_96,
716 !if(!eq(NumWords, 4), VReg_128,
717 !if(!eq(NumWords, 5), VReg_160,
718 !if(!eq(NumWords, 6), VReg_192,
719 !if(!eq(NumWords, 7), VReg_224,
720 !if(!le(NumWords, 8), VReg_256,
721 !if(!le(NumWords, 16), VReg_512, ?))))))))));
723 // Whether the instruction variant with this vaddr size should be enabled for
724 // the auto-generated disassembler.
725 bit Disassemble = enable_disasm;
726 }
728 // Return whether x is in lst.
729 class isIntInList<int x, list<int> lst> {
730 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y)));
731 }
733 // Return whether a value inside the range [min, max] (endpoints inclusive)
734 // is in the given list.
735 class isRangeInList<int min, int max, list<int> lst> {
736 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max))));
737 }
739 class MIMGAddrSizes_dw_range<list<int> range> {
740 int Min = !head(range);
741 int Max = !if(!empty(!tail(range)), Min, !head(!tail(range)));
742 }
744 class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
745 // List of all possible numbers of address words, taking all combinations of
746 // A16 and image dimension into account (note: no MSAA, since this is for
747 // sample/gather ops).
748 list<int> AllNumAddrWords =
749 !foreach(dw, !if(sample.Gradients,
750 !if(!eq(sample.LodOrClamp, ""),
751 [2, 3, 4, 5, 6, 7, 8, 9],
752 [2, 3, 4, 5, 6, 7, 8, 9, 10]),
753 !if(!eq(sample.LodOrClamp, ""),
754 [1, 2, 3],
755 [1, 2, 3, 4])),
756 !add(dw, !size(sample.ExtraAddrArgs)));
758 // Generate machine instructions based on possible register classes for the
759 // required numbers of address words. The disassembler defaults to the
760 // smallest register class.
761 list<MIMGAddrSize> MachineInstrs =
762 !foldl([]<MIMGAddrSize>,
763 !foreach(range,
764 // V4 is generated for V3 and V4
765 // V8 is generated for V5 through V8
766 // V16 is generated for V9 through V16
767 [[1],[2],[3],[3,4],[5],[6],[7],[5,8],[9,16]],
768 MIMGAddrSizes_dw_range<range>),
769 lhs, dw,
770 !if(isRangeInList<dw.Min, dw.Max, AllNumAddrWords>.ret,
771 !listconcat(lhs, [MIMGAddrSize<dw.Max, !empty(lhs)>]),
772 lhs));
774 // For NSA, generate machine instructions for all possible numbers of words
775 // except 1 (which is already covered by the non-NSA case).
776 // The disassembler defaults to the largest number of arguments among the
777 // variants with the same number of NSA words, and custom code then derives
778 // the exact variant based on the sample variant and the image dimension.
779 list<MIMGAddrSize> NSAInstrs =
780 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group,
781 !listconcat(prev,
782 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw,
783 !if(isIntInList<dw, AllNumAddrWords>.ret,
784 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]),
785 lhs))));
786 }
788 multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
789 AMDGPUSampleVariant sample, RegisterClass dst_rc,
790 bit enableDisasm = 0,
791 bit ExtendedImageInst = 1> {
792 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
793 let VAddrDwords = addr.NumWords in {
794 if op.HAS_BASE then {
795 def _V # addr.NumWords
796 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
797 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
798 if !not(ExtendedImageInst) then
799 def _V # addr.NumWords # _gfx90a
800 : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,
801 !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>;
802 def _V # addr.NumWords # _gfx10
803 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
804 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
805 }
806 }
807 }
809 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
810 let VAddrDwords = addr.NumWords in {
811 if op.HAS_BASE then {
812 def _V # addr.NumWords # _nsa_gfx10
813 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
814 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
815 }
816 }
817 }
818 }
820 class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample>
821 : MIMGBaseOpcode {
822 let Sampler = 1;
823 let NumExtraArgs = !size(sample.ExtraAddrArgs);
824 let Gradients = sample.Gradients;
825 let LodOrClampOrMip = !ne(sample.LodOrClamp, "");
826 }
828 multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
829 bit isG16 = 0, bit isGetLod = 0,
830 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""),
831 bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> {
832 def "" : MIMG_Sampler_BaseOpcode<sample> {
833 let HasD16 = !not(isGetLod);
834 let G16 = isG16;
835 }
837 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
838 mayLoad = !not(isGetLod) in {
839 let VDataDwords = 1 in
840 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>;
841 let VDataDwords = 2 in
842 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>;
843 let VDataDwords = 3 in
844 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>;
845 let VDataDwords = 4 in
846 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>;
847 let VDataDwords = 5 in
848 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>;
849 }
850 }
852 multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample>
853 : MIMG_Sampler<op, sample, 1>;
855 multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
856 string asm = "image_gather4"#sample.LowerCaseMod> {
857 def "" : MIMG_Sampler_BaseOpcode<sample> {
858 let HasD16 = 1;
859 let Gather4 = 1;
860 }
862 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
863 Gather4 = 1 in {
864 let VDataDwords = 2 in
865 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */
866 let VDataDwords = 4 in
867 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>;
868 let VDataDwords = 5 in
869 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
870 }
871 }
873 multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
874 : MIMG_Gather<op, sample, 1>;
876 class MIMG_IntersectRay_Helper<bit Is64, bit A16> {
877 int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11));
878 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple,
879 // when we only need 9, 11 or 12 depending on A16 field and ptr size.
880 RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
881 int VAddrDwords = !srl(RegClass.Size, 5);
882 }
884 class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16>
885 : MIMG_gfx10<op.BASE, (outs VReg_128:$vdata), "AMDGPU"> {
887 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc),
888 !if(A16, (ins GFX10A16:$a16), (ins)));
889 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", "");
891 let nsa = 0;
892 }
894 class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16>
895 : MIMG_nsa_gfx10<op.BASE, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> {
896 let InOperandList = !con(nsah.AddrIns,
897 (ins SReg_128:$srsrc),
898 !if(A16, (ins GFX10A16:$a16), (ins)));
899 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", "");
900 }
902 multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit A16> {
903 defvar info = MIMG_IntersectRay_Helper<Is64, A16>;
904 def "" : MIMGBaseOpcode {
905 let BVH = 1;
906 }
907 let SubtargetPredicate = HasGFX10_AEncoding,
908 AssemblerPredicate = HasGFX10_AEncoding,
909 AsmMatchConverter = !if(A16, "cvtIntersectRay", ""),
910 dmask = 0xf,
911 unorm = 1,
912 d16 = 0,
913 cpol = 0,
914 tfe = 0,
915 lwe = 0,
916 r128 = 1,
917 ssamp = 0,
918 dim = {0, 0, 0},
919 a16 = A16,
920 d16 = 0,
921 BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
922 VDataDwords = 4 in {
923 def _sa_gfx10 : MIMG_IntersectRay_gfx10<op, opcode, info.RegClass, A16> {
924 let VAddrDwords = info.VAddrDwords;
925 }
926 def _nsa_gfx10 : MIMG_IntersectRay_nsa_gfx10<op, opcode, info.num_addrs, A16> {
927 let VAddrDwords = info.num_addrs;
928 }
929 }
930 }
932 //===----------------------------------------------------------------------===//
933 // MIMG Instructions
934 //===----------------------------------------------------------------------===//
935 defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>;
936 defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>;
937 defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>;
938 defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>;
939 defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>;
940 defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>;
941 defm IMAGE_STORE : MIMG_Store <mimgopc<0x08>, "image_store", 1>;
942 defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>;
943 defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a>, "image_store_pck", 0>;
944 defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b>, "image_store_mip_pck", 0, 1>;
946 defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e>, "image_get_resinfo", 0, 1, 1>;
948 defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x10, 0x0f>, "image_atomic_swap">;
949 defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>;
950 defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x11, 0x12, 0x11>, "image_atomic_add">;
951 defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x12, 0x13, 0x12>, "image_atomic_sub">;
952 defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">;
953 defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x14>, "image_atomic_smin">;
954 defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x15>, "image_atomic_umin">;
955 defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x16>, "image_atomic_smax">;
956 defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x17>, "image_atomic_umax">;
957 defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18>, "image_atomic_and">;
958 defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">;
959 defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">;
960 defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">;
961 defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">;
962 defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 0, 1>;
963 defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>;
964 defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>;
966 defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20>, AMDGPUSample>;
967 let OtherPredicates = [HasExtendedImageInsts] in {
968 defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21>, AMDGPUSample_cl>;
969 defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22>, AMDGPUSample_d>;
970 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23>, AMDGPUSample_d_cl>;
971 defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2>, AMDGPUSample_d, 0, 1>;
972 defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3>, AMDGPUSample_d_cl, 0, 1>;
973 defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24>, AMDGPUSample_l>;
974 defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25>, AMDGPUSample_b>;
975 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26>, AMDGPUSample_b_cl>;
976 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27>, AMDGPUSample_lz>;
977 defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28>, AMDGPUSample_c>;
978 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29>, AMDGPUSample_c_cl>;
979 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a>, AMDGPUSample_c_d>;
980 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b>, AMDGPUSample_c_d_cl>;
981 defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa>, AMDGPUSample_c_d, 0, 1>;
982 defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab>, AMDGPUSample_c_d_cl, 0, 1>;
983 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c>, AMDGPUSample_c_l>;
984 defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d>, AMDGPUSample_c_b>;
985 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e>, AMDGPUSample_c_b_cl>;
986 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f>, AMDGPUSample_c_lz>;
987 defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30>, AMDGPUSample_o>;
988 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31>, AMDGPUSample_cl_o>;
989 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32>, AMDGPUSample_d_o>;
990 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33>, AMDGPUSample_d_cl_o>;
991 defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2>, AMDGPUSample_d_o, 0, 1>;
992 defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3>, AMDGPUSample_d_cl_o, 0, 1>;
993 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34>, AMDGPUSample_l_o>;
994 defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35>, AMDGPUSample_b_o>;
995 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36>, AMDGPUSample_b_cl_o>;
996 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37>, AMDGPUSample_lz_o>;
997 defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38>, AMDGPUSample_c_o>;
998 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39>, AMDGPUSample_c_cl_o>;
999 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a>, AMDGPUSample_c_d_o>;
1000 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b>, AMDGPUSample_c_d_cl_o>;
1001 defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba>, AMDGPUSample_c_d_o, 0, 1>;
1002 defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>;
1003 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c>, AMDGPUSample_c_l_o>;
1004 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e>, AMDGPUSample_c_b_cl_o>;
1005 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d>, AMDGPUSample_c_b_o>;
1006 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f>, AMDGPUSample_c_lz_o>;
1007 defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40>, AMDGPUSample>;
1008 defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41>, AMDGPUSample_cl>;
1009 defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44>, AMDGPUSample_l>;
1010 defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45>, AMDGPUSample_b>;
1011 defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46>, AMDGPUSample_b_cl>;
1012 defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47>, AMDGPUSample_lz>;
1013 defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48>, AMDGPUSample_c>;
1014 defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49>, AMDGPUSample_c_cl>;
1015 defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c>, AMDGPUSample_c_l>;
1016 defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d>, AMDGPUSample_c_b>;
1017 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e>, AMDGPUSample_c_b_cl>;
1018 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f>, AMDGPUSample_c_lz>;
1019 defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50>, AMDGPUSample_o>;
1020 defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<0x51>, AMDGPUSample_cl_o>;
1021 defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<0x54>, AMDGPUSample_l_o>;
1022 defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<0x55>, AMDGPUSample_b_o>;
1023 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<0x56>, AMDGPUSample_b_cl_o>;
1024 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57>, AMDGPUSample_lz_o>;
1025 defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<0x58>, AMDGPUSample_c_o>;
1026 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<0x59>, AMDGPUSample_c_cl_o>;
1027 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<0x5c>, AMDGPUSample_c_l_o>;
1028 defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<0x5d>, AMDGPUSample_c_b_o>;
1029 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<0x5e>, AMDGPUSample_c_b_cl_o>;
1030 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f>, AMDGPUSample_c_lz_o>;
1031 //defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x61>, ?>;
1033 defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">;
1035 defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<0x68>, AMDGPUSample_cd>;
1036 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<0x69>, AMDGPUSample_cd_cl>;
1037 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<0x6a>, AMDGPUSample_c_cd>;
1038 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<0x6b>, AMDGPUSample_c_cd_cl>;
1039 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<0x6c>, AMDGPUSample_cd_o>;
1040 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<0x6d>, AMDGPUSample_cd_cl_o>;
1041 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<0x6e>, AMDGPUSample_c_cd_o>;
1042 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<0x6f>, AMDGPUSample_c_cd_cl_o>;
1043 defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<0xe8>, AMDGPUSample_cd, 0, 1>;
1044 defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<0xe9>, AMDGPUSample_cd_cl, 0, 1>;
1045 defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<0xea>, AMDGPUSample_c_cd, 0, 1>;
1046 defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<0xeb>, AMDGPUSample_c_cd_cl, 0, 1>;
1047 defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<0xec>, AMDGPUSample_cd_o, 0, 1>;
1048 defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xed>, AMDGPUSample_cd_cl_o, 0, 1>;
1049 defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<0xee>, AMDGPUSample_c_cd_o, 0, 1>;
1050 defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>;
1051 } // End OtherPredicates = [HasExtendedImageInsts]
1052 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
1053 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
1055 let SubtargetPredicate = HasGFX10_AEncoding in
1056 defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>;
1058 defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 0>;
1059 defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 1>;
1060 defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 0>;
1061 defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 1>;
1063 /********** ========================================= **********/
1064 /********** Table of dimension-aware image intrinsics **********/
1065 /********** ========================================= **********/
1067 class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> {
1068 Intrinsic Intr = I;
1069 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod));
1070 AMDGPUDimProps Dim = I.P.Dim;
1071 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>;
1073 bits<8> NumGradients = DimEval.NumGradientArgs;
1074 bits<8> NumDmask = DimEval.NumDmaskArgs;
1075 bits<8> NumData = DimEval.NumDataArgs;
1076 bits<8> NumVAddrs = DimEval.NumVAddrArgs;
1077 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1);
1079 bits<8> DMaskIndex = DimEval.DmaskArgIndex;
1080 bits<8> VAddrStart = DimEval.VAddrArgIndex;
1081 bits<8> GradientStart = DimEval.GradientArgIndex;
1082 bits<8> CoordStart = DimEval.CoordArgIndex;
1083 bits<8> LodIndex = DimEval.LodArgIndex;
1084 bits<8> MipIndex = DimEval.MipArgIndex;
1085 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs);
1086 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1087 bits<8> SampIndex = DimEval.SampArgIndex;
1088 bits<8> UnormIndex = DimEval.UnormArgIndex;
1089 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex;
1090 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex;
1092 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes,
1093 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny)));
1094 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0));
1095 }
1097 def ImageDimIntrinsicTable : GenericTable {
1098 let FilterClass = "ImageDimIntrinsicInfo";
1099 let Fields = ["Intr", "BaseOpcode", "Dim", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs",
1100 "DMaskIndex", "VAddrStart", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd",
1101 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
1102 "GradientTyArg", "CoordTyArg"];
1103 string TypeOf_BaseOpcode = "MIMGBaseOpcode";
1104 string TypeOf_Dim = "MIMGDim";
1106 let PrimaryKey = ["Intr"];
1107 let PrimaryKeyName = "getImageDimIntrinsicInfo";
1108 let PrimaryKeyEarlyOut = 1;
1109 }
1111 def getImageDimInstrinsicByBaseOpcode : SearchIndex {
1112 let Table = ImageDimIntrinsicTable;
1113 let Key = ["BaseOpcode", "Dim"];
1114 }
1116 foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
1117 AMDGPUImageDimAtomicIntrinsics) in {
1118 def : ImageDimIntrinsicInfo<intr>;
1119 }
1121 // L to LZ Optimization Mapping
1122 def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>;
1123 def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>;
1124 def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>;
1125 def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>;
1126 def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>;
1127 def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>;
1128 def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>;
1129 def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>;
1131 // MIP to NONMIP Optimization Mapping
1132 def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>;
1133 def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>;
1135 // G to G16 Optimization Mapping
1136 def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>;
1137 def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>;
1138 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>;
1139 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>;
1140 def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>;
1141 def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>;
1142 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>;
1143 def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>;
1144 def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>;
1145 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>;
1146 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>;
1147 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>;
1148 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>;
1149 def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>;
1150 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>;
1151 def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>;