llvm/lib/Target/AMDGPU/R600RegisterInfo.h

   1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Interface definition for R600RegisterInfo
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
  15 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
  16
  17 #define GET_REGINFO_HEADER
  18 #include "R600GenRegisterInfo.inc"
  19
  20 namespace llvm {
  21
  22 struct R600RegisterInfo final : public R600GenRegisterInfo {
  23   R600RegisterInfo() : R600GenRegisterInfo(0) {}
  24
  25   /// \returns the sub reg enum value for the given \p Channel
  26   /// (e.g. getSubRegFromChannel(0) -> R600::sub0)
  27   static unsigned getSubRegFromChannel(unsigned Channel);
  28
  29   BitVector getReservedRegs(const MachineFunction &MF) const override;
  30   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  31   Register getFrameRegister(const MachineFunction &MF) const override;
  32
  33   /// get the HW encoding for a register's channel.
  34   unsigned getHWRegChan(unsigned reg) const;
  35
  36   unsigned getHWRegIndex(unsigned Reg) const;
  37
  38   /// get the register class of the specified type to use in the
  39   /// CFGStructurizer
  40   const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
  41
  42   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
  43     return false;
  44   }
  45
  46   // \returns true if \p Reg can be defined in one ALU clause and used in
  47   // another.
  48   bool isPhysRegLiveAcrossClauses(Register Reg) const;
  49
  50   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
  51                            unsigned FIOperandNum,
  52                            RegScavenger *RS = nullptr) const override;
  53
  54   void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
  55 };
  56
  57 } // End namespace llvm
  58
  59 #endif