llvm/lib/Target/AMDGPU/SIISelLowering.h

   1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// SI DAG Lowering interface definition
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
  15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
  16
  17 #include "AMDGPUISelLowering.h"
  18 #include "AMDGPUArgumentUsageInfo.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20
  21 namespace llvm {
  22
  23 class GCNSubtarget;
  24 class SIMachineFunctionInfo;
  25 class SIRegisterInfo;
  26
  27 namespace AMDGPU {
  28 struct ImageDimIntrinsicInfo;
  29 }
  30
  31 class SITargetLowering final : public AMDGPUTargetLowering {
  32 private:
  33   const GCNSubtarget *Subtarget;
  34
  35 public:
  36   MVT getRegisterTypeForCallingConv(LLVMContext &Context,
  37                                     CallingConv::ID CC,
  38                                     EVT VT) const override;
  39   unsigned getNumRegistersForCallingConv(LLVMContext &Context,
  40                                          CallingConv::ID CC,
  41                                          EVT VT) const override;
  42
  43   unsigned getVectorTypeBreakdownForCallingConv(
  44     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
  45     unsigned &NumIntermediates, MVT &RegisterVT) const override;
  46
  47 private:
  48   SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
  49                                    SDValue Chain, uint64_t Offset) const;
  50   SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
  51   SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
  52                                    const SDLoc &SL, SDValue Chain,
  53                                    uint64_t Offset, Align Alignment,
  54                                    bool Signed,
  55                                    const ISD::InputArg *Arg = nullptr) const;
  56
  57   SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
  58                               const SDLoc &SL, SDValue Chain,
  59                               const ISD::InputArg &Arg) const;
  60   SDValue getPreloadedValue(SelectionDAG &DAG,
  61                             const SIMachineFunctionInfo &MFI,
  62                             EVT VT,
  63                             AMDGPUFunctionArgInfo::PreloadedValue) const;
  64
  65   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
  66                              SelectionDAG &DAG) const override;
  67   SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
  68                                  MVT VT, unsigned Offset) const;
  69   SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
  70                      SelectionDAG &DAG, bool WithChain) const;
  71   SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
  72                        SDValue CachePolicy, SelectionDAG &DAG) const;
  73
  74   SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
  75                                      unsigned NewOpcode) const;
  76   SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
  77                                         unsigned NewOpcode) const;
  78
  79   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  80   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  81   SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  82
  83   // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
  84   // (the offset that is included in bounds checking and swizzling, to be split
  85   // between the instruction's voffset and immoffset fields) and soffset (the
  86   // offset that is excluded from bounds checking and swizzling, to go in the
  87   // instruction's soffset field).  This function takes the first kind of
  88   // offset and figures out how to split it between voffset and immoffset.
  89   std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
  90                                                  SelectionDAG &DAG) const;
  91
  92   SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
  93   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  94   SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
  95   SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
  96   SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
  97   SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
  98   SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
  99   SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
 100   SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
 101   SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
 102   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 103   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
 104   SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
 105   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 106   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 107   SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
 108                               SelectionDAG &DAG, ArrayRef<SDValue> Ops,
 109                               bool IsIntrinsic = false) const;
 110
 111   SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
 112                              ArrayRef<SDValue> Ops) const;
 113
 114   // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
 115   // dwordx4 if on SI.
 116   SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
 117                               ArrayRef<SDValue> Ops, EVT MemVT,
 118                               MachineMemOperand *MMO, SelectionDAG &DAG) const;
 119
 120   SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
 121                          bool ImageStore = false) const;
 122
 123   /// Converts \p Op, which must be of floating point type, to the
 124   /// floating point type \p VT, by either extending or truncating it.
 125   SDValue getFPExtOrFPRound(SelectionDAG &DAG,
 126                             SDValue Op,
 127                             const SDLoc &DL,
 128                             EVT VT) const;
 129
 130   SDValue convertArgType(
 131     SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
 132     bool Signed, const ISD::InputArg *Arg = nullptr) const;
 133
 134   /// Custom lowering for ISD::FP_ROUND for MVT::f16.
 135   SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 136   SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
 137   SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
 138
 139   SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
 140                              SelectionDAG &DAG) const;
 141
 142   SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
 143   SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 144   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 145   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 146   SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 147   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 148
 149   SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
 150   SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
 151   SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
 152   SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
 153   SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
 154
 155   SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
 156
 157   SDValue performUCharToFloatCombine(SDNode *N,
 158                                      DAGCombinerInfo &DCI) const;
 159   SDValue performSHLPtrCombine(SDNode *N,
 160                                unsigned AS,
 161                                EVT MemVT,
 162                                DAGCombinerInfo &DCI) const;
 163
 164   SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
 165
 166   SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
 167                                    unsigned Opc, SDValue LHS,
 168                                    const ConstantSDNode *CRHS) const;
 169
 170   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 171   SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 172   SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 173   SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 174   SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 175   SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 176   SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
 177                                  const APFloat &C) const;
 178   SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 179
 180   SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
 181                                   SDValue Op0, SDValue Op1) const;
 182   SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
 183                                    SDValue Op0, SDValue Op1, bool Signed) const;
 184   SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 185   SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
 186   SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 187   SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 188   SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 189
 190   SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
 191   unsigned getFusedOpcode(const SelectionDAG &DAG,
 192                           const SDNode *N0, const SDNode *N1) const;
 193   SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 194   SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 195   SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 196   SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 197   SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 198   SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
 199   SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 200   SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 201   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 202   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 203
 204   bool isLegalFlatAddressingMode(const AddrMode &AM) const;
 205   bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
 206
 207   unsigned isCFIntrinsic(const SDNode *Intr) const;
 208
 209 public:
 210   /// \returns True if fixup needs to be emitted for given global value \p GV,
 211   /// false otherwise.
 212   bool shouldEmitFixup(const GlobalValue *GV) const;
 213
 214   /// \returns True if GOT relocation needs to be emitted for given global value
 215   /// \p GV, false otherwise.
 216   bool shouldEmitGOTReloc(const GlobalValue *GV) const;
 217
 218   /// \returns True if PC-relative relocation needs to be emitted for given
 219   /// global value \p GV, false otherwise.
 220   bool shouldEmitPCReloc(const GlobalValue *GV) const;
 221
 222   /// \returns true if this should use a literal constant for an LDS address,
 223   /// and not emit a relocation for an LDS global.
 224   bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
 225
 226   /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
 227   /// expanded into a set of cmp/select instructions.
 228   static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
 229                                        bool IsDivergentIdx);
 230
 231 private:
 232   // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
 233   // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
 234   // pointed to by Offsets.
 235   void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
 236                         SDValue *Offsets, Align Alignment = Align(4)) const;
 237
 238   // Handle 8 bit and 16 bit buffer loads
 239   SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
 240                                      ArrayRef<SDValue> Ops, MemSDNode *M) const;
 241
 242   // Handle 8 bit and 16 bit buffer stores
 243   SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
 244                                       SDLoc DL, SDValue Ops[],
 245                                       MemSDNode *M) const;
 246
 247 public:
 248   SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
 249
 250   const GCNSubtarget *getSubtarget() const;
 251
 252   bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
 253                        EVT SrcVT) const override;
 254
 255   bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
 256
 257   bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
 258                           MachineFunction &MF,
 259                           unsigned IntrinsicID) const override;
 260
 261   bool getAddrModeArguments(IntrinsicInst * /*I*/,
 262                             SmallVectorImpl<Value*> &/*Ops*/,
 263                             Type *&/*AccessTy*/) const override;
 264
 265   bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
 266   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
 267                              unsigned AS,
 268                              Instruction *I = nullptr) const override;
 269
 270   bool canMergeStoresTo(unsigned AS, EVT MemVT,
 271                         const MachineFunction &MF) const override;
 272
 273   bool allowsMisalignedMemoryAccessesImpl(
 274       unsigned Size, unsigned AddrSpace, Align Alignment,
 275       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 276       bool *IsFast = nullptr) const;
 277
 278   bool allowsMisalignedMemoryAccesses(
 279       LLT Ty, unsigned AddrSpace, Align Alignment,
 280       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 281       bool *IsFast = nullptr) const override {
 282     if (IsFast)
 283       *IsFast = false;
 284     return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
 285                                               Alignment, Flags, IsFast);
 286   }
 287
 288   bool allowsMisalignedMemoryAccesses(
 289       EVT VT, unsigned AS, Align Alignment,
 290       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 291       bool *IsFast = nullptr) const override;
 292
 293   EVT getOptimalMemOpType(const MemOp &Op,
 294                           const AttributeList &FuncAttributes) const override;
 295
 296   bool isMemOpUniform(const SDNode *N) const;
 297   bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
 298
 299   static bool isNonGlobalAddrSpace(unsigned AS);
 300
 301   bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 302
 303   TargetLoweringBase::LegalizeTypeAction
 304   getPreferredVectorAction(MVT VT) const override;
 305
 306   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 307                                         Type *Ty) const override;
 308
 309   bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
 310
 311   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 312
 313   bool supportSplitCSR(MachineFunction *MF) const override;
 314   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 315   void insertCopiesSplitCSR(
 316     MachineBasicBlock *Entry,
 317     const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 318
 319   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
 320                                bool isVarArg,
 321                                const SmallVectorImpl<ISD::InputArg> &Ins,
 322                                const SDLoc &DL, SelectionDAG &DAG,
 323                                SmallVectorImpl<SDValue> &InVals) const override;
 324
 325   bool CanLowerReturn(CallingConv::ID CallConv,
 326                       MachineFunction &MF, bool isVarArg,
 327                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 328                       LLVMContext &Context) const override;
 329
 330   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 331                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 332                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 333                       SelectionDAG &DAG) const override;
 334
 335   void passSpecialInputs(
 336     CallLoweringInfo &CLI,
 337     CCState &CCInfo,
 338     const SIMachineFunctionInfo &Info,
 339     SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
 340     SmallVectorImpl<SDValue> &MemOpChains,
 341     SDValue Chain) const;
 342
 343   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 344                           CallingConv::ID CallConv, bool isVarArg,
 345                           const SmallVectorImpl<ISD::InputArg> &Ins,
 346                           const SDLoc &DL, SelectionDAG &DAG,
 347                           SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
 348                           SDValue ThisVal) const;
 349
 350   bool mayBeEmittedAsTailCall(const CallInst *) const override;
 351
 352   bool isEligibleForTailCallOptimization(
 353     SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
 354     const SmallVectorImpl<ISD::OutputArg> &Outs,
 355     const SmallVectorImpl<SDValue> &OutVals,
 356     const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
 357
 358   SDValue LowerCall(CallLoweringInfo &CLI,
 359                     SmallVectorImpl<SDValue> &InVals) const override;
 360
 361   SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
 362   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 363
 364   Register getRegisterByName(const char* RegName, LLT VT,
 365                              const MachineFunction &MF) const override;
 366
 367   MachineBasicBlock *splitKillBlock(MachineInstr &MI,
 368                                     MachineBasicBlock *BB) const;
 369
 370   void bundleInstWithWaitcnt(MachineInstr &MI) const;
 371   MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
 372                                             MachineBasicBlock *BB) const;
 373
 374   MachineBasicBlock *
 375   EmitInstrWithCustomInserter(MachineInstr &MI,
 376                               MachineBasicBlock *BB) const override;
 377
 378   bool hasBitPreservingFPLogic(EVT VT) const override;
 379   bool enableAggressiveFMAFusion(EVT VT) const override;
 380   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 381                          EVT VT) const override;
 382   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
 383   LLT getPreferredShiftAmountTy(LLT Ty) const override;
 384
 385   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
 386                                   EVT VT) const override;
 387   bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
 388
 389   SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
 390   SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
 391   SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
 392   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 393
 394   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
 395                           SelectionDAG &DAG) const override;
 396
 397   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 398   SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
 399   void AddIMGInit(MachineInstr &MI) const;
 400   void AdjustInstrPostInstrSelection(MachineInstr &MI,
 401                                      SDNode *Node) const override;
 402
 403   SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
 404
 405   MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
 406                                 SDValue Ptr) const;
 407   MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
 408                            uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
 409   std::pair<unsigned, const TargetRegisterClass *>
 410   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 411                                StringRef Constraint, MVT VT) const override;
 412   ConstraintType getConstraintType(StringRef Constraint) const override;
 413   void LowerAsmOperandForConstraint(SDValue Op,
 414                                     std::string &Constraint,
 415                                     std::vector<SDValue> &Ops,
 416                                     SelectionDAG &DAG) const override;
 417   bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
 418   bool checkAsmConstraintVal(SDValue Op,
 419                              const std::string &Constraint,
 420                              uint64_t Val) const;
 421   bool checkAsmConstraintValA(SDValue Op,
 422                               uint64_t Val,
 423                               unsigned MaxSize = 64) const;
 424   SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
 425                    SDValue V) const;
 426
 427   void finalizeLowering(MachineFunction &MF) const override;
 428
 429   void computeKnownBitsForFrameIndex(int FrameIdx,
 430                                      KnownBits &Known,
 431                                      const MachineFunction &MF) const override;
 432   void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R,
 433                                       KnownBits &Known,
 434                                       const APInt &DemandedElts,
 435                                       const MachineRegisterInfo &MRI,
 436                                       unsigned Depth = 0) const override;
 437
 438   Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
 439                                         const MachineRegisterInfo &MRI,
 440                                         unsigned Depth = 0) const override;
 441   bool isSDNodeSourceOfDivergence(const SDNode *N,
 442     FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
 443
 444   bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
 445                        unsigned MaxDepth = 5) const;
 446   bool isCanonicalized(Register Reg, MachineFunction &MF,
 447                        unsigned MaxDepth = 5) const;
 448   bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
 449   bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
 450
 451   bool isKnownNeverNaNForTargetNode(SDValue Op,
 452                                     const SelectionDAG &DAG,
 453                                     bool SNaN = false,
 454                                     unsigned Depth = 0) const override;
 455   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 456
 457   virtual const TargetRegisterClass *
 458   getRegClassFor(MVT VT, bool isDivergent) const override;
 459   virtual bool requiresUniformRegister(MachineFunction &MF,
 460                                        const Value *V) const override;
 461   Align getPrefLoopAlignment(MachineLoop *ML) const override;
 462
 463   void allocateHSAUserSGPRs(CCState &CCInfo,
 464                             MachineFunction &MF,
 465                             const SIRegisterInfo &TRI,
 466                             SIMachineFunctionInfo &Info) const;
 467
 468   void allocateSystemSGPRs(CCState &CCInfo,
 469                            MachineFunction &MF,
 470                            SIMachineFunctionInfo &Info,
 471                            CallingConv::ID CallConv,
 472                            bool IsShader) const;
 473
 474   void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
 475                                       MachineFunction &MF,
 476                                       const SIRegisterInfo &TRI,
 477                                       SIMachineFunctionInfo &Info) const;
 478   void allocateSpecialInputSGPRs(
 479     CCState &CCInfo,
 480     MachineFunction &MF,
 481     const SIRegisterInfo &TRI,
 482     SIMachineFunctionInfo &Info) const;
 483
 484   void allocateSpecialInputVGPRs(CCState &CCInfo,
 485                                  MachineFunction &MF,
 486                                  const SIRegisterInfo &TRI,
 487                                  SIMachineFunctionInfo &Info) const;
 488   void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
 489                                       MachineFunction &MF,
 490                                       const SIRegisterInfo &TRI,
 491                                       SIMachineFunctionInfo &Info) const;
 492
 493   std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
 494                                                           Type *Ty) const;
 495 };
 496
 497 } // End namespace llvm
 498
 499 #endif