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[ORC] Add std::tuple support to SimplePackedSerialization.
[llvm-project.git] / llvm / lib / Target / ARM / MCTargetDesc / ARMMCCodeEmitter.cpp
blobced48ccc98834a8e1429c3eaf497120c78c2f3b5
1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMFixupKinds.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "mccodeemitter"
44
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47
48 namespace {
49
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51 const MCInstrInfo &MCII;
52 MCContext &CTX;
53 bool IsLittleEndian;
54
55 public:
56 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58 }
59 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61 ~ARMMCCodeEmitter() override = default;
62
63 bool isThumb(const MCSubtargetInfo &STI) const {
64 return STI.getFeatureBits()[ARM::ModeThumb];
65 }
66
67 bool isThumb2(const MCSubtargetInfo &STI) const {
68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69 }
70
71 bool isTargetMachO(const MCSubtargetInfo &STI) const {
72 const Triple &TT = STI.getTargetTriple();
73 return TT.isOSBinFormatMachO();
74 }
75
76 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77
78 // getBinaryCodeForInstr - TableGen'erated function for getting the
79 // binary encoding for an instruction.
80 uint64_t getBinaryCodeForInstr(const MCInst &MI,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const;
83
84 /// getMachineOpValue - Return binary encoding of operand. If the machine
85 /// operand requires relocation, record the relocation and return zero.
86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
87 SmallVectorImpl<MCFixup> &Fixups,
88 const MCSubtargetInfo &STI) const;
89
90 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91 /// the specified operand. This is used for operands with :lower16: and
92 /// :upper16: prefixes.
93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
96
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98 unsigned &Reg, unsigned &Imm,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
101
102 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103 /// BL branch target.
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107
108 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109 /// BLX branch target.
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
113
114 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
118
119 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 SmallVectorImpl<MCFixup> &Fixups,
122 const MCSubtargetInfo &STI) const;
123
124 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI) const;
128
129 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130 /// branch target.
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134
135 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136 /// immediate Thumb2 direct branch target.
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
140
141 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142 /// branch target.
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
152
153 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154 /// ADR label target.
155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups,
157 const MCSubtargetInfo &STI) const;
158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const;
164
165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups,
167 const MCSubtargetInfo &STI) const;
168
169 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170 /// operand.
171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI) const;
174
175 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176 /// operand.
177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups,
179 const MCSubtargetInfo &STI) const;
180
181 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &Fixups,
184 const MCSubtargetInfo &STI) const;
185
186 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187 /// operand.
188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
189 SmallVectorImpl<MCFixup> &Fixups,
190 const MCSubtargetInfo &STI) const;
191
192 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193 /// operand.
194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups,
196 const MCSubtargetInfo &STI) const;
197
198 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199 /// operand.
200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups,
202 const MCSubtargetInfo &STI) const;
203
204 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205 /// operand.
206 template<unsigned Bits, unsigned Shift>
207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups,
209 const MCSubtargetInfo &STI) const;
210
211 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212 /// operand.
213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI) const;
216
217 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218 /// operand.
219 template<int shift>
220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups,
222 const MCSubtargetInfo &STI) const;
223
224 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225 /// operand as needed by load/store instructions.
226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const;
229
230 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
232 SmallVectorImpl<MCFixup> &Fixups,
233 const MCSubtargetInfo &STI) const {
234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
235 switch (Mode) {
236 default: llvm_unreachable("Unknown addressing sub-mode!");
237 case ARM_AM::da: return 0;
238 case ARM_AM::ia: return 1;
239 case ARM_AM::db: return 2;
240 case ARM_AM::ib: return 3;
241 }
242 }
243
244 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245 ///
246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247 switch (ShOpc) {
248 case ARM_AM::no_shift:
249 case ARM_AM::lsl: return 0;
250 case ARM_AM::lsr: return 1;
251 case ARM_AM::asr: return 2;
252 case ARM_AM::ror:
253 case ARM_AM::rrx: return 3;
254 default:
255 llvm_unreachable("Invalid ShiftOpc!");
256 }
257 }
258
259 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
261 SmallVectorImpl<MCFixup> &Fixups,
262 const MCSubtargetInfo &STI) const;
263
264 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
266 SmallVectorImpl<MCFixup> &Fixups,
267 const MCSubtargetInfo &STI) const;
268
269 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
271 SmallVectorImpl<MCFixup> &Fixups,
272 const MCSubtargetInfo &STI) const;
273
274 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
276 SmallVectorImpl<MCFixup> &Fixups,
277 const MCSubtargetInfo &STI) const;
278
279 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280 /// operand.
281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
282 SmallVectorImpl<MCFixup> &Fixups,
283 const MCSubtargetInfo &STI) const;
284
285 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
287 SmallVectorImpl<MCFixup> &Fixups,
288 const MCSubtargetInfo &STI) const;
289
290 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
292 SmallVectorImpl<MCFixup> &Fixups,
293 const MCSubtargetInfo &STI) const;
294
295 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
297 SmallVectorImpl<MCFixup> &Fixups,
298 const MCSubtargetInfo &STI) const;
299
300 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
302 SmallVectorImpl<MCFixup> &Fixups,
303 const MCSubtargetInfo &STI) const;
304
305 /// getCCOutOpValue - Return encoding of the 's' bit.
306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups,
308 const MCSubtargetInfo &STI) const {
309 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310 // '1' respectively.
311 return MI.getOperand(Op).getReg() == ARM::CPSR;
312 }
313
314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315 SmallVectorImpl<MCFixup> &Fixups,
316 const MCSubtargetInfo &ST) const {
317 const MCOperand &MO = MI.getOperand(Op);
318
319 // Support for fixups (MCFixup)
320 if (MO.isExpr()) {
321 const MCExpr *Expr = MO.getExpr();
322 // Fixups resolve to plain values that need to be encoded.
323 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
324 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325 return 0;
326 }
327
328 // Immediate is already in its encoded format
329 return MO.getImm();
330 }
331
332 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
334 SmallVectorImpl<MCFixup> &Fixups,
335 const MCSubtargetInfo &STI) const {
336 const MCOperand &MO = MI.getOperand(Op);
337
338 // Support for fixups (MCFixup)
339 if (MO.isExpr()) {
340 const MCExpr *Expr = MO.getExpr();
341 // Fixups resolve to plain values that need to be encoded.
342 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
343 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
344 return 0;
345 }
346 unsigned SoImm = MO.getImm();
347 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
348 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349 return Encoded;
350 }
351
352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
353 SmallVectorImpl<MCFixup> &Fixups,
354 const MCSubtargetInfo &STI) const;
355 template<unsigned Bits, unsigned Shift>
356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
357 SmallVectorImpl<MCFixup> &Fixups,
358 const MCSubtargetInfo &STI) const;
359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
360 SmallVectorImpl<MCFixup> &Fixups,
361 const MCSubtargetInfo &STI) const;
362
363 /// getSORegOpValue - Return an encoded so_reg shifted register value.
364 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
365 SmallVectorImpl<MCFixup> &Fixups,
366 const MCSubtargetInfo &STI) const;
367 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI) const;
370 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
371 SmallVectorImpl<MCFixup> &Fixups,
372 const MCSubtargetInfo &STI) const;
373
374 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI) const {
377 return 64 - MI.getOperand(Op).getImm();
378 }
379
380 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
381 SmallVectorImpl<MCFixup> &Fixups,
382 const MCSubtargetInfo &STI) const;
383
384 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
385 SmallVectorImpl<MCFixup> &Fixups,
386 const MCSubtargetInfo &STI) const;
387 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
388 SmallVectorImpl<MCFixup> &Fixups,
389 const MCSubtargetInfo &STI) const;
390 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const;
393 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
394 SmallVectorImpl<MCFixup> &Fixups,
395 const MCSubtargetInfo &STI) const;
396 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
397 SmallVectorImpl<MCFixup> &Fixups,
398 const MCSubtargetInfo &STI) const;
399
400 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
401 SmallVectorImpl<MCFixup> &Fixups,
402 const MCSubtargetInfo &STI) const;
403 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
404 SmallVectorImpl<MCFixup> &Fixups,
405 const MCSubtargetInfo &STI) const;
406 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
407 SmallVectorImpl<MCFixup> &Fixups,
408 const MCSubtargetInfo &STI) const;
409 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
410 SmallVectorImpl<MCFixup> &Fixups,
411 const MCSubtargetInfo &STI) const;
412
413 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
414 SmallVectorImpl<MCFixup> &Fixups,
415 const MCSubtargetInfo &STI) const;
416
417 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
418 unsigned EncodedValue,
419 const MCSubtargetInfo &STI) const;
420 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
421 unsigned EncodedValue,
422 const MCSubtargetInfo &STI) const;
423 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
424 unsigned EncodedValue,
425 const MCSubtargetInfo &STI) const;
426 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
427 unsigned EncodedValue,
428 const MCSubtargetInfo &STI) const;
429
430 unsigned VFPThumb2PostEncoder(const MCInst &MI,
431 unsigned EncodedValue,
432 const MCSubtargetInfo &STI) const;
433
434 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
435 SmallVectorImpl<MCFixup> &Fixups,
436 const MCSubtargetInfo &STI) const;
437
438 void EmitByte(unsigned char C, raw_ostream &OS) const {
439 OS << (char)C;
440 }
441
442 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
443 // Output the constant in little endian byte order.
444 for (unsigned i = 0; i != Size; ++i) {
445 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
446 EmitByte((Val >> Shift) & 0xff, OS);
447 }
448 }
449
450 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
451 SmallVectorImpl<MCFixup> &Fixups,
452 const MCSubtargetInfo &STI) const override;
453
454 template <bool isNeg, ARM::Fixups fixup>
455 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
456 SmallVectorImpl<MCFixup> &Fixups,
457 const MCSubtargetInfo &STI) const;
458
459 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
460 SmallVectorImpl<MCFixup> &Fixups,
461 const MCSubtargetInfo &STI) const;
462
463 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups,
465 const MCSubtargetInfo &STI) const;
466 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
467 SmallVectorImpl<MCFixup> &Fixups,
468 const MCSubtargetInfo &STI) const;
469 template <unsigned size>
470 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
471 SmallVectorImpl<MCFixup> &Fixups,
472 const MCSubtargetInfo &STI) const;
473 };
474
475 } // end anonymous namespace
476
477 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
478 /// instructions, and rewrite them to their Thumb2 form if we are currently in
479 /// Thumb2 mode.
480 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
481 unsigned EncodedValue,
482 const MCSubtargetInfo &STI) const {
483 if (isThumb2(STI)) {
484 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
485 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
486 // set to 1111.
487 unsigned Bit24 = EncodedValue & 0x01000000;
488 unsigned Bit28 = Bit24 << 4;
489 EncodedValue &= 0xEFFFFFFF;
490 EncodedValue |= Bit28;
491 EncodedValue |= 0x0F000000;
492 }
493
494 return EncodedValue;
495 }
496
497 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
498 /// instructions, and rewrite them to their Thumb2 form if we are currently in
499 /// Thumb2 mode.
500 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
501 unsigned EncodedValue,
502 const MCSubtargetInfo &STI) const {
503 if (isThumb2(STI)) {
504 EncodedValue &= 0xF0FFFFFF;
505 EncodedValue |= 0x09000000;
506 }
507
508 return EncodedValue;
509 }
510
511 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
512 /// instructions, and rewrite them to their Thumb2 form if we are currently in
513 /// Thumb2 mode.
514 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
515 unsigned EncodedValue,
516 const MCSubtargetInfo &STI) const {
517 if (isThumb2(STI)) {
518 EncodedValue &= 0x00FFFFFF;
519 EncodedValue |= 0xEE000000;
520 }
521
522 return EncodedValue;
523 }
524
525 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
526 /// if we are in Thumb2.
527 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
528 unsigned EncodedValue,
529 const MCSubtargetInfo &STI) const {
530 if (isThumb2(STI)) {
531 EncodedValue |= 0xC000000; // Set bits 27-26
532 }
533
534 return EncodedValue;
535 }
536
537 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
538 /// them to their Thumb2 form if we are currently in Thumb2 mode.
539 unsigned ARMMCCodeEmitter::
540 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
541 const MCSubtargetInfo &STI) const {
542 if (isThumb2(STI)) {
543 EncodedValue &= 0x0FFFFFFF;
544 EncodedValue |= 0xE0000000;
545 }
546 return EncodedValue;
547 }
548
549 /// getMachineOpValue - Return binary encoding of operand. If the machine
550 /// operand requires relocation, record the relocation and return zero.
551 unsigned ARMMCCodeEmitter::
552 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
553 SmallVectorImpl<MCFixup> &Fixups,
554 const MCSubtargetInfo &STI) const {
555 if (MO.isReg()) {
556 unsigned Reg = MO.getReg();
557 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
558
559 // In NEON, Q registers are encoded as 2x their register number,
560 // because they're using the same indices as the D registers they
561 // overlap. In MVE, there are no 64-bit vector instructions, so
562 // the encodings all refer to Q-registers by their literal
563 // register number.
564
565 if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
566 return RegNo;
567
568 switch (Reg) {
569 default:
570 return RegNo;
571 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
572 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
573 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
574 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
575 return 2 * RegNo;
576 }
577 } else if (MO.isImm()) {
578 return static_cast<unsigned>(MO.getImm());
579 } else if (MO.isDFPImm()) {
580 return static_cast<unsigned>(APFloat(bit_cast<double>(MO.getDFPImm()))
581 .bitcastToAPInt()
582 .getHiBits(32)
583 .getLimitedValue());
584 }
585
586 llvm_unreachable("Unable to encode MCOperand!");
587 }
588
589 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
590 bool ARMMCCodeEmitter::
591 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
592 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
593 const MCSubtargetInfo &STI) const {
594 const MCOperand &MO = MI.getOperand(OpIdx);
595 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
596
597 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
598
599 int32_t SImm = MO1.getImm();
600 bool isAdd = true;
601
602 // Special value for #-0
603 if (SImm == INT32_MIN) {
604 SImm = 0;
605 isAdd = false;
606 }
607
608 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
609 if (SImm < 0) {
610 SImm = -SImm;
611 isAdd = false;
612 }
613
614 Imm = SImm;
615 return isAdd;
616 }
617
618 /// getBranchTargetOpValue - Helper function to get the branch target operand,
619 /// which is either an immediate or requires a fixup.
620 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
621 unsigned FixupKind,
622 SmallVectorImpl<MCFixup> &Fixups,
623 const MCSubtargetInfo &STI) {
624 const MCOperand &MO = MI.getOperand(OpIdx);
625
626 // If the destination is an immediate, we have nothing to do.
627 if (MO.isImm()) return MO.getImm();
628 assert(MO.isExpr() && "Unexpected branch target type!");
629 const MCExpr *Expr = MO.getExpr();
630 MCFixupKind Kind = MCFixupKind(FixupKind);
631 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
632
633 // All of the information is in the fixup.
634 return 0;
635 }
636
637 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
638 // determined by negating them and XOR'ing them with bit 23.
639 static int32_t encodeThumbBLOffset(int32_t offset) {
640 offset >>= 1;
641 uint32_t S = (offset & 0x800000) >> 23;
642 uint32_t J1 = (offset & 0x400000) >> 22;
643 uint32_t J2 = (offset & 0x200000) >> 21;
644 J1 = (~J1 & 0x1);
645 J2 = (~J2 & 0x1);
646 J1 ^= S;
647 J2 ^= S;
648
649 offset &= ~0x600000;
650 offset |= J1 << 22;
651 offset |= J2 << 21;
652
653 return offset;
654 }
655
656 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
657 uint32_t ARMMCCodeEmitter::
658 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
659 SmallVectorImpl<MCFixup> &Fixups,
660 const MCSubtargetInfo &STI) const {
661 const MCOperand MO = MI.getOperand(OpIdx);
662 if (MO.isExpr())
663 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
664 Fixups, STI);
665 return encodeThumbBLOffset(MO.getImm());
666 }
667
668 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
669 /// BLX branch target.
670 uint32_t ARMMCCodeEmitter::
671 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
672 SmallVectorImpl<MCFixup> &Fixups,
673 const MCSubtargetInfo &STI) const {
674 const MCOperand MO = MI.getOperand(OpIdx);
675 if (MO.isExpr())
676 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
677 Fixups, STI);
678 return encodeThumbBLOffset(MO.getImm());
679 }
680
681 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
682 uint32_t ARMMCCodeEmitter::
683 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
684 SmallVectorImpl<MCFixup> &Fixups,
685 const MCSubtargetInfo &STI) const {
686 const MCOperand MO = MI.getOperand(OpIdx);
687 if (MO.isExpr())
688 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
689 Fixups, STI);
690 return (MO.getImm() >> 1);
691 }
692
693 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
694 uint32_t ARMMCCodeEmitter::
695 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
696 SmallVectorImpl<MCFixup> &Fixups,
697 const MCSubtargetInfo &STI) const {
698 const MCOperand MO = MI.getOperand(OpIdx);
699 if (MO.isExpr())
700 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
701 Fixups, STI);
702 return (MO.getImm() >> 1);
703 }
704
705 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
706 uint32_t ARMMCCodeEmitter::
707 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
708 SmallVectorImpl<MCFixup> &Fixups,
709 const MCSubtargetInfo &STI) const {
710 const MCOperand MO = MI.getOperand(OpIdx);
711 if (MO.isExpr())
712 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
713 return (MO.getImm() >> 1);
714 }
715
716 /// Return true if this branch has a non-always predication
717 static bool HasConditionalBranch(const MCInst &MI) {
718 int NumOp = MI.getNumOperands();
719 if (NumOp >= 2) {
720 for (int i = 0; i < NumOp-1; ++i) {
721 const MCOperand &MCOp1 = MI.getOperand(i);
722 const MCOperand &MCOp2 = MI.getOperand(i + 1);
723 if (MCOp1.isImm() && MCOp2.isReg() &&
724 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
725 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
726 return true;
727 }
728 }
729 }
730 return false;
731 }
732
733 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
734 /// target.
735 uint32_t ARMMCCodeEmitter::
736 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
737 SmallVectorImpl<MCFixup> &Fixups,
738 const MCSubtargetInfo &STI) const {
739 // FIXME: This really, really shouldn't use TargetMachine. We don't want
740 // coupling between MC and TM anywhere we can help it.
741 if (isThumb2(STI))
742 return
743 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
744 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
745 }
746
747 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
748 /// target.
749 uint32_t ARMMCCodeEmitter::
750 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
751 SmallVectorImpl<MCFixup> &Fixups,
752 const MCSubtargetInfo &STI) const {
753 const MCOperand MO = MI.getOperand(OpIdx);
754 if (MO.isExpr()) {
755 if (HasConditionalBranch(MI))
756 return ::getBranchTargetOpValue(MI, OpIdx,
757 ARM::fixup_arm_condbranch, Fixups, STI);
758 return ::getBranchTargetOpValue(MI, OpIdx,
759 ARM::fixup_arm_uncondbranch, Fixups, STI);
760 }
761
762 return MO.getImm() >> 2;
763 }
764
765 uint32_t ARMMCCodeEmitter::
766 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
767 SmallVectorImpl<MCFixup> &Fixups,
768 const MCSubtargetInfo &STI) const {
769 const MCOperand MO = MI.getOperand(OpIdx);
770 if (MO.isExpr()) {
771 if (HasConditionalBranch(MI))
772 return ::getBranchTargetOpValue(MI, OpIdx,
773 ARM::fixup_arm_condbl, Fixups, STI);
774 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
775 }
776
777 return MO.getImm() >> 2;
778 }
779
780 uint32_t ARMMCCodeEmitter::
781 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
782 SmallVectorImpl<MCFixup> &Fixups,
783 const MCSubtargetInfo &STI) const {
784 const MCOperand MO = MI.getOperand(OpIdx);
785 if (MO.isExpr())
786 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
787
788 return MO.getImm() >> 1;
789 }
790
791 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
792 /// immediate branch target.
793 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
794 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
795 const MCSubtargetInfo &STI) const {
796 unsigned Val = 0;
797 const MCOperand MO = MI.getOperand(OpIdx);
798
799 if(MO.isExpr())
800 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
801 else
802 Val = MO.getImm() >> 1;
803
804 bool I = (Val & 0x800000);
805 bool J1 = (Val & 0x400000);
806 bool J2 = (Val & 0x200000);
807 if (I ^ J1)
808 Val &= ~0x400000;
809 else
810 Val |= 0x400000;
811
812 if (I ^ J2)
813 Val &= ~0x200000;
814 else
815 Val |= 0x200000;
816
817 return Val;
818 }
819
820 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
821 /// ADR label target.
822 uint32_t ARMMCCodeEmitter::
823 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
824 SmallVectorImpl<MCFixup> &Fixups,
825 const MCSubtargetInfo &STI) const {
826 const MCOperand MO = MI.getOperand(OpIdx);
827 if (MO.isExpr())
828 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
829 Fixups, STI);
830 int64_t offset = MO.getImm();
831 uint32_t Val = 0x2000;
832
833 int SoImmVal;
834 if (offset == INT32_MIN) {
835 Val = 0x1000;
836 SoImmVal = 0;
837 } else if (offset < 0) {
838 Val = 0x1000;
839 offset *= -1;
840 SoImmVal = ARM_AM::getSOImmVal(offset);
841 if(SoImmVal == -1) {
842 Val = 0x2000;
843 offset *= -1;
844 SoImmVal = ARM_AM::getSOImmVal(offset);
845 }
846 } else {
847 SoImmVal = ARM_AM::getSOImmVal(offset);
848 if(SoImmVal == -1) {
849 Val = 0x1000;
850 offset *= -1;
851 SoImmVal = ARM_AM::getSOImmVal(offset);
852 }
853 }
854
855 assert(SoImmVal != -1 && "Not a valid so_imm value!");
856
857 Val |= SoImmVal;
858 return Val;
859 }
860
861 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
862 /// target.
863 uint32_t ARMMCCodeEmitter::
864 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
865 SmallVectorImpl<MCFixup> &Fixups,
866 const MCSubtargetInfo &STI) const {
867 const MCOperand MO = MI.getOperand(OpIdx);
868 if (MO.isExpr())
869 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
870 Fixups, STI);
871 int32_t Val = MO.getImm();
872 if (Val == INT32_MIN)
873 Val = 0x1000;
874 else if (Val < 0) {
875 Val *= -1;
876 Val |= 0x1000;
877 }
878 return Val;
879 }
880
881 /// getITMaskOpValue - Return the architectural encoding of an IT
882 /// predication mask, given the MCOperand format.
883 uint32_t ARMMCCodeEmitter::
884 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
885 SmallVectorImpl<MCFixup> &Fixups,
886 const MCSubtargetInfo &STI) const {
887 const MCOperand MaskMO = MI.getOperand(OpIdx);
888 assert(MaskMO.isImm() && "Unexpected operand type!");
889
890 unsigned Mask = MaskMO.getImm();
891
892 // IT masks are encoded as a sequence of replacement low-order bits
893 // for the condition code. So if the low bit of the starting
894 // condition code is 1, then we have to flip all the bits above the
895 // terminating bit (which is the lowest 1 bit).
896 assert(OpIdx > 0 && "IT mask appears first!");
897 const MCOperand CondMO = MI.getOperand(OpIdx-1);
898 assert(CondMO.isImm() && "Unexpected operand type!");
899 if (CondMO.getImm() & 1) {
900 unsigned LowBit = Mask & -Mask;
901 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
902 Mask ^= BitsAboveLowBit;
903 }
904
905 return Mask;
906 }
907
908 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
909 /// target.
910 uint32_t ARMMCCodeEmitter::
911 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
912 SmallVectorImpl<MCFixup> &Fixups,
913 const MCSubtargetInfo &STI) const {
914 const MCOperand MO = MI.getOperand(OpIdx);
915 if (MO.isExpr())
916 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
917 Fixups, STI);
918 return MO.getImm();
919 }
920
921 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
922 /// operand.
923 uint32_t ARMMCCodeEmitter::
924 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
925 SmallVectorImpl<MCFixup> &,
926 const MCSubtargetInfo &STI) const {
927 // [Rn, Rm]
928 // {5-3} = Rm
929 // {2-0} = Rn
930 const MCOperand &MO1 = MI.getOperand(OpIdx);
931 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
933 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
934 return (Rm << 3) | Rn;
935 }
936
937 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
938 /// operand.
939 uint32_t
940 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
941 SmallVectorImpl<MCFixup> &Fixups,
942 const MCSubtargetInfo &STI) const {
943 // {4-0} = szimm5
944 // The value we are trying to encode is an immediate between either the
945 // range of [1-7] or [1-15] depending on whether we are dealing with the
946 // u8/s8 or the u16/s16 variants respectively.
947 // This value is encoded as follows, if ShiftImm is the value within those
948 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
949 // or 16.
950
951 unsigned Size, ShiftImm;
952 switch(MI.getOpcode()) {
953 case ARM::MVE_VSHLL_imms16bh:
954 case ARM::MVE_VSHLL_imms16th:
955 case ARM::MVE_VSHLL_immu16bh:
956 case ARM::MVE_VSHLL_immu16th:
957 Size = 16;
958 break;
959 case ARM::MVE_VSHLL_imms8bh:
960 case ARM::MVE_VSHLL_imms8th:
961 case ARM::MVE_VSHLL_immu8bh:
962 case ARM::MVE_VSHLL_immu8th:
963 Size = 8;
964 break;
965 default:
966 llvm_unreachable("Use of operand not supported by this instruction");
967 }
968 ShiftImm = MI.getOperand(OpIdx).getImm();
969 return Size + ShiftImm;
970 }
971
972 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
973 uint32_t ARMMCCodeEmitter::
974 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
975 SmallVectorImpl<MCFixup> &Fixups,
976 const MCSubtargetInfo &STI) const {
977 // {17-13} = reg
978 // {12} = (U)nsigned (add == '1', sub == '0')
979 // {11-0} = imm12
980 unsigned Reg = 0, Imm12 = 0;
981 bool isAdd = true;
982 // If The first operand isn't a register, we have a label reference.
983 const MCOperand &MO = MI.getOperand(OpIdx);
984 if (MO.isReg()) {
985 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
986 if (MO1.isImm()) {
987 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
988 } else if (MO1.isExpr()) {
989 assert(!isThumb(STI) && !isThumb2(STI) &&
990 "Thumb mode requires different encoding");
991 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
992 isAdd = false; // 'U' bit is set as part of the fixup.
993 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
994 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
995 }
996 } else if (MO.isExpr()) {
997 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
998 isAdd = false; // 'U' bit is set as part of the fixup.
999 MCFixupKind Kind;
1000 if (isThumb2(STI))
1001 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
1002 else
1003 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
1004 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
1005
1006 ++MCNumCPRelocations;
1007 } else {
1008 Reg = ARM::PC;
1009 int32_t Offset = MO.getImm();
1010 if (Offset == INT32_MIN) {
1011 Offset = 0;
1012 isAdd = false;
1013 } else if (Offset < 0) {
1014 Offset *= -1;
1015 isAdd = false;
1016 }
1017 Imm12 = Offset;
1018 }
1019 uint32_t Binary = Imm12 & 0xfff;
1020 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1021 if (isAdd)
1022 Binary |= (1 << 12);
1023 Binary |= (Reg << 13);
1024 return Binary;
1025 }
1026
1027 template<unsigned Bits, unsigned Shift>
1028 uint32_t ARMMCCodeEmitter::
1029 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1030 SmallVectorImpl<MCFixup> &Fixups,
1031 const MCSubtargetInfo &STI) const {
1032 // FIXME: The immediate operand should have already been encoded like this
1033 // before ever getting here. The encoder method should just need to combine
1034 // the MI operands for the register and the offset into a single
1035 // representation for the complex operand in the .td file. This isn't just
1036 // style, unfortunately. As-is, we can't represent the distinct encoding
1037 // for #-0.
1038
1039 // {Bits} = (U)nsigned (add == '1', sub == '0')
1040 // {(Bits-1)-0} = immediate
1041 int32_t Imm = MI.getOperand(OpIdx).getImm();
1042 bool isAdd = Imm >= 0;
1043
1044 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1045 if (Imm < 0)
1046 Imm = -(uint32_t)Imm;
1047
1048 Imm >>= Shift;
1049
1050 uint32_t Binary = Imm & ((1U << Bits) - 1);
1051 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1052 if (isAdd)
1053 Binary |= (1U << Bits);
1054 return Binary;
1055 }
1056
1057 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1058 /// operand.
1059 uint32_t ARMMCCodeEmitter::
1060 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1061 SmallVectorImpl<MCFixup> &Fixups,
1062 const MCSubtargetInfo &STI) const {
1063 // {6-3} Rn
1064 // {2-0} Qm
1065 const MCOperand &M0 = MI.getOperand(OpIdx);
1066 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1067
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1069 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1070
1071 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1072
1073 return (Rn << 3) | Qm;
1074 }
1075
1076 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1077 /// operand.
1078 template<int shift>
1079 uint32_t ARMMCCodeEmitter::
1080 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1081 SmallVectorImpl<MCFixup> &Fixups,
1082 const MCSubtargetInfo &STI) const {
1083 // {10-8} Qm
1084 // {7-0} Imm
1085 const MCOperand &M0 = MI.getOperand(OpIdx);
1086 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1087
1088 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1089 int32_t Imm = M1.getImm();
1090
1091 bool isAdd = Imm >= 0;
1092
1093 Imm >>= shift;
1094
1095 if (!isAdd)
1096 Imm = -(uint32_t)Imm;
1097
1098 Imm &= 0x7f;
1099
1100 if (isAdd)
1101 Imm |= 0x80;
1102
1103 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1104
1105 return (Qm << 8) | Imm;
1106 }
1107
1108 /// getT2AddrModeImm8s4OpValue - Return encoding info for
1109 /// 'reg +/- imm8<<2' operand.
1110 uint32_t ARMMCCodeEmitter::
1111 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1112 SmallVectorImpl<MCFixup> &Fixups,
1113 const MCSubtargetInfo &STI) const {
1114 // {12-9} = reg
1115 // {8} = (U)nsigned (add == '1', sub == '0')
1116 // {7-0} = imm8
1117 unsigned Reg, Imm8;
1118 bool isAdd = true;
1119 // If The first operand isn't a register, we have a label reference.
1120 const MCOperand &MO = MI.getOperand(OpIdx);
1121 if (!MO.isReg()) {
1122 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1123 Imm8 = 0;
1124 isAdd = false ; // 'U' bit is set as part of the fixup.
1125
1126 assert(MO.isExpr() && "Unexpected machine operand type!");
1127 const MCExpr *Expr = MO.getExpr();
1128 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1129 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1130
1131 ++MCNumCPRelocations;
1132 } else
1133 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1134
1135 // FIXME: The immediate operand should have already been encoded like this
1136 // before ever getting here. The encoder method should just need to combine
1137 // the MI operands for the register and the offset into a single
1138 // representation for the complex operand in the .td file. This isn't just
1139 // style, unfortunately. As-is, we can't represent the distinct encoding
1140 // for #-0.
1141 uint32_t Binary = (Imm8 >> 2) & 0xff;
1142 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1143 if (isAdd)
1144 Binary |= (1 << 8);
1145 Binary |= (Reg << 9);
1146 return Binary;
1147 }
1148
1149 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1150 /// 'reg +/- imm7<<2' operand.
1151 uint32_t
1152 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1153 SmallVectorImpl<MCFixup> &Fixups,
1154 const MCSubtargetInfo &STI) const {
1155 // {11-8} = reg
1156 // {7} = (A)dd (add == '1', sub == '0')
1157 // {6-0} = imm7
1158 unsigned Reg, Imm7;
1159 // If The first operand isn't a register, we have a label reference.
1160 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1161
1162 // FIXME: The immediate operand should have already been encoded like this
1163 // before ever getting here. The encoder method should just need to combine
1164 // the MI operands for the register and the offset into a single
1165 // representation for the complex operand in the .td file. This isn't just
1166 // style, unfortunately. As-is, we can't represent the distinct encoding
1167 // for #-0.
1168 uint32_t Binary = (Imm7 >> 2) & 0xff;
1169 // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1170 if (isAdd)
1171 Binary |= (1 << 7);
1172 Binary |= (Reg << 8);
1173 return Binary;
1174 }
1175
1176 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1177 /// 'reg + imm8<<2' operand.
1178 uint32_t ARMMCCodeEmitter::
1179 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1180 SmallVectorImpl<MCFixup> &Fixups,
1181 const MCSubtargetInfo &STI) const {
1182 // {11-8} = reg
1183 // {7-0} = imm8
1184 const MCOperand &MO = MI.getOperand(OpIdx);
1185 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1186 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1187 unsigned Imm8 = MO1.getImm();
1188 return (Reg << 8) | Imm8;
1189 }
1190
1191 uint32_t
1192 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1193 SmallVectorImpl<MCFixup> &Fixups,
1194 const MCSubtargetInfo &STI) const {
1195 // {20-16} = imm{15-12}
1196 // {11-0} = imm{11-0}
1197 const MCOperand &MO = MI.getOperand(OpIdx);
1198 if (MO.isImm())
1199 // Hi / lo 16 bits already extracted during earlier passes.
1200 return static_cast<unsigned>(MO.getImm());
1201
1202 // Handle :upper16: and :lower16: assembly prefixes.
1203 const MCExpr *E = MO.getExpr();
1204 MCFixupKind Kind;
1205 if (E->getKind() == MCExpr::Target) {
1206 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1207 E = ARM16Expr->getSubExpr();
1208
1209 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1210 const int64_t Value = MCE->getValue();
1211 if (Value > UINT32_MAX)
1212 report_fatal_error("constant value truncated (limited to 32-bit)");
1213
1214 switch (ARM16Expr->getKind()) {
1215 case ARMMCExpr::VK_ARM_HI16:
1216 return (int32_t(Value) & 0xffff0000) >> 16;
1217 case ARMMCExpr::VK_ARM_LO16:
1218 return (int32_t(Value) & 0x0000ffff);
1219 default: llvm_unreachable("Unsupported ARMFixup");
1220 }
1221 }
1222
1223 switch (ARM16Expr->getKind()) {
1224 default: llvm_unreachable("Unsupported ARMFixup");
1225 case ARMMCExpr::VK_ARM_HI16:
1226 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1227 : ARM::fixup_arm_movt_hi16);
1228 break;
1229 case ARMMCExpr::VK_ARM_LO16:
1230 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1231 : ARM::fixup_arm_movw_lo16);
1232 break;
1233 }
1234
1235 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1236 return 0;
1237 }
1238 // If the expression doesn't have :upper16: or :lower16: on it,
1239 // it's just a plain immediate expression, previously those evaluated to
1240 // the lower 16 bits of the expression regardless of whether
1241 // we have a movt or a movw, but that led to misleadingly results.
1242 // This is disallowed in the AsmParser in validateInstruction()
1243 // so this should never happen.
1244 llvm_unreachable("expression without :upper16: or :lower16:");
1245 }
1246
1247 uint32_t ARMMCCodeEmitter::
1248 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1249 SmallVectorImpl<MCFixup> &Fixups,
1250 const MCSubtargetInfo &STI) const {
1251 const MCOperand &MO = MI.getOperand(OpIdx);
1252 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1253 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1254 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1255 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1256 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1257 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1258 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1259 unsigned SBits = getShiftOp(ShOp);
1260
1261 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1262 // amount. However, it would be an easy mistake to make so check here.
1263 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1264
1265 // {16-13} = Rn
1266 // {12} = isAdd
1267 // {11-0} = shifter
1268 // {3-0} = Rm
1269 // {4} = 0
1270 // {6-5} = type
1271 // {11-7} = imm
1272 uint32_t Binary = Rm;
1273 Binary |= Rn << 13;
1274 Binary |= SBits << 5;
1275 Binary |= ShImm << 7;
1276 if (isAdd)
1277 Binary |= 1 << 12;
1278 return Binary;
1279 }
1280
1281 uint32_t ARMMCCodeEmitter::
1282 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1283 SmallVectorImpl<MCFixup> &Fixups,
1284 const MCSubtargetInfo &STI) const {
1285 // {13} 1 == imm12, 0 == Rm
1286 // {12} isAdd
1287 // {11-0} imm12/Rm
1288 const MCOperand &MO = MI.getOperand(OpIdx);
1289 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1290 unsigned Imm = MO1.getImm();
1291 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1292 bool isReg = MO.getReg() != 0;
1293 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1294 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1295 if (isReg) {
1296 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1297 Binary <<= 7; // Shift amount is bits [11:7]
1298 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1299 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1300 }
1301 return Binary | (isAdd << 12) | (isReg << 13);
1302 }
1303
1304 uint32_t ARMMCCodeEmitter::
1305 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1306 SmallVectorImpl<MCFixup> &Fixups,
1307 const MCSubtargetInfo &STI) const {
1308 // {4} isAdd
1309 // {3-0} Rm
1310 const MCOperand &MO = MI.getOperand(OpIdx);
1311 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1312 bool isAdd = MO1.getImm() != 0;
1313 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1314 }
1315
1316 uint32_t ARMMCCodeEmitter::
1317 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1318 SmallVectorImpl<MCFixup> &Fixups,
1319 const MCSubtargetInfo &STI) const {
1320 // {9} 1 == imm8, 0 == Rm
1321 // {8} isAdd
1322 // {7-4} imm7_4/zero
1323 // {3-0} imm3_0/Rm
1324 const MCOperand &MO = MI.getOperand(OpIdx);
1325 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1326 unsigned Imm = MO1.getImm();
1327 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1328 bool isImm = MO.getReg() == 0;
1329 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1330 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1331 if (!isImm)
1332 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1333 return Imm8 | (isAdd << 8) | (isImm << 9);
1334 }
1335
1336 uint32_t ARMMCCodeEmitter::
1337 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1338 SmallVectorImpl<MCFixup> &Fixups,
1339 const MCSubtargetInfo &STI) const {
1340 // {13} 1 == imm8, 0 == Rm
1341 // {12-9} Rn
1342 // {8} isAdd
1343 // {7-4} imm7_4/zero
1344 // {3-0} imm3_0/Rm
1345 const MCOperand &MO = MI.getOperand(OpIdx);
1346 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1347 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1348
1349 // If The first operand isn't a register, we have a label reference.
1350 if (!MO.isReg()) {
1351 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1352
1353 assert(MO.isExpr() && "Unexpected machine operand type!");
1354 const MCExpr *Expr = MO.getExpr();
1355 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1356 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1357
1358 ++MCNumCPRelocations;
1359 return (Rn << 9) | (1 << 13);
1360 }
1361 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1362 unsigned Imm = MO2.getImm();
1363 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1364 bool isImm = MO1.getReg() == 0;
1365 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1366 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1367 if (!isImm)
1368 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1369 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1370 }
1371
1372 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1373 uint32_t ARMMCCodeEmitter::
1374 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1375 SmallVectorImpl<MCFixup> &Fixups,
1376 const MCSubtargetInfo &STI) const {
1377 // [SP, #imm]
1378 // {7-0} = imm8
1379 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1380 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1381 "Unexpected base register!");
1382
1383 // The immediate is already shifted for the implicit zeroes, so no change
1384 // here.
1385 return MO1.getImm() & 0xff;
1386 }
1387
1388 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1389 uint32_t ARMMCCodeEmitter::
1390 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1391 SmallVectorImpl<MCFixup> &Fixups,
1392 const MCSubtargetInfo &STI) const {
1393 // [Rn, #imm]
1394 // {7-3} = imm5
1395 // {2-0} = Rn
1396 const MCOperand &MO = MI.getOperand(OpIdx);
1397 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1398 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1399 unsigned Imm5 = MO1.getImm();
1400 return ((Imm5 & 0x1f) << 3) | Rn;
1401 }
1402
1403 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1404 uint32_t ARMMCCodeEmitter::
1405 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1406 SmallVectorImpl<MCFixup> &Fixups,
1407 const MCSubtargetInfo &STI) const {
1408 const MCOperand MO = MI.getOperand(OpIdx);
1409 if (MO.isExpr())
1410 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1411 return (MO.getImm() >> 2);
1412 }
1413
1414 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1415 uint32_t ARMMCCodeEmitter::
1416 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1417 SmallVectorImpl<MCFixup> &Fixups,
1418 const MCSubtargetInfo &STI) const {
1419 // {12-9} = reg
1420 // {8} = (U)nsigned (add == '1', sub == '0')
1421 // {7-0} = imm8
1422 unsigned Reg, Imm8;
1423 bool isAdd;
1424 // If The first operand isn't a register, we have a label reference.
1425 const MCOperand &MO = MI.getOperand(OpIdx);
1426 if (!MO.isReg()) {
1427 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1428 Imm8 = 0;
1429 isAdd = false; // 'U' bit is handled as part of the fixup.
1430
1431 assert(MO.isExpr() && "Unexpected machine operand type!");
1432 const MCExpr *Expr = MO.getExpr();
1433 MCFixupKind Kind;
1434 if (isThumb2(STI))
1435 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1436 else
1437 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1438 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1439
1440 ++MCNumCPRelocations;
1441 } else {
1442 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1443 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1444 }
1445
1446 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1447 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1448 if (isAdd)
1449 Binary |= (1 << 8);
1450 Binary |= (Reg << 9);
1451 return Binary;
1452 }
1453
1454 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1455 uint32_t ARMMCCodeEmitter::
1456 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1457 SmallVectorImpl<MCFixup> &Fixups,
1458 const MCSubtargetInfo &STI) const {
1459 // {12-9} = reg
1460 // {8} = (U)nsigned (add == '1', sub == '0')
1461 // {7-0} = imm8
1462 unsigned Reg, Imm8;
1463 bool isAdd;
1464 // If The first operand isn't a register, we have a label reference.
1465 const MCOperand &MO = MI.getOperand(OpIdx);
1466 if (!MO.isReg()) {
1467 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1468 Imm8 = 0;
1469 isAdd = false; // 'U' bit is handled as part of the fixup.
1470
1471 assert(MO.isExpr() && "Unexpected machine operand type!");
1472 const MCExpr *Expr = MO.getExpr();
1473 MCFixupKind Kind;
1474 if (isThumb2(STI))
1475 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1476 else
1477 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1478 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1479
1480 ++MCNumCPRelocations;
1481 } else {
1482 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1483 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1484 }
1485
1486 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1487 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1488 if (isAdd)
1489 Binary |= (1 << 8);
1490 Binary |= (Reg << 9);
1491 return Binary;
1492 }
1493
1494 unsigned ARMMCCodeEmitter::
1495 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1496 SmallVectorImpl<MCFixup> &Fixups,
1497 const MCSubtargetInfo &STI) const {
1498 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1499 // shifted. The second is Rs, the amount to shift by, and the third specifies
1500 // the type of the shift.
1501 //
1502 // {3-0} = Rm.
1503 // {4} = 1
1504 // {6-5} = type
1505 // {11-8} = Rs
1506 // {7} = 0
1507
1508 const MCOperand &MO = MI.getOperand(OpIdx);
1509 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1510 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1511 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1512
1513 // Encode Rm.
1514 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1515
1516 // Encode the shift opcode.
1517 unsigned SBits = 0;
1518 unsigned Rs = MO1.getReg();
1519 if (Rs) {
1520 // Set shift operand (bit[7:4]).
1521 // LSL - 0001
1522 // LSR - 0011
1523 // ASR - 0101
1524 // ROR - 0111
1525 switch (SOpc) {
1526 default: llvm_unreachable("Unknown shift opc!");
1527 case ARM_AM::lsl: SBits = 0x1; break;
1528 case ARM_AM::lsr: SBits = 0x3; break;
1529 case ARM_AM::asr: SBits = 0x5; break;
1530 case ARM_AM::ror: SBits = 0x7; break;
1531 }
1532 }
1533
1534 Binary |= SBits << 4;
1535
1536 // Encode the shift operation Rs.
1537 // Encode Rs bit[11:8].
1538 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1539 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1540 }
1541
1542 unsigned ARMMCCodeEmitter::
1543 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1544 SmallVectorImpl<MCFixup> &Fixups,
1545 const MCSubtargetInfo &STI) const {
1546 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1547 // shifted. The second is the amount to shift by.
1548 //
1549 // {3-0} = Rm.
1550 // {4} = 0
1551 // {6-5} = type
1552 // {11-7} = imm
1553
1554 const MCOperand &MO = MI.getOperand(OpIdx);
1555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1556 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1557
1558 // Encode Rm.
1559 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1560
1561 // Encode the shift opcode.
1562 unsigned SBits = 0;
1563
1564 // Set shift operand (bit[6:4]).
1565 // LSL - 000
1566 // LSR - 010
1567 // ASR - 100
1568 // ROR - 110
1569 // RRX - 110 and bit[11:8] clear.
1570 switch (SOpc) {
1571 default: llvm_unreachable("Unknown shift opc!");
1572 case ARM_AM::lsl: SBits = 0x0; break;
1573 case ARM_AM::lsr: SBits = 0x2; break;
1574 case ARM_AM::asr: SBits = 0x4; break;
1575 case ARM_AM::ror: SBits = 0x6; break;
1576 case ARM_AM::rrx:
1577 Binary |= 0x60;
1578 return Binary;
1579 }
1580
1581 // Encode shift_imm bit[11:7].
1582 Binary |= SBits << 4;
1583 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1584 assert(Offset < 32 && "Offset must be in range 0-31!");
1585 return Binary | (Offset << 7);
1586 }
1587
1588
1589 unsigned ARMMCCodeEmitter::
1590 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1591 SmallVectorImpl<MCFixup> &Fixups,
1592 const MCSubtargetInfo &STI) const {
1593 const MCOperand &MO1 = MI.getOperand(OpNum);
1594 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1595 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1596
1597 // Encoded as [Rn, Rm, imm].
1598 // FIXME: Needs fixup support.
1599 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1600 Value <<= 4;
1601 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1602 Value <<= 2;
1603 Value |= MO3.getImm();
1604
1605 return Value;
1606 }
1607
1608 template<unsigned Bits, unsigned Shift>
1609 unsigned ARMMCCodeEmitter::
1610 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1611 SmallVectorImpl<MCFixup> &Fixups,
1612 const MCSubtargetInfo &STI) const {
1613 const MCOperand &MO1 = MI.getOperand(OpNum);
1614 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1615
1616 // FIXME: Needs fixup support.
1617 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1618
1619 // If the immediate is B bits long, we need B+1 bits in order
1620 // to represent the (inverse of the) sign bit.
1621 Value <<= (Bits + 1);
1622 int32_t tmp = (int32_t)MO2.getImm();
1623 if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1624 tmp = 0;
1625 } else if (tmp < 0) {
1626 tmp = abs(tmp);
1627 } else {
1628 Value |= (1U << Bits); // Set the ADD bit
1629 }
1630 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1631 return Value;
1632 }
1633
1634 unsigned ARMMCCodeEmitter::
1635 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1636 SmallVectorImpl<MCFixup> &Fixups,
1637 const MCSubtargetInfo &STI) const {
1638 const MCOperand &MO1 = MI.getOperand(OpNum);
1639
1640 // FIXME: Needs fixup support.
1641 unsigned Value = 0;
1642 int32_t tmp = (int32_t)MO1.getImm();
1643 if (tmp < 0)
1644 tmp = abs(tmp);
1645 else
1646 Value |= 256; // Set the ADD bit
1647 Value |= tmp & 255;
1648 return Value;
1649 }
1650
1651 unsigned ARMMCCodeEmitter::
1652 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1653 SmallVectorImpl<MCFixup> &Fixups,
1654 const MCSubtargetInfo &STI) const {
1655 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1656 // shifted. The second is the amount to shift by.
1657 //
1658 // {3-0} = Rm.
1659 // {4} = 0
1660 // {6-5} = type
1661 // {11-7} = imm
1662
1663 const MCOperand &MO = MI.getOperand(OpIdx);
1664 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1666
1667 // Encode Rm.
1668 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1669
1670 // Encode the shift opcode.
1671 unsigned SBits = 0;
1672 // Set shift operand (bit[6:4]).
1673 // LSL - 000
1674 // LSR - 010
1675 // ASR - 100
1676 // ROR - 110
1677 switch (SOpc) {
1678 default: llvm_unreachable("Unknown shift opc!");
1679 case ARM_AM::lsl: SBits = 0x0; break;
1680 case ARM_AM::lsr: SBits = 0x2; break;
1681 case ARM_AM::asr: SBits = 0x4; break;
1682 case ARM_AM::rrx: LLVM_FALLTHROUGH;
1683 case ARM_AM::ror: SBits = 0x6; break;
1684 }
1685
1686 Binary |= SBits << 4;
1687 if (SOpc == ARM_AM::rrx)
1688 return Binary;
1689
1690 // Encode shift_imm bit[11:7].
1691 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1692 }
1693
1694 unsigned ARMMCCodeEmitter::
1695 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1696 SmallVectorImpl<MCFixup> &Fixups,
1697 const MCSubtargetInfo &STI) const {
1698 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1699 // msb of the mask.
1700 const MCOperand &MO = MI.getOperand(Op);
1701 uint32_t v = ~MO.getImm();
1702 uint32_t lsb = countTrailingZeros(v);
1703 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1704 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1705 return lsb | (msb << 5);
1706 }
1707
1708 unsigned ARMMCCodeEmitter::
1709 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1710 SmallVectorImpl<MCFixup> &Fixups,
1711 const MCSubtargetInfo &STI) const {
1712 // VLDM/VSTM/VSCCLRM:
1713 // {12-8} = Vd
1714 // {7-0} = Number of registers
1715 //
1716 // LDM/STM:
1717 // {15-0} = Bitfield of GPRs.
1718 unsigned Reg = MI.getOperand(Op).getReg();
1719 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1720 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1721
1722 unsigned Binary = 0;
1723
1724 if (SPRRegs || DPRRegs) {
1725 // VLDM/VSTM/VSCCLRM
1726 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1727 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1728 Binary |= (RegNo & 0x1f) << 8;
1729
1730 // Ignore VPR
1731 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1732 --NumRegs;
1733 if (SPRRegs)
1734 Binary |= NumRegs;
1735 else
1736 Binary |= NumRegs * 2;
1737 } else {
1738 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1739 assert(is_sorted(drop_begin(MI, Op),
1740 [&](const MCOperand &LHS, const MCOperand &RHS) {
1741 return MRI.getEncodingValue(LHS.getReg()) <
1742 MRI.getEncodingValue(RHS.getReg());
1743 }));
1744 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1745 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1746 Binary |= 1 << RegNo;
1747 }
1748 }
1749
1750 return Binary;
1751 }
1752
1753 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1754 /// with the alignment operand.
1755 unsigned ARMMCCodeEmitter::
1756 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1757 SmallVectorImpl<MCFixup> &Fixups,
1758 const MCSubtargetInfo &STI) const {
1759 const MCOperand &Reg = MI.getOperand(Op);
1760 const MCOperand &Imm = MI.getOperand(Op + 1);
1761
1762 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1763 unsigned Align = 0;
1764
1765 switch (Imm.getImm()) {
1766 default: break;
1767 case 2:
1768 case 4:
1769 case 8: Align = 0x01; break;
1770 case 16: Align = 0x02; break;
1771 case 32: Align = 0x03; break;
1772 }
1773
1774 return RegNo | (Align << 4);
1775 }
1776
1777 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1778 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1779 unsigned ARMMCCodeEmitter::
1780 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1781 SmallVectorImpl<MCFixup> &Fixups,
1782 const MCSubtargetInfo &STI) const {
1783 const MCOperand &Reg = MI.getOperand(Op);
1784 const MCOperand &Imm = MI.getOperand(Op + 1);
1785
1786 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1787 unsigned Align = 0;
1788
1789 switch (Imm.getImm()) {
1790 default: break;
1791 case 8:
1792 case 16:
1793 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1794 case 2: Align = 0x00; break;
1795 case 4: Align = 0x03; break;
1796 }
1797
1798 return RegNo | (Align << 4);
1799 }
1800
1801
1802 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1803 /// alignment operand for use in VLD-dup instructions. This is the same as
1804 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1805 /// different for VLD4-dup.
1806 unsigned ARMMCCodeEmitter::
1807 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1808 SmallVectorImpl<MCFixup> &Fixups,
1809 const MCSubtargetInfo &STI) const {
1810 const MCOperand &Reg = MI.getOperand(Op);
1811 const MCOperand &Imm = MI.getOperand(Op + 1);
1812
1813 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1814 unsigned Align = 0;
1815
1816 switch (Imm.getImm()) {
1817 default: break;
1818 case 2:
1819 case 4:
1820 case 8: Align = 0x01; break;
1821 case 16: Align = 0x03; break;
1822 }
1823
1824 return RegNo | (Align << 4);
1825 }
1826
1827 unsigned ARMMCCodeEmitter::
1828 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1829 SmallVectorImpl<MCFixup> &Fixups,
1830 const MCSubtargetInfo &STI) const {
1831 const MCOperand &MO = MI.getOperand(Op);
1832 if (MO.getReg() == 0) return 0x0D;
1833 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1834 }
1835
1836 unsigned ARMMCCodeEmitter::
1837 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1838 SmallVectorImpl<MCFixup> &Fixups,
1839 const MCSubtargetInfo &STI) const {
1840 return 8 - MI.getOperand(Op).getImm();
1841 }
1842
1843 unsigned ARMMCCodeEmitter::
1844 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1845 SmallVectorImpl<MCFixup> &Fixups,
1846 const MCSubtargetInfo &STI) const {
1847 return 16 - MI.getOperand(Op).getImm();
1848 }
1849
1850 unsigned ARMMCCodeEmitter::
1851 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1852 SmallVectorImpl<MCFixup> &Fixups,
1853 const MCSubtargetInfo &STI) const {
1854 return 32 - MI.getOperand(Op).getImm();
1855 }
1856
1857 unsigned ARMMCCodeEmitter::
1858 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1859 SmallVectorImpl<MCFixup> &Fixups,
1860 const MCSubtargetInfo &STI) const {
1861 return 64 - MI.getOperand(Op).getImm();
1862 }
1863
1864 void ARMMCCodeEmitter::
1865 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1866 SmallVectorImpl<MCFixup> &Fixups,
1867 const MCSubtargetInfo &STI) const {
1868 // Pseudo instructions don't get encoded.
1869 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1870 uint64_t TSFlags = Desc.TSFlags;
1871 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1872 return;
1873
1874 int Size;
1875 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1876 Size = Desc.getSize();
1877 else
1878 llvm_unreachable("Unexpected instruction size!");
1879
1880 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1881 // Thumb 32-bit wide instructions need to emit the high order halfword
1882 // first.
1883 if (isThumb(STI) && Size == 4) {
1884 EmitConstant(Binary >> 16, 2, OS);
1885 EmitConstant(Binary & 0xffff, 2, OS);
1886 } else
1887 EmitConstant(Binary, Size, OS);
1888 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1889 }
1890
1891 template <bool isNeg, ARM::Fixups fixup>
1892 uint32_t
1893 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1894 SmallVectorImpl<MCFixup> &Fixups,
1895 const MCSubtargetInfo &STI) const {
1896 const MCOperand MO = MI.getOperand(OpIdx);
1897 if (MO.isExpr())
1898 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1899 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1900 }
1901
1902 uint32_t
1903 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1904 SmallVectorImpl<MCFixup> &Fixups,
1905 const MCSubtargetInfo &STI) const {
1906 const MCOperand MO = MI.getOperand(OpIdx);
1907 const MCOperand BranchMO = MI.getOperand(0);
1908
1909 if (MO.isExpr()) {
1910 assert(BranchMO.isExpr());
1911 const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1912 MO.getExpr(), BranchMO.getExpr(), CTX);
1913 MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1914 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1915 return 0;
1916 }
1917
1918 assert(MO.isImm() && BranchMO.isImm());
1919 int Diff = MO.getImm() - BranchMO.getImm();
1920 assert(Diff == 4 || Diff == 2);
1921
1922 return Diff == 4;
1923 }
1924
1925 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1926 SmallVectorImpl<MCFixup> &Fixups,
1927 const MCSubtargetInfo &STI)const {
1928 const MCOperand MO = MI.getOperand(OpIdx);
1929 assert(MO.isImm() && "Unexpected operand type!");
1930
1931 int Value = MO.getImm();
1932 int Imm = 0;
1933
1934 // VPT Masks are actually encoded as a series of invert/don't invert bits,
1935 // rather than true/false bits.
1936 unsigned PrevBit = 0;
1937 for (int i = 3; i >= 0; --i) {
1938 unsigned Bit = (Value >> i) & 1;
1939
1940 // Check if we are at the end of the mask.
1941 if ((Value & ~(~0U << i)) == 0) {
1942 Imm |= (1 << i);
1943 break;
1944 }
1945
1946 // Convert the bit in the mask based on the previous bit.
1947 if (Bit != PrevBit)
1948 Imm |= (1 << i);
1949
1950 PrevBit = Bit;
1951 }
1952
1953 return Imm;
1954 }
1955
1956 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1957 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1958 const MCSubtargetInfo &STI) const {
1959
1960 const MCOperand MO = MI.getOperand(OpIdx);
1961 assert(MO.isImm() && "Unexpected operand type!");
1962
1963 switch (MO.getImm()) {
1964 default:
1965 assert(0 && "Unexpected Condition!");
1966 return 0;
1967 case ARMCC::HS:
1968 case ARMCC::EQ:
1969 return 0;
1970 case ARMCC::HI:
1971 case ARMCC::NE:
1972 return 1;
1973 case ARMCC::GE:
1974 return 4;
1975 case ARMCC::LT:
1976 return 5;
1977 case ARMCC::GT:
1978 return 6;
1979 case ARMCC::LE:
1980 return 7;
1981 }
1982 }
1983
1984 uint32_t ARMMCCodeEmitter::
1985 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1986 SmallVectorImpl<MCFixup> &Fixups,
1987 const MCSubtargetInfo &STI) const {
1988 const MCOperand &MO = MI.getOperand(OpIdx);
1989 assert(MO.isImm() && "Unexpected operand type!");
1990 return countTrailingZeros((uint64_t)MO.getImm());
1991 }
1992
1993 template <unsigned start>
1994 uint32_t ARMMCCodeEmitter::
1995 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
1996 SmallVectorImpl<MCFixup> &Fixups,
1997 const MCSubtargetInfo &STI) const {
1998 const MCOperand MO = MI.getOperand(OpIdx);
1999 assert(MO.isImm() && "Unexpected operand type!");
2000
2001 int Value = MO.getImm();
2002 return Value - start;
2003 }
2004
2005 #include "ARMGenMCCodeEmitter.inc"
2006
2007 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
2008 const MCRegisterInfo &MRI,
2009 MCContext &Ctx) {
2010 return new ARMMCCodeEmitter(MCII, Ctx, true);
2011 }
2012
2013 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
2014 const MCRegisterInfo &MRI,
2015 MCContext &Ctx) {
2016 return new ARMMCCodeEmitter(MCII, Ctx, false);
2017 }
LLVM monorepo