llvm/lib/Target/AVR/AVRTargetMachine.cpp

   1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the AVR specific subclass of TargetMachine.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AVRTargetMachine.h"
  14
  15 #include "llvm/CodeGen/Passes.h"
  16 #include "llvm/CodeGen/TargetPassConfig.h"
  17 #include "llvm/IR/LegacyPassManager.h"
  18 #include "llvm/IR/Module.h"
  19 #include "llvm/Support/TargetRegistry.h"
  20
  21 #include "AVR.h"
  22 #include "AVRTargetObjectFile.h"
  23 #include "MCTargetDesc/AVRMCTargetDesc.h"
  24 #include "TargetInfo/AVRTargetInfo.h"
  25
  26 namespace llvm {
  27
  28 static const char *AVRDataLayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
  29
  30 /// Processes a CPU name.
  31 static StringRef getCPU(StringRef CPU) {
  32   if (CPU.empty() || CPU == "generic") {
  33     return "avr2";
  34   }
  35
  36   return CPU;
  37 }
  38
  39 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
  40   return RM.getValueOr(Reloc::Static);
  41 }
  42
  43 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
  44                                    StringRef CPU, StringRef FS,
  45                                    const TargetOptions &Options,
  46                                    Optional<Reloc::Model> RM,
  47                                    Optional<CodeModel::Model> CM,
  48                                    CodeGenOpt::Level OL, bool JIT)
  49     : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
  50                         getEffectiveRelocModel(RM),
  51                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
  52       SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {
  53   this->TLOF = std::make_unique<AVRTargetObjectFile>();
  54   initAsmInfo();
  55 }
  56
  57 namespace {
  58 /// AVR Code Generator Pass Configuration Options.
  59 class AVRPassConfig : public TargetPassConfig {
  60 public:
  61   AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
  62       : TargetPassConfig(TM, PM) {}
  63
  64   AVRTargetMachine &getAVRTargetMachine() const {
  65     return getTM<AVRTargetMachine>();
  66   }
  67
  68   void addIRPasses() override;
  69   bool addInstSelector() override;
  70   void addPreSched2() override;
  71   void addPreEmitPass() override;
  72   void addPreRegAlloc() override;
  73 };
  74 } // namespace
  75
  76 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
  77   return new AVRPassConfig(*this, PM);
  78 }
  79
  80 void AVRPassConfig::addIRPasses() {
  81   // Expand instructions like
  82   //   %result = shl i32 %n, %amount
  83   // to a loop so that library calls are avoided.
  84   addPass(createAVRShiftExpandPass());
  85
  86   TargetPassConfig::addIRPasses();
  87 }
  88
  89 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
  90   // Register the target.
  91   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
  92
  93   auto &PR = *PassRegistry::getPassRegistry();
  94   initializeAVRExpandPseudoPass(PR);
  95   initializeAVRRelaxMemPass(PR);
  96   initializeAVRShiftExpandPass(PR);
  97 }
  98
  99 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
 100   return &SubTarget;
 101 }
 102
 103 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
 104   return &SubTarget;
 105 }
 106
 107 //===----------------------------------------------------------------------===//
 108 // Pass Pipeline Configuration
 109 //===----------------------------------------------------------------------===//
 110
 111 bool AVRPassConfig::addInstSelector() {
 112   // Install an instruction selector.
 113   addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
 114   // Create the frame analyzer pass used by the PEI pass.
 115   addPass(createAVRFrameAnalyzerPass());
 116
 117   return false;
 118 }
 119
 120 void AVRPassConfig::addPreRegAlloc() {
 121   // Create the dynalloc SP save/restore pass to handle variable sized allocas.
 122   addPass(createAVRDynAllocaSRPass());
 123 }
 124
 125 void AVRPassConfig::addPreSched2() {
 126   addPass(createAVRRelaxMemPass());
 127   addPass(createAVRExpandPseudoPass());
 128 }
 129
 130 void AVRPassConfig::addPreEmitPass() {
 131   // Must run branch selection immediately preceding the asm printer.
 132   addPass(&BranchRelaxationPassID);
 133 }
 134
 135 } // end of namespace llvm