llvm/lib/Target/BPF/BPFISelLowering.h

   1 //===-- BPFISelLowering.h - BPF DAG Lowering Interface ----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that BPF uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
  15 #define LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
  16
  17 #include "BPF.h"
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/CodeGen/TargetLowering.h"
  20
  21 namespace llvm {
  22 class BPFSubtarget;
  23 namespace BPFISD {
  24 enum NodeType : unsigned {
  25   FIRST_NUMBER = ISD::BUILTIN_OP_END,
  26   RET_FLAG,
  27   CALL,
  28   SELECT_CC,
  29   BR_CC,
  30   Wrapper,
  31   MEMCPY
  32 };
  33 }
  34
  35 class BPFTargetLowering : public TargetLowering {
  36 public:
  37   explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
  38
  39   // Provide custom lowering hooks for some operations.
  40   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  41
  42   // This method returns the name of a target specific DAG node.
  43   const char *getTargetNodeName(unsigned Opcode) const override;
  44
  45   // This method decides whether folding a constant offset
  46   // with the given GlobalAddress is legal.
  47   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
  48
  49   BPFTargetLowering::ConstraintType
  50   getConstraintType(StringRef Constraint) const override;
  51
  52   std::pair<unsigned, const TargetRegisterClass *>
  53   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
  54                                StringRef Constraint, MVT VT) const override;
  55
  56   MachineBasicBlock *
  57   EmitInstrWithCustomInserter(MachineInstr &MI,
  58                               MachineBasicBlock *BB) const override;
  59
  60   bool getHasAlu32() const { return HasAlu32; }
  61   bool getHasJmp32() const { return HasJmp32; }
  62   bool getHasJmpExt() const { return HasJmpExt; }
  63
  64   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
  65                          EVT VT) const override;
  66
  67   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
  68
  69 private:
  70   // Control Instruction Selection Features
  71   bool HasAlu32;
  72   bool HasJmp32;
  73   bool HasJmpExt;
  74
  75   SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
  76   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
  77   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
  78
  79   // Lower the result values of a call, copying them out of physregs into vregs
  80   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
  81                           CallingConv::ID CallConv, bool IsVarArg,
  82                           const SmallVectorImpl<ISD::InputArg> &Ins,
  83                           const SDLoc &DL, SelectionDAG &DAG,
  84                           SmallVectorImpl<SDValue> &InVals) const;
  85
  86   // Maximum number of arguments to a call
  87   static const unsigned MaxArgs;
  88
  89   // Lower a call into CALLSEQ_START - BPFISD:CALL - CALLSEQ_END chain
  90   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
  91                     SmallVectorImpl<SDValue> &InVals) const override;
  92
  93   // Lower incoming arguments, copy physregs into vregs
  94   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
  95                                bool IsVarArg,
  96                                const SmallVectorImpl<ISD::InputArg> &Ins,
  97                                const SDLoc &DL, SelectionDAG &DAG,
  98                                SmallVectorImpl<SDValue> &InVals) const override;
  99
 100   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 101                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 102                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 103                       SelectionDAG &DAG) const override;
 104
 105   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
 106                           SelectionDAG &DAG) const override;
 107
 108   EVT getOptimalMemOpType(const MemOp &Op,
 109                           const AttributeList &FuncAttributes) const override {
 110     return Op.size() >= 8 ? MVT::i64 : MVT::i32;
 111   }
 112
 113   bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; }
 114
 115   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 116                                          Type *Ty) const override {
 117     return true;
 118   }
 119
 120   // Prevent reducing load width during SelectionDag phase.
 121   // Otherwise, we may transform the following
 122   //   ctx = ctx + reloc_offset
 123   //   ... (*(u32 *)ctx) & 0x8000...
 124   // to
 125   //   ctx = ctx + reloc_offset
 126   //   ... (*(u8 *)(ctx + 1)) & 0x80 ...
 127   // which will be rejected by the verifier.
 128   bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
 129                              EVT NewVT) const override {
 130     return false;
 131   }
 132
 133   // isTruncateFree - Return true if it's free to truncate a value of
 134   // type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate
 135   // a i64 value in register R1 to i32 by referencing its sub-register W1.
 136   bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 137   bool isTruncateFree(EVT VT1, EVT VT2) const override;
 138
 139   // For 32bit ALU result zext to 64bit is free.
 140   bool isZExtFree(Type *Ty1, Type *Ty2) const override;
 141   bool isZExtFree(EVT VT1, EVT VT2) const override;
 142
 143   unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg,
 144                          bool isSigned) const;
 145
 146   MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
 147                                                         MachineBasicBlock *BB)
 148                                                         const;
 149
 150 };
 151 }
 152
 153 #endif