[ORC] Add std::tuple support to SimplePackedSerialization.
[llvm-project.git] / llvm / lib / Target / Hexagon / HexagonDepTimingClasses.h
blob1afe0f00e2bad55b296a18276f4269dc90d75fe6
1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // Automatically generated file, do not edit!
9 //===----------------------------------------------------------------------===//
12 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H
13 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H
15 #include "HexagonInstrInfo.h"
17 namespace llvm {
19 inline bool is_TC1(unsigned SchedClass) {
20 switch (SchedClass) {
21 case Hexagon::Sched::tc_112d30d6:
22 case Hexagon::Sched::tc_151bf368:
23 case Hexagon::Sched::tc_1c2c7a4a:
24 case Hexagon::Sched::tc_1d41f8b7:
25 case Hexagon::Sched::tc_23708a21:
26 case Hexagon::Sched::tc_24f426ab:
27 case Hexagon::Sched::tc_2f573607:
28 case Hexagon::Sched::tc_388f9897:
29 case Hexagon::Sched::tc_3d14a17b:
30 case Hexagon::Sched::tc_3fbf1042:
31 case Hexagon::Sched::tc_407e96f9:
32 case Hexagon::Sched::tc_42ff66ba:
33 case Hexagon::Sched::tc_4a55d03c:
34 case Hexagon::Sched::tc_5502c366:
35 case Hexagon::Sched::tc_55b33fda:
36 case Hexagon::Sched::tc_56a124a7:
37 case Hexagon::Sched::tc_57a55b54:
38 case Hexagon::Sched::tc_59a7822c:
39 case Hexagon::Sched::tc_5b347363:
40 case Hexagon::Sched::tc_5da50c4b:
41 case Hexagon::Sched::tc_60e324ff:
42 case Hexagon::Sched::tc_651cbe02:
43 case Hexagon::Sched::tc_6fc5dbea:
44 case Hexagon::Sched::tc_711c805f:
45 case Hexagon::Sched::tc_713b66bf:
46 case Hexagon::Sched::tc_9124c04f:
47 case Hexagon::Sched::tc_9c52f549:
48 case Hexagon::Sched::tc_9e27f2f9:
49 case Hexagon::Sched::tc_9f6cd987:
50 case Hexagon::Sched::tc_a1297125:
51 case Hexagon::Sched::tc_a7a13fac:
52 case Hexagon::Sched::tc_b837298f:
53 case Hexagon::Sched::tc_c57d9f39:
54 case Hexagon::Sched::tc_d33e5eee:
55 case Hexagon::Sched::tc_decdde8a:
56 case Hexagon::Sched::tc_ed03645c:
57 case Hexagon::Sched::tc_eeda4109:
58 case Hexagon::Sched::tc_ef921005:
59 case Hexagon::Sched::tc_f999c66e:
60 return true;
61 default:
62 return false;
66 inline bool is_TC2(unsigned SchedClass) {
67 switch (SchedClass) {
68 case Hexagon::Sched::tc_01d44cb2:
69 case Hexagon::Sched::tc_0dfac0a7:
70 case Hexagon::Sched::tc_1fcb8495:
71 case Hexagon::Sched::tc_20131976:
72 case Hexagon::Sched::tc_2c13e7f5:
73 case Hexagon::Sched::tc_3edca78f:
74 case Hexagon::Sched::tc_5e4cf0e8:
75 case Hexagon::Sched::tc_65279839:
76 case Hexagon::Sched::tc_7401744f:
77 case Hexagon::Sched::tc_84a7500d:
78 case Hexagon::Sched::tc_8a825db2:
79 case Hexagon::Sched::tc_8b5bd4f5:
80 case Hexagon::Sched::tc_95a33176:
81 case Hexagon::Sched::tc_9b3c0462:
82 case Hexagon::Sched::tc_a08b630b:
83 case Hexagon::Sched::tc_a4e22bbd:
84 case Hexagon::Sched::tc_a7bdb22c:
85 case Hexagon::Sched::tc_bb831a7c:
86 case Hexagon::Sched::tc_c20701f0:
87 case Hexagon::Sched::tc_d3632d88:
88 case Hexagon::Sched::tc_d61dfdc3:
89 case Hexagon::Sched::tc_e3d699e3:
90 case Hexagon::Sched::tc_f098b237:
91 case Hexagon::Sched::tc_f34c1c21:
92 return true;
93 default:
94 return false;
98 inline bool is_TC2early(unsigned SchedClass) {
99 switch (SchedClass) {
100 case Hexagon::Sched::tc_45f9d1be:
101 case Hexagon::Sched::tc_a4ee89db:
102 return true;
103 default:
104 return false;
108 inline bool is_TC3x(unsigned SchedClass) {
109 switch (SchedClass) {
110 case Hexagon::Sched::tc_01e1be3b:
111 case Hexagon::Sched::tc_1248597c:
112 case Hexagon::Sched::tc_197dce51:
113 case Hexagon::Sched::tc_28e55c6f:
114 case Hexagon::Sched::tc_2c3e17fc:
115 case Hexagon::Sched::tc_38382228:
116 case Hexagon::Sched::tc_38e0bae9:
117 case Hexagon::Sched::tc_4abdbdc6:
118 case Hexagon::Sched::tc_503ce0f3:
119 case Hexagon::Sched::tc_556f6577:
120 case Hexagon::Sched::tc_5a4b5e58:
121 case Hexagon::Sched::tc_6ae3426b:
122 case Hexagon::Sched::tc_6d861a95:
123 case Hexagon::Sched::tc_788b1d09:
124 case Hexagon::Sched::tc_7f8ae742:
125 case Hexagon::Sched::tc_9406230a:
126 case Hexagon::Sched::tc_a154b476:
127 case Hexagon::Sched::tc_a38c45dc:
128 case Hexagon::Sched::tc_c21d7447:
129 case Hexagon::Sched::tc_d7718fbe:
130 case Hexagon::Sched::tc_db596beb:
131 case Hexagon::Sched::tc_f0cdeccf:
132 case Hexagon::Sched::tc_fae9dfa5:
133 return true;
134 default:
135 return false;
139 inline bool is_TC4x(unsigned SchedClass) {
140 switch (SchedClass) {
141 case Hexagon::Sched::tc_02fe1c65:
142 case Hexagon::Sched::tc_0a195f2c:
143 case Hexagon::Sched::tc_7f7f45f5:
144 case Hexagon::Sched::tc_9783714b:
145 case Hexagon::Sched::tc_9e72dc89:
146 case Hexagon::Sched::tc_9edb7c77:
147 case Hexagon::Sched::tc_f0e8e832:
148 case Hexagon::Sched::tc_f7569068:
149 return true;
150 default:
151 return false;
154 } // namespace llvm
156 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H