1 //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 // Hexagon specific code to select Hexagon machine instructions for
9 // SelectionDAG operations.
10 //===----------------------------------------------------------------------===//
12 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
13 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/Support/CodeGen.h"
25 class MachineFunction
;
26 class HexagonInstrInfo
;
27 class HexagonRegisterInfo
;
29 class HexagonDAGToDAGISel
: public SelectionDAGISel
{
30 const HexagonSubtarget
*HST
;
31 const HexagonInstrInfo
*HII
;
32 const HexagonRegisterInfo
*HRI
;
34 explicit HexagonDAGToDAGISel(HexagonTargetMachine
&tm
,
35 CodeGenOpt::Level OptLevel
)
36 : SelectionDAGISel(tm
, OptLevel
), HST(nullptr), HII(nullptr),
39 bool runOnMachineFunction(MachineFunction
&MF
) override
{
40 // Reset the subtarget each time through.
41 HST
= &MF
.getSubtarget
<HexagonSubtarget
>();
42 HII
= HST
->getInstrInfo();
43 HRI
= HST
->getRegisterInfo();
44 SelectionDAGISel::runOnMachineFunction(MF
);
49 bool ComplexPatternFuncMutatesDAG() const override
{
52 void PreprocessISelDAG() override
;
53 void emitFunctionEntryCode() override
;
55 void Select(SDNode
*N
) override
;
57 // Complex Pattern Selectors.
58 inline bool SelectAddrGA(SDValue
&N
, SDValue
&R
);
59 inline bool SelectAddrGP(SDValue
&N
, SDValue
&R
);
60 inline bool SelectAnyImm(SDValue
&N
, SDValue
&R
);
61 inline bool SelectAnyInt(SDValue
&N
, SDValue
&R
);
62 bool SelectAnyImmediate(SDValue
&N
, SDValue
&R
, Align Alignment
);
63 bool SelectGlobalAddress(SDValue
&N
, SDValue
&R
, bool UseGP
, Align Alignment
);
64 bool SelectAddrFI(SDValue
&N
, SDValue
&R
);
65 bool DetectUseSxtw(SDValue
&N
, SDValue
&R
);
67 inline bool SelectAnyImm0(SDValue
&N
, SDValue
&R
);
68 inline bool SelectAnyImm1(SDValue
&N
, SDValue
&R
);
69 inline bool SelectAnyImm2(SDValue
&N
, SDValue
&R
);
70 inline bool SelectAnyImm3(SDValue
&N
, SDValue
&R
);
72 StringRef
getPassName() const override
{
73 return "Hexagon DAG->DAG Pattern Instruction Selection";
76 // Generate a machine instruction node corresponding to the circ/brev
78 MachineSDNode
*LoadInstrForLoadIntrinsic(SDNode
*IntN
);
79 // Given the circ/brev load intrinsic and the already generated machine
80 // instruction, generate the appropriate store (that is a part of the
81 // intrinsic's functionality).
82 SDNode
*StoreInstrForLoadIntrinsic(MachineSDNode
*LoadN
, SDNode
*IntN
);
84 void SelectFrameIndex(SDNode
*N
);
85 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
86 /// inline asm expressions.
87 bool SelectInlineAsmMemoryOperand(const SDValue
&Op
,
88 unsigned ConstraintID
,
89 std::vector
<SDValue
> &OutOps
) override
;
90 bool tryLoadOfLoadIntrinsic(LoadSDNode
*N
);
91 bool SelectBrevLdIntrinsic(SDNode
*IntN
);
92 bool SelectNewCircIntrinsic(SDNode
*IntN
);
93 void SelectLoad(SDNode
*N
);
94 void SelectIndexedLoad(LoadSDNode
*LD
, const SDLoc
&dl
);
95 void SelectIndexedStore(StoreSDNode
*ST
, const SDLoc
&dl
);
96 void SelectStore(SDNode
*N
);
97 void SelectSHL(SDNode
*N
);
98 void SelectZeroExtend(SDNode
*N
);
99 void SelectIntrinsicWChain(SDNode
*N
);
100 void SelectIntrinsicWOChain(SDNode
*N
);
101 void SelectConstant(SDNode
*N
);
102 void SelectConstantFP(SDNode
*N
);
103 void SelectV65Gather(SDNode
*N
);
104 void SelectV65GatherPred(SDNode
*N
);
105 void SelectHVXDualOutput(SDNode
*N
);
106 void SelectAddSubCarry(SDNode
*N
);
107 void SelectVAlign(SDNode
*N
);
108 void SelectVAlignAddr(SDNode
*N
);
109 void SelectTypecast(SDNode
*N
);
110 void SelectP2D(SDNode
*N
);
111 void SelectD2P(SDNode
*N
);
112 void SelectQ2V(SDNode
*N
);
113 void SelectV2Q(SDNode
*N
);
115 // Include the declarations autogenerated from the selection patterns.
116 #define GET_DAGISEL_DECL
117 #include "HexagonGenDAGISel.inc"
120 // This is really only to get access to ReplaceNode (which is a protected
121 // member). Any other members used by HvxSelector can be moved around to
122 // make them accessible).
123 friend struct HvxSelector
;
125 SDValue
selectUndef(const SDLoc
&dl
, MVT ResTy
) {
126 SDNode
*U
= CurDAG
->getMachineNode(TargetOpcode::IMPLICIT_DEF
, dl
, ResTy
);
127 return SDValue(U
, 0);
130 void SelectHvxShuffle(SDNode
*N
);
131 void SelectHvxRor(SDNode
*N
);
132 void SelectHvxVAlign(SDNode
*N
);
134 bool keepsLowBits(const SDValue
&Val
, unsigned NumBits
, SDValue
&Src
);
135 bool isAlignedMemNode(const MemSDNode
*N
) const;
136 bool isSmallStackStore(const StoreSDNode
*N
) const;
137 bool isPositiveHalfWord(const SDNode
*N
) const;
138 bool hasOneUse(const SDNode
*N
) const;
140 // DAG preprocessing functions.
141 void ppSimplifyOrSelect0(std::vector
<SDNode
*> &&Nodes
);
142 void ppAddrReorderAddShl(std::vector
<SDNode
*> &&Nodes
);
143 void ppAddrRewriteAndSrl(std::vector
<SDNode
*> &&Nodes
);
144 void ppHoistZextI1(std::vector
<SDNode
*> &&Nodes
);
146 // Function postprocessing.
149 SmallDenseMap
<SDNode
*,int> RootWeights
;
150 SmallDenseMap
<SDNode
*,int> RootHeights
;
151 SmallDenseMap
<const Value
*,int> GAUsesInFunction
;
152 int getWeight(SDNode
*N
);
153 int getHeight(SDNode
*N
);
154 SDValue
getMultiplierForSHL(SDNode
*N
);
155 SDValue
factorOutPowerOf2(SDValue V
, unsigned Power
);
156 unsigned getUsesInFunction(const Value
*V
);
157 SDValue
balanceSubTree(SDNode
*N
, bool Factorize
= false);
158 void rebalanceAddressTrees();
159 }; // end HexagonDAGToDAGISel
162 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H