llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

   1 //===-- M68kBaseInfo.h - Top level definitions for M68k MC --*- C++ -*-----===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file contains small standalone helper functions and enum definitions
  11 /// for the M68k target useful for the compiler back-end and the MC
  12 /// libraries.  As such, it deliberately does not include references to LLVM
  13 /// core code gen types, passes, etc..
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef LLVM_LIB_TARGET_M68K_MCTARGETDESC_M68KBASEINFO_H
  18 #define LLVM_LIB_TARGET_M68K_MCTARGETDESC_M68KBASEINFO_H
  19
  20 #include "M68kMCTargetDesc.h"
  21
  22 #include "llvm/MC/MCExpr.h"
  23 #include "llvm/Support/DataTypes.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25
  26 #define GET_INSTRINFO_MI_OPS_INFO
  27 #define GET_INSTRINFO_OPERAND_TYPES_ENUM
  28 #define GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
  29 #include "M68kGenInstrInfo.inc"
  30
  31 namespace llvm {
  32
  33 namespace M68k {
  34
  35 /// Enums for memory operand decoding. Supports these forms:
  36 /// (d,An)
  37 /// (d,An,Xn)
  38 /// ([bd,An],Xn,od)
  39 /// ([bd,An,Xn],od)
  40 /// TODO Implement scaling other than 1
  41 enum { MemDisp = 0, MemBase = 1, MemIndex = 2, MemOuter = 3 };
  42
  43 /// Enums for pc-relative memory operand decoding. Supports these forms:
  44 /// (d,PC)
  45 /// (d,PC,Xn)
  46 /// ([bd,PC],Xn,od)
  47 /// ([bd,PC,Xn],od)
  48 enum { PCRelDisp = 0, PCRelIndex = 1, PCRelOuter = 2 };
  49 } // namespace M68k
  50
  51 namespace M68kBeads {
  52 enum {
  53   Ctrl = 0x0,
  54   Bits1 = 0x1,
  55   Bits2 = 0x2,
  56   Bits3 = 0x3,
  57   Bits4 = 0x4,
  58   DAReg = 0x5,
  59   DA = 0x6,
  60   Reg = 0x7,
  61   DReg = 0x8,
  62   Disp8 = 0x9,
  63   Imm8 = 0xA,
  64   Imm16 = 0xB,
  65   Imm32 = 0xC,
  66   Imm3 = 0xD,
  67 };
  68
  69 // Ctrl payload
  70 enum {
  71   Term = 0x0,
  72   Ignore = 0x1,
  73 };
  74 } // namespace M68kBeads
  75
  76 /// This namespace holds all of the target specific flags that instruction info
  77 /// tracks.
  78 namespace M68kII {
  79 /// Target Operand Flag enum.
  80 enum TOF {
  81
  82   MO_NO_FLAG,
  83
  84   /// On a symbol operand this indicates that the immediate is the absolute
  85   /// address of the symbol.
  86   MO_ABSOLUTE_ADDRESS,
  87
  88   /// On a symbol operand this indicates that the immediate is the pc-relative
  89   /// address of the symbol.
  90   MO_PC_RELATIVE_ADDRESS,
  91
  92   /// On a symbol operand this indicates that the immediate is the offset to
  93   /// the GOT entry for the symbol name from the base of the GOT.
  94   ///
  95   ///    name@GOT
  96   MO_GOT,
  97
  98   /// On a symbol operand this indicates that the immediate is the offset to
  99   /// the location of the symbol name from the base of the GOT.
 100   ///
 101   ///    name@GOTOFF
 102   MO_GOTOFF,
 103
 104   /// On a symbol operand this indicates that the immediate is offset to the
 105   /// GOT entry for the symbol name from the current code location.
 106   ///
 107   ///    name@GOTPCREL
 108   MO_GOTPCREL,
 109
 110   /// On a symbol operand this indicates that the immediate is offset to the
 111   /// PLT entry of symbol name from the current code location.
 112   ///
 113   ///    name@PLT
 114   MO_PLT,
 115 }; // enum TOF
 116
 117 /// Return true if the specified TargetFlag operand is a reference to a stub
 118 /// for a global, not the global itself.
 119 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
 120   switch (TargetFlag) {
 121   default:
 122     return false;
 123   case M68kII::MO_GOTPCREL: // pc-relative GOT reference.
 124   case M68kII::MO_GOT:      // normal GOT reference.
 125     return true;
 126   }
 127 }
 128
 129 /// Return True if the specified GlobalValue is a direct reference for a
 130 /// symbol.
 131 inline static bool isDirectGlobalReference(unsigned char Flag) {
 132   switch (Flag) {
 133   default:
 134     return false;
 135   case M68kII::MO_NO_FLAG:
 136   case M68kII::MO_ABSOLUTE_ADDRESS:
 137   case M68kII::MO_PC_RELATIVE_ADDRESS:
 138     return true;
 139   }
 140 }
 141
 142 /// Return true if the specified global value reference is relative to a 32-bit
 143 /// PIC base (M68kISD::GLOBAL_BASE_REG). If this is true, the addressing mode
 144 /// has the PIC base register added in.
 145 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
 146   switch (TargetFlag) {
 147   default:
 148     return false;
 149   case M68kII::MO_GOTOFF: // isPICStyleGOT: local global.
 150   case M68kII::MO_GOT:    // isPICStyleGOT: other global.
 151     return true;
 152   }
 153 }
 154
 155 /// Return True if the specified GlobalValue requires PC addressing mode.
 156 inline static bool isPCRelGlobalReference(unsigned char Flag) {
 157   switch (Flag) {
 158   default:
 159     return false;
 160   case M68kII::MO_GOTPCREL:
 161   case M68kII::MO_PC_RELATIVE_ADDRESS:
 162     return true;
 163   }
 164 }
 165
 166 /// Return True if the Block is referenced using PC
 167 inline static bool isPCRelBlockReference(unsigned char Flag) {
 168   switch (Flag) {
 169   default:
 170     return false;
 171   case M68kII::MO_PC_RELATIVE_ADDRESS:
 172     return true;
 173   }
 174 }
 175
 176 static inline bool isAddressRegister(unsigned RegNo) {
 177   switch (RegNo) {
 178   case M68k::WA0:
 179   case M68k::WA1:
 180   case M68k::WA2:
 181   case M68k::WA3:
 182   case M68k::WA4:
 183   case M68k::WA5:
 184   case M68k::WA6:
 185   case M68k::WSP:
 186   case M68k::A0:
 187   case M68k::A1:
 188   case M68k::A2:
 189   case M68k::A3:
 190   case M68k::A4:
 191   case M68k::A5:
 192   case M68k::A6:
 193   case M68k::SP:
 194     return true;
 195   default:
 196     return false;
 197   }
 198 }
 199
 200 static inline bool hasMultiMIOperands(unsigned Op, unsigned LogicalOpIdx) {
 201   return M68k::getLogicalOperandSize(Op, LogicalOpIdx) > 1;
 202 }
 203
 204 static inline unsigned getMaskedSpillRegister(unsigned order) {
 205   switch (order) {
 206   default:
 207     return 0;
 208   case 0:
 209     return M68k::D0;
 210   case 1:
 211     return M68k::D1;
 212   case 2:
 213     return M68k::D2;
 214   case 3:
 215     return M68k::D3;
 216   case 4:
 217     return M68k::D4;
 218   case 5:
 219     return M68k::D5;
 220   case 6:
 221     return M68k::D6;
 222   case 7:
 223     return M68k::D7;
 224   case 8:
 225     return M68k::A0;
 226   case 9:
 227     return M68k::A1;
 228   case 10:
 229     return M68k::A2;
 230   case 11:
 231     return M68k::A3;
 232   case 12:
 233     return M68k::A4;
 234   case 13:
 235     return M68k::A5;
 236   case 14:
 237     return M68k::A6;
 238   case 15:
 239     return M68k::SP;
 240   }
 241 }
 242
 243 } // namespace M68kII
 244
 245 } // namespace llvm
 246
 247 #endif