llvm/lib/Target/Mips/MipsFastISel.cpp

   1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file defines the MIPS-specific support for the FastISel class.
  11 /// Some of the target-specific code is generated by tablegen in the file
  12 /// MipsGenFastISel.inc, which is #included here.
  13 ///
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "MCTargetDesc/MipsABIInfo.h"
  17 #include "MCTargetDesc/MipsBaseInfo.h"
  18 #include "MipsCCState.h"
  19 #include "MipsISelLowering.h"
  20 #include "MipsInstrInfo.h"
  21 #include "MipsMachineFunction.h"
  22 #include "MipsSubtarget.h"
  23 #include "MipsTargetMachine.h"
  24 #include "llvm/ADT/APInt.h"
  25 #include "llvm/ADT/ArrayRef.h"
  26 #include "llvm/ADT/DenseMap.h"
  27 #include "llvm/ADT/SmallVector.h"
  28 #include "llvm/Analysis/TargetLibraryInfo.h"
  29 #include "llvm/CodeGen/CallingConvLower.h"
  30 #include "llvm/CodeGen/FastISel.h"
  31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
  32 #include "llvm/CodeGen/ISDOpcodes.h"
  33 #include "llvm/CodeGen/MachineBasicBlock.h"
  34 #include "llvm/CodeGen/MachineFrameInfo.h"
  35 #include "llvm/CodeGen/MachineInstrBuilder.h"
  36 #include "llvm/CodeGen/MachineMemOperand.h"
  37 #include "llvm/CodeGen/MachineRegisterInfo.h"
  38 #include "llvm/CodeGen/TargetInstrInfo.h"
  39 #include "llvm/CodeGen/TargetLowering.h"
  40 #include "llvm/CodeGen/ValueTypes.h"
  41 #include "llvm/IR/Attributes.h"
  42 #include "llvm/IR/CallingConv.h"
  43 #include "llvm/IR/Constant.h"
  44 #include "llvm/IR/Constants.h"
  45 #include "llvm/IR/DataLayout.h"
  46 #include "llvm/IR/Function.h"
  47 #include "llvm/IR/GetElementPtrTypeIterator.h"
  48 #include "llvm/IR/GlobalValue.h"
  49 #include "llvm/IR/GlobalVariable.h"
  50 #include "llvm/IR/InstrTypes.h"
  51 #include "llvm/IR/Instruction.h"
  52 #include "llvm/IR/Instructions.h"
  53 #include "llvm/IR/IntrinsicInst.h"
  54 #include "llvm/IR/Operator.h"
  55 #include "llvm/IR/Type.h"
  56 #include "llvm/IR/User.h"
  57 #include "llvm/IR/Value.h"
  58 #include "llvm/MC/MCContext.h"
  59 #include "llvm/MC/MCInstrDesc.h"
  60 #include "llvm/MC/MCRegisterInfo.h"
  61 #include "llvm/MC/MCSymbol.h"
  62 #include "llvm/Support/Casting.h"
  63 #include "llvm/Support/Compiler.h"
  64 #include "llvm/Support/Debug.h"
  65 #include "llvm/Support/ErrorHandling.h"
  66 #include "llvm/Support/MachineValueType.h"
  67 #include "llvm/Support/MathExtras.h"
  68 #include "llvm/Support/raw_ostream.h"
  69 #include <algorithm>
  70 #include <array>
  71 #include <cassert>
  72 #include <cstdint>
  73
  74 #define DEBUG_TYPE "mips-fastisel"
  75
  76 using namespace llvm;
  77
  78 extern cl::opt<bool> EmitJalrReloc;
  79
  80 namespace {
  81
  82 class MipsFastISel final : public FastISel {
  83
  84   // All possible address modes.
  85   class Address {
  86   public:
  87     using BaseKind = enum { RegBase, FrameIndexBase };
  88
  89   private:
  90     BaseKind Kind = RegBase;
  91     union {
  92       unsigned Reg;
  93       int FI;
  94     } Base;
  95
  96     int64_t Offset = 0;
  97
  98     const GlobalValue *GV = nullptr;
  99
 100   public:
 101     // Innocuous defaults for our address.
 102     Address() { Base.Reg = 0; }
 103
 104     void setKind(BaseKind K) { Kind = K; }
 105     BaseKind getKind() const { return Kind; }
 106     bool isRegBase() const { return Kind == RegBase; }
 107     bool isFIBase() const { return Kind == FrameIndexBase; }
 108
 109     void setReg(unsigned Reg) {
 110       assert(isRegBase() && "Invalid base register access!");
 111       Base.Reg = Reg;
 112     }
 113
 114     unsigned getReg() const {
 115       assert(isRegBase() && "Invalid base register access!");
 116       return Base.Reg;
 117     }
 118
 119     void setFI(unsigned FI) {
 120       assert(isFIBase() && "Invalid base frame index access!");
 121       Base.FI = FI;
 122     }
 123
 124     unsigned getFI() const {
 125       assert(isFIBase() && "Invalid base frame index access!");
 126       return Base.FI;
 127     }
 128
 129     void setOffset(int64_t Offset_) { Offset = Offset_; }
 130     int64_t getOffset() const { return Offset; }
 131     void setGlobalValue(const GlobalValue *G) { GV = G; }
 132     const GlobalValue *getGlobalValue() { return GV; }
 133   };
 134
 135   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
 136   /// make the right decision when generating code for different targets.
 137   const TargetMachine &TM;
 138   const MipsSubtarget *Subtarget;
 139   const TargetInstrInfo &TII;
 140   const TargetLowering &TLI;
 141   MipsFunctionInfo *MFI;
 142
 143   // Convenience variables to avoid some queries.
 144   LLVMContext *Context;
 145
 146   bool fastLowerArguments() override;
 147   bool fastLowerCall(CallLoweringInfo &CLI) override;
 148   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
 149
 150   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
 151   // floating point but not reject doing fast-isel in other
 152   // situations
 153
 154 private:
 155   // Selection routines.
 156   bool selectLogicalOp(const Instruction *I);
 157   bool selectLoad(const Instruction *I);
 158   bool selectStore(const Instruction *I);
 159   bool selectBranch(const Instruction *I);
 160   bool selectSelect(const Instruction *I);
 161   bool selectCmp(const Instruction *I);
 162   bool selectFPExt(const Instruction *I);
 163   bool selectFPTrunc(const Instruction *I);
 164   bool selectFPToInt(const Instruction *I, bool IsSigned);
 165   bool selectRet(const Instruction *I);
 166   bool selectTrunc(const Instruction *I);
 167   bool selectIntExt(const Instruction *I);
 168   bool selectShift(const Instruction *I);
 169   bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
 170
 171   // Utility helper routines.
 172   bool isTypeLegal(Type *Ty, MVT &VT);
 173   bool isTypeSupported(Type *Ty, MVT &VT);
 174   bool isLoadTypeLegal(Type *Ty, MVT &VT);
 175   bool computeAddress(const Value *Obj, Address &Addr);
 176   bool computeCallAddress(const Value *V, Address &Addr);
 177   void simplifyAddress(Address &Addr);
 178
 179   // Emit helper routines.
 180   bool emitCmp(unsigned DestReg, const CmpInst *CI);
 181   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
 182                 unsigned Alignment = 0);
 183   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
 184                  MachineMemOperand *MMO = nullptr);
 185   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
 186                  unsigned Alignment = 0);
 187   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
 188   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
 189
 190                   bool IsZExt);
 191   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
 192
 193   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
 194   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
 195                        unsigned DestReg);
 196   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
 197                        unsigned DestReg);
 198
 199   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
 200
 201   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
 202                          const Value *RHS);
 203
 204   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
 205   unsigned materializeGV(const GlobalValue *GV, MVT VT);
 206   unsigned materializeInt(const Constant *C, MVT VT);
 207   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
 208   unsigned materializeExternalCallSym(MCSymbol *Syn);
 209
 210   MachineInstrBuilder emitInst(unsigned Opc) {
 211     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
 212   }
 213
 214   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
 215     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
 216                    DstReg);
 217   }
 218
 219   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
 220                                     unsigned MemReg, int64_t MemOffset) {
 221     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
 222   }
 223
 224   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
 225                                    unsigned MemReg, int64_t MemOffset) {
 226     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
 227   }
 228
 229   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
 230                            const TargetRegisterClass *RC,
 231                            unsigned Op0, unsigned Op1);
 232
 233   // for some reason, this default is not generated by tablegen
 234   // so we explicitly generate it here.
 235   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
 236                              unsigned Op0, uint64_t imm1, uint64_t imm2,
 237                              unsigned Op3) {
 238     return 0;
 239   }
 240
 241   // Call handling routines.
 242 private:
 243   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
 244   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
 245                        unsigned &NumBytes);
 246   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
 247
 248   const MipsABIInfo &getABI() const {
 249     return static_cast<const MipsTargetMachine &>(TM).getABI();
 250   }
 251
 252 public:
 253   // Backend specific FastISel code.
 254   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
 255                         const TargetLibraryInfo *libInfo)
 256       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
 257         Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
 258         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
 259     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
 260     Context = &funcInfo.Fn->getContext();
 261     UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
 262   }
 263
 264   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
 265   unsigned fastMaterializeConstant(const Constant *C) override;
 266   bool fastSelectInstruction(const Instruction *I) override;
 267
 268 #include "MipsGenFastISel.inc"
 269 };
 270
 271 } // end anonymous namespace
 272
 273 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
 274                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
 275                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
 276
 277 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
 278                             CCValAssign::LocInfo LocInfo,
 279                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
 280   llvm_unreachable("should not be called");
 281 }
 282
 283 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
 284                             CCValAssign::LocInfo LocInfo,
 285                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
 286   llvm_unreachable("should not be called");
 287 }
 288
 289 #include "MipsGenCallingConv.inc"
 290
 291 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
 292   return CC_MipsO32;
 293 }
 294
 295 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
 296                                      const Value *LHS, const Value *RHS) {
 297   // Canonicalize immediates to the RHS first.
 298   if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
 299     std::swap(LHS, RHS);
 300
 301   unsigned Opc;
 302   switch (ISDOpc) {
 303   case ISD::AND:
 304     Opc = Mips::AND;
 305     break;
 306   case ISD::OR:
 307     Opc = Mips::OR;
 308     break;
 309   case ISD::XOR:
 310     Opc = Mips::XOR;
 311     break;
 312   default:
 313     llvm_unreachable("unexpected opcode");
 314   }
 315
 316   unsigned LHSReg = getRegForValue(LHS);
 317   if (!LHSReg)
 318     return 0;
 319
 320   unsigned RHSReg;
 321   if (const auto *C = dyn_cast<ConstantInt>(RHS))
 322     RHSReg = materializeInt(C, MVT::i32);
 323   else
 324     RHSReg = getRegForValue(RHS);
 325   if (!RHSReg)
 326     return 0;
 327
 328   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
 329   if (!ResultReg)
 330     return 0;
 331
 332   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
 333   return ResultReg;
 334 }
 335
 336 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
 337   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
 338          "Alloca should always return a pointer.");
 339
 340   DenseMap<const AllocaInst *, int>::iterator SI =
 341       FuncInfo.StaticAllocaMap.find(AI);
 342
 343   if (SI != FuncInfo.StaticAllocaMap.end()) {
 344     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
 345     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
 346             ResultReg)
 347         .addFrameIndex(SI->second)
 348         .addImm(0);
 349     return ResultReg;
 350   }
 351
 352   return 0;
 353 }
 354
 355 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
 356   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
 357     return 0;
 358   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
 359   const ConstantInt *CI = cast<ConstantInt>(C);
 360   return materialize32BitInt(CI->getZExtValue(), RC);
 361 }
 362
 363 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
 364                                            const TargetRegisterClass *RC) {
 365   unsigned ResultReg = createResultReg(RC);
 366
 367   if (isInt<16>(Imm)) {
 368     unsigned Opc = Mips::ADDiu;
 369     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
 370     return ResultReg;
 371   } else if (isUInt<16>(Imm)) {
 372     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
 373     return ResultReg;
 374   }
 375   unsigned Lo = Imm & 0xFFFF;
 376   unsigned Hi = (Imm >> 16) & 0xFFFF;
 377   if (Lo) {
 378     // Both Lo and Hi have nonzero bits.
 379     unsigned TmpReg = createResultReg(RC);
 380     emitInst(Mips::LUi, TmpReg).addImm(Hi);
 381     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
 382   } else {
 383     emitInst(Mips::LUi, ResultReg).addImm(Hi);
 384   }
 385   return ResultReg;
 386 }
 387
 388 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
 389   if (UnsupportedFPMode)
 390     return 0;
 391   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
 392   if (VT == MVT::f32) {
 393     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
 394     unsigned DestReg = createResultReg(RC);
 395     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
 396     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
 397     return DestReg;
 398   } else if (VT == MVT::f64) {
 399     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
 400     unsigned DestReg = createResultReg(RC);
 401     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
 402     unsigned TempReg2 =
 403         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
 404     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
 405     return DestReg;
 406   }
 407   return 0;
 408 }
 409
 410 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
 411   // For now 32-bit only.
 412   if (VT != MVT::i32)
 413     return 0;
 414   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
 415   unsigned DestReg = createResultReg(RC);
 416   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
 417   bool IsThreadLocal = GVar && GVar->isThreadLocal();
 418   // TLS not supported at this time.
 419   if (IsThreadLocal)
 420     return 0;
 421   emitInst(Mips::LW, DestReg)
 422       .addReg(MFI->getGlobalBaseReg(*MF))
 423       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
 424   if ((GV->hasInternalLinkage() ||
 425        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
 426     unsigned TempReg = createResultReg(RC);
 427     emitInst(Mips::ADDiu, TempReg)
 428         .addReg(DestReg)
 429         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
 430     DestReg = TempReg;
 431   }
 432   return DestReg;
 433 }
 434
 435 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
 436   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
 437   unsigned DestReg = createResultReg(RC);
 438   emitInst(Mips::LW, DestReg)
 439       .addReg(MFI->getGlobalBaseReg(*MF))
 440       .addSym(Sym, MipsII::MO_GOT);
 441   return DestReg;
 442 }
 443
 444 // Materialize a constant into a register, and return the register
 445 // number (or zero if we failed to handle it).
 446 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
 447   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 448
 449   // Only handle simple types.
 450   if (!CEVT.isSimple())
 451     return 0;
 452   MVT VT = CEVT.getSimpleVT();
 453
 454   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
 455     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
 456   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
 457     return materializeGV(GV, VT);
 458   else if (isa<ConstantInt>(C))
 459     return materializeInt(C, VT);
 460
 461   return 0;
 462 }
 463
 464 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
 465   const User *U = nullptr;
 466   unsigned Opcode = Instruction::UserOp1;
 467   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
 468     // Don't walk into other basic blocks unless the object is an alloca from
 469     // another block, otherwise it may not have a virtual register assigned.
 470     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
 471         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
 472       Opcode = I->getOpcode();
 473       U = I;
 474     }
 475   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
 476     Opcode = C->getOpcode();
 477     U = C;
 478   }
 479   switch (Opcode) {
 480   default:
 481     break;
 482   case Instruction::BitCast:
 483     // Look through bitcasts.
 484     return computeAddress(U->getOperand(0), Addr);
 485   case Instruction::GetElementPtr: {
 486     Address SavedAddr = Addr;
 487     int64_t TmpOffset = Addr.getOffset();
 488     // Iterate through the GEP folding the constants into offsets where
 489     // we can.
 490     gep_type_iterator GTI = gep_type_begin(U);
 491     for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
 492          ++i, ++GTI) {
 493       const Value *Op = *i;
 494       if (StructType *STy = GTI.getStructTypeOrNull()) {
 495         const StructLayout *SL = DL.getStructLayout(STy);
 496         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
 497         TmpOffset += SL->getElementOffset(Idx);
 498       } else {
 499         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
 500         while (true) {
 501           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
 502             // Constant-offset addressing.
 503             TmpOffset += CI->getSExtValue() * S;
 504             break;
 505           }
 506           if (canFoldAddIntoGEP(U, Op)) {
 507             // A compatible add with a constant operand. Fold the constant.
 508             ConstantInt *CI =
 509                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
 510             TmpOffset += CI->getSExtValue() * S;
 511             // Iterate on the other operand.
 512             Op = cast<AddOperator>(Op)->getOperand(0);
 513             continue;
 514           }
 515           // Unsupported
 516           goto unsupported_gep;
 517         }
 518       }
 519     }
 520     // Try to grab the base operand now.
 521     Addr.setOffset(TmpOffset);
 522     if (computeAddress(U->getOperand(0), Addr))
 523       return true;
 524     // We failed, restore everything and try the other options.
 525     Addr = SavedAddr;
 526   unsupported_gep:
 527     break;
 528   }
 529   case Instruction::Alloca: {
 530     const AllocaInst *AI = cast<AllocaInst>(Obj);
 531     DenseMap<const AllocaInst *, int>::iterator SI =
 532         FuncInfo.StaticAllocaMap.find(AI);
 533     if (SI != FuncInfo.StaticAllocaMap.end()) {
 534       Addr.setKind(Address::FrameIndexBase);
 535       Addr.setFI(SI->second);
 536       return true;
 537     }
 538     break;
 539   }
 540   }
 541   Addr.setReg(getRegForValue(Obj));
 542   return Addr.getReg() != 0;
 543 }
 544
 545 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
 546   const User *U = nullptr;
 547   unsigned Opcode = Instruction::UserOp1;
 548
 549   if (const auto *I = dyn_cast<Instruction>(V)) {
 550     // Check if the value is defined in the same basic block. This information
 551     // is crucial to know whether or not folding an operand is valid.
 552     if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
 553       Opcode = I->getOpcode();
 554       U = I;
 555     }
 556   } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
 557     Opcode = C->getOpcode();
 558     U = C;
 559   }
 560
 561   switch (Opcode) {
 562   default:
 563     break;
 564   case Instruction::BitCast:
 565     // Look past bitcasts if its operand is in the same BB.
 566       return computeCallAddress(U->getOperand(0), Addr);
 567     break;
 568   case Instruction::IntToPtr:
 569     // Look past no-op inttoptrs if its operand is in the same BB.
 570     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
 571         TLI.getPointerTy(DL))
 572       return computeCallAddress(U->getOperand(0), Addr);
 573     break;
 574   case Instruction::PtrToInt:
 575     // Look past no-op ptrtoints if its operand is in the same BB.
 576     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
 577       return computeCallAddress(U->getOperand(0), Addr);
 578     break;
 579   }
 580
 581   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
 582     Addr.setGlobalValue(GV);
 583     return true;
 584   }
 585
 586   // If all else fails, try to materialize the value in a register.
 587   if (!Addr.getGlobalValue()) {
 588     Addr.setReg(getRegForValue(V));
 589     return Addr.getReg() != 0;
 590   }
 591
 592   return false;
 593 }
 594
 595 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
 596   EVT evt = TLI.getValueType(DL, Ty, true);
 597   // Only handle simple types.
 598   if (evt == MVT::Other || !evt.isSimple())
 599     return false;
 600   VT = evt.getSimpleVT();
 601
 602   // Handle all legal types, i.e. a register that will directly hold this
 603   // value.
 604   return TLI.isTypeLegal(VT);
 605 }
 606
 607 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
 608   if (Ty->isVectorTy())
 609     return false;
 610
 611   if (isTypeLegal(Ty, VT))
 612     return true;
 613
 614   // If this is a type than can be sign or zero-extended to a basic operation
 615   // go ahead and accept it now.
 616   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
 617     return true;
 618
 619   return false;
 620 }
 621
 622 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
 623   if (isTypeLegal(Ty, VT))
 624     return true;
 625   // We will extend this in a later patch:
 626   //   If this is a type than can be sign or zero-extended to a basic operation
 627   //   go ahead and accept it now.
 628   if (VT == MVT::i8 || VT == MVT::i16)
 629     return true;
 630   return false;
 631 }
 632
 633 // Because of how EmitCmp is called with fast-isel, you can
 634 // end up with redundant "andi" instructions after the sequences emitted below.
 635 // We should try and solve this issue in the future.
 636 //
 637 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
 638   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
 639   bool IsUnsigned = CI->isUnsigned();
 640   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
 641   if (LeftReg == 0)
 642     return false;
 643   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
 644   if (RightReg == 0)
 645     return false;
 646   CmpInst::Predicate P = CI->getPredicate();
 647
 648   switch (P) {
 649   default:
 650     return false;
 651   case CmpInst::ICMP_EQ: {
 652     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 653     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
 654     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
 655     break;
 656   }
 657   case CmpInst::ICMP_NE: {
 658     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 659     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
 660     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
 661     break;
 662   }
 663   case CmpInst::ICMP_UGT:
 664     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
 665     break;
 666   case CmpInst::ICMP_ULT:
 667     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
 668     break;
 669   case CmpInst::ICMP_UGE: {
 670     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 671     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
 672     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
 673     break;
 674   }
 675   case CmpInst::ICMP_ULE: {
 676     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 677     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
 678     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
 679     break;
 680   }
 681   case CmpInst::ICMP_SGT:
 682     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
 683     break;
 684   case CmpInst::ICMP_SLT:
 685     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
 686     break;
 687   case CmpInst::ICMP_SGE: {
 688     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 689     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
 690     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
 691     break;
 692   }
 693   case CmpInst::ICMP_SLE: {
 694     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
 695     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
 696     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
 697     break;
 698   }
 699   case CmpInst::FCMP_OEQ:
 700   case CmpInst::FCMP_UNE:
 701   case CmpInst::FCMP_OLT:
 702   case CmpInst::FCMP_OLE:
 703   case CmpInst::FCMP_OGT:
 704   case CmpInst::FCMP_OGE: {
 705     if (UnsupportedFPMode)
 706       return false;
 707     bool IsFloat = Left->getType()->isFloatTy();
 708     bool IsDouble = Left->getType()->isDoubleTy();
 709     if (!IsFloat && !IsDouble)
 710       return false;
 711     unsigned Opc, CondMovOpc;
 712     switch (P) {
 713     case CmpInst::FCMP_OEQ:
 714       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
 715       CondMovOpc = Mips::MOVT_I;
 716       break;
 717     case CmpInst::FCMP_UNE:
 718       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
 719       CondMovOpc = Mips::MOVF_I;
 720       break;
 721     case CmpInst::FCMP_OLT:
 722       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
 723       CondMovOpc = Mips::MOVT_I;
 724       break;
 725     case CmpInst::FCMP_OLE:
 726       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
 727       CondMovOpc = Mips::MOVT_I;
 728       break;
 729     case CmpInst::FCMP_OGT:
 730       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
 731       CondMovOpc = Mips::MOVF_I;
 732       break;
 733     case CmpInst::FCMP_OGE:
 734       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
 735       CondMovOpc = Mips::MOVF_I;
 736       break;
 737     default:
 738       llvm_unreachable("Only switching of a subset of CCs.");
 739     }
 740     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
 741     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
 742     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
 743     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
 744     emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
 745                  .addReg(RightReg);
 746     emitInst(CondMovOpc, ResultReg)
 747         .addReg(RegWithOne)
 748         .addReg(Mips::FCC0)
 749         .addReg(RegWithZero);
 750     break;
 751   }
 752   }
 753   return true;
 754 }
 755
 756 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
 757                             unsigned Alignment) {
 758   //
 759   // more cases will be handled here in following patches.
 760   //
 761   unsigned Opc;
 762   switch (VT.SimpleTy) {
 763   case MVT::i32:
 764     ResultReg = createResultReg(&Mips::GPR32RegClass);
 765     Opc = Mips::LW;
 766     break;
 767   case MVT::i16:
 768     ResultReg = createResultReg(&Mips::GPR32RegClass);
 769     Opc = Mips::LHu;
 770     break;
 771   case MVT::i8:
 772     ResultReg = createResultReg(&Mips::GPR32RegClass);
 773     Opc = Mips::LBu;
 774     break;
 775   case MVT::f32:
 776     if (UnsupportedFPMode)
 777       return false;
 778     ResultReg = createResultReg(&Mips::FGR32RegClass);
 779     Opc = Mips::LWC1;
 780     break;
 781   case MVT::f64:
 782     if (UnsupportedFPMode)
 783       return false;
 784     ResultReg = createResultReg(&Mips::AFGR64RegClass);
 785     Opc = Mips::LDC1;
 786     break;
 787   default:
 788     return false;
 789   }
 790   if (Addr.isRegBase()) {
 791     simplifyAddress(Addr);
 792     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
 793     return true;
 794   }
 795   if (Addr.isFIBase()) {
 796     unsigned FI = Addr.getFI();
 797     int64_t Offset = Addr.getOffset();
 798     MachineFrameInfo &MFI = MF->getFrameInfo();
 799     MachineMemOperand *MMO = MF->getMachineMemOperand(
 800         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
 801         MFI.getObjectSize(FI), Align(4));
 802     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
 803         .addFrameIndex(FI)
 804         .addImm(Offset)
 805         .addMemOperand(MMO);
 806     return true;
 807   }
 808   return false;
 809 }
 810
 811 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
 812                              unsigned Alignment) {
 813   //
 814   // more cases will be handled here in following patches.
 815   //
 816   unsigned Opc;
 817   switch (VT.SimpleTy) {
 818   case MVT::i8:
 819     Opc = Mips::SB;
 820     break;
 821   case MVT::i16:
 822     Opc = Mips::SH;
 823     break;
 824   case MVT::i32:
 825     Opc = Mips::SW;
 826     break;
 827   case MVT::f32:
 828     if (UnsupportedFPMode)
 829       return false;
 830     Opc = Mips::SWC1;
 831     break;
 832   case MVT::f64:
 833     if (UnsupportedFPMode)
 834       return false;
 835     Opc = Mips::SDC1;
 836     break;
 837   default:
 838     return false;
 839   }
 840   if (Addr.isRegBase()) {
 841     simplifyAddress(Addr);
 842     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
 843     return true;
 844   }
 845   if (Addr.isFIBase()) {
 846     unsigned FI = Addr.getFI();
 847     int64_t Offset = Addr.getOffset();
 848     MachineFrameInfo &MFI = MF->getFrameInfo();
 849     MachineMemOperand *MMO = MF->getMachineMemOperand(
 850         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
 851         MFI.getObjectSize(FI), Align(4));
 852     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
 853         .addReg(SrcReg)
 854         .addFrameIndex(FI)
 855         .addImm(Offset)
 856         .addMemOperand(MMO);
 857     return true;
 858   }
 859   return false;
 860 }
 861
 862 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
 863   MVT VT;
 864   if (!isTypeSupported(I->getType(), VT))
 865     return false;
 866
 867   unsigned ResultReg;
 868   switch (I->getOpcode()) {
 869   default:
 870     llvm_unreachable("Unexpected instruction.");
 871   case Instruction::And:
 872     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
 873     break;
 874   case Instruction::Or:
 875     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
 876     break;
 877   case Instruction::Xor:
 878     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
 879     break;
 880   }
 881
 882   if (!ResultReg)
 883     return false;
 884
 885   updateValueMap(I, ResultReg);
 886   return true;
 887 }
 888
 889 bool MipsFastISel::selectLoad(const Instruction *I) {
 890   // Atomic loads need special handling.
 891   if (cast<LoadInst>(I)->isAtomic())
 892     return false;
 893
 894   // Verify we have a legal type before going any further.
 895   MVT VT;
 896   if (!isLoadTypeLegal(I->getType(), VT))
 897     return false;
 898
 899   // See if we can handle this address.
 900   Address Addr;
 901   if (!computeAddress(I->getOperand(0), Addr))
 902     return false;
 903
 904   unsigned ResultReg;
 905   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
 906     return false;
 907   updateValueMap(I, ResultReg);
 908   return true;
 909 }
 910
 911 bool MipsFastISel::selectStore(const Instruction *I) {
 912   Value *Op0 = I->getOperand(0);
 913   unsigned SrcReg = 0;
 914
 915   // Atomic stores need special handling.
 916   if (cast<StoreInst>(I)->isAtomic())
 917     return false;
 918
 919   // Verify we have a legal type before going any further.
 920   MVT VT;
 921   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
 922     return false;
 923
 924   // Get the value to be stored into a register.
 925   SrcReg = getRegForValue(Op0);
 926   if (SrcReg == 0)
 927     return false;
 928
 929   // See if we can handle this address.
 930   Address Addr;
 931   if (!computeAddress(I->getOperand(1), Addr))
 932     return false;
 933
 934   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
 935     return false;
 936   return true;
 937 }
 938
 939 // This can cause a redundant sltiu to be generated.
 940 // FIXME: try and eliminate this in a future patch.
 941 bool MipsFastISel::selectBranch(const Instruction *I) {
 942   const BranchInst *BI = cast<BranchInst>(I);
 943   MachineBasicBlock *BrBB = FuncInfo.MBB;
 944   //
 945   // TBB is the basic block for the case where the comparison is true.
 946   // FBB is the basic block for the case where the comparison is false.
 947   // if (cond) goto TBB
 948   // goto FBB
 949   // TBB:
 950   //
 951   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
 952   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
 953
 954   // Fold the common case of a conditional branch with a comparison
 955   // in the same block.
 956   unsigned ZExtCondReg = 0;
 957   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
 958     if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
 959       ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
 960       if (!emitCmp(ZExtCondReg, CI))
 961         return false;
 962     }
 963   }
 964
 965   // For the general case, we need to mask with 1.
 966   if (ZExtCondReg == 0) {
 967     unsigned CondReg = getRegForValue(BI->getCondition());
 968     if (CondReg == 0)
 969       return false;
 970
 971     ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
 972     if (ZExtCondReg == 0)
 973       return false;
 974   }
 975
 976   BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
 977       .addReg(ZExtCondReg)
 978       .addMBB(TBB);
 979   finishCondBranch(BI->getParent(), TBB, FBB);
 980   return true;
 981 }
 982
 983 bool MipsFastISel::selectCmp(const Instruction *I) {
 984   const CmpInst *CI = cast<CmpInst>(I);
 985   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
 986   if (!emitCmp(ResultReg, CI))
 987     return false;
 988   updateValueMap(I, ResultReg);
 989   return true;
 990 }
 991
 992 // Attempt to fast-select a floating-point extend instruction.
 993 bool MipsFastISel::selectFPExt(const Instruction *I) {
 994   if (UnsupportedFPMode)
 995     return false;
 996   Value *Src = I->getOperand(0);
 997   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
 998   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
 999
1000   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1001     return false;
1002
1003   unsigned SrcReg =
1004       getRegForValue(Src); // this must be a 32bit floating point register class
1005                            // maybe we should handle this differently
1006   if (!SrcReg)
1007     return false;
1008
1009   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1010   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1011   updateValueMap(I, DestReg);
1012   return true;
1013 }
1014
1015 bool MipsFastISel::selectSelect(const Instruction *I) {
1016   assert(isa<SelectInst>(I) && "Expected a select instruction.");
1017
1018   LLVM_DEBUG(dbgs() << "selectSelect\n");
1019
1020   MVT VT;
1021   if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1022     LLVM_DEBUG(
1023         dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1024     return false;
1025   }
1026
1027   unsigned CondMovOpc;
1028   const TargetRegisterClass *RC;
1029
1030   if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1031     CondMovOpc = Mips::MOVN_I_I;
1032     RC = &Mips::GPR32RegClass;
1033   } else if (VT == MVT::f32) {
1034     CondMovOpc = Mips::MOVN_I_S;
1035     RC = &Mips::FGR32RegClass;
1036   } else if (VT == MVT::f64) {
1037     CondMovOpc = Mips::MOVN_I_D32;
1038     RC = &Mips::AFGR64RegClass;
1039   } else
1040     return false;
1041
1042   const SelectInst *SI = cast<SelectInst>(I);
1043   const Value *Cond = SI->getCondition();
1044   unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1045   unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1046   unsigned CondReg = getRegForValue(Cond);
1047
1048   if (!Src1Reg || !Src2Reg || !CondReg)
1049     return false;
1050
1051   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1052   if (!ZExtCondReg)
1053     return false;
1054
1055   if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1056     return false;
1057
1058   unsigned ResultReg = createResultReg(RC);
1059   unsigned TempReg = createResultReg(RC);
1060
1061   if (!ResultReg || !TempReg)
1062     return false;
1063
1064   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1065   emitInst(CondMovOpc, ResultReg)
1066     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1067   updateValueMap(I, ResultReg);
1068   return true;
1069 }
1070
1071 // Attempt to fast-select a floating-point truncate instruction.
1072 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1073   if (UnsupportedFPMode)
1074     return false;
1075   Value *Src = I->getOperand(0);
1076   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1077   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1078
1079   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1080     return false;
1081
1082   unsigned SrcReg = getRegForValue(Src);
1083   if (!SrcReg)
1084     return false;
1085
1086   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1087   if (!DestReg)
1088     return false;
1089
1090   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1091   updateValueMap(I, DestReg);
1092   return true;
1093 }
1094
1095 // Attempt to fast-select a floating-point-to-integer conversion.
1096 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1097   if (UnsupportedFPMode)
1098     return false;
1099   MVT DstVT, SrcVT;
1100   if (!IsSigned)
1101     return false; // We don't handle this case yet. There is no native
1102                   // instruction for this but it can be synthesized.
1103   Type *DstTy = I->getType();
1104   if (!isTypeLegal(DstTy, DstVT))
1105     return false;
1106
1107   if (DstVT != MVT::i32)
1108     return false;
1109
1110   Value *Src = I->getOperand(0);
1111   Type *SrcTy = Src->getType();
1112   if (!isTypeLegal(SrcTy, SrcVT))
1113     return false;
1114
1115   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1116     return false;
1117
1118   unsigned SrcReg = getRegForValue(Src);
1119   if (SrcReg == 0)
1120     return false;
1121
1122   // Determine the opcode for the conversion, which takes place
1123   // entirely within FPRs.
1124   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1125   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1126   unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1127
1128   // Generate the convert.
1129   emitInst(Opc, TempReg).addReg(SrcReg);
1130   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1131
1132   updateValueMap(I, DestReg);
1133   return true;
1134 }
1135
1136 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1137                                    SmallVectorImpl<MVT> &OutVTs,
1138                                    unsigned &NumBytes) {
1139   CallingConv::ID CC = CLI.CallConv;
1140   SmallVector<CCValAssign, 16> ArgLocs;
1141   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1142   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1143   // Get a count of how many bytes are to be pushed on the stack.
1144   NumBytes = CCInfo.getNextStackOffset();
1145   // This is the minimum argument area used for A0-A3.
1146   if (NumBytes < 16)
1147     NumBytes = 16;
1148
1149   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1150   // Process the args.
1151   MVT firstMVT;
1152   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1153     CCValAssign &VA = ArgLocs[i];
1154     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1155     MVT ArgVT = OutVTs[VA.getValNo()];
1156
1157     if (i == 0) {
1158       firstMVT = ArgVT;
1159       if (ArgVT == MVT::f32) {
1160         VA.convertToReg(Mips::F12);
1161       } else if (ArgVT == MVT::f64) {
1162         if (Subtarget->isFP64bit())
1163           VA.convertToReg(Mips::D6_64);
1164         else
1165           VA.convertToReg(Mips::D6);
1166       }
1167     } else if (i == 1) {
1168       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1169         if (ArgVT == MVT::f32) {
1170           VA.convertToReg(Mips::F14);
1171         } else if (ArgVT == MVT::f64) {
1172           if (Subtarget->isFP64bit())
1173             VA.convertToReg(Mips::D7_64);
1174           else
1175             VA.convertToReg(Mips::D7);
1176         }
1177       }
1178     }
1179     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1180          (ArgVT == MVT::i8)) &&
1181         VA.isMemLoc()) {
1182       switch (VA.getLocMemOffset()) {
1183       case 0:
1184         VA.convertToReg(Mips::A0);
1185         break;
1186       case 4:
1187         VA.convertToReg(Mips::A1);
1188         break;
1189       case 8:
1190         VA.convertToReg(Mips::A2);
1191         break;
1192       case 12:
1193         VA.convertToReg(Mips::A3);
1194         break;
1195       default:
1196         break;
1197       }
1198     }
1199     unsigned ArgReg = getRegForValue(ArgVal);
1200     if (!ArgReg)
1201       return false;
1202
1203     // Handle arg promotion: SExt, ZExt, AExt.
1204     switch (VA.getLocInfo()) {
1205     case CCValAssign::Full:
1206       break;
1207     case CCValAssign::AExt:
1208     case CCValAssign::SExt: {
1209       MVT DestVT = VA.getLocVT();
1210       MVT SrcVT = ArgVT;
1211       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1212       if (!ArgReg)
1213         return false;
1214       break;
1215     }
1216     case CCValAssign::ZExt: {
1217       MVT DestVT = VA.getLocVT();
1218       MVT SrcVT = ArgVT;
1219       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1220       if (!ArgReg)
1221         return false;
1222       break;
1223     }
1224     default:
1225       llvm_unreachable("Unknown arg promotion!");
1226     }
1227
1228     // Now copy/store arg to correct locations.
1229     if (VA.isRegLoc() && !VA.needsCustom()) {
1230       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1231               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1232       CLI.OutRegs.push_back(VA.getLocReg());
1233     } else if (VA.needsCustom()) {
1234       llvm_unreachable("Mips does not use custom args.");
1235       return false;
1236     } else {
1237       //
1238       // FIXME: This path will currently return false. It was copied
1239       // from the AArch64 port and should be essentially fine for Mips too.
1240       // The work to finish up this path will be done in a follow-on patch.
1241       //
1242       assert(VA.isMemLoc() && "Assuming store on stack.");
1243       // Don't emit stores for undef values.
1244       if (isa<UndefValue>(ArgVal))
1245         continue;
1246
1247       // Need to store on the stack.
1248       // FIXME: This alignment is incorrect but this path is disabled
1249       // for now (will return false). We need to determine the right alignment
1250       // based on the normal alignment for the underlying machine type.
1251       //
1252       unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1253
1254       unsigned BEAlign = 0;
1255       if (ArgSize < 8 && !Subtarget->isLittle())
1256         BEAlign = 8 - ArgSize;
1257
1258       Address Addr;
1259       Addr.setKind(Address::RegBase);
1260       Addr.setReg(Mips::SP);
1261       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1262
1263       Align Alignment = DL.getABITypeAlign(ArgVal->getType());
1264       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1265           MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1266           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1267       (void)(MMO);
1268       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1269       return false; // can't store on the stack yet.
1270     }
1271   }
1272
1273   return true;
1274 }
1275
1276 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1277                               unsigned NumBytes) {
1278   CallingConv::ID CC = CLI.CallConv;
1279   emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1280   if (RetVT != MVT::isVoid) {
1281     SmallVector<CCValAssign, 16> RVLocs;
1282     MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1283
1284     CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1285                              CLI.Symbol ? CLI.Symbol->getName().data()
1286                                         : nullptr);
1287
1288     // Only handle a single return value.
1289     if (RVLocs.size() != 1)
1290       return false;
1291     // Copy all of the result registers out of their specified physreg.
1292     MVT CopyVT = RVLocs[0].getValVT();
1293     // Special handling for extended integers.
1294     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1295       CopyVT = MVT::i32;
1296
1297     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1298     if (!ResultReg)
1299       return false;
1300     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1301             TII.get(TargetOpcode::COPY),
1302             ResultReg).addReg(RVLocs[0].getLocReg());
1303     CLI.InRegs.push_back(RVLocs[0].getLocReg());
1304
1305     CLI.ResultReg = ResultReg;
1306     CLI.NumResultRegs = 1;
1307   }
1308   return true;
1309 }
1310
1311 bool MipsFastISel::fastLowerArguments() {
1312   LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1313
1314   if (!FuncInfo.CanLowerReturn) {
1315     LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1316     return false;
1317   }
1318
1319   const Function *F = FuncInfo.Fn;
1320   if (F->isVarArg()) {
1321     LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1322     return false;
1323   }
1324
1325   CallingConv::ID CC = F->getCallingConv();
1326   if (CC != CallingConv::C) {
1327     LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1328     return false;
1329   }
1330
1331   std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1332                                            Mips::A3}};
1333   std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1334   std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1335   auto NextGPR32 = GPR32ArgRegs.begin();
1336   auto NextFGR32 = FGR32ArgRegs.begin();
1337   auto NextAFGR64 = AFGR64ArgRegs.begin();
1338
1339   struct AllocatedReg {
1340     const TargetRegisterClass *RC;
1341     unsigned Reg;
1342     AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1343         : RC(RC), Reg(Reg) {}
1344   };
1345
1346   // Only handle simple cases. i.e. All arguments are directly mapped to
1347   // registers of the appropriate type.
1348   SmallVector<AllocatedReg, 4> Allocation;
1349   for (const auto &FormalArg : F->args()) {
1350     if (FormalArg.hasAttribute(Attribute::InReg) ||
1351         FormalArg.hasAttribute(Attribute::StructRet) ||
1352         FormalArg.hasAttribute(Attribute::ByVal)) {
1353       LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1354       return false;
1355     }
1356
1357     Type *ArgTy = FormalArg.getType();
1358     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1359       LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1360       return false;
1361     }
1362
1363     EVT ArgVT = TLI.getValueType(DL, ArgTy);
1364     LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1365                       << ArgVT.getEVTString() << "\n");
1366     if (!ArgVT.isSimple()) {
1367       LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1368       return false;
1369     }
1370
1371     switch (ArgVT.getSimpleVT().SimpleTy) {
1372     case MVT::i1:
1373     case MVT::i8:
1374     case MVT::i16:
1375       if (!FormalArg.hasAttribute(Attribute::SExt) &&
1376           !FormalArg.hasAttribute(Attribute::ZExt)) {
1377         // It must be any extend, this shouldn't happen for clang-generated IR
1378         // so just fall back on SelectionDAG.
1379         LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1380         return false;
1381       }
1382
1383       if (NextGPR32 == GPR32ArgRegs.end()) {
1384         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1385         return false;
1386       }
1387
1388       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1389       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1390
1391       // Allocating any GPR32 prohibits further use of floating point arguments.
1392       NextFGR32 = FGR32ArgRegs.end();
1393       NextAFGR64 = AFGR64ArgRegs.end();
1394       break;
1395
1396     case MVT::i32:
1397       if (FormalArg.hasAttribute(Attribute::ZExt)) {
1398         // The O32 ABI does not permit a zero-extended i32.
1399         LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1400         return false;
1401       }
1402
1403       if (NextGPR32 == GPR32ArgRegs.end()) {
1404         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1405         return false;
1406       }
1407
1408       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1409       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1410
1411       // Allocating any GPR32 prohibits further use of floating point arguments.
1412       NextFGR32 = FGR32ArgRegs.end();
1413       NextAFGR64 = AFGR64ArgRegs.end();
1414       break;
1415
1416     case MVT::f32:
1417       if (UnsupportedFPMode) {
1418         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1419         return false;
1420       }
1421       if (NextFGR32 == FGR32ArgRegs.end()) {
1422         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1423         return false;
1424       }
1425       LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1426       Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1427       // Allocating an FGR32 also allocates the super-register AFGR64, and
1428       // ABI rules require us to skip the corresponding GPR32.
1429       if (NextGPR32 != GPR32ArgRegs.end())
1430         NextGPR32++;
1431       if (NextAFGR64 != AFGR64ArgRegs.end())
1432         NextAFGR64++;
1433       break;
1434
1435     case MVT::f64:
1436       if (UnsupportedFPMode) {
1437         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1438         return false;
1439       }
1440       if (NextAFGR64 == AFGR64ArgRegs.end()) {
1441         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1442         return false;
1443       }
1444       LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1445       Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1446       // Allocating an FGR32 also allocates the super-register AFGR64, and
1447       // ABI rules require us to skip the corresponding GPR32 pair.
1448       if (NextGPR32 != GPR32ArgRegs.end())
1449         NextGPR32++;
1450       if (NextGPR32 != GPR32ArgRegs.end())
1451         NextGPR32++;
1452       if (NextFGR32 != FGR32ArgRegs.end())
1453         NextFGR32++;
1454       break;
1455
1456     default:
1457       LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1458       return false;
1459     }
1460   }
1461
1462   for (const auto &FormalArg : F->args()) {
1463     unsigned ArgNo = FormalArg.getArgNo();
1464     unsigned SrcReg = Allocation[ArgNo].Reg;
1465     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1466     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1467     // Without this, EmitLiveInCopies may eliminate the livein if its only
1468     // use is a bitcast (which isn't turned into an instruction).
1469     unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1470     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1471             TII.get(TargetOpcode::COPY), ResultReg)
1472         .addReg(DstReg, getKillRegState(true));
1473     updateValueMap(&FormalArg, ResultReg);
1474   }
1475
1476   // Calculate the size of the incoming arguments area.
1477   // We currently reject all the cases where this would be non-zero.
1478   unsigned IncomingArgSizeInBytes = 0;
1479
1480   // Account for the reserved argument area on ABI's that have one (O32).
1481   // It seems strange to do this on the caller side but it's necessary in
1482   // SelectionDAG's implementation.
1483   IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1484                                     IncomingArgSizeInBytes);
1485
1486   MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1487                                                     false);
1488
1489   return true;
1490 }
1491
1492 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1493   CallingConv::ID CC = CLI.CallConv;
1494   bool IsTailCall = CLI.IsTailCall;
1495   bool IsVarArg = CLI.IsVarArg;
1496   const Value *Callee = CLI.Callee;
1497   MCSymbol *Symbol = CLI.Symbol;
1498
1499   // Do not handle FastCC.
1500   if (CC == CallingConv::Fast)
1501     return false;
1502
1503   // Allow SelectionDAG isel to handle tail calls.
1504   if (IsTailCall)
1505     return false;
1506
1507   // Let SDISel handle vararg functions.
1508   if (IsVarArg)
1509     return false;
1510
1511   // FIXME: Only handle *simple* calls for now.
1512   MVT RetVT;
1513   if (CLI.RetTy->isVoidTy())
1514     RetVT = MVT::isVoid;
1515   else if (!isTypeSupported(CLI.RetTy, RetVT))
1516     return false;
1517
1518   for (auto Flag : CLI.OutFlags)
1519     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1520       return false;
1521
1522   // Set up the argument vectors.
1523   SmallVector<MVT, 16> OutVTs;
1524   OutVTs.reserve(CLI.OutVals.size());
1525
1526   for (auto *Val : CLI.OutVals) {
1527     MVT VT;
1528     if (!isTypeLegal(Val->getType(), VT) &&
1529         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1530       return false;
1531
1532     // We don't handle vector parameters yet.
1533     if (VT.isVector() || VT.getSizeInBits() > 64)
1534       return false;
1535
1536     OutVTs.push_back(VT);
1537   }
1538
1539   Address Addr;
1540   if (!computeCallAddress(Callee, Addr))
1541     return false;
1542
1543   // Handle the arguments now that we've gotten them.
1544   unsigned NumBytes;
1545   if (!processCallArgs(CLI, OutVTs, NumBytes))
1546     return false;
1547
1548   if (!Addr.getGlobalValue())
1549     return false;
1550
1551   // Issue the call.
1552   unsigned DestAddress;
1553   if (Symbol)
1554     DestAddress = materializeExternalCallSym(Symbol);
1555   else
1556     DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1557   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1558   MachineInstrBuilder MIB =
1559       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1560               Mips::RA).addReg(Mips::T9);
1561
1562   // Add implicit physical register uses to the call.
1563   for (auto Reg : CLI.OutRegs)
1564     MIB.addReg(Reg, RegState::Implicit);
1565
1566   // Add a register mask with the call-preserved registers.
1567   // Proper defs for return values will be added by setPhysRegsDeadExcept().
1568   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1569
1570   CLI.Call = MIB;
1571
1572   if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1573     // Attach callee address to the instruction, let asm printer emit
1574     // .reloc R_MIPS_JALR.
1575     if (Symbol)
1576       MIB.addSym(Symbol, MipsII::MO_JALR);
1577     else
1578       MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1579                            Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1580   }
1581
1582   // Finish off the call including any return values.
1583   return finishCall(CLI, RetVT, NumBytes);
1584 }
1585
1586 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1587   switch (II->getIntrinsicID()) {
1588   default:
1589     return false;
1590   case Intrinsic::bswap: {
1591     Type *RetTy = II->getCalledFunction()->getReturnType();
1592
1593     MVT VT;
1594     if (!isTypeSupported(RetTy, VT))
1595       return false;
1596
1597     unsigned SrcReg = getRegForValue(II->getOperand(0));
1598     if (SrcReg == 0)
1599       return false;
1600     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1601     if (DestReg == 0)
1602       return false;
1603     if (VT == MVT::i16) {
1604       if (Subtarget->hasMips32r2()) {
1605         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1606         updateValueMap(II, DestReg);
1607         return true;
1608       } else {
1609         unsigned TempReg[3];
1610         for (int i = 0; i < 3; i++) {
1611           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1612           if (TempReg[i] == 0)
1613             return false;
1614         }
1615         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1616         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1617         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1618         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1619         updateValueMap(II, DestReg);
1620         return true;
1621       }
1622     } else if (VT == MVT::i32) {
1623       if (Subtarget->hasMips32r2()) {
1624         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1625         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1626         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1627         updateValueMap(II, DestReg);
1628         return true;
1629       } else {
1630         unsigned TempReg[8];
1631         for (int i = 0; i < 8; i++) {
1632           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1633           if (TempReg[i] == 0)
1634             return false;
1635         }
1636
1637         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1638         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1639         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1640         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1641
1642         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1643         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1644
1645         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1646         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1647         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1648         updateValueMap(II, DestReg);
1649         return true;
1650       }
1651     }
1652     return false;
1653   }
1654   case Intrinsic::memcpy:
1655   case Intrinsic::memmove: {
1656     const auto *MTI = cast<MemTransferInst>(II);
1657     // Don't handle volatile.
1658     if (MTI->isVolatile())
1659       return false;
1660     if (!MTI->getLength()->getType()->isIntegerTy(32))
1661       return false;
1662     const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1663     return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1664   }
1665   case Intrinsic::memset: {
1666     const MemSetInst *MSI = cast<MemSetInst>(II);
1667     // Don't handle volatile.
1668     if (MSI->isVolatile())
1669       return false;
1670     if (!MSI->getLength()->getType()->isIntegerTy(32))
1671       return false;
1672     return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1673   }
1674   }
1675   return false;
1676 }
1677
1678 bool MipsFastISel::selectRet(const Instruction *I) {
1679   const Function &F = *I->getParent()->getParent();
1680   const ReturnInst *Ret = cast<ReturnInst>(I);
1681
1682   LLVM_DEBUG(dbgs() << "selectRet\n");
1683
1684   if (!FuncInfo.CanLowerReturn)
1685     return false;
1686
1687   // Build a list of return value registers.
1688   SmallVector<unsigned, 4> RetRegs;
1689
1690   if (Ret->getNumOperands() > 0) {
1691     CallingConv::ID CC = F.getCallingConv();
1692
1693     // Do not handle FastCC.
1694     if (CC == CallingConv::Fast)
1695       return false;
1696
1697     SmallVector<ISD::OutputArg, 4> Outs;
1698     GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1699
1700     // Analyze operands of the call, assigning locations to each operand.
1701     SmallVector<CCValAssign, 16> ValLocs;
1702     MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1703                        I->getContext());
1704     CCAssignFn *RetCC = RetCC_Mips;
1705     CCInfo.AnalyzeReturn(Outs, RetCC);
1706
1707     // Only handle a single return value for now.
1708     if (ValLocs.size() != 1)
1709       return false;
1710
1711     CCValAssign &VA = ValLocs[0];
1712     const Value *RV = Ret->getOperand(0);
1713
1714     // Don't bother handling odd stuff for now.
1715     if ((VA.getLocInfo() != CCValAssign::Full) &&
1716         (VA.getLocInfo() != CCValAssign::BCvt))
1717       return false;
1718
1719     // Only handle register returns for now.
1720     if (!VA.isRegLoc())
1721       return false;
1722
1723     unsigned Reg = getRegForValue(RV);
1724     if (Reg == 0)
1725       return false;
1726
1727     unsigned SrcReg = Reg + VA.getValNo();
1728     Register DestReg = VA.getLocReg();
1729     // Avoid a cross-class copy. This is very unlikely.
1730     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1731       return false;
1732
1733     EVT RVEVT = TLI.getValueType(DL, RV->getType());
1734     if (!RVEVT.isSimple())
1735       return false;
1736
1737     if (RVEVT.isVector())
1738       return false;
1739
1740     MVT RVVT = RVEVT.getSimpleVT();
1741     if (RVVT == MVT::f128)
1742       return false;
1743
1744     // Do not handle FGR64 returns for now.
1745     if (RVVT == MVT::f64 && UnsupportedFPMode) {
1746       LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1747       return false;
1748     }
1749
1750     MVT DestVT = VA.getValVT();
1751     // Special handling for extended integers.
1752     if (RVVT != DestVT) {
1753       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1754         return false;
1755
1756       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1757         bool IsZExt = Outs[0].Flags.isZExt();
1758         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1759         if (SrcReg == 0)
1760           return false;
1761       }
1762     }
1763
1764     // Make the copy.
1765     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1766             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1767
1768     // Add register to return instruction.
1769     RetRegs.push_back(VA.getLocReg());
1770   }
1771   MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1772   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1773     MIB.addReg(RetRegs[i], RegState::Implicit);
1774   return true;
1775 }
1776
1777 bool MipsFastISel::selectTrunc(const Instruction *I) {
1778   // The high bits for a type smaller than the register size are assumed to be
1779   // undefined.
1780   Value *Op = I->getOperand(0);
1781
1782   EVT SrcVT, DestVT;
1783   SrcVT = TLI.getValueType(DL, Op->getType(), true);
1784   DestVT = TLI.getValueType(DL, I->getType(), true);
1785
1786   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1787     return false;
1788   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1789     return false;
1790
1791   unsigned SrcReg = getRegForValue(Op);
1792   if (!SrcReg)
1793     return false;
1794
1795   // Because the high bits are undefined, a truncate doesn't generate
1796   // any code.
1797   updateValueMap(I, SrcReg);
1798   return true;
1799 }
1800
1801 bool MipsFastISel::selectIntExt(const Instruction *I) {
1802   Type *DestTy = I->getType();
1803   Value *Src = I->getOperand(0);
1804   Type *SrcTy = Src->getType();
1805
1806   bool isZExt = isa<ZExtInst>(I);
1807   unsigned SrcReg = getRegForValue(Src);
1808   if (!SrcReg)
1809     return false;
1810
1811   EVT SrcEVT, DestEVT;
1812   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1813   DestEVT = TLI.getValueType(DL, DestTy, true);
1814   if (!SrcEVT.isSimple())
1815     return false;
1816   if (!DestEVT.isSimple())
1817     return false;
1818
1819   MVT SrcVT = SrcEVT.getSimpleVT();
1820   MVT DestVT = DestEVT.getSimpleVT();
1821   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1822
1823   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1824     return false;
1825   updateValueMap(I, ResultReg);
1826   return true;
1827 }
1828
1829 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1830                                    unsigned DestReg) {
1831   unsigned ShiftAmt;
1832   switch (SrcVT.SimpleTy) {
1833   default:
1834     return false;
1835   case MVT::i8:
1836     ShiftAmt = 24;
1837     break;
1838   case MVT::i16:
1839     ShiftAmt = 16;
1840     break;
1841   }
1842   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1843   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1844   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1845   return true;
1846 }
1847
1848 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1849                                    unsigned DestReg) {
1850   switch (SrcVT.SimpleTy) {
1851   default:
1852     return false;
1853   case MVT::i8:
1854     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1855     break;
1856   case MVT::i16:
1857     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1858     break;
1859   }
1860   return true;
1861 }
1862
1863 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1864                                unsigned DestReg) {
1865   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1866     return false;
1867   if (Subtarget->hasMips32r2())
1868     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1869   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1870 }
1871
1872 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1873                                unsigned DestReg) {
1874   int64_t Imm;
1875
1876   switch (SrcVT.SimpleTy) {
1877   default:
1878     return false;
1879   case MVT::i1:
1880     Imm = 1;
1881     break;
1882   case MVT::i8:
1883     Imm = 0xff;
1884     break;
1885   case MVT::i16:
1886     Imm = 0xffff;
1887     break;
1888   }
1889
1890   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1891   return true;
1892 }
1893
1894 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1895                               unsigned DestReg, bool IsZExt) {
1896   // FastISel does not have plumbing to deal with extensions where the SrcVT or
1897   // DestVT are odd things, so test to make sure that they are both types we can
1898   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1899   // bail out to SelectionDAG.
1900   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1901       ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1902     return false;
1903   if (IsZExt)
1904     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1905   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1906 }
1907
1908 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1909                                   bool isZExt) {
1910   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1911   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1912   return Success ? DestReg : 0;
1913 }
1914
1915 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1916   EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1917   if (!DestEVT.isSimple())
1918     return false;
1919
1920   MVT DestVT = DestEVT.getSimpleVT();
1921   if (DestVT != MVT::i32)
1922     return false;
1923
1924   unsigned DivOpc;
1925   switch (ISDOpcode) {
1926   default:
1927     return false;
1928   case ISD::SDIV:
1929   case ISD::SREM:
1930     DivOpc = Mips::SDIV;
1931     break;
1932   case ISD::UDIV:
1933   case ISD::UREM:
1934     DivOpc = Mips::UDIV;
1935     break;
1936   }
1937
1938   unsigned Src0Reg = getRegForValue(I->getOperand(0));
1939   unsigned Src1Reg = getRegForValue(I->getOperand(1));
1940   if (!Src0Reg || !Src1Reg)
1941     return false;
1942
1943   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1944   emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1945
1946   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1947   if (!ResultReg)
1948     return false;
1949
1950   unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1951                        ? Mips::MFHI
1952                        : Mips::MFLO;
1953   emitInst(MFOpc, ResultReg);
1954
1955   updateValueMap(I, ResultReg);
1956   return true;
1957 }
1958
1959 bool MipsFastISel::selectShift(const Instruction *I) {
1960   MVT RetVT;
1961
1962   if (!isTypeSupported(I->getType(), RetVT))
1963     return false;
1964
1965   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1966   if (!ResultReg)
1967     return false;
1968
1969   unsigned Opcode = I->getOpcode();
1970   const Value *Op0 = I->getOperand(0);
1971   unsigned Op0Reg = getRegForValue(Op0);
1972   if (!Op0Reg)
1973     return false;
1974
1975   // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1976   if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1977     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1978     if (!TempReg)
1979       return false;
1980
1981     MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1982     bool IsZExt = Opcode == Instruction::LShr;
1983     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1984       return false;
1985
1986     Op0Reg = TempReg;
1987   }
1988
1989   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1990     uint64_t ShiftVal = C->getZExtValue();
1991
1992     switch (Opcode) {
1993     default:
1994       llvm_unreachable("Unexpected instruction.");
1995     case Instruction::Shl:
1996       Opcode = Mips::SLL;
1997       break;
1998     case Instruction::AShr:
1999       Opcode = Mips::SRA;
2000       break;
2001     case Instruction::LShr:
2002       Opcode = Mips::SRL;
2003       break;
2004     }
2005
2006     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
2007     updateValueMap(I, ResultReg);
2008     return true;
2009   }
2010
2011   unsigned Op1Reg = getRegForValue(I->getOperand(1));
2012   if (!Op1Reg)
2013     return false;
2014
2015   switch (Opcode) {
2016   default:
2017     llvm_unreachable("Unexpected instruction.");
2018   case Instruction::Shl:
2019     Opcode = Mips::SLLV;
2020     break;
2021   case Instruction::AShr:
2022     Opcode = Mips::SRAV;
2023     break;
2024   case Instruction::LShr:
2025     Opcode = Mips::SRLV;
2026     break;
2027   }
2028
2029   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2030   updateValueMap(I, ResultReg);
2031   return true;
2032 }
2033
2034 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2035   switch (I->getOpcode()) {
2036   default:
2037     break;
2038   case Instruction::Load:
2039     return selectLoad(I);
2040   case Instruction::Store:
2041     return selectStore(I);
2042   case Instruction::SDiv:
2043     if (!selectBinaryOp(I, ISD::SDIV))
2044       return selectDivRem(I, ISD::SDIV);
2045     return true;
2046   case Instruction::UDiv:
2047     if (!selectBinaryOp(I, ISD::UDIV))
2048       return selectDivRem(I, ISD::UDIV);
2049     return true;
2050   case Instruction::SRem:
2051     if (!selectBinaryOp(I, ISD::SREM))
2052       return selectDivRem(I, ISD::SREM);
2053     return true;
2054   case Instruction::URem:
2055     if (!selectBinaryOp(I, ISD::UREM))
2056       return selectDivRem(I, ISD::UREM);
2057     return true;
2058   case Instruction::Shl:
2059   case Instruction::LShr:
2060   case Instruction::AShr:
2061     return selectShift(I);
2062   case Instruction::And:
2063   case Instruction::Or:
2064   case Instruction::Xor:
2065     return selectLogicalOp(I);
2066   case Instruction::Br:
2067     return selectBranch(I);
2068   case Instruction::Ret:
2069     return selectRet(I);
2070   case Instruction::Trunc:
2071     return selectTrunc(I);
2072   case Instruction::ZExt:
2073   case Instruction::SExt:
2074     return selectIntExt(I);
2075   case Instruction::FPTrunc:
2076     return selectFPTrunc(I);
2077   case Instruction::FPExt:
2078     return selectFPExt(I);
2079   case Instruction::FPToSI:
2080     return selectFPToInt(I, /*isSigned*/ true);
2081   case Instruction::FPToUI:
2082     return selectFPToInt(I, /*isSigned*/ false);
2083   case Instruction::ICmp:
2084   case Instruction::FCmp:
2085     return selectCmp(I);
2086   case Instruction::Select:
2087     return selectSelect(I);
2088   }
2089   return false;
2090 }
2091
2092 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2093                                                            bool IsUnsigned) {
2094   unsigned VReg = getRegForValue(V);
2095   if (VReg == 0)
2096     return 0;
2097   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2098
2099   if (VMVT == MVT::i1)
2100     return 0;
2101
2102   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2103     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2104     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2105       return 0;
2106     VReg = TempReg;
2107   }
2108   return VReg;
2109 }
2110
2111 void MipsFastISel::simplifyAddress(Address &Addr) {
2112   if (!isInt<16>(Addr.getOffset())) {
2113     unsigned TempReg =
2114         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2115     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2116     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2117     Addr.setReg(DestReg);
2118     Addr.setOffset(0);
2119   }
2120 }
2121
2122 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2123                                        const TargetRegisterClass *RC,
2124                                        unsigned Op0, unsigned Op1) {
2125   // We treat the MUL instruction in a special way because it clobbers
2126   // the HI0 & LO0 registers. The TableGen definition of this instruction can
2127   // mark these registers only as implicitly defined. As a result, the
2128   // register allocator runs out of registers when this instruction is
2129   // followed by another instruction that defines the same registers too.
2130   // We can fix this by explicitly marking those registers as dead.
2131   if (MachineInstOpcode == Mips::MUL) {
2132     unsigned ResultReg = createResultReg(RC);
2133     const MCInstrDesc &II = TII.get(MachineInstOpcode);
2134     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2135     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2136     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2137       .addReg(Op0)
2138       .addReg(Op1)
2139       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2140       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2141     return ResultReg;
2142   }
2143
2144   return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op1);
2145 }
2146
2147 namespace llvm {
2148
2149 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2150                                const TargetLibraryInfo *libInfo) {
2151   return new MipsFastISel(funcInfo, libInfo);
2152 }
2153
2154 } // end namespace llvm