llvm/lib/Target/Mips/MipsInstrInfo.cpp

   1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the Mips implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsInstrInfo.h"
  14 #include "MCTargetDesc/MipsBaseInfo.h"
  15 #include "MCTargetDesc/MipsMCTargetDesc.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/ADT/SmallVector.h"
  18 #include "llvm/CodeGen/MachineBasicBlock.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineOperand.h"
  24 #include "llvm/CodeGen/TargetOpcodes.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/IR/DebugInfoMetadata.h"
  27 #include "llvm/IR/DebugLoc.h"
  28 #include "llvm/MC/MCInstrDesc.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include <cassert>
  31
  32 using namespace llvm;
  33
  34 #define GET_INSTRINFO_CTOR_DTOR
  35 #include "MipsGenInstrInfo.inc"
  36
  37 // Pin the vtable to this file.
  38 void MipsInstrInfo::anchor() {}
  39
  40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
  41     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
  42       Subtarget(STI), UncondBrOpc(UncondBr) {}
  43
  44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
  45   if (STI.inMips16Mode())
  46     return createMips16InstrInfo(STI);
  47
  48   return createMipsSEInstrInfo(STI);
  49 }
  50
  51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
  52   return op.isImm() && op.getImm() == 0;
  53 }
  54
  55 /// insertNoop - If data hazard condition is found insert the target nop
  56 /// instruction.
  57 // FIXME: This appears to be dead code.
  58 void MipsInstrInfo::
  59 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
  60 {
  61   DebugLoc DL;
  62   BuildMI(MBB, MI, DL, get(Mips::NOP));
  63 }
  64
  65 MachineMemOperand *
  66 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
  67                              MachineMemOperand::Flags Flags) const {
  68   MachineFunction &MF = *MBB.getParent();
  69   MachineFrameInfo &MFI = MF.getFrameInfo();
  70
  71   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
  72                                  Flags, MFI.getObjectSize(FI),
  73                                  MFI.getObjectAlign(FI));
  74 }
  75
  76 //===----------------------------------------------------------------------===//
  77 // Branch Analysis
  78 //===----------------------------------------------------------------------===//
  79
  80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
  81                                   MachineBasicBlock *&BB,
  82                                   SmallVectorImpl<MachineOperand> &Cond) const {
  83   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
  84   int NumOp = Inst->getNumExplicitOperands();
  85
  86   // for both int and fp branches, the last explicit operand is the
  87   // MBB.
  88   BB = Inst->getOperand(NumOp-1).getMBB();
  89   Cond.push_back(MachineOperand::CreateImm(Opc));
  90
  91   for (int i = 0; i < NumOp-1; i++)
  92     Cond.push_back(Inst->getOperand(i));
  93 }
  94
  95 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
  96                                   MachineBasicBlock *&TBB,
  97                                   MachineBasicBlock *&FBB,
  98                                   SmallVectorImpl<MachineOperand> &Cond,
  99                                   bool AllowModify) const {
 100   SmallVector<MachineInstr*, 2> BranchInstrs;
 101   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
 102
 103   return (BT == BT_None) || (BT == BT_Indirect);
 104 }
 105
 106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 107                                 const DebugLoc &DL,
 108                                 ArrayRef<MachineOperand> Cond) const {
 109   unsigned Opc = Cond[0].getImm();
 110   const MCInstrDesc &MCID = get(Opc);
 111   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
 112
 113   for (unsigned i = 1; i < Cond.size(); ++i) {
 114     assert((Cond[i].isImm() || Cond[i].isReg()) &&
 115            "Cannot copy operand for conditional branch!");
 116     MIB.add(Cond[i]);
 117   }
 118   MIB.addMBB(TBB);
 119 }
 120
 121 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
 122                                      MachineBasicBlock *TBB,
 123                                      MachineBasicBlock *FBB,
 124                                      ArrayRef<MachineOperand> Cond,
 125                                      const DebugLoc &DL,
 126                                      int *BytesAdded) const {
 127   // Shouldn't be a fall through.
 128   assert(TBB && "insertBranch must not be told to insert a fallthrough");
 129   assert(!BytesAdded && "code size not handled");
 130
 131   // # of condition operands:
 132   //  Unconditional branches: 0
 133   //  Floating point branches: 1 (opc)
 134   //  Int BranchZero: 2 (opc, reg)
 135   //  Int Branch: 3 (opc, reg0, reg1)
 136   assert((Cond.size() <= 3) &&
 137          "# of Mips branch conditions must be <= 3!");
 138
 139   // Two-way Conditional branch.
 140   if (FBB) {
 141     BuildCondBr(MBB, TBB, DL, Cond);
 142     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
 143     return 2;
 144   }
 145
 146   // One way branch.
 147   // Unconditional branch.
 148   if (Cond.empty())
 149     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
 150   else // Conditional branch.
 151     BuildCondBr(MBB, TBB, DL, Cond);
 152   return 1;
 153 }
 154
 155 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
 156                                      int *BytesRemoved) const {
 157   assert(!BytesRemoved && "code size not handled");
 158
 159   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
 160   unsigned removed = 0;
 161
 162   // Up to 2 branches are removed.
 163   // Note that indirect branches are not removed.
 164   while (I != REnd && removed < 2) {
 165     // Skip past debug instructions.
 166     if (I->isDebugInstr()) {
 167       ++I;
 168       continue;
 169     }
 170     if (!getAnalyzableBrOpc(I->getOpcode()))
 171       break;
 172     // Remove the branch.
 173     I->eraseFromParent();
 174     I = MBB.rbegin();
 175     ++removed;
 176   }
 177
 178   return removed;
 179 }
 180
 181 /// reverseBranchCondition - Return the inverse opcode of the
 182 /// specified Branch instruction.
 183 bool MipsInstrInfo::reverseBranchCondition(
 184     SmallVectorImpl<MachineOperand> &Cond) const {
 185   assert( (Cond.size() && Cond.size() <= 3) &&
 186           "Invalid Mips branch condition!");
 187   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
 188   return false;
 189 }
 190
 191 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
 192     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
 193     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
 194     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
 195   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
 196
 197   // Skip all the debug instructions.
 198   while (I != REnd && I->isDebugInstr())
 199     ++I;
 200
 201   if (I == REnd || !isUnpredicatedTerminator(*I)) {
 202     // This block ends with no branches (it just falls through to its succ).
 203     // Leave TBB/FBB null.
 204     TBB = FBB = nullptr;
 205     return BT_NoBranch;
 206   }
 207
 208   MachineInstr *LastInst = &*I;
 209   unsigned LastOpc = LastInst->getOpcode();
 210   BranchInstrs.push_back(LastInst);
 211
 212   // Not an analyzable branch (e.g., indirect jump).
 213   if (!getAnalyzableBrOpc(LastOpc))
 214     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
 215
 216   // Get the second to last instruction in the block.
 217   unsigned SecondLastOpc = 0;
 218   MachineInstr *SecondLastInst = nullptr;
 219
 220   // Skip past any debug instruction to see if the second last actual
 221   // is a branch.
 222   ++I;
 223   while (I != REnd && I->isDebugInstr())
 224     ++I;
 225
 226   if (I != REnd) {
 227     SecondLastInst = &*I;
 228     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
 229
 230     // Not an analyzable branch (must be an indirect jump).
 231     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
 232       return BT_None;
 233   }
 234
 235   // If there is only one terminator instruction, process it.
 236   if (!SecondLastOpc) {
 237     // Unconditional branch.
 238     if (LastInst->isUnconditionalBranch()) {
 239       TBB = LastInst->getOperand(0).getMBB();
 240       return BT_Uncond;
 241     }
 242
 243     // Conditional branch
 244     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
 245     return BT_Cond;
 246   }
 247
 248   // If we reached here, there are two branches.
 249   // If there are three terminators, we don't know what sort of block this is.
 250   if (++I != REnd && isUnpredicatedTerminator(*I))
 251     return BT_None;
 252
 253   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
 254
 255   // If second to last instruction is an unconditional branch,
 256   // analyze it and remove the last instruction.
 257   if (SecondLastInst->isUnconditionalBranch()) {
 258     // Return if the last instruction cannot be removed.
 259     if (!AllowModify)
 260       return BT_None;
 261
 262     TBB = SecondLastInst->getOperand(0).getMBB();
 263     LastInst->eraseFromParent();
 264     BranchInstrs.pop_back();
 265     return BT_Uncond;
 266   }
 267
 268   // Conditional branch followed by an unconditional branch.
 269   // The last one must be unconditional.
 270   if (!LastInst->isUnconditionalBranch())
 271     return BT_None;
 272
 273   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
 274   FBB = LastInst->getOperand(0).getMBB();
 275
 276   return BT_CondUncond;
 277 }
 278
 279 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
 280                                           int64_t BrOffset) const {
 281   switch (BranchOpc) {
 282   case Mips::B:
 283   case Mips::BAL:
 284   case Mips::BAL_BR:
 285   case Mips::BAL_BR_MM:
 286   case Mips::BC1F:
 287   case Mips::BC1FL:
 288   case Mips::BC1T:
 289   case Mips::BC1TL:
 290   case Mips::BEQ:     case Mips::BEQ64:
 291   case Mips::BEQL:
 292   case Mips::BGEZ:    case Mips::BGEZ64:
 293   case Mips::BGEZL:
 294   case Mips::BGEZAL:
 295   case Mips::BGEZALL:
 296   case Mips::BGTZ:    case Mips::BGTZ64:
 297   case Mips::BGTZL:
 298   case Mips::BLEZ:    case Mips::BLEZ64:
 299   case Mips::BLEZL:
 300   case Mips::BLTZ:    case Mips::BLTZ64:
 301   case Mips::BLTZL:
 302   case Mips::BLTZAL:
 303   case Mips::BLTZALL:
 304   case Mips::BNE:     case Mips::BNE64:
 305   case Mips::BNEL:
 306     return isInt<18>(BrOffset);
 307
 308   // microMIPSr3 branches
 309   case Mips::B_MM:
 310   case Mips::BC1F_MM:
 311   case Mips::BC1T_MM:
 312   case Mips::BEQ_MM:
 313   case Mips::BGEZ_MM:
 314   case Mips::BGEZAL_MM:
 315   case Mips::BGTZ_MM:
 316   case Mips::BLEZ_MM:
 317   case Mips::BLTZ_MM:
 318   case Mips::BLTZAL_MM:
 319   case Mips::BNE_MM:
 320   case Mips::BEQZC_MM:
 321   case Mips::BNEZC_MM:
 322     return isInt<17>(BrOffset);
 323
 324   // microMIPSR3 short branches.
 325   case Mips::B16_MM:
 326     return isInt<11>(BrOffset);
 327
 328   case Mips::BEQZ16_MM:
 329   case Mips::BNEZ16_MM:
 330     return isInt<8>(BrOffset);
 331
 332   // MIPSR6 branches.
 333   case Mips::BALC:
 334   case Mips::BC:
 335     return isInt<28>(BrOffset);
 336
 337   case Mips::BC1EQZ:
 338   case Mips::BC1NEZ:
 339   case Mips::BC2EQZ:
 340   case Mips::BC2NEZ:
 341   case Mips::BEQC:   case Mips::BEQC64:
 342   case Mips::BNEC:   case Mips::BNEC64:
 343   case Mips::BGEC:   case Mips::BGEC64:
 344   case Mips::BGEUC:  case Mips::BGEUC64:
 345   case Mips::BGEZC:  case Mips::BGEZC64:
 346   case Mips::BGTZC:  case Mips::BGTZC64:
 347   case Mips::BLEZC:  case Mips::BLEZC64:
 348   case Mips::BLTC:   case Mips::BLTC64:
 349   case Mips::BLTUC:  case Mips::BLTUC64:
 350   case Mips::BLTZC:  case Mips::BLTZC64:
 351   case Mips::BNVC:
 352   case Mips::BOVC:
 353   case Mips::BGEZALC:
 354   case Mips::BEQZALC:
 355   case Mips::BGTZALC:
 356   case Mips::BLEZALC:
 357   case Mips::BLTZALC:
 358   case Mips::BNEZALC:
 359     return isInt<18>(BrOffset);
 360
 361   case Mips::BEQZC:  case Mips::BEQZC64:
 362   case Mips::BNEZC:  case Mips::BNEZC64:
 363     return isInt<23>(BrOffset);
 364
 365   // microMIPSR6 branches
 366   case Mips::BC16_MMR6:
 367     return isInt<11>(BrOffset);
 368
 369   case Mips::BEQZC16_MMR6:
 370   case Mips::BNEZC16_MMR6:
 371     return isInt<8>(BrOffset);
 372
 373   case Mips::BALC_MMR6:
 374   case Mips::BC_MMR6:
 375     return isInt<27>(BrOffset);
 376
 377   case Mips::BC1EQZC_MMR6:
 378   case Mips::BC1NEZC_MMR6:
 379   case Mips::BC2EQZC_MMR6:
 380   case Mips::BC2NEZC_MMR6:
 381   case Mips::BGEZALC_MMR6:
 382   case Mips::BEQZALC_MMR6:
 383   case Mips::BGTZALC_MMR6:
 384   case Mips::BLEZALC_MMR6:
 385   case Mips::BLTZALC_MMR6:
 386   case Mips::BNEZALC_MMR6:
 387   case Mips::BNVC_MMR6:
 388   case Mips::BOVC_MMR6:
 389     return isInt<17>(BrOffset);
 390
 391   case Mips::BEQC_MMR6:
 392   case Mips::BNEC_MMR6:
 393   case Mips::BGEC_MMR6:
 394   case Mips::BGEUC_MMR6:
 395   case Mips::BGEZC_MMR6:
 396   case Mips::BGTZC_MMR6:
 397   case Mips::BLEZC_MMR6:
 398   case Mips::BLTC_MMR6:
 399   case Mips::BLTUC_MMR6:
 400   case Mips::BLTZC_MMR6:
 401     return isInt<18>(BrOffset);
 402
 403   case Mips::BEQZC_MMR6:
 404   case Mips::BNEZC_MMR6:
 405     return isInt<23>(BrOffset);
 406
 407   // DSP branches.
 408   case Mips::BPOSGE32:
 409     return isInt<18>(BrOffset);
 410   case Mips::BPOSGE32_MM:
 411   case Mips::BPOSGE32C_MMR3:
 412     return isInt<17>(BrOffset);
 413
 414   // cnMIPS branches.
 415   case Mips::BBIT0:
 416   case Mips::BBIT032:
 417   case Mips::BBIT1:
 418   case Mips::BBIT132:
 419     return isInt<18>(BrOffset);
 420
 421   // MSA branches.
 422   case Mips::BZ_B:
 423   case Mips::BZ_H:
 424   case Mips::BZ_W:
 425   case Mips::BZ_D:
 426   case Mips::BZ_V:
 427   case Mips::BNZ_B:
 428   case Mips::BNZ_H:
 429   case Mips::BNZ_W:
 430   case Mips::BNZ_D:
 431   case Mips::BNZ_V:
 432     return isInt<18>(BrOffset);
 433   }
 434
 435   llvm_unreachable("Unknown branch instruction!");
 436 }
 437
 438 /// Return the corresponding compact (no delay slot) form of a branch.
 439 unsigned MipsInstrInfo::getEquivalentCompactForm(
 440     const MachineBasicBlock::iterator I) const {
 441   unsigned Opcode = I->getOpcode();
 442   bool canUseShortMicroMipsCTI = false;
 443
 444   if (Subtarget.inMicroMipsMode()) {
 445     switch (Opcode) {
 446     case Mips::BNE:
 447     case Mips::BNE_MM:
 448     case Mips::BEQ:
 449     case Mips::BEQ_MM:
 450     // microMIPS has NE,EQ branches that do not have delay slots provided one
 451     // of the operands is zero.
 452       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
 453         canUseShortMicroMipsCTI = true;
 454       break;
 455     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
 456     // expanded to JR_MM, so they can be replaced with JRC16_MM.
 457     case Mips::JR:
 458     case Mips::PseudoReturn:
 459     case Mips::PseudoIndirectBranch:
 460       canUseShortMicroMipsCTI = true;
 461       break;
 462     }
 463   }
 464
 465   // MIPSR6 forbids both operands being the zero register.
 466   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
 467       (I->getOperand(0).isReg() &&
 468        (I->getOperand(0).getReg() == Mips::ZERO ||
 469         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
 470       (I->getOperand(1).isReg() &&
 471        (I->getOperand(1).getReg() == Mips::ZERO ||
 472         I->getOperand(1).getReg() == Mips::ZERO_64)))
 473     return 0;
 474
 475   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
 476     switch (Opcode) {
 477     case Mips::B:
 478       return Mips::BC;
 479     case Mips::BAL:
 480       return Mips::BALC;
 481     case Mips::BEQ:
 482     case Mips::BEQ_MM:
 483       if (canUseShortMicroMipsCTI)
 484         return Mips::BEQZC_MM;
 485       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 486         return 0;
 487       return Mips::BEQC;
 488     case Mips::BNE:
 489     case Mips::BNE_MM:
 490       if (canUseShortMicroMipsCTI)
 491         return Mips::BNEZC_MM;
 492       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 493         return 0;
 494       return Mips::BNEC;
 495     case Mips::BGE:
 496       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 497         return 0;
 498       return Mips::BGEC;
 499     case Mips::BGEU:
 500       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 501         return 0;
 502       return Mips::BGEUC;
 503     case Mips::BGEZ:
 504       return Mips::BGEZC;
 505     case Mips::BGTZ:
 506       return Mips::BGTZC;
 507     case Mips::BLEZ:
 508       return Mips::BLEZC;
 509     case Mips::BLT:
 510       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 511         return 0;
 512       return Mips::BLTC;
 513     case Mips::BLTU:
 514       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 515         return 0;
 516       return Mips::BLTUC;
 517     case Mips::BLTZ:
 518       return Mips::BLTZC;
 519     case Mips::BEQ64:
 520       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 521         return 0;
 522       return Mips::BEQC64;
 523     case Mips::BNE64:
 524       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 525         return 0;
 526       return Mips::BNEC64;
 527     case Mips::BGTZ64:
 528       return Mips::BGTZC64;
 529     case Mips::BGEZ64:
 530       return Mips::BGEZC64;
 531     case Mips::BLTZ64:
 532       return Mips::BLTZC64;
 533     case Mips::BLEZ64:
 534       return Mips::BLEZC64;
 535     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
 536     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
 537     case Mips::JR:
 538     case Mips::PseudoIndirectBranchR6:
 539     case Mips::PseudoReturn:
 540     case Mips::TAILCALLR6REG:
 541       if (canUseShortMicroMipsCTI)
 542         return Mips::JRC16_MM;
 543       return Mips::JIC;
 544     case Mips::JALRPseudo:
 545       return Mips::JIALC;
 546     case Mips::JR64:
 547     case Mips::PseudoIndirectBranch64R6:
 548     case Mips::PseudoReturn64:
 549     case Mips::TAILCALL64R6REG:
 550       return Mips::JIC64;
 551     case Mips::JALR64Pseudo:
 552       return Mips::JIALC64;
 553     default:
 554       return 0;
 555     }
 556   }
 557
 558   return 0;
 559 }
 560
 561 /// Predicate for distingushing between control transfer instructions and all
 562 /// other instructions for handling forbidden slots. Consider inline assembly
 563 /// as unsafe as well.
 564 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
 565   if (MI.isInlineAsm())
 566     return false;
 567
 568   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
 569 }
 570
 571 /// Predicate for distingushing instructions that have forbidden slots.
 572 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
 573   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
 574 }
 575
 576 /// Return the number of bytes of code the specified instruction may be.
 577 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
 578   switch (MI.getOpcode()) {
 579   default:
 580     return MI.getDesc().getSize();
 581   case  TargetOpcode::INLINEASM:
 582   case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.
 583     const MachineFunction *MF = MI.getParent()->getParent();
 584     const char *AsmStr = MI.getOperand(0).getSymbolName();
 585     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
 586   }
 587   case Mips::CONSTPOOL_ENTRY:
 588     // If this machine instr is a constant pool entry, its size is recorded as
 589     // operand #2.
 590     return MI.getOperand(2).getImm();
 591   }
 592 }
 593
 594 MachineInstrBuilder
 595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
 596                                   MachineBasicBlock::iterator I) const {
 597   MachineInstrBuilder MIB;
 598
 599   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
 600   // Pick the zero form of the branch for readable assembly and for greater
 601   // branch distance in non-microMIPS mode.
 602   // Additional MIPSR6 does not permit the use of register $zero for compact
 603   // branches.
 604   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
 605   // Mips::ZERO, which is incorrect. This test should be updated to use
 606   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
 607   // are fixed.
 608   int ZeroOperandPosition = -1;
 609   bool BranchWithZeroOperand = false;
 610   if (I->isBranch() && !I->isPseudo()) {
 611     auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
 612     ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
 613     BranchWithZeroOperand = ZeroOperandPosition != -1;
 614   }
 615
 616   if (BranchWithZeroOperand) {
 617     switch (NewOpc) {
 618     case Mips::BEQC:
 619       NewOpc = Mips::BEQZC;
 620       break;
 621     case Mips::BNEC:
 622       NewOpc = Mips::BNEZC;
 623       break;
 624     case Mips::BGEC:
 625       NewOpc = Mips::BGEZC;
 626       break;
 627     case Mips::BLTC:
 628       NewOpc = Mips::BLTZC;
 629       break;
 630     case Mips::BEQC64:
 631       NewOpc = Mips::BEQZC64;
 632       break;
 633     case Mips::BNEC64:
 634       NewOpc = Mips::BNEZC64;
 635       break;
 636     }
 637   }
 638
 639   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
 640
 641   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
 642   // immediate 0 as an operand and requires the removal of it's implicit-def %ra
 643   // implicit operand as copying the implicit operations of the instructio we're
 644   // looking at will give us the correct flags.
 645   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
 646       NewOpc == Mips::JIALC64) {
 647
 648     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
 649       MIB->RemoveOperand(0);
 650
 651     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
 652       MIB.add(I->getOperand(J));
 653     }
 654
 655     MIB.addImm(0);
 656
 657     // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
 658     // add it to the new instruction.
 659     for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
 660          J < E; ++J) {
 661       const MachineOperand &MO = I->getOperand(J);
 662       if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
 663         MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
 664     }
 665
 666
 667   } else {
 668     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
 669       if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
 670         continue;
 671
 672       MIB.add(I->getOperand(J));
 673     }
 674   }
 675
 676   MIB.copyImplicitOps(*I);
 677   MIB.cloneMemRefs(*I);
 678   return MIB;
 679 }
 680
 681 bool MipsInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
 682                                           unsigned &SrcOpIdx1,
 683                                           unsigned &SrcOpIdx2) const {
 684   assert(!MI.isBundle() &&
 685          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
 686
 687   const MCInstrDesc &MCID = MI.getDesc();
 688   if (!MCID.isCommutable())
 689     return false;
 690
 691   switch (MI.getOpcode()) {
 692   case Mips::DPADD_U_H:
 693   case Mips::DPADD_U_W:
 694   case Mips::DPADD_U_D:
 695   case Mips::DPADD_S_H:
 696   case Mips::DPADD_S_W:
 697   case Mips::DPADD_S_D:
 698     // The first operand is both input and output, so it should not commute
 699     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
 700       return false;
 701
 702     if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
 703       return false;
 704     return true;
 705   }
 706   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
 707 }
 708
 709 // ins, ext, dext*, dins have the following constraints:
 710 // X <= pos      <  Y
 711 // X <  size     <= Y
 712 // X <  pos+size <= Y
 713 //
 714 // dinsm and dinsu have the following constraints:
 715 // X <= pos      <  Y
 716 // X <= size     <= Y
 717 // X <  pos+size <= Y
 718 //
 719 // The callee of verifyInsExtInstruction however gives the bounds of
 720 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
 721 // function doesn't have to vary it's behaviour based on the instruction
 722 // being checked.
 723 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
 724                                     const int64_t PosLow, const int64_t PosHigh,
 725                                     const int64_t SizeLow,
 726                                     const int64_t SizeHigh,
 727                                     const int64_t BothLow,
 728                                     const int64_t BothHigh) {
 729   MachineOperand MOPos = MI.getOperand(2);
 730   if (!MOPos.isImm()) {
 731     ErrInfo = "Position is not an immediate!";
 732     return false;
 733   }
 734   int64_t Pos = MOPos.getImm();
 735   if (!((PosLow <= Pos) && (Pos < PosHigh))) {
 736     ErrInfo = "Position operand is out of range!";
 737     return false;
 738   }
 739
 740   MachineOperand MOSize = MI.getOperand(3);
 741   if (!MOSize.isImm()) {
 742     ErrInfo = "Size operand is not an immediate!";
 743     return false;
 744   }
 745   int64_t Size = MOSize.getImm();
 746   if (!((SizeLow < Size) && (Size <= SizeHigh))) {
 747     ErrInfo = "Size operand is out of range!";
 748     return false;
 749   }
 750
 751   if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
 752     ErrInfo = "Position + Size is out of range!";
 753     return false;
 754   }
 755
 756   return true;
 757 }
 758
 759 //  Perform target specific instruction verification.
 760 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
 761                                       StringRef &ErrInfo) const {
 762   // Verify that ins and ext instructions are well formed.
 763   switch (MI.getOpcode()) {
 764     case Mips::EXT:
 765     case Mips::EXT_MM:
 766     case Mips::INS:
 767     case Mips::INS_MM:
 768     case Mips::DINS:
 769       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
 770     case Mips::DINSM:
 771       // The ISA spec has a subtle difference between dinsm and dextm
 772       // in that it says:
 773       // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
 774       // To make the bounds checks similar, the range 1 < size <= 64 is checked
 775       // for 'dinsm'.
 776       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
 777     case Mips::DINSU:
 778       // The ISA spec has a subtle difference between dinsu and dextu in that
 779       // the size range of dinsu is specified as 1 <= size <= 32 whereas size
 780       // for dextu is 0 < size <= 32. The range checked for dinsu here is
 781       // 0 < size <= 32, which is equivalent and similar to dextu.
 782       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
 783     case Mips::DEXT:
 784       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
 785     case Mips::DEXTM:
 786       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
 787     case Mips::DEXTU:
 788       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
 789     case Mips::TAILCALLREG:
 790     case Mips::PseudoIndirectBranch:
 791     case Mips::JR:
 792     case Mips::JR64:
 793     case Mips::JALR:
 794     case Mips::JALR64:
 795     case Mips::JALRPseudo:
 796       if (!Subtarget.useIndirectJumpsHazard())
 797         return true;
 798
 799       ErrInfo = "invalid instruction when using jump guards!";
 800       return false;
 801     default:
 802       return true;
 803   }
 804
 805   return true;
 806 }
 807
 808 std::pair<unsigned, unsigned>
 809 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
 810   return std::make_pair(TF, 0u);
 811 }
 812
 813 ArrayRef<std::pair<unsigned, const char*>>
 814 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
 815  using namespace MipsII;
 816
 817  static const std::pair<unsigned, const char*> Flags[] = {
 818     {MO_GOT,          "mips-got"},
 819     {MO_GOT_CALL,     "mips-got-call"},
 820     {MO_GPREL,        "mips-gprel"},
 821     {MO_ABS_HI,       "mips-abs-hi"},
 822     {MO_ABS_LO,       "mips-abs-lo"},
 823     {MO_TLSGD,        "mips-tlsgd"},
 824     {MO_TLSLDM,       "mips-tlsldm"},
 825     {MO_DTPREL_HI,    "mips-dtprel-hi"},
 826     {MO_DTPREL_LO,    "mips-dtprel-lo"},
 827     {MO_GOTTPREL,     "mips-gottprel"},
 828     {MO_TPREL_HI,     "mips-tprel-hi"},
 829     {MO_TPREL_LO,     "mips-tprel-lo"},
 830     {MO_GPOFF_HI,     "mips-gpoff-hi"},
 831     {MO_GPOFF_LO,     "mips-gpoff-lo"},
 832     {MO_GOT_DISP,     "mips-got-disp"},
 833     {MO_GOT_PAGE,     "mips-got-page"},
 834     {MO_GOT_OFST,     "mips-got-ofst"},
 835     {MO_HIGHER,       "mips-higher"},
 836     {MO_HIGHEST,      "mips-highest"},
 837     {MO_GOT_HI16,     "mips-got-hi16"},
 838     {MO_GOT_LO16,     "mips-got-lo16"},
 839     {MO_CALL_HI16,    "mips-call-hi16"},
 840     {MO_CALL_LO16,    "mips-call-lo16"},
 841     {MO_JALR,         "mips-jalr"}
 842   };
 843   return makeArrayRef(Flags);
 844 }
 845
 846 Optional<ParamLoadedValue>
 847 MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
 848   DIExpression *Expr =
 849       DIExpression::get(MI.getMF()->getFunction().getContext(), {});
 850
 851   // TODO: Special MIPS instructions that need to be described separately.
 852   if (auto RegImm = isAddImmediate(MI, Reg)) {
 853     Register SrcReg = RegImm->Reg;
 854     int64_t Offset = RegImm->Imm;
 855     // When SrcReg is $zero, treat loaded value as immediate only.
 856     // Ex. $a2 = ADDiu $zero, 10
 857     if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
 858       return ParamLoadedValue(MI.getOperand(2), Expr);
 859     }
 860     Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
 861     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
 862   } else if (auto DestSrc = isCopyInstr(MI)) {
 863     const MachineFunction *MF = MI.getMF();
 864     const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 865     Register DestReg = DestSrc->Destination->getReg();
 866     // TODO: Handle cases where the Reg is sub- or super-register of the
 867     // DestReg.
 868     if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
 869       return None;
 870   }
 871
 872   return TargetInstrInfo::describeLoadedValue(MI, Reg);
 873 }
 874
 875 Optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
 876                                                    Register Reg) const {
 877   // TODO: Handle cases where Reg is a super- or sub-register of the
 878   // destination register.
 879   const MachineOperand &Op0 = MI.getOperand(0);
 880   if (!Op0.isReg() || Reg != Op0.getReg())
 881     return None;
 882
 883   switch (MI.getOpcode()) {
 884   case Mips::ADDiu:
 885   case Mips::DADDiu: {
 886     const MachineOperand &Dop = MI.getOperand(0);
 887     const MachineOperand &Sop1 = MI.getOperand(1);
 888     const MachineOperand &Sop2 = MI.getOperand(2);
 889     // Value is sum of register and immediate. Immediate value could be
 890     // global string address which is not supported.
 891     if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
 892       return RegImmPair{Sop1.getReg(), Sop2.getImm()};
 893     // TODO: Handle case where Sop1 is a frame-index.
 894   }
 895   }
 896   return None;
 897 }