llvm/lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is the top level entry point for the PowerPC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // Get the target-independent interfaces which we are implementing.
  14 //
  15 include "llvm/Target/Target.td"
  16
  17 //===----------------------------------------------------------------------===//
  18 // PowerPC Subtarget features.
  19 //
  20
  21 //===----------------------------------------------------------------------===//
  22 // CPU Directives                                                             //
  23 //===----------------------------------------------------------------------===//
  24
  25 def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
  26 def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
  27 def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
  28 def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  29 def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  30 def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  31 def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
  32 def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
  33 def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
  34 def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
  35 def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
  36 def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
  37 def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
  38                                        "PPC::DIR_E500", "">;
  39 def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
  40                                        "PPC::DIR_E500mc", "">;
  41 def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
  42                                        "PPC::DIR_E5500", "">;
  43 def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
  44 def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
  45 def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
  46 def DirectivePwr5x
  47     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
  48 def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
  49 def DirectivePwr6x
  50     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
  51 def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
  52 def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
  53 def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
  54 def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
  55 def DirectivePwrFuture
  56     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
  57
  58 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  59                                         "Enable 64-bit instructions">;
  60 def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
  61 def FeatureModernAIXAs
  62     : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
  63                        "AIX system assembler is modern enough to support new mnes">;
  64 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
  65                               "Enable floating-point instructions">;
  66 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  67                               "Enable 64-bit registers usage for ppc32 [beta]">;
  68 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  69                               "Use condition-register bits individually">;
  70 def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
  71                                         "Enable classic FPU instructions",
  72                                         [FeatureHardFloat]>;
  73 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  74                                         "Enable Altivec instructions",
  75                                         [FeatureFPU]>;
  76 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  77                                         "Enable SPE instructions",
  78                                         [FeatureHardFloat]>;
  79 def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
  80                                         "Enable Embedded Floating-Point APU 2 instructions",
  81                                         [FeatureSPE]>;
  82 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  83                                         "Enable the MFOCRF instruction">;
  84 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  85                                         "Enable the fsqrt instruction",
  86                                         [FeatureFPU]>;
  87 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  88                                         "Enable the fcpsgn instruction",
  89                                         [FeatureFPU]>;
  90 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  91                                         "Enable the fre instruction",
  92                                         [FeatureFPU]>;
  93 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  94                                         "Enable the fres instruction",
  95                                         [FeatureFPU]>;
  96 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  97                                         "Enable the frsqrte instruction",
  98                                         [FeatureFPU]>;
  99 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
 100                                         "Enable the frsqrtes instruction",
 101                                         [FeatureFPU]>;
 102 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
 103                               "Assume higher precision reciprocal estimates">;
 104 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
 105                                         "Enable the stfiwx instruction",
 106                                         [FeatureFPU]>;
 107 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
 108                                         "Enable the lfiwax instruction",
 109                                         [FeatureFPU]>;
 110 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
 111                                         "Enable the fri[mnpz] instructions",
 112                                         [FeatureFPU]>;
 113 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
 114   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
 115                                         [FeatureFPU]>;
 116 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
 117                                         "Enable the isel instruction">;
 118 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
 119                                         "Enable the bpermd instruction">;
 120 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
 121                                         "Enable extended divide instructions">;
 122 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
 123                                         "Enable the ldbrx instruction">;
 124 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
 125                                         "Enable the cmpb instruction">;
 126 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 127                                         "Enable icbt instruction">;
 128 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 129                                         "Enable Book E instructions",
 130                                         [FeatureICBT]>;
 131 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 132                               "Has only the msync instruction instead of sync",
 133                               [FeatureBookE]>;
 134 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 135                                         "Enable E500/E500mc instructions">;
 136 def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
 137                                         "Enable secure plt mode">;
 138 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 139                                         "Enable PPC 4xx instructions">;
 140 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 141                                         "Enable PPC 6xx instructions">;
 142 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 143                                         "Enable VSX instructions",
 144                                         [FeatureAltivec]>;
 145 def FeatureTwoConstNR :
 146   SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
 147                    "Requires two constant Newton-Raphson computation">;
 148 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 149                                         "Enable POWER8 Altivec instructions",
 150                                         [FeatureAltivec]>;
 151 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 152                                        "Enable POWER8 Crypto instructions",
 153                                        [FeatureP8Altivec]>;
 154 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 155                                         "Enable POWER8 vector instructions",
 156                                         [FeatureVSX, FeatureP8Altivec]>;
 157 def FeatureDirectMove :
 158   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 159                    "Enable Power8 direct move instructions",
 160                    [FeatureVSX]>;
 161 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 162                                              "HasPartwordAtomics", "true",
 163                                              "Enable l[bh]arx and st[bh]cx.">;
 164 def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
 165                                              "HasQuadwordAtomics", "true",
 166                                              "Enable lqarx and stqcx.">;
 167 def FeatureInvariantFunctionDescriptors :
 168   SubtargetFeature<"invariant-function-descriptors",
 169                    "HasInvariantFunctionDescriptors", "true",
 170                    "Assume function descriptors are invariant">;
 171 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
 172                                        "Always use indirect calls">;
 173 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 174                                   "Enable Hardware Transactional Memory instructions">;
 175 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 176                                         "Implement mftb using the mfspr instruction">;
 177 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
 178                                      "Target supports instruction fusion">;
 179 def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
 180                                              "HasAddiLoadFusion", "true",
 181                                              "Power8 Addi-Load fusion",
 182                                              [FeatureFusion]>;
 183 def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
 184                                               "HasAddisLoadFusion", "true",
 185                                               "Power8 Addis-Load fusion",
 186                                               [FeatureFusion]>;
 187 def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
 188                                           "Target supports store clustering",
 189                                           [FeatureFusion]>;
 190 def FeatureUnalignedFloats :
 191   SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
 192                    "true", "CPU does not trap on unaligned FP access">;
 193 def FeaturePPCPreRASched:
 194   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
 195                    "Use PowerPC pre-RA scheduling strategy">;
 196 def FeaturePPCPostRASched:
 197   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
 198                    "Use PowerPC post-RA scheduling strategy">;
 199 def FeatureFloat128 :
 200   SubtargetFeature<"float128", "HasFloat128", "true",
 201                    "Enable the __float128 data type for IEEE-754R Binary128.",
 202                    [FeatureVSX]>;
 203 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
 204                                         "POPCNTD_Fast",
 205                                         "Enable the popcnt[dw] instructions">;
 206 // Note that for the a2 processor models we should not use popcnt[dw] by
 207 // default. These processors do support the instructions, but they're
 208 // microcoded, and the software emulation is about twice as fast.
 209 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
 210                                           "POPCNTD_Slow",
 211                                           "Has slow popcnt[dw] instructions">;
 212
 213 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 214   "Treat vector data stream cache control instructions as deprecated">;
 215
 216 def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
 217                                       "true",
 218                                       "Enable instructions in ISA 2.07.">;
 219 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
 220                                      "true",
 221                                      "Enable instructions in ISA 3.0.",
 222                                      [FeatureISA2_07]>;
 223 def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
 224                                      "true",
 225                                      "Enable instructions in ISA 3.1.",
 226                                      [FeatureISA3_0]>;
 227 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
 228                                         "Enable POWER9 Altivec instructions",
 229                                         [FeatureISA3_0, FeatureP8Altivec]>;
 230 def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
 231                                         "Enable POWER9 vector instructions",
 232                                         [FeatureISA3_0, FeatureP8Vector,
 233                                          FeatureP9Altivec]>;
 234 def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
 235                                          "true",
 236                                          "Enable POWER10 vector instructions",
 237                                          [FeatureISA3_1, FeatureP9Vector]>;
 238 // A separate feature for this even though it is equivalent to P9Vector
 239 // because this is a feature of the implementation rather than the architecture
 240 // and may go away with future CPU's.
 241 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
 242                                                  "VectorsUseTwoUnits",
 243                                                  "true",
 244                                                  "Vectors use two units">;
 245 def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
 246                                            "true",
 247                                            "Enable prefixed instructions",
 248                                            [FeatureISA3_0, FeatureP8Vector,
 249                                             FeatureP9Altivec]>;
 250 def FeaturePCRelativeMemops :
 251   SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
 252                    "Enable PC relative Memory Ops",
 253                    [FeatureISA3_0, FeaturePrefixInstrs]>;
 254 def FeaturePairedVectorMemops:
 255   SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
 256                    "32Byte load and store instructions",
 257                    [FeatureISA3_0]>;
 258 def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
 259                                   "Enable MMA instructions",
 260                                   [FeatureP8Vector, FeatureP9Altivec,
 261                                    FeaturePairedVectorMemops]>;
 262 def FeatureROPProtect :
 263   SubtargetFeature<"rop-protect", "HasROPProtect", "true",
 264                    "Add ROP protect">;
 265
 266 def FeaturePrivileged :
 267   SubtargetFeature<"privileged", "HasPrivileged", "true",
 268                    "Add privileged instructions">;
 269
 270 def FeaturePredictableSelectIsExpensive :
 271   SubtargetFeature<"predictable-select-expensive",
 272                    "PredictableSelectIsExpensive",
 273                    "true",
 274                    "Prefer likely predicted branches over selects">;
 275
 276 // Since new processors generally contain a superset of features of those that
 277 // came before them, the idea is to make implementations of new processors
 278 // less error prone and easier to read.
 279 // Namely:
 280 //     list<SubtargetFeature> P8InheritableFeatures = ...
 281 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 282 //         [ features that Power8 does not support but inheritable ]
 283 //     list<SubtargetFeature> FutureProcessorSpecificFeatures =
 284 //         [ features that Power8 does not support and not inheritable ]
 285 //     list<SubtargetFeature> FutureProcessorInheritableFeatures =
 286 //         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
 287 //     list<SubtargetFeature> FutureProcessorFeatures =
 288 //         !listconcat(FutureProcessorInheritableFeatures,
 289 //                     FutureProcessorSpecificFeatures)
 290
 291 // Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
 292 // well as providing a single point of definition if the feature set will be
 293 // used elsewhere.
 294 def ProcessorFeatures {
 295   // Power7
 296   list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
 297                                                   FeatureAltivec,
 298                                                   FeatureVSX,
 299                                                   FeatureMFOCRF,
 300                                                   FeatureFCPSGN,
 301                                                   FeatureFSqrt,
 302                                                   FeatureFRE,
 303                                                   FeatureFRES,
 304                                                   FeatureFRSQRTE,
 305                                                   FeatureFRSQRTES,
 306                                                   FeatureRecipPrec,
 307                                                   FeatureSTFIWX,
 308                                                   FeatureLFIWAX,
 309                                                   FeatureFPRND,
 310                                                   FeatureFPCVT,
 311                                                   FeatureISEL,
 312                                                   FeaturePOPCNTD,
 313                                                   FeatureCMPB,
 314                                                   FeatureLDBRX,
 315                                                   Feature64Bit,
 316                                                   /* Feature64BitRegs, */
 317                                                   FeatureBPERMD,
 318                                                   FeatureExtDiv,
 319                                                   FeatureMFTB,
 320                                                   DeprecatedDST,
 321                                                   FeatureTwoConstNR,
 322                                                   FeatureUnalignedFloats];
 323   list<SubtargetFeature> P7SpecificFeatures = [];
 324   list<SubtargetFeature> P7Features =
 325     !listconcat(P7InheritableFeatures, P7SpecificFeatures);
 326
 327   // Power8
 328   list<SubtargetFeature> P8AdditionalFeatures =
 329     [DirectivePwr8,
 330      FeatureP8Altivec,
 331      FeatureP8Vector,
 332      FeatureP8Crypto,
 333      FeatureHTM,
 334      FeatureDirectMove,
 335      FeatureICBT,
 336      FeaturePartwordAtomic,
 337      FeatureQuadwordAtomic,
 338      FeaturePredictableSelectIsExpensive,
 339      FeatureISA2_07
 340     ];
 341
 342   list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
 343                                                FeatureAddisLoadFusion];
 344   list<SubtargetFeature> P8InheritableFeatures =
 345     !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
 346   list<SubtargetFeature> P8Features =
 347     !listconcat(P8InheritableFeatures, P8SpecificFeatures);
 348
 349   // Power9
 350   list<SubtargetFeature> P9AdditionalFeatures =
 351     [DirectivePwr9,
 352      FeatureP9Altivec,
 353      FeatureP9Vector,
 354      FeaturePPCPreRASched,
 355      FeaturePPCPostRASched,
 356      FeatureISA3_0,
 357      FeaturePredictableSelectIsExpensive
 358     ];
 359
 360   // Some features are unique to Power9 and there is no reason to assume
 361   // they will be part of any future CPUs. One example is the narrower
 362   // dispatch for vector operations than scalar ones. For the time being,
 363   // this list also includes scheduling-related features since we do not have
 364   // enough info to create custom scheduling strategies for future CPUs.
 365   list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
 366   list<SubtargetFeature> P9InheritableFeatures =
 367     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
 368   list<SubtargetFeature> P9Features =
 369     !listconcat(P9InheritableFeatures, P9SpecificFeatures);
 370
 371   // Power10
 372   // For P10 CPU we assume that all of the existing features from Power9
 373   // still exist with the exception of those we know are Power9 specific.
 374   list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion];
 375   list<SubtargetFeature> P10AdditionalFeatures =
 376     !listconcat(FusionFeatures, [
 377        DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
 378        FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
 379        FeaturePairedVectorMemops]);
 380   list<SubtargetFeature> P10SpecificFeatures = [];
 381   list<SubtargetFeature> P10InheritableFeatures =
 382     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
 383   list<SubtargetFeature> P10Features =
 384     !listconcat(P10InheritableFeatures, P10SpecificFeatures);
 385
 386   // Future
 387   // For future CPU we assume that all of the existing features from Power10
 388   // still exist with the exception of those we know are Power10 specific.
 389   list<SubtargetFeature> FutureAdditionalFeatures = [];
 390   list<SubtargetFeature> FutureSpecificFeatures = [];
 391   list<SubtargetFeature> FutureInheritableFeatures =
 392     !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
 393   list<SubtargetFeature> FutureFeatures =
 394     !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
 395 }
 396
 397 // Note: Future features to add when support is extended to more
 398 // recent ISA levels:
 399 //
 400 // DFP          p6, p6x, p7        decimal floating-point instructions
 401 // POPCNTB      p5 through p7      popcntb and related instructions
 402
 403 //===----------------------------------------------------------------------===//
 404 // Classes used for relation maps.
 405 //===----------------------------------------------------------------------===//
 406 // RecFormRel - Filter class used to relate non-record-form instructions with
 407 // their record-form variants.
 408 class RecFormRel;
 409
 410 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 411 // FMA instruction forms with their corresponding factor-killing forms.
 412 class AltVSXFMARel {
 413   bit IsVSXFMAAlt = 0;
 414 }
 415
 416 //===----------------------------------------------------------------------===//
 417 // Relation Map Definitions.
 418 //===----------------------------------------------------------------------===//
 419
 420 def getRecordFormOpcode : InstrMapping {
 421   let FilterClass = "RecFormRel";
 422   // Instructions with the same BaseName and Interpretation64Bit values
 423   // form a row.
 424   let RowFields = ["BaseName", "Interpretation64Bit"];
 425   // Instructions with the same RC value form a column.
 426   let ColFields = ["RC"];
 427   // The key column are the non-record-form instructions.
 428   let KeyCol = ["0"];
 429   // Value columns RC=1
 430   let ValueCols = [["1"]];
 431 }
 432
 433 def getNonRecordFormOpcode : InstrMapping {
 434   let FilterClass = "RecFormRel";
 435   // Instructions with the same BaseName and Interpretation64Bit values
 436   // form a row.
 437   let RowFields = ["BaseName", "Interpretation64Bit"];
 438   // Instructions with the same RC value form a column.
 439   let ColFields = ["RC"];
 440   // The key column are the record-form instructions.
 441   let KeyCol = ["1"];
 442   // Value columns are RC=0
 443   let ValueCols = [["0"]];
 444 }
 445
 446 def getAltVSXFMAOpcode : InstrMapping {
 447   let FilterClass = "AltVSXFMARel";
 448   // Instructions with the same BaseName value form a row.
 449   let RowFields = ["BaseName"];
 450   // Instructions with the same IsVSXFMAAlt value form a column.
 451   let ColFields = ["IsVSXFMAAlt"];
 452   // The key column are the (default) addend-killing instructions.
 453   let KeyCol = ["0"];
 454   // Value columns IsVSXFMAAlt=1
 455   let ValueCols = [["1"]];
 456 }
 457
 458 //===----------------------------------------------------------------------===//
 459 // Register File Description
 460 //===----------------------------------------------------------------------===//
 461
 462 include "PPCRegisterInfo.td"
 463 include "PPCSchedule.td"
 464 include "GISel/PPCRegisterBanks.td"
 465
 466 //===----------------------------------------------------------------------===//
 467 // PowerPC processors supported.
 468 //
 469
 470 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
 471                                            FeatureMFTB]>;
 472 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 473                                           FeatureFRES, FeatureFRSQRTE,
 474                                           FeatureICBT, FeatureBookE,
 475                                           FeatureMSYNC, FeatureMFTB]>;
 476 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 477                                           FeatureFRES, FeatureFRSQRTE,
 478                                           FeatureICBT, FeatureBookE,
 479                                           FeatureMSYNC, FeatureMFTB]>;
 480 def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
 481 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
 482                                        FeatureMFTB]>;
 483 def : Processor<"603", G3Itineraries, [Directive603,
 484                                        FeatureFRES, FeatureFRSQRTE,
 485                                        FeatureMFTB]>;
 486 def : Processor<"603e", G3Itineraries, [Directive603,
 487                                         FeatureFRES, FeatureFRSQRTE,
 488                                         FeatureMFTB]>;
 489 def : Processor<"603ev", G3Itineraries, [Directive603,
 490                                          FeatureFRES, FeatureFRSQRTE,
 491                                          FeatureMFTB]>;
 492 def : Processor<"604", G3Itineraries, [Directive604,
 493                                        FeatureFRES, FeatureFRSQRTE,
 494                                        FeatureMFTB]>;
 495 def : Processor<"604e", G3Itineraries, [Directive604,
 496                                         FeatureFRES, FeatureFRSQRTE,
 497                                         FeatureMFTB]>;
 498 def : Processor<"620", G3Itineraries, [Directive620,
 499                                        FeatureFRES, FeatureFRSQRTE,
 500                                        FeatureMFTB]>;
 501 def : Processor<"750", G4Itineraries, [Directive750,
 502                                        FeatureFRES, FeatureFRSQRTE,
 503                                        FeatureMFTB]>;
 504 def : Processor<"g3", G3Itineraries, [Directive750,
 505                                       FeatureFRES, FeatureFRSQRTE,
 506                                       FeatureMFTB]>;
 507 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 508                                         FeatureFRES, FeatureFRSQRTE,
 509                                         FeatureMFTB]>;
 510 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 511                                       FeatureFRES, FeatureFRSQRTE,
 512                                       FeatureMFTB]>;
 513 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 514                                             FeatureFRES, FeatureFRSQRTE,
 515                                             FeatureMFTB]>;
 516 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 517                                            FeatureFRES, FeatureFRSQRTE,
 518                                            FeatureMFTB]>;
 519
 520 def : ProcessorModel<"970", G5Model,
 521                   [Directive970, FeatureAltivec,
 522                    FeatureMFOCRF, FeatureFSqrt,
 523                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 524                    Feature64Bit /*, Feature64BitRegs */,
 525                    FeatureMFTB]>;
 526 def : ProcessorModel<"g5", G5Model,
 527                   [Directive970, FeatureAltivec,
 528                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 529                    FeatureFRES, FeatureFRSQRTE,
 530                    Feature64Bit /*, Feature64BitRegs */,
 531                    FeatureMFTB, DeprecatedDST]>;
 532 def : ProcessorModel<"e500", PPCE500Model,
 533                   [DirectiveE500,
 534                    FeatureICBT, FeatureBookE,
 535                    FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
 536 def : ProcessorModel<"e500mc", PPCE500mcModel,
 537                   [DirectiveE500mc,
 538                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 539                    FeatureISEL, FeatureMFTB]>;
 540 def : ProcessorModel<"e5500", PPCE5500Model,
 541                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 542                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 543                    FeatureISEL, FeatureMFTB]>;
 544 def : ProcessorModel<"a2", PPCA2Model,
 545                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 546                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 547                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 548                    FeatureSTFIWX, FeatureLFIWAX,
 549                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 550                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 551                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
 552 def : ProcessorModel<"pwr3", G5Model,
 553                   [DirectivePwr3, FeatureAltivec,
 554                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 555                    FeatureSTFIWX, Feature64Bit]>;
 556 def : ProcessorModel<"pwr4", G5Model,
 557                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 558                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 559                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 560 def : ProcessorModel<"pwr5", G5Model,
 561                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 562                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 563                    FeatureFRSQRTE, FeatureFRSQRTES,
 564                    FeatureSTFIWX, Feature64Bit,
 565                    FeatureMFTB, DeprecatedDST]>;
 566 def : ProcessorModel<"pwr5x", G5Model,
 567                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 568                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 569                    FeatureFRSQRTE, FeatureFRSQRTES,
 570                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 571                    FeatureMFTB, DeprecatedDST]>;
 572 def : ProcessorModel<"pwr6", G5Model,
 573                   [DirectivePwr6, FeatureAltivec,
 574                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 575                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 576                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 577                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 578                    FeatureMFTB, DeprecatedDST]>;
 579 def : ProcessorModel<"pwr6x", G5Model,
 580                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 581                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 582                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 583                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 584                    FeatureFPRND, Feature64Bit,
 585                    FeatureMFTB, DeprecatedDST]>;
 586 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
 587 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
 588 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
 589 // No scheduler model yet.
 590 def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>;
 591 // No scheduler model for future CPU.
 592 def : ProcessorModel<"future", NoSchedModel,
 593                   ProcessorFeatures.FutureFeatures>;
 594 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
 595                                        FeatureMFTB]>;
 596 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
 597                                          FeatureMFTB]>;
 598 def : ProcessorModel<"ppc64", G5Model,
 599                   [Directive64, FeatureAltivec,
 600                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 601                    FeatureFRSQRTE, FeatureSTFIWX,
 602                    Feature64Bit /*, Feature64BitRegs */,
 603                    FeatureMFTB]>;
 604 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
 605
 606 //===----------------------------------------------------------------------===//
 607 // Calling Conventions
 608 //===----------------------------------------------------------------------===//
 609
 610 include "PPCCallingConv.td"
 611
 612 def PPCInstrInfo : InstrInfo {
 613   let isLittleEndianEncoding = 1;
 614
 615   // FIXME: Unset this when no longer needed!
 616   let decodePositionallyEncodedOperands = 1;
 617
 618   let noNamedPositionallyEncodedOperands = 1;
 619 }
 620
 621 def PPCAsmWriter : AsmWriter {
 622   string AsmWriterClassName  = "InstPrinter";
 623   int PassSubtarget = 1;
 624   int Variant = 0;
 625   bit isMCAsmWriter = 1;
 626 }
 627
 628 def PPCAsmParser : AsmParser {
 629   let ShouldEmitMatchRegisterName = 0;
 630 }
 631
 632 def PPCAsmParserVariant : AsmParserVariant {
 633   int Variant = 0;
 634
 635   // We do not use hard coded registers in asm strings.  However, some
 636   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 637   // so that those are not misinterpreted as registers.
 638   string RegisterPrefix = "%";
 639   string BreakCharacters = ".";
 640 }
 641
 642 def PPC : Target {
 643   // Information about the instructions.
 644   let InstructionSet = PPCInstrInfo;
 645
 646   let AssemblyWriters = [PPCAsmWriter];
 647   let AssemblyParsers = [PPCAsmParser];
 648   let AssemblyParserVariants = [PPCAsmParserVariant];
 649   let AllowRegisterRenaming = 1;
 650 }
 651
 652 //===----------------------------------------------------------------------===//
 653 // Pfm Counters
 654 //===----------------------------------------------------------------------===//
 655
 656 include "PPCPfmCounters.td"