llvm/lib/Target/PowerPC/PPCSubtarget.h

   1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
  14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
  15
  16 #include "PPCFrameLowering.h"
  17 #include "PPCISelLowering.h"
  18 #include "PPCInstrInfo.h"
  19 #include "llvm/ADT/Triple.h"
  20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
  24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  25 #include "llvm/IR/DataLayout.h"
  26 #include "llvm/MC/MCInstrItineraries.h"
  27 #include <string>
  28
  29 #define GET_SUBTARGETINFO_HEADER
  30 #include "PPCGenSubtargetInfo.inc"
  31
  32 // GCC #defines PPC on Linux but we use it as our namespace name
  33 #undef PPC
  34
  35 namespace llvm {
  36 class StringRef;
  37
  38 namespace PPC {
  39   // -m directive values.
  40 enum {
  41   DIR_NONE,
  42   DIR_32,
  43   DIR_440,
  44   DIR_601,
  45   DIR_602,
  46   DIR_603,
  47   DIR_7400,
  48   DIR_750,
  49   DIR_970,
  50   DIR_A2,
  51   DIR_E500,
  52   DIR_E500mc,
  53   DIR_E5500,
  54   DIR_PWR3,
  55   DIR_PWR4,
  56   DIR_PWR5,
  57   DIR_PWR5X,
  58   DIR_PWR6,
  59   DIR_PWR6X,
  60   DIR_PWR7,
  61   DIR_PWR8,
  62   DIR_PWR9,
  63   DIR_PWR10,
  64   DIR_PWR_FUTURE,
  65   DIR_64
  66 };
  67 }
  68
  69 class GlobalValue;
  70
  71 class PPCSubtarget : public PPCGenSubtargetInfo {
  72 public:
  73   enum POPCNTDKind {
  74     POPCNTD_Unavailable,
  75     POPCNTD_Slow,
  76     POPCNTD_Fast
  77   };
  78
  79 protected:
  80   /// TargetTriple - What processor and OS we're targeting.
  81   Triple TargetTriple;
  82
  83   /// stackAlignment - The minimum alignment known to hold of the stack frame on
  84   /// entry to the function and which must be maintained by every function.
  85   Align StackAlignment;
  86
  87   /// Selected instruction itineraries (one entry per itinerary class.)
  88   InstrItineraryData InstrItins;
  89
  90   /// Which cpu directive was used.
  91   unsigned CPUDirective;
  92
  93   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
  94   bool HasMFOCRF;
  95   bool Has64BitSupport;
  96   bool Use64BitRegs;
  97   bool UseCRBits;
  98   bool HasHardFloat;
  99   bool IsPPC64;
 100   bool HasAltivec;
 101   bool HasFPU;
 102   bool HasSPE;
 103   bool HasEFPU2;
 104   bool HasVSX;
 105   bool NeedsTwoConstNR;
 106   bool HasP8Vector;
 107   bool HasP8Altivec;
 108   bool HasP8Crypto;
 109   bool HasP9Vector;
 110   bool HasP9Altivec;
 111   bool HasP10Vector;
 112   bool HasPrefixInstrs;
 113   bool HasPCRelativeMemops;
 114   bool HasMMA;
 115   bool HasROPProtect;
 116   bool HasPrivileged;
 117   bool HasFCPSGN;
 118   bool HasFSQRT;
 119   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
 120   bool HasRecipPrec;
 121   bool HasSTFIWX;
 122   bool HasLFIWAX;
 123   bool HasFPRND;
 124   bool HasFPCVT;
 125   bool HasISEL;
 126   bool HasBPERMD;
 127   bool HasExtDiv;
 128   bool HasCMPB;
 129   bool HasLDBRX;
 130   bool IsBookE;
 131   bool HasOnlyMSYNC;
 132   bool IsE500;
 133   bool IsPPC4xx;
 134   bool IsPPC6xx;
 135   bool FeatureMFTB;
 136   bool AllowsUnalignedFPAccess;
 137   bool DeprecatedDST;
 138   bool IsLittleEndian;
 139   bool HasICBT;
 140   bool HasInvariantFunctionDescriptors;
 141   bool HasPartwordAtomics;
 142   bool HasQuadwordAtomics;
 143   bool HasDirectMove;
 144   bool HasHTM;
 145   bool HasFloat128;
 146   bool HasFusion;
 147   bool HasStoreFusion;
 148   bool HasAddiLoadFusion;
 149   bool HasAddisLoadFusion;
 150   bool IsISA2_07;
 151   bool IsISA3_0;
 152   bool IsISA3_1;
 153   bool UseLongCalls;
 154   bool SecurePlt;
 155   bool VectorsUseTwoUnits;
 156   bool UsePPCPreRASchedStrategy;
 157   bool UsePPCPostRASchedStrategy;
 158   bool PairedVectorMemops;
 159   bool PredictableSelectIsExpensive;
 160   bool HasModernAIXAs;
 161   bool IsAIX;
 162
 163   POPCNTDKind HasPOPCNTD;
 164
 165   const PPCTargetMachine &TM;
 166   PPCFrameLowering FrameLowering;
 167   PPCInstrInfo InstrInfo;
 168   PPCTargetLowering TLInfo;
 169   SelectionDAGTargetInfo TSInfo;
 170
 171   /// GlobalISel related APIs.
 172   std::unique_ptr<CallLowering> CallLoweringInfo;
 173   std::unique_ptr<LegalizerInfo> Legalizer;
 174   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 175   std::unique_ptr<InstructionSelector> InstSelector;
 176
 177 public:
 178   /// This constructor initializes the data members to match that
 179   /// of the specified triple.
 180   ///
 181   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
 182                const PPCTargetMachine &TM);
 183
 184   /// ParseSubtargetFeatures - Parses features string setting specified
 185   /// subtarget options.  Definition of function is auto generated by tblgen.
 186   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 187
 188   /// getStackAlignment - Returns the minimum alignment known to hold of the
 189   /// stack frame on entry to the function and which must be maintained by every
 190   /// function for this subtarget.
 191   Align getStackAlignment() const { return StackAlignment; }
 192
 193   /// getCPUDirective - Returns the -m directive specified for the cpu.
 194   ///
 195   unsigned getCPUDirective() const { return CPUDirective; }
 196
 197   /// getInstrItins - Return the instruction itineraries based on subtarget
 198   /// selection.
 199   const InstrItineraryData *getInstrItineraryData() const override {
 200     return &InstrItins;
 201   }
 202
 203   const PPCFrameLowering *getFrameLowering() const override {
 204     return &FrameLowering;
 205   }
 206   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
 207   const PPCTargetLowering *getTargetLowering() const override {
 208     return &TLInfo;
 209   }
 210   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
 211     return &TSInfo;
 212   }
 213   const PPCRegisterInfo *getRegisterInfo() const override {
 214     return &getInstrInfo()->getRegisterInfo();
 215   }
 216   const PPCTargetMachine &getTargetMachine() const { return TM; }
 217
 218   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
 219   /// so that we can use initializer lists for subtarget initialization.
 220   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 221
 222 private:
 223   void initializeEnvironment();
 224   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 225
 226 public:
 227   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
 228   ///
 229   bool isPPC64() const;
 230
 231   /// has64BitSupport - Return true if the selected CPU supports 64-bit
 232   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
 233   bool has64BitSupport() const { return Has64BitSupport; }
 234   // useSoftFloat - Return true if soft-float option is turned on.
 235   bool useSoftFloat() const {
 236     if (isAIXABI() && !HasHardFloat)
 237       report_fatal_error("soft-float is not yet supported on AIX.");
 238     return !HasHardFloat;
 239   }
 240
 241   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
 242   /// registers in 32-bit mode when possible.  This can only true if
 243   /// has64BitSupport() returns true.
 244   bool use64BitRegs() const { return Use64BitRegs; }
 245
 246   /// useCRBits - Return true if we should store and manipulate i1 values in
 247   /// the individual condition register bits.
 248   bool useCRBits() const { return UseCRBits; }
 249
 250   // isLittleEndian - True if generating little-endian code
 251   bool isLittleEndian() const { return IsLittleEndian; }
 252
 253   // Specific obvious features.
 254   bool hasFCPSGN() const { return HasFCPSGN; }
 255   bool hasFSQRT() const { return HasFSQRT; }
 256   bool hasFRE() const { return HasFRE; }
 257   bool hasFRES() const { return HasFRES; }
 258   bool hasFRSQRTE() const { return HasFRSQRTE; }
 259   bool hasFRSQRTES() const { return HasFRSQRTES; }
 260   bool hasRecipPrec() const { return HasRecipPrec; }
 261   bool hasSTFIWX() const { return HasSTFIWX; }
 262   bool hasLFIWAX() const { return HasLFIWAX; }
 263   bool hasFPRND() const { return HasFPRND; }
 264   bool hasFPCVT() const { return HasFPCVT; }
 265   bool hasAltivec() const { return HasAltivec; }
 266   bool hasSPE() const { return HasSPE; }
 267   bool hasEFPU2() const { return HasEFPU2; }
 268   bool hasFPU() const { return HasFPU; }
 269   bool hasVSX() const { return HasVSX; }
 270   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
 271   bool hasP8Vector() const { return HasP8Vector; }
 272   bool hasP8Altivec() const { return HasP8Altivec; }
 273   bool hasP8Crypto() const { return HasP8Crypto; }
 274   bool hasP9Vector() const { return HasP9Vector; }
 275   bool hasP9Altivec() const { return HasP9Altivec; }
 276   bool hasP10Vector() const { return HasP10Vector; }
 277   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
 278   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
 279   bool hasMMA() const { return HasMMA; }
 280   bool hasROPProtect() const { return HasROPProtect; }
 281   bool hasPrivileged() const { return HasPrivileged; }
 282   bool pairedVectorMemops() const { return PairedVectorMemops; }
 283   bool hasMFOCRF() const { return HasMFOCRF; }
 284   bool hasISEL() const { return HasISEL; }
 285   bool hasBPERMD() const { return HasBPERMD; }
 286   bool hasExtDiv() const { return HasExtDiv; }
 287   bool hasCMPB() const { return HasCMPB; }
 288   bool hasLDBRX() const { return HasLDBRX; }
 289   bool isBookE() const { return IsBookE; }
 290   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
 291   bool isPPC4xx() const { return IsPPC4xx; }
 292   bool isPPC6xx() const { return IsPPC6xx; }
 293   bool isSecurePlt() const {return SecurePlt; }
 294   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
 295   bool isE500() const { return IsE500; }
 296   bool isFeatureMFTB() const { return FeatureMFTB; }
 297   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
 298   bool isDeprecatedDST() const { return DeprecatedDST; }
 299   bool hasICBT() const { return HasICBT; }
 300   bool hasInvariantFunctionDescriptors() const {
 301     return HasInvariantFunctionDescriptors;
 302   }
 303   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
 304   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
 305   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
 306   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
 307   bool hasDirectMove() const { return HasDirectMove; }
 308
 309   Align getPlatformStackAlignment() const {
 310     return Align(16);
 311   }
 312
 313   unsigned  getRedZoneSize() const {
 314     if (isPPC64())
 315       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
 316       return 288;
 317
 318     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
 319     // PPC32 SVR4ABI has no redzone.
 320     return isAIXABI() ? 220 : 0;
 321   }
 322
 323   bool hasHTM() const { return HasHTM; }
 324   bool hasFloat128() const { return HasFloat128; }
 325   bool isISA2_07() const { return IsISA2_07; }
 326   bool isISA3_0() const { return IsISA3_0; }
 327   bool isISA3_1() const { return IsISA3_1; }
 328   bool useLongCalls() const { return UseLongCalls; }
 329   bool hasFusion() const { return HasFusion; }
 330   bool hasStoreFusion() const { return HasStoreFusion; }
 331   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
 332   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
 333   bool needsSwapsForVSXMemOps() const {
 334     return hasVSX() && isLittleEndian() && !hasP9Vector();
 335   }
 336
 337   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
 338
 339   const Triple &getTargetTriple() const { return TargetTriple; }
 340
 341   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 342   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 343   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 344
 345   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
 346   bool isSVR4ABI() const { return !isAIXABI(); }
 347   bool isELFv2ABI() const;
 348
 349   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
 350   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
 351   bool isUsingPCRelativeCalls() const;
 352
 353   /// Originally, this function return hasISEL(). Now we always enable it,
 354   /// but may expand the ISEL instruction later.
 355   bool enableEarlyIfConversion() const override { return true; }
 356
 357   /// Scheduling customization.
 358   bool enableMachineScheduler() const override;
 359   /// Pipeliner customization.
 360   bool enableMachinePipeliner() const override;
 361   /// Machine Pipeliner customization
 362   bool useDFAforSMS() const override;
 363   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
 364   bool enablePostRAScheduler() const override;
 365   AntiDepBreakMode getAntiDepBreakMode() const override;
 366   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
 367
 368   void overrideSchedPolicy(MachineSchedPolicy &Policy,
 369                            unsigned NumRegionInstrs) const override;
 370   bool useAA() const override;
 371
 372   bool enableSubRegLiveness() const override;
 373
 374   /// True if the GV will be accessed via an indirect symbol.
 375   bool isGVIndirectSymbol(const GlobalValue *GV) const;
 376
 377   /// True if the ABI is descriptor based.
 378   bool usesFunctionDescriptors() const {
 379     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
 380     // v1 ABI uses descriptors.
 381     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
 382   }
 383
 384   unsigned descriptorTOCAnchorOffset() const {
 385     assert(usesFunctionDescriptors() &&
 386            "Should only be called when the target uses descriptors.");
 387     return IsPPC64 ? 8 : 4;
 388   }
 389
 390   unsigned descriptorEnvironmentPointerOffset() const {
 391     assert(usesFunctionDescriptors() &&
 392            "Should only be called when the target uses descriptors.");
 393     return IsPPC64 ? 16 : 8;
 394   }
 395
 396   MCRegister getEnvironmentPointerRegister() const {
 397     assert(usesFunctionDescriptors() &&
 398            "Should only be called when the target uses descriptors.");
 399      return IsPPC64 ? PPC::X11 : PPC::R11;
 400   }
 401
 402   MCRegister getTOCPointerRegister() const {
 403     assert((is64BitELFABI() || isAIXABI()) &&
 404            "Should only be called when the target is a TOC based ABI.");
 405     return IsPPC64 ? PPC::X2 : PPC::R2;
 406   }
 407
 408   MCRegister getStackPointerRegister() const {
 409     return IsPPC64 ? PPC::X1 : PPC::R1;
 410   }
 411
 412   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
 413
 414   bool isPredictableSelectIsExpensive() const {
 415     return PredictableSelectIsExpensive;
 416   }
 417
 418   // Select allocation orders of GPRC and G8RC. It should be strictly consistent
 419   // with corresponding AltOrders in PPCRegisterInfo.td.
 420   unsigned getGPRAllocationOrderIdx() const {
 421     if (is64BitELFABI())
 422       return 1;
 423     if (isAIXABI())
 424       return 2;
 425     return 0;
 426   }
 427
 428   // GlobalISEL
 429   const CallLowering *getCallLowering() const override;
 430   const RegisterBankInfo *getRegBankInfo() const override;
 431   const LegalizerInfo *getLegalizerInfo() const override;
 432   InstructionSelector *getInstructionSelector() const override;
 433 };
 434 } // End llvm namespace
 435
 436 #endif