llvm/lib/Target/RISCV/RISCVInstrInfo.h

   1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the RISCV implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
  14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
  15
  16 #include "RISCVRegisterInfo.h"
  17 #include "llvm/CodeGen/TargetInstrInfo.h"
  18 #include "llvm/IR/DiagnosticInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "RISCVGenInstrInfo.inc"
  22
  23 namespace llvm {
  24
  25 class RISCVSubtarget;
  26
  27 namespace RISCVCC {
  28
  29 enum CondCode {
  30   COND_EQ,
  31   COND_NE,
  32   COND_LT,
  33   COND_GE,
  34   COND_LTU,
  35   COND_GEU,
  36   COND_INVALID
  37 };
  38
  39 CondCode getOppositeBranchCondition(CondCode);
  40
  41 } // end of namespace RISCVCC
  42
  43 class RISCVInstrInfo : public RISCVGenInstrInfo {
  44
  45 public:
  46   explicit RISCVInstrInfo(RISCVSubtarget &STI);
  47
  48   MCInst getNop() const override;
  49   const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
  50
  51   unsigned isLoadFromStackSlot(const MachineInstr &MI,
  52                                int &FrameIndex) const override;
  53   unsigned isStoreToStackSlot(const MachineInstr &MI,
  54                               int &FrameIndex) const override;
  55
  56   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  57                    const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
  58                    bool KillSrc) const override;
  59
  60   void storeRegToStackSlot(MachineBasicBlock &MBB,
  61                            MachineBasicBlock::iterator MBBI, Register SrcReg,
  62                            bool IsKill, int FrameIndex,
  63                            const TargetRegisterClass *RC,
  64                            const TargetRegisterInfo *TRI) const override;
  65
  66   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  67                             MachineBasicBlock::iterator MBBI, Register DstReg,
  68                             int FrameIndex, const TargetRegisterClass *RC,
  69                             const TargetRegisterInfo *TRI) const override;
  70
  71   // Materializes the given integer Val into DstReg.
  72   void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  73               const DebugLoc &DL, Register DstReg, uint64_t Val,
  74               MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
  75
  76   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
  77
  78   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  79                      MachineBasicBlock *&FBB,
  80                      SmallVectorImpl<MachineOperand> &Cond,
  81                      bool AllowModify) const override;
  82
  83   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  84                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  85                         const DebugLoc &dl,
  86                         int *BytesAdded = nullptr) const override;
  87
  88   unsigned insertIndirectBranch(MachineBasicBlock &MBB,
  89                                 MachineBasicBlock &NewDestBB,
  90                                 const DebugLoc &DL, int64_t BrOffset,
  91                                 RegScavenger *RS = nullptr) const override;
  92
  93   unsigned removeBranch(MachineBasicBlock &MBB,
  94                         int *BytesRemoved = nullptr) const override;
  95
  96   bool
  97   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
  98
  99   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 100
 101   bool isBranchOffsetInRange(unsigned BranchOpc,
 102                              int64_t BrOffset) const override;
 103
 104   bool isAsCheapAsAMove(const MachineInstr &MI) const override;
 105
 106   Optional<DestSourcePair>
 107   isCopyInstrImpl(const MachineInstr &MI) const override;
 108
 109   bool verifyInstruction(const MachineInstr &MI,
 110                          StringRef &ErrInfo) const override;
 111
 112   bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
 113                                     const MachineOperand *&BaseOp,
 114                                     int64_t &Offset, unsigned &Width,
 115                                     const TargetRegisterInfo *TRI) const;
 116
 117   bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 118                                        const MachineInstr &MIb) const override;
 119
 120
 121   std::pair<unsigned, unsigned>
 122   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 123
 124   ArrayRef<std::pair<unsigned, const char *>>
 125   getSerializableDirectMachineOperandTargetFlags() const override;
 126
 127   // Return true if the function can safely be outlined from.
 128   virtual bool
 129   isFunctionSafeToOutlineFrom(MachineFunction &MF,
 130                               bool OutlineFromLinkOnceODRs) const override;
 131
 132   // Return true if MBB is safe to outline from, and return any target-specific
 133   // information in Flags.
 134   virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
 135                                       unsigned &Flags) const override;
 136
 137   // Calculate target-specific information for a set of outlining candidates.
 138   outliner::OutlinedFunction getOutliningCandidateInfo(
 139       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
 140
 141   // Return if/how a given MachineInstr should be outlined.
 142   virtual outliner::InstrType
 143   getOutliningType(MachineBasicBlock::iterator &MBBI,
 144                    unsigned Flags) const override;
 145
 146   // Insert a custom frame for outlined functions.
 147   virtual void
 148   buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
 149                      const outliner::OutlinedFunction &OF) const override;
 150
 151   // Insert a call to an outlined function into a given basic block.
 152   virtual MachineBasicBlock::iterator
 153   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
 154                      MachineBasicBlock::iterator &It, MachineFunction &MF,
 155                      const outliner::Candidate &C) const override;
 156
 157   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
 158                              unsigned &SrcOpIdx2) const override;
 159   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
 160                                        unsigned OpIdx1,
 161                                        unsigned OpIdx2) const override;
 162
 163   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
 164                                       MachineInstr &MI,
 165                                       LiveVariables *LV) const override;
 166
 167   Register getVLENFactoredAmount(
 168       MachineFunction &MF, MachineBasicBlock &MBB,
 169       MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount,
 170       MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
 171
 172   // Returns true if the given MI is an RVV instruction opcode for which we may
 173   // expect to see a FrameIndex operand. When CheckFIs is true, the instruction
 174   // must contain at least one FrameIndex operand.
 175   bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const;
 176
 177   Optional<std::pair<unsigned, unsigned>>
 178   isRVVSpillForZvlsseg(unsigned Opcode) const;
 179
 180 protected:
 181   const RISCVSubtarget &STI;
 182 };
 183
 184 namespace RISCVVPseudosTable {
 185
 186 struct PseudoInfo {
 187   uint16_t Pseudo;
 188   uint16_t BaseInstr;
 189 };
 190
 191 #define GET_RISCVVPseudosTable_DECL
 192 #include "RISCVGenSearchableTables.inc"
 193
 194 } // end namespace RISCVVPseudosTable
 195
 196 } // end namespace llvm
 197 #endif