llvm/lib/Target/RISCV/RISCVSchedRocket.td

   1 //==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 // ===---------------------------------------------------------------------===//
  10 // The following definitions describe the simpler per-operand machine model.
  11 // This works with MachineScheduler. See MCSchedule.h for details.
  12
  13 // Rocket machine model for scheduling and other instruction cost heuristics.
  14 def RocketModel : SchedMachineModel {
  15   let MicroOpBufferSize = 0; // Rocket is in-order.
  16   let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
  17   let LoadLatency = 3;
  18   let MispredictPenalty = 3;
  19   let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
  20 }
  21
  22 //===----------------------------------------------------------------------===//
  23 // Define each kind of processor resource and number available.
  24
  25 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
  26 // Rocket is in-order.
  27
  28 let BufferSize = 0 in {
  29 def RocketUnitALU        : ProcResource<1>; // Int ALU
  30 def RocketUnitIMul       : ProcResource<1>; // Int Multiply
  31 def RocketUnitMem        : ProcResource<1>; // Load/Store
  32 def RocketUnitB          : ProcResource<1>; // Branch
  33
  34 def RocketUnitFPALU      : ProcResource<1>; // FP ALU
  35 }
  36
  37 let BufferSize = 1 in {
  38 def RocketUnitIDiv       : ProcResource<1>; // Int Division
  39 def RocketUnitFPDivSqrt  : ProcResource<1>; // FP Divide/Sqrt
  40 }
  41
  42 //===----------------------------------------------------------------------===//
  43
  44 let SchedModel = RocketModel in {
  45
  46 // Branching
  47 def : WriteRes<WriteJmp, [RocketUnitB]>;
  48 def : WriteRes<WriteJal, [RocketUnitB]>;
  49 def : WriteRes<WriteJalr, [RocketUnitB]>;
  50 def : WriteRes<WriteJmpReg, [RocketUnitB]>;
  51
  52 // Integer arithmetic and logic
  53 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
  54 def : WriteRes<WriteIALU, [RocketUnitALU]>;
  55 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
  56 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
  57 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
  58 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
  59
  60 // Integer multiplication
  61 let Latency = 4 in {
  62 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
  63 def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
  64 }
  65
  66 // Integer division
  67 // Worst case latency is used.
  68 def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
  69   let Latency = 34;
  70   let ResourceCycles = [34];
  71 }
  72 def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
  73   let Latency = 33;
  74   let ResourceCycles = [33];
  75 }
  76
  77 // Memory
  78 def : WriteRes<WriteSTB, [RocketUnitMem]>;
  79 def : WriteRes<WriteSTH, [RocketUnitMem]>;
  80 def : WriteRes<WriteSTW, [RocketUnitMem]>;
  81 def : WriteRes<WriteSTD, [RocketUnitMem]>;
  82 def : WriteRes<WriteFST32, [RocketUnitMem]>;
  83 def : WriteRes<WriteFST64, [RocketUnitMem]>;
  84
  85 let Latency = 3 in {
  86 def : WriteRes<WriteLDB, [RocketUnitMem]>;
  87 def : WriteRes<WriteLDH, [RocketUnitMem]>;
  88 }
  89
  90 let Latency = 2 in {
  91 def : WriteRes<WriteLDW, [RocketUnitMem]>;
  92 def : WriteRes<WriteLDWU, [RocketUnitMem]>;
  93 def : WriteRes<WriteLDD, [RocketUnitMem]>;
  94 def : WriteRes<WriteFLD32, [RocketUnitMem]>;
  95 def : WriteRes<WriteFLD64, [RocketUnitMem]>;
  96
  97 // Atomic memory
  98 def : WriteRes<WriteAtomicW, [RocketUnitMem]>;
  99 def : WriteRes<WriteAtomicD, [RocketUnitMem]>;
 100
 101 def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;
 102 def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;
 103 }
 104
 105 def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;
 106 def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;
 107
 108 // Single precision.
 109 let Latency = 4 in {
 110 def : WriteRes<WriteFALU32, [RocketUnitFPALU]>;
 111 def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
 112 def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
 113 }
 114
 115 // Double precision
 116 let Latency = 6 in {
 117 def : WriteRes<WriteFALU64, [RocketUnitFPALU]>;
 118 def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
 119 def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
 120 }
 121
 122 // Conversions
 123 let Latency = 2 in {
 124 def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;
 125 def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;
 126 def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;
 127 def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;
 128 def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;
 129 def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;
 130 def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;
 131 def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;
 132 def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;
 133 def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;
 134
 135 def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;
 136 def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;
 137 def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;
 138 def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;
 139 def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;
 140 def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;
 141 def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;
 142 def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
 143 }
 144
 145 // FP multiplication
 146 let Latency = 5 in {
 147 def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
 148 def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
 149 }
 150
 151 let Latency = 7 in {
 152 def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
 153 def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
 154 }
 155
 156 // FP division
 157 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
 158 let Latency = 20, ResourceCycles = [20] in {
 159 def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
 160 def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
 161 }
 162
 163 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
 164 def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
 165                                                       let ResourceCycles = [20]; }
 166 def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
 167                                                       let ResourceCycles = [25]; }
 168
 169 // Others
 170 def : WriteRes<WriteCSR, []>;
 171 def : WriteRes<WriteNop, []>;
 172
 173 def : InstRW<[WriteIALU], (instrs COPY)>;
 174
 175 //===----------------------------------------------------------------------===//
 176 // Bypass and advance
 177 def : ReadAdvance<ReadJmp, 0>;
 178 def : ReadAdvance<ReadJalr, 0>;
 179 def : ReadAdvance<ReadCSR, 0>;
 180 def : ReadAdvance<ReadStoreData, 0>;
 181 def : ReadAdvance<ReadMemBase, 0>;
 182 def : ReadAdvance<ReadIALU, 0>;
 183 def : ReadAdvance<ReadIALU32, 0>;
 184 def : ReadAdvance<ReadShiftImm, 0>;
 185 def : ReadAdvance<ReadShiftImm32, 0>;
 186 def : ReadAdvance<ReadShiftReg, 0>;
 187 def : ReadAdvance<ReadShiftReg32, 0>;
 188 def : ReadAdvance<ReadIDiv, 0>;
 189 def : ReadAdvance<ReadIDiv32, 0>;
 190 def : ReadAdvance<ReadIMul, 0>;
 191 def : ReadAdvance<ReadIMul32, 0>;
 192 def : ReadAdvance<ReadAtomicWA, 0>;
 193 def : ReadAdvance<ReadAtomicWD, 0>;
 194 def : ReadAdvance<ReadAtomicDA, 0>;
 195 def : ReadAdvance<ReadAtomicDD, 0>;
 196 def : ReadAdvance<ReadAtomicLDW, 0>;
 197 def : ReadAdvance<ReadAtomicLDD, 0>;
 198 def : ReadAdvance<ReadAtomicSTW, 0>;
 199 def : ReadAdvance<ReadAtomicSTD, 0>;
 200 def : ReadAdvance<ReadFMemBase, 0>;
 201 def : ReadAdvance<ReadFALU32, 0>;
 202 def : ReadAdvance<ReadFALU64, 0>;
 203 def : ReadAdvance<ReadFMul32, 0>;
 204 def : ReadAdvance<ReadFMA32, 0>;
 205 def : ReadAdvance<ReadFMul64, 0>;
 206 def : ReadAdvance<ReadFMA64, 0>;
 207 def : ReadAdvance<ReadFDiv32, 0>;
 208 def : ReadAdvance<ReadFDiv64, 0>;
 209 def : ReadAdvance<ReadFSqrt32, 0>;
 210 def : ReadAdvance<ReadFSqrt64, 0>;
 211 def : ReadAdvance<ReadFCmp32, 0>;
 212 def : ReadAdvance<ReadFCmp64, 0>;
 213 def : ReadAdvance<ReadFSGNJ32, 0>;
 214 def : ReadAdvance<ReadFSGNJ64, 0>;
 215 def : ReadAdvance<ReadFMinMax32, 0>;
 216 def : ReadAdvance<ReadFMinMax64, 0>;
 217 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 218 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 219 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 220 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
 221 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 222 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
 223 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 224 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 225 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 226 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
 227 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 228 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 229 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 230 def : ReadAdvance<ReadFMovI64ToF64, 0>;
 231 def : ReadAdvance<ReadFClass32, 0>;
 232 def : ReadAdvance<ReadFClass64, 0>;
 233
 234 //===----------------------------------------------------------------------===//
 235 // Unsupported extensions
 236 defm : UnsupportedSchedV;
 237 defm : UnsupportedSchedZba;
 238 defm : UnsupportedSchedZbb;
 239 defm : UnsupportedSchedZfh;
 240 }