llvm/lib/Target/RISCV/RISCVSubtarget.h

   1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
  14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
  15
  16 #include "MCTargetDesc/RISCVBaseInfo.h"
  17 #include "RISCVFrameLowering.h"
  18 #include "RISCVISelLowering.h"
  19 #include "RISCVInstrInfo.h"
  20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/IR/DataLayout.h"
  27 #include "llvm/Target/TargetMachine.h"
  28
  29 #define GET_SUBTARGETINFO_HEADER
  30 #include "RISCVGenSubtargetInfo.inc"
  31
  32 namespace llvm {
  33 class StringRef;
  34
  35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
  36   virtual void anchor();
  37   bool HasStdExtM = false;
  38   bool HasStdExtA = false;
  39   bool HasStdExtF = false;
  40   bool HasStdExtD = false;
  41   bool HasStdExtC = false;
  42   bool HasStdExtB = false;
  43   bool HasStdExtZba = false;
  44   bool HasStdExtZbb = false;
  45   bool HasStdExtZbc = false;
  46   bool HasStdExtZbe = false;
  47   bool HasStdExtZbf = false;
  48   bool HasStdExtZbm = false;
  49   bool HasStdExtZbp = false;
  50   bool HasStdExtZbr = false;
  51   bool HasStdExtZbs = false;
  52   bool HasStdExtZbt = false;
  53   bool HasStdExtZbproposedc = false;
  54   bool HasStdExtV = false;
  55   bool HasStdExtZvlsseg = false;
  56   bool HasStdExtZvamo = false;
  57   bool HasStdExtZfh = false;
  58   bool HasRV64 = false;
  59   bool IsRV32E = false;
  60   bool EnableLinkerRelax = false;
  61   bool EnableRVCHintInstrs = true;
  62   bool EnableSaveRestore = false;
  63   unsigned XLen = 32;
  64   MVT XLenVT = MVT::i32;
  65   uint8_t MaxInterleaveFactor = 2;
  66   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
  67   BitVector UserReservedRegister;
  68   RISCVFrameLowering FrameLowering;
  69   RISCVInstrInfo InstrInfo;
  70   RISCVRegisterInfo RegInfo;
  71   RISCVTargetLowering TLInfo;
  72   SelectionDAGTargetInfo TSInfo;
  73
  74   /// Initializes using the passed in CPU and feature strings so that we can
  75   /// use initializer lists for subtarget initialization.
  76   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
  77                                                   StringRef CPU,
  78                                                   StringRef TuneCPU,
  79                                                   StringRef FS,
  80                                                   StringRef ABIName);
  81
  82 public:
  83   // Initializes the data members to match that of the specified triple.
  84   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
  85                  StringRef FS, StringRef ABIName, const TargetMachine &TM);
  86
  87   // Parses features string setting specified subtarget options. The
  88   // definition of this function is auto-generated by tblgen.
  89   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
  90
  91   const RISCVFrameLowering *getFrameLowering() const override {
  92     return &FrameLowering;
  93   }
  94   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
  95   const RISCVRegisterInfo *getRegisterInfo() const override {
  96     return &RegInfo;
  97   }
  98   const RISCVTargetLowering *getTargetLowering() const override {
  99     return &TLInfo;
 100   }
 101   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
 102     return &TSInfo;
 103   }
 104   bool enableMachineScheduler() const override { return true; }
 105   bool hasStdExtM() const { return HasStdExtM; }
 106   bool hasStdExtA() const { return HasStdExtA; }
 107   bool hasStdExtF() const { return HasStdExtF; }
 108   bool hasStdExtD() const { return HasStdExtD; }
 109   bool hasStdExtC() const { return HasStdExtC; }
 110   bool hasStdExtB() const { return HasStdExtB; }
 111   bool hasStdExtZba() const { return HasStdExtZba; }
 112   bool hasStdExtZbb() const { return HasStdExtZbb; }
 113   bool hasStdExtZbc() const { return HasStdExtZbc; }
 114   bool hasStdExtZbe() const { return HasStdExtZbe; }
 115   bool hasStdExtZbf() const { return HasStdExtZbf; }
 116   bool hasStdExtZbm() const { return HasStdExtZbm; }
 117   bool hasStdExtZbp() const { return HasStdExtZbp; }
 118   bool hasStdExtZbr() const { return HasStdExtZbr; }
 119   bool hasStdExtZbs() const { return HasStdExtZbs; }
 120   bool hasStdExtZbt() const { return HasStdExtZbt; }
 121   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
 122   bool hasStdExtV() const { return HasStdExtV; }
 123   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
 124   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
 125   bool hasStdExtZfh() const { return HasStdExtZfh; }
 126   bool is64Bit() const { return HasRV64; }
 127   bool isRV32E() const { return IsRV32E; }
 128   bool enableLinkerRelax() const { return EnableLinkerRelax; }
 129   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
 130   bool enableSaveRestore() const { return EnableSaveRestore; }
 131   MVT getXLenVT() const { return XLenVT; }
 132   unsigned getXLen() const { return XLen; }
 133   RISCVABI::ABI getTargetABI() const { return TargetABI; }
 134   bool isRegisterReservedByUser(Register i) const {
 135     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
 136     return UserReservedRegister[i];
 137   }
 138   unsigned getMaxInterleaveFactor() const {
 139     return hasStdExtV() ? MaxInterleaveFactor : 1;
 140   }
 141
 142 protected:
 143   // GlobalISel related APIs.
 144   std::unique_ptr<CallLowering> CallLoweringInfo;
 145   std::unique_ptr<InstructionSelector> InstSelector;
 146   std::unique_ptr<LegalizerInfo> Legalizer;
 147   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 148
 149 public:
 150   const CallLowering *getCallLowering() const override;
 151   InstructionSelector *getInstructionSelector() const override;
 152   const LegalizerInfo *getLegalizerInfo() const override;
 153   const RegisterBankInfo *getRegBankInfo() const override;
 154
 155   // Return the known range for the bit length of RVV data registers. A value
 156   // of 0 means nothing is known about that particular limit beyond what's
 157   // implied by the architecture.
 158   unsigned getMaxRVVVectorSizeInBits() const;
 159   unsigned getMinRVVVectorSizeInBits() const;
 160   unsigned getMaxLMULForFixedLengthVectors() const;
 161   bool useRVVForFixedLengthVectors() const;
 162 };
 163 } // End llvm namespace
 164
 165 #endif