llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

   1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "MCTargetDesc/SystemZInstPrinter.h"
  10 #include "MCTargetDesc/SystemZMCAsmInfo.h"
  11 #include "MCTargetDesc/SystemZMCTargetDesc.h"
  12 #include "TargetInfo/SystemZTargetInfo.h"
  13 #include "llvm/ADT/STLExtras.h"
  14 #include "llvm/ADT/SmallVector.h"
  15 #include "llvm/ADT/StringRef.h"
  16 #include "llvm/MC/MCAsmInfo.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCExpr.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCInstBuilder.h"
  21 #include "llvm/MC/MCParser/MCAsmLexer.h"
  22 #include "llvm/MC/MCParser/MCAsmParser.h"
  23 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
  24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
  25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
  26 #include "llvm/MC/MCStreamer.h"
  27 #include "llvm/MC/MCSubtargetInfo.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/SMLoc.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include <algorithm>
  33 #include <cassert>
  34 #include <cstddef>
  35 #include <cstdint>
  36 #include <iterator>
  37 #include <memory>
  38 #include <string>
  39
  40 using namespace llvm;
  41
  42 // Return true if Expr is in the range [MinValue, MaxValue].
  43 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
  44   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
  45     int64_t Value = CE->getValue();
  46     return Value >= MinValue && Value <= MaxValue;
  47   }
  48   return false;
  49 }
  50
  51 namespace {
  52
  53 enum RegisterKind {
  54   GR32Reg,
  55   GRH32Reg,
  56   GR64Reg,
  57   GR128Reg,
  58   FP32Reg,
  59   FP64Reg,
  60   FP128Reg,
  61   VR32Reg,
  62   VR64Reg,
  63   VR128Reg,
  64   AR32Reg,
  65   CR64Reg,
  66 };
  67
  68 enum MemoryKind {
  69   BDMem,
  70   BDXMem,
  71   BDLMem,
  72   BDRMem,
  73   BDVMem
  74 };
  75
  76 class SystemZOperand : public MCParsedAsmOperand {
  77 private:
  78   enum OperandKind {
  79     KindInvalid,
  80     KindToken,
  81     KindReg,
  82     KindImm,
  83     KindImmTLS,
  84     KindMem
  85   };
  86
  87   OperandKind Kind;
  88   SMLoc StartLoc, EndLoc;
  89
  90   // A string of length Length, starting at Data.
  91   struct TokenOp {
  92     const char *Data;
  93     unsigned Length;
  94   };
  95
  96   // LLVM register Num, which has kind Kind.  In some ways it might be
  97   // easier for this class to have a register bank (general, floating-point
  98   // or access) and a raw register number (0-15).  This would postpone the
  99   // interpretation of the operand to the add*() methods and avoid the need
 100   // for context-dependent parsing.  However, we do things the current way
 101   // because of the virtual getReg() method, which needs to distinguish
 102   // between (say) %r0 used as a single register and %r0 used as a pair.
 103   // Context-dependent parsing can also give us slightly better error
 104   // messages when invalid pairs like %r1 are used.
 105   struct RegOp {
 106     RegisterKind Kind;
 107     unsigned Num;
 108   };
 109
 110   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
 111   // MemKind says what type of memory this is and RegKind says what type
 112   // the base register has (GR32Reg or GR64Reg).  Length is the operand
 113   // length for D(L,B)-style operands, otherwise it is null.
 114   struct MemOp {
 115     unsigned Base : 12;
 116     unsigned Index : 12;
 117     unsigned MemKind : 4;
 118     unsigned RegKind : 4;
 119     const MCExpr *Disp;
 120     union {
 121       const MCExpr *Imm;
 122       unsigned Reg;
 123     } Length;
 124   };
 125
 126   // Imm is an immediate operand, and Sym is an optional TLS symbol
 127   // for use with a __tls_get_offset marker relocation.
 128   struct ImmTLSOp {
 129     const MCExpr *Imm;
 130     const MCExpr *Sym;
 131   };
 132
 133   union {
 134     TokenOp Token;
 135     RegOp Reg;
 136     const MCExpr *Imm;
 137     ImmTLSOp ImmTLS;
 138     MemOp Mem;
 139   };
 140
 141   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
 142     // Add as immediates when possible.  Null MCExpr = 0.
 143     if (!Expr)
 144       Inst.addOperand(MCOperand::createImm(0));
 145     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
 146       Inst.addOperand(MCOperand::createImm(CE->getValue()));
 147     else
 148       Inst.addOperand(MCOperand::createExpr(Expr));
 149   }
 150
 151 public:
 152   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
 153       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
 154
 155   // Create particular kinds of operand.
 156   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
 157                                                        SMLoc EndLoc) {
 158     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
 159   }
 160
 161   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
 162     auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
 163     Op->Token.Data = Str.data();
 164     Op->Token.Length = Str.size();
 165     return Op;
 166   }
 167
 168   static std::unique_ptr<SystemZOperand>
 169   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
 170     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
 171     Op->Reg.Kind = Kind;
 172     Op->Reg.Num = Num;
 173     return Op;
 174   }
 175
 176   static std::unique_ptr<SystemZOperand>
 177   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
 178     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
 179     Op->Imm = Expr;
 180     return Op;
 181   }
 182
 183   static std::unique_ptr<SystemZOperand>
 184   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
 185             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
 186             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
 187     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
 188     Op->Mem.MemKind = MemKind;
 189     Op->Mem.RegKind = RegKind;
 190     Op->Mem.Base = Base;
 191     Op->Mem.Index = Index;
 192     Op->Mem.Disp = Disp;
 193     if (MemKind == BDLMem)
 194       Op->Mem.Length.Imm = LengthImm;
 195     if (MemKind == BDRMem)
 196       Op->Mem.Length.Reg = LengthReg;
 197     return Op;
 198   }
 199
 200   static std::unique_ptr<SystemZOperand>
 201   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
 202                SMLoc StartLoc, SMLoc EndLoc) {
 203     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
 204     Op->ImmTLS.Imm = Imm;
 205     Op->ImmTLS.Sym = Sym;
 206     return Op;
 207   }
 208
 209   // Token operands
 210   bool isToken() const override {
 211     return Kind == KindToken;
 212   }
 213   StringRef getToken() const {
 214     assert(Kind == KindToken && "Not a token");
 215     return StringRef(Token.Data, Token.Length);
 216   }
 217
 218   // Register operands.
 219   bool isReg() const override {
 220     return Kind == KindReg;
 221   }
 222   bool isReg(RegisterKind RegKind) const {
 223     return Kind == KindReg && Reg.Kind == RegKind;
 224   }
 225   unsigned getReg() const override {
 226     assert(Kind == KindReg && "Not a register");
 227     return Reg.Num;
 228   }
 229
 230   // Immediate operands.
 231   bool isImm() const override {
 232     return Kind == KindImm;
 233   }
 234   bool isImm(int64_t MinValue, int64_t MaxValue) const {
 235     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
 236   }
 237   const MCExpr *getImm() const {
 238     assert(Kind == KindImm && "Not an immediate");
 239     return Imm;
 240   }
 241
 242   // Immediate operands with optional TLS symbol.
 243   bool isImmTLS() const {
 244     return Kind == KindImmTLS;
 245   }
 246
 247   const ImmTLSOp getImmTLS() const {
 248     assert(Kind == KindImmTLS && "Not a TLS immediate");
 249     return ImmTLS;
 250   }
 251
 252   // Memory operands.
 253   bool isMem() const override {
 254     return Kind == KindMem;
 255   }
 256   bool isMem(MemoryKind MemKind) const {
 257     return (Kind == KindMem &&
 258             (Mem.MemKind == MemKind ||
 259              // A BDMem can be treated as a BDXMem in which the index
 260              // register field is 0.
 261              (Mem.MemKind == BDMem && MemKind == BDXMem)));
 262   }
 263   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
 264     return isMem(MemKind) && Mem.RegKind == RegKind;
 265   }
 266   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
 267     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
 268   }
 269   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
 270     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
 271   }
 272   bool isMemDisp12Len4(RegisterKind RegKind) const {
 273     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
 274   }
 275   bool isMemDisp12Len8(RegisterKind RegKind) const {
 276     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
 277   }
 278
 279   const MemOp& getMem() const {
 280     assert(Kind == KindMem && "Not a Mem operand");
 281     return Mem;
 282   }
 283
 284   // Override MCParsedAsmOperand.
 285   SMLoc getStartLoc() const override { return StartLoc; }
 286   SMLoc getEndLoc() const override { return EndLoc; }
 287   void print(raw_ostream &OS) const override;
 288
 289   /// getLocRange - Get the range between the first and last token of this
 290   /// operand.
 291   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
 292
 293   // Used by the TableGen code to add particular types of operand
 294   // to an instruction.
 295   void addRegOperands(MCInst &Inst, unsigned N) const {
 296     assert(N == 1 && "Invalid number of operands");
 297     Inst.addOperand(MCOperand::createReg(getReg()));
 298   }
 299   void addImmOperands(MCInst &Inst, unsigned N) const {
 300     assert(N == 1 && "Invalid number of operands");
 301     addExpr(Inst, getImm());
 302   }
 303   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
 304     assert(N == 2 && "Invalid number of operands");
 305     assert(isMem(BDMem) && "Invalid operand type");
 306     Inst.addOperand(MCOperand::createReg(Mem.Base));
 307     addExpr(Inst, Mem.Disp);
 308   }
 309   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
 310     assert(N == 3 && "Invalid number of operands");
 311     assert(isMem(BDXMem) && "Invalid operand type");
 312     Inst.addOperand(MCOperand::createReg(Mem.Base));
 313     addExpr(Inst, Mem.Disp);
 314     Inst.addOperand(MCOperand::createReg(Mem.Index));
 315   }
 316   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
 317     assert(N == 3 && "Invalid number of operands");
 318     assert(isMem(BDLMem) && "Invalid operand type");
 319     Inst.addOperand(MCOperand::createReg(Mem.Base));
 320     addExpr(Inst, Mem.Disp);
 321     addExpr(Inst, Mem.Length.Imm);
 322   }
 323   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
 324     assert(N == 3 && "Invalid number of operands");
 325     assert(isMem(BDRMem) && "Invalid operand type");
 326     Inst.addOperand(MCOperand::createReg(Mem.Base));
 327     addExpr(Inst, Mem.Disp);
 328     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
 329   }
 330   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
 331     assert(N == 3 && "Invalid number of operands");
 332     assert(isMem(BDVMem) && "Invalid operand type");
 333     Inst.addOperand(MCOperand::createReg(Mem.Base));
 334     addExpr(Inst, Mem.Disp);
 335     Inst.addOperand(MCOperand::createReg(Mem.Index));
 336   }
 337   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
 338     assert(N == 2 && "Invalid number of operands");
 339     assert(Kind == KindImmTLS && "Invalid operand type");
 340     addExpr(Inst, ImmTLS.Imm);
 341     if (ImmTLS.Sym)
 342       addExpr(Inst, ImmTLS.Sym);
 343   }
 344
 345   // Used by the TableGen code to check for particular operand types.
 346   bool isGR32() const { return isReg(GR32Reg); }
 347   bool isGRH32() const { return isReg(GRH32Reg); }
 348   bool isGRX32() const { return false; }
 349   bool isGR64() const { return isReg(GR64Reg); }
 350   bool isGR128() const { return isReg(GR128Reg); }
 351   bool isADDR32() const { return isReg(GR32Reg); }
 352   bool isADDR64() const { return isReg(GR64Reg); }
 353   bool isADDR128() const { return false; }
 354   bool isFP32() const { return isReg(FP32Reg); }
 355   bool isFP64() const { return isReg(FP64Reg); }
 356   bool isFP128() const { return isReg(FP128Reg); }
 357   bool isVR32() const { return isReg(VR32Reg); }
 358   bool isVR64() const { return isReg(VR64Reg); }
 359   bool isVF128() const { return false; }
 360   bool isVR128() const { return isReg(VR128Reg); }
 361   bool isAR32() const { return isReg(AR32Reg); }
 362   bool isCR64() const { return isReg(CR64Reg); }
 363   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
 364   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
 365   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
 366   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
 367   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
 368   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
 369   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
 370   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
 371   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
 372   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
 373   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
 374   bool isU1Imm() const { return isImm(0, 1); }
 375   bool isU2Imm() const { return isImm(0, 3); }
 376   bool isU3Imm() const { return isImm(0, 7); }
 377   bool isU4Imm() const { return isImm(0, 15); }
 378   bool isU6Imm() const { return isImm(0, 63); }
 379   bool isU8Imm() const { return isImm(0, 255); }
 380   bool isS8Imm() const { return isImm(-128, 127); }
 381   bool isU12Imm() const { return isImm(0, 4095); }
 382   bool isU16Imm() const { return isImm(0, 65535); }
 383   bool isS16Imm() const { return isImm(-32768, 32767); }
 384   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
 385   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
 386   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
 387 };
 388
 389 class SystemZAsmParser : public MCTargetAsmParser {
 390 #define GET_ASSEMBLER_HEADER
 391 #include "SystemZGenAsmMatcher.inc"
 392
 393 private:
 394   MCAsmParser &Parser;
 395   enum RegisterGroup {
 396     RegGR,
 397     RegFP,
 398     RegV,
 399     RegAR,
 400     RegCR
 401   };
 402   struct Register {
 403     RegisterGroup Group;
 404     unsigned Num;
 405     SMLoc StartLoc, EndLoc;
 406   };
 407
 408   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
 409
 410   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
 411
 412   OperandMatchResultTy parseRegister(OperandVector &Operands,
 413                                      RegisterKind Kind);
 414
 415   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
 416
 417   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
 418                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
 419                     bool HasLength = false, bool HasVectorIndex = false);
 420   bool parseAddressRegister(Register &Reg);
 421
 422   bool ParseDirectiveInsn(SMLoc L);
 423
 424   OperandMatchResultTy parseAddress(OperandVector &Operands,
 425                                     MemoryKind MemKind,
 426                                     RegisterKind RegKind);
 427
 428   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
 429                                   int64_t MaxVal, bool AllowTLS);
 430
 431   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 432
 433   // Both the hlasm and att variants still rely on the basic gnu asm
 434   // format with respect to inputs, clobbers, outputs etc.
 435   //
 436   // However, calling the overriden getAssemblerDialect() method in
 437   // AsmParser is problematic. It either returns the AssemblerDialect field
 438   // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
 439   // unset, otherwise it returns the private AssemblerDialect field in
 440   // AsmParser.
 441   //
 442   // The problematic part is because, we forcibly set the inline asm dialect
 443   // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
 444   // to the overriden getAssemblerDialect function in AsmParser.cpp, will
 445   // not return the assembler dialect set in the respective MCAsmInfo instance.
 446   //
 447   // For this purpose, we explicitly query the SystemZMCAsmInfo instance
 448   // here, to get the "correct" assembler dialect, and use it in various
 449   // functions.
 450   unsigned getMAIAssemblerDialect() {
 451     return Parser.getContext().getAsmInfo()->getAssemblerDialect();
 452   }
 453
 454   // An alphabetic character in HLASM is a letter from 'A' through 'Z',
 455   // or from 'a' through 'z', or '$', '_','#', or '@'.
 456   inline bool isHLASMAlpha(char C) {
 457     return isAlpha(C) || llvm::is_contained("_@#$", C);
 458   }
 459
 460   // A digit in HLASM is a number from 0 to 9.
 461   inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
 462
 463   // Are we parsing using the AD_HLASM dialect?
 464   inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
 465
 466   // Are we parsing using the AD_ATT dialect?
 467   inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
 468
 469 public:
 470   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
 471                    const MCInstrInfo &MII,
 472                    const MCTargetOptions &Options)
 473     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
 474     MCAsmParserExtension::Initialize(Parser);
 475
 476     // Alias the .word directive to .short.
 477     parser.addAliasForDirective(".word", ".short");
 478
 479     // Initialize the set of available features.
 480     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
 481   }
 482
 483   // Override MCTargetAsmParser.
 484   bool ParseDirective(AsmToken DirectiveID) override;
 485   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 486   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
 487                      bool RestoreOnFailure);
 488   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
 489                                         SMLoc &EndLoc) override;
 490   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 491                         SMLoc NameLoc, OperandVector &Operands) override;
 492   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
 493                                OperandVector &Operands, MCStreamer &Out,
 494                                uint64_t &ErrorInfo,
 495                                bool MatchingInlineAsm) override;
 496   bool isLabel(AsmToken &Token) override;
 497
 498   // Used by the TableGen code to parse particular operand types.
 499   OperandMatchResultTy parseGR32(OperandVector &Operands) {
 500     return parseRegister(Operands, GR32Reg);
 501   }
 502   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
 503     return parseRegister(Operands, GRH32Reg);
 504   }
 505   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
 506     llvm_unreachable("GRX32 should only be used for pseudo instructions");
 507   }
 508   OperandMatchResultTy parseGR64(OperandVector &Operands) {
 509     return parseRegister(Operands, GR64Reg);
 510   }
 511   OperandMatchResultTy parseGR128(OperandVector &Operands) {
 512     return parseRegister(Operands, GR128Reg);
 513   }
 514   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
 515     // For the AsmParser, we will accept %r0 for ADDR32 as well.
 516     return parseRegister(Operands, GR32Reg);
 517   }
 518   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
 519     // For the AsmParser, we will accept %r0 for ADDR64 as well.
 520     return parseRegister(Operands, GR64Reg);
 521   }
 522   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
 523     llvm_unreachable("Shouldn't be used as an operand");
 524   }
 525   OperandMatchResultTy parseFP32(OperandVector &Operands) {
 526     return parseRegister(Operands, FP32Reg);
 527   }
 528   OperandMatchResultTy parseFP64(OperandVector &Operands) {
 529     return parseRegister(Operands, FP64Reg);
 530   }
 531   OperandMatchResultTy parseFP128(OperandVector &Operands) {
 532     return parseRegister(Operands, FP128Reg);
 533   }
 534   OperandMatchResultTy parseVR32(OperandVector &Operands) {
 535     return parseRegister(Operands, VR32Reg);
 536   }
 537   OperandMatchResultTy parseVR64(OperandVector &Operands) {
 538     return parseRegister(Operands, VR64Reg);
 539   }
 540   OperandMatchResultTy parseVF128(OperandVector &Operands) {
 541     llvm_unreachable("Shouldn't be used as an operand");
 542   }
 543   OperandMatchResultTy parseVR128(OperandVector &Operands) {
 544     return parseRegister(Operands, VR128Reg);
 545   }
 546   OperandMatchResultTy parseAR32(OperandVector &Operands) {
 547     return parseRegister(Operands, AR32Reg);
 548   }
 549   OperandMatchResultTy parseCR64(OperandVector &Operands) {
 550     return parseRegister(Operands, CR64Reg);
 551   }
 552   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
 553     return parseAnyRegister(Operands);
 554   }
 555   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
 556     return parseAddress(Operands, BDMem, GR32Reg);
 557   }
 558   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
 559     return parseAddress(Operands, BDMem, GR64Reg);
 560   }
 561   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
 562     return parseAddress(Operands, BDXMem, GR64Reg);
 563   }
 564   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
 565     return parseAddress(Operands, BDLMem, GR64Reg);
 566   }
 567   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
 568     return parseAddress(Operands, BDRMem, GR64Reg);
 569   }
 570   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
 571     return parseAddress(Operands, BDVMem, GR64Reg);
 572   }
 573   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
 574     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
 575   }
 576   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
 577     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
 578   }
 579   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
 580     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
 581   }
 582   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
 583     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
 584   }
 585   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
 586     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
 587   }
 588   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
 589     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
 590   }
 591 };
 592
 593 } // end anonymous namespace
 594
 595 #define GET_REGISTER_MATCHER
 596 #define GET_SUBTARGET_FEATURE_NAME
 597 #define GET_MATCHER_IMPLEMENTATION
 598 #define GET_MNEMONIC_SPELL_CHECKER
 599 #include "SystemZGenAsmMatcher.inc"
 600
 601 // Used for the .insn directives; contains information needed to parse the
 602 // operands in the directive.
 603 struct InsnMatchEntry {
 604   StringRef Format;
 605   uint64_t Opcode;
 606   int32_t NumOperands;
 607   MatchClassKind OperandKinds[7];
 608 };
 609
 610 // For equal_range comparison.
 611 struct CompareInsn {
 612   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
 613     return LHS.Format < RHS;
 614   }
 615   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
 616     return LHS < RHS.Format;
 617   }
 618   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
 619     return LHS.Format < RHS.Format;
 620   }
 621 };
 622
 623 // Table initializing information for parsing the .insn directive.
 624 static struct InsnMatchEntry InsnMatchTable[] = {
 625   /* Format, Opcode, NumOperands, OperandKinds */
 626   { "e", SystemZ::InsnE, 1,
 627     { MCK_U16Imm } },
 628   { "ri", SystemZ::InsnRI, 3,
 629     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
 630   { "rie", SystemZ::InsnRIE, 4,
 631     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
 632   { "ril", SystemZ::InsnRIL, 3,
 633     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
 634   { "rilu", SystemZ::InsnRILU, 3,
 635     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
 636   { "ris", SystemZ::InsnRIS, 5,
 637     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
 638   { "rr", SystemZ::InsnRR, 3,
 639     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
 640   { "rre", SystemZ::InsnRRE, 3,
 641     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
 642   { "rrf", SystemZ::InsnRRF, 5,
 643     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
 644   { "rrs", SystemZ::InsnRRS, 5,
 645     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
 646   { "rs", SystemZ::InsnRS, 4,
 647     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
 648   { "rse", SystemZ::InsnRSE, 4,
 649     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
 650   { "rsi", SystemZ::InsnRSI, 4,
 651     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
 652   { "rsy", SystemZ::InsnRSY, 4,
 653     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
 654   { "rx", SystemZ::InsnRX, 3,
 655     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
 656   { "rxe", SystemZ::InsnRXE, 3,
 657     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
 658   { "rxf", SystemZ::InsnRXF, 4,
 659     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
 660   { "rxy", SystemZ::InsnRXY, 3,
 661     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
 662   { "s", SystemZ::InsnS, 2,
 663     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
 664   { "si", SystemZ::InsnSI, 3,
 665     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
 666   { "sil", SystemZ::InsnSIL, 3,
 667     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
 668   { "siy", SystemZ::InsnSIY, 3,
 669     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
 670   { "ss", SystemZ::InsnSS, 4,
 671     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
 672   { "sse", SystemZ::InsnSSE, 3,
 673     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
 674   { "ssf", SystemZ::InsnSSF, 4,
 675     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
 676   { "vri", SystemZ::InsnVRI, 6,
 677     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
 678   { "vrr", SystemZ::InsnVRR, 7,
 679     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
 680       MCK_U4Imm } },
 681   { "vrs", SystemZ::InsnVRS, 5,
 682     { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
 683   { "vrv", SystemZ::InsnVRV, 4,
 684     { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
 685   { "vrx", SystemZ::InsnVRX, 4,
 686     { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
 687   { "vsi", SystemZ::InsnVSI, 4,
 688     { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
 689 };
 690
 691 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
 692   if (!E)
 693     return;
 694   if (auto *CE = dyn_cast<MCConstantExpr>(E))
 695     OS << *CE;
 696   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
 697     OS << *UE;
 698   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
 699     OS << *BE;
 700   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
 701     OS << *SRE;
 702   else
 703     OS << *E;
 704 }
 705
 706 void SystemZOperand::print(raw_ostream &OS) const {
 707   switch (Kind) {
 708   case KindToken:
 709     OS << "Token:" << getToken();
 710     break;
 711   case KindReg:
 712     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
 713     break;
 714   case KindImm:
 715     OS << "Imm:";
 716     printMCExpr(getImm(), OS);
 717     break;
 718   case KindImmTLS:
 719     OS << "ImmTLS:";
 720     printMCExpr(getImmTLS().Imm, OS);
 721     if (getImmTLS().Sym) {
 722       OS << ", ";
 723       printMCExpr(getImmTLS().Sym, OS);
 724     }
 725     break;
 726   case KindMem: {
 727     const MemOp &Op = getMem();
 728     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
 729     if (Op.Base) {
 730       OS << "(";
 731       if (Op.MemKind == BDLMem)
 732         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
 733       else if (Op.MemKind == BDRMem)
 734         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
 735       if (Op.Index)
 736         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
 737       OS << SystemZInstPrinter::getRegisterName(Op.Base);
 738       OS << ")";
 739     }
 740     break;
 741   }
 742   case KindInvalid:
 743     break;
 744   }
 745 }
 746
 747 // Parse one register of the form %<prefix><number>.
 748 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
 749   Reg.StartLoc = Parser.getTok().getLoc();
 750
 751   // Eat the % prefix.
 752   if (Parser.getTok().isNot(AsmToken::Percent))
 753     return Error(Parser.getTok().getLoc(), "register expected");
 754   const AsmToken &PercentTok = Parser.getTok();
 755   Parser.Lex();
 756
 757   // Expect a register name.
 758   if (Parser.getTok().isNot(AsmToken::Identifier)) {
 759     if (RestoreOnFailure)
 760       getLexer().UnLex(PercentTok);
 761     return Error(Reg.StartLoc, "invalid register");
 762   }
 763
 764   // Check that there's a prefix.
 765   StringRef Name = Parser.getTok().getString();
 766   if (Name.size() < 2) {
 767     if (RestoreOnFailure)
 768       getLexer().UnLex(PercentTok);
 769     return Error(Reg.StartLoc, "invalid register");
 770   }
 771   char Prefix = Name[0];
 772
 773   // Treat the rest of the register name as a register number.
 774   if (Name.substr(1).getAsInteger(10, Reg.Num)) {
 775     if (RestoreOnFailure)
 776       getLexer().UnLex(PercentTok);
 777     return Error(Reg.StartLoc, "invalid register");
 778   }
 779
 780   // Look for valid combinations of prefix and number.
 781   if (Prefix == 'r' && Reg.Num < 16)
 782     Reg.Group = RegGR;
 783   else if (Prefix == 'f' && Reg.Num < 16)
 784     Reg.Group = RegFP;
 785   else if (Prefix == 'v' && Reg.Num < 32)
 786     Reg.Group = RegV;
 787   else if (Prefix == 'a' && Reg.Num < 16)
 788     Reg.Group = RegAR;
 789   else if (Prefix == 'c' && Reg.Num < 16)
 790     Reg.Group = RegCR;
 791   else {
 792     if (RestoreOnFailure)
 793       getLexer().UnLex(PercentTok);
 794     return Error(Reg.StartLoc, "invalid register");
 795   }
 796
 797   Reg.EndLoc = Parser.getTok().getLoc();
 798   Parser.Lex();
 799   return false;
 800 }
 801
 802 // Parse a register of kind Kind and add it to Operands.
 803 OperandMatchResultTy
 804 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
 805   Register Reg;
 806   RegisterGroup Group;
 807   switch (Kind) {
 808   case GR32Reg:
 809   case GRH32Reg:
 810   case GR64Reg:
 811   case GR128Reg:
 812     Group = RegGR;
 813     break;
 814   case FP32Reg:
 815   case FP64Reg:
 816   case FP128Reg:
 817     Group = RegFP;
 818     break;
 819   case VR32Reg:
 820   case VR64Reg:
 821   case VR128Reg:
 822     Group = RegV;
 823     break;
 824   case AR32Reg:
 825     Group = RegAR;
 826     break;
 827   case CR64Reg:
 828     Group = RegCR;
 829     break;
 830   }
 831
 832   // Handle register names of the form %<prefix><number>
 833   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
 834     if (parseRegister(Reg))
 835       return MatchOperand_ParseFail;
 836
 837     // Check the parsed register group "Reg.Group" with the expected "Group"
 838     // Have to error out if user specified wrong prefix.
 839     switch (Group) {
 840     case RegGR:
 841     case RegFP:
 842     case RegAR:
 843     case RegCR:
 844       if (Group != Reg.Group) {
 845         Error(Reg.StartLoc, "invalid operand for instruction");
 846         return MatchOperand_ParseFail;
 847       }
 848       break;
 849     case RegV:
 850       if (Reg.Group != RegV && Reg.Group != RegFP) {
 851         Error(Reg.StartLoc, "invalid operand for instruction");
 852         return MatchOperand_ParseFail;
 853       }
 854       break;
 855     }
 856   } else if (Parser.getTok().is(AsmToken::Integer)) {
 857     if (parseIntegerRegister(Reg, Group))
 858       return MatchOperand_ParseFail;
 859   }
 860   // Otherwise we didn't match a register operand.
 861   else
 862     return MatchOperand_NoMatch;
 863
 864   // Determine the LLVM register number according to Kind.
 865   const unsigned *Regs;
 866   switch (Kind) {
 867   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
 868   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
 869   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
 870   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
 871   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
 872   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
 873   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
 874   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
 875   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
 876   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
 877   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
 878   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
 879   }
 880   if (Regs[Reg.Num] == 0) {
 881     Error(Reg.StartLoc, "invalid register pair");
 882     return MatchOperand_ParseFail;
 883   }
 884
 885   Operands.push_back(
 886       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
 887   return MatchOperand_Success;
 888 }
 889
 890 // Parse any type of register (including integers) and add it to Operands.
 891 OperandMatchResultTy
 892 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
 893   SMLoc StartLoc = Parser.getTok().getLoc();
 894
 895   // Handle integer values.
 896   if (Parser.getTok().is(AsmToken::Integer)) {
 897     const MCExpr *Register;
 898     if (Parser.parseExpression(Register))
 899       return MatchOperand_ParseFail;
 900
 901     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
 902       int64_t Value = CE->getValue();
 903       if (Value < 0 || Value > 15) {
 904         Error(StartLoc, "invalid register");
 905         return MatchOperand_ParseFail;
 906       }
 907     }
 908
 909     SMLoc EndLoc =
 910       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 911
 912     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
 913   }
 914   else {
 915     if (isParsingHLASM())
 916       return MatchOperand_NoMatch;
 917
 918     Register Reg;
 919     if (parseRegister(Reg))
 920       return MatchOperand_ParseFail;
 921
 922     if (Reg.Num > 15) {
 923       Error(StartLoc, "invalid register");
 924       return MatchOperand_ParseFail;
 925     }
 926
 927     // Map to the correct register kind.
 928     RegisterKind Kind;
 929     unsigned RegNo;
 930     if (Reg.Group == RegGR) {
 931       Kind = GR64Reg;
 932       RegNo = SystemZMC::GR64Regs[Reg.Num];
 933     }
 934     else if (Reg.Group == RegFP) {
 935       Kind = FP64Reg;
 936       RegNo = SystemZMC::FP64Regs[Reg.Num];
 937     }
 938     else if (Reg.Group == RegV) {
 939       Kind = VR128Reg;
 940       RegNo = SystemZMC::VR128Regs[Reg.Num];
 941     }
 942     else if (Reg.Group == RegAR) {
 943       Kind = AR32Reg;
 944       RegNo = SystemZMC::AR32Regs[Reg.Num];
 945     }
 946     else if (Reg.Group == RegCR) {
 947       Kind = CR64Reg;
 948       RegNo = SystemZMC::CR64Regs[Reg.Num];
 949     }
 950     else {
 951       return MatchOperand_ParseFail;
 952     }
 953
 954     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
 955                                                  Reg.StartLoc, Reg.EndLoc));
 956   }
 957   return MatchOperand_Success;
 958 }
 959
 960 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
 961                                             RegisterGroup Group) {
 962   Reg.StartLoc = Parser.getTok().getLoc();
 963   // We have an integer token
 964   const MCExpr *Register;
 965   if (Parser.parseExpression(Register))
 966     return true;
 967
 968   const auto *CE = dyn_cast<MCConstantExpr>(Register);
 969   if (!CE)
 970     return true;
 971
 972   int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
 973   int64_t Value = CE->getValue();
 974   if (Value < 0 || Value > MaxRegNum) {
 975     Error(Parser.getTok().getLoc(), "invalid register");
 976     return true;
 977   }
 978
 979   // Assign the Register Number
 980   Reg.Num = (unsigned)Value;
 981   Reg.Group = Group;
 982   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 983
 984   // At this point, successfully parsed an integer register.
 985   return false;
 986 }
 987
 988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
 989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
 990                                     bool &HaveReg2, Register &Reg2,
 991                                     const MCExpr *&Disp, const MCExpr *&Length,
 992                                     bool HasLength, bool HasVectorIndex) {
 993   // Parse the displacement, which must always be present.
 994   if (getParser().parseExpression(Disp))
 995     return true;
 996
 997   // Parse the optional base and index.
 998   HaveReg1 = false;
 999   HaveReg2 = false;
1000   Length = nullptr;
1001
1002   // If we have a scenario as below:
1003   //   vgef %v0, 0(0), 0
1004   // This is an example of a "BDVMem" instruction type.
1005   //
1006   // So when we parse this as an integer register, the register group
1007   // needs to be tied to "RegV". Usually when the prefix is passed in
1008   // as %<prefix><reg-number> its easy to check which group it should belong to
1009   // However, if we're passing in just the integer there's no real way to
1010   // "check" what register group it should belong to.
1011   //
1012   // When the user passes in the register as an integer, the user assumes that
1013   // the compiler is responsible for substituting it as the right kind of
1014   // register. Whereas, when the user specifies a "prefix", the onus is on
1015   // the user to make sure they pass in the right kind of register.
1016   //
1017   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1018   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1019   // (i.e. insn is of type BDVMem) is true.
1020   RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1021
1022   if (getLexer().is(AsmToken::LParen)) {
1023     Parser.Lex();
1024
1025     if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
1026       // Parse the first register.
1027       HaveReg1 = true;
1028       if (parseRegister(Reg1))
1029         return true;
1030     }
1031     // So if we have an integer as the first token in ([tok1], ..), it could:
1032     // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1033     // instructions)
1034     // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1035     else if (getLexer().is(AsmToken::Integer)) {
1036       if (HasLength) {
1037         // Instruction has a "Length" field, safe to parse the first token as
1038         // the "Length" field
1039         if (getParser().parseExpression(Length))
1040           return true;
1041       } else {
1042         // Otherwise, if the instruction has no "Length" field, parse the
1043         // token as a "Register". We don't have to worry about whether the
1044         // instruction is invalid here, because the caller will take care of
1045         // error reporting.
1046         HaveReg1 = true;
1047         if (parseIntegerRegister(Reg1, RegGroup))
1048           return true;
1049       }
1050     } else {
1051       // If its not an integer or a percent token, then if the instruction
1052       // is reported to have a "Length" then, parse it as "Length".
1053       if (HasLength) {
1054         if (getParser().parseExpression(Length))
1055           return true;
1056       }
1057     }
1058
1059     // Check whether there's a second register.
1060     if (getLexer().is(AsmToken::Comma)) {
1061       Parser.Lex();
1062       HaveReg2 = true;
1063
1064       if (getLexer().is(AsmToken::Integer)) {
1065         if (parseIntegerRegister(Reg2, RegGR))
1066           return true;
1067       } else {
1068         if (isParsingATT() && parseRegister(Reg2))
1069           return true;
1070       }
1071     }
1072
1073     // Consume the closing bracket.
1074     if (getLexer().isNot(AsmToken::RParen))
1075       return Error(Parser.getTok().getLoc(), "unexpected token in address");
1076     Parser.Lex();
1077   }
1078   return false;
1079 }
1080
1081 // Verify that Reg is a valid address register (base or index).
1082 bool
1083 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1084   if (Reg.Group == RegV) {
1085     Error(Reg.StartLoc, "invalid use of vector addressing");
1086     return true;
1087   } else if (Reg.Group != RegGR) {
1088     Error(Reg.StartLoc, "invalid address register");
1089     return true;
1090   }
1091   return false;
1092 }
1093
1094 // Parse a memory operand and add it to Operands.  The other arguments
1095 // are as above.
1096 OperandMatchResultTy
1097 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1098                                RegisterKind RegKind) {
1099   SMLoc StartLoc = Parser.getTok().getLoc();
1100   unsigned Base = 0, Index = 0, LengthReg = 0;
1101   Register Reg1, Reg2;
1102   bool HaveReg1, HaveReg2;
1103   const MCExpr *Disp;
1104   const MCExpr *Length;
1105
1106   bool HasLength = (MemKind == BDLMem) ? true : false;
1107   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1108   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1109                    HasVectorIndex))
1110     return MatchOperand_ParseFail;
1111
1112   const unsigned *Regs;
1113   switch (RegKind) {
1114   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1115   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1116   default: llvm_unreachable("invalid RegKind");
1117   }
1118
1119   switch (MemKind) {
1120   case BDMem:
1121     // If we have Reg1, it must be an address register.
1122     if (HaveReg1) {
1123       if (parseAddressRegister(Reg1))
1124         return MatchOperand_ParseFail;
1125       Base = Regs[Reg1.Num];
1126     }
1127     // There must be no Reg2.
1128     if (HaveReg2) {
1129       Error(StartLoc, "invalid use of indexed addressing");
1130       return MatchOperand_ParseFail;
1131     }
1132     break;
1133   case BDXMem:
1134     // If we have Reg1, it must be an address register.
1135     if (HaveReg1) {
1136       if (parseAddressRegister(Reg1))
1137         return MatchOperand_ParseFail;
1138       // If the are two registers, the first one is the index and the
1139       // second is the base.
1140       if (HaveReg2)
1141         Index = Regs[Reg1.Num];
1142       else
1143         Base = Regs[Reg1.Num];
1144     }
1145     // If we have Reg2, it must be an address register.
1146     if (HaveReg2) {
1147       if (parseAddressRegister(Reg2))
1148         return MatchOperand_ParseFail;
1149       Base = Regs[Reg2.Num];
1150     }
1151     break;
1152   case BDLMem:
1153     // If we have Reg2, it must be an address register.
1154     if (HaveReg2) {
1155       if (parseAddressRegister(Reg2))
1156         return MatchOperand_ParseFail;
1157       Base = Regs[Reg2.Num];
1158     }
1159     // We cannot support base+index addressing.
1160     if (HaveReg1 && HaveReg2) {
1161       Error(StartLoc, "invalid use of indexed addressing");
1162       return MatchOperand_ParseFail;
1163     }
1164     // We must have a length.
1165     if (!Length) {
1166       Error(StartLoc, "missing length in address");
1167       return MatchOperand_ParseFail;
1168     }
1169     break;
1170   case BDRMem:
1171     // We must have Reg1, and it must be a GPR.
1172     if (!HaveReg1 || Reg1.Group != RegGR) {
1173       Error(StartLoc, "invalid operand for instruction");
1174       return MatchOperand_ParseFail;
1175     }
1176     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1177     // If we have Reg2, it must be an address register.
1178     if (HaveReg2) {
1179       if (parseAddressRegister(Reg2))
1180         return MatchOperand_ParseFail;
1181       Base = Regs[Reg2.Num];
1182     }
1183     break;
1184   case BDVMem:
1185     // We must have Reg1, and it must be a vector register.
1186     if (!HaveReg1 || Reg1.Group != RegV) {
1187       Error(StartLoc, "vector index required in address");
1188       return MatchOperand_ParseFail;
1189     }
1190     Index = SystemZMC::VR128Regs[Reg1.Num];
1191     // If we have Reg2, it must be an address register.
1192     if (HaveReg2) {
1193       if (parseAddressRegister(Reg2))
1194         return MatchOperand_ParseFail;
1195       Base = Regs[Reg2.Num];
1196     }
1197     break;
1198   }
1199
1200   SMLoc EndLoc =
1201       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1202   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1203                                                Index, Length, LengthReg,
1204                                                StartLoc, EndLoc));
1205   return MatchOperand_Success;
1206 }
1207
1208 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1209   StringRef IDVal = DirectiveID.getIdentifier();
1210
1211   if (IDVal == ".insn")
1212     return ParseDirectiveInsn(DirectiveID.getLoc());
1213
1214   return true;
1215 }
1216
1217 /// ParseDirectiveInsn
1218 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1219 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1220   MCAsmParser &Parser = getParser();
1221
1222   // Expect instruction format as identifier.
1223   StringRef Format;
1224   SMLoc ErrorLoc = Parser.getTok().getLoc();
1225   if (Parser.parseIdentifier(Format))
1226     return Error(ErrorLoc, "expected instruction format");
1227
1228   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1229
1230   // Find entry for this format in InsnMatchTable.
1231   auto EntryRange =
1232     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1233                      Format, CompareInsn());
1234
1235   // If first == second, couldn't find a match in the table.
1236   if (EntryRange.first == EntryRange.second)
1237     return Error(ErrorLoc, "unrecognized format");
1238
1239   struct InsnMatchEntry *Entry = EntryRange.first;
1240
1241   // Format should match from equal_range.
1242   assert(Entry->Format == Format);
1243
1244   // Parse the following operands using the table's information.
1245   for (int i = 0; i < Entry->NumOperands; i++) {
1246     MatchClassKind Kind = Entry->OperandKinds[i];
1247
1248     SMLoc StartLoc = Parser.getTok().getLoc();
1249
1250     // Always expect commas as separators for operands.
1251     if (getLexer().isNot(AsmToken::Comma))
1252       return Error(StartLoc, "unexpected token in directive");
1253     Lex();
1254
1255     // Parse operands.
1256     OperandMatchResultTy ResTy;
1257     if (Kind == MCK_AnyReg)
1258       ResTy = parseAnyReg(Operands);
1259     else if (Kind == MCK_VR128)
1260       ResTy = parseVR128(Operands);
1261     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1262       ResTy = parseBDXAddr64(Operands);
1263     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1264       ResTy = parseBDAddr64(Operands);
1265     else if (Kind == MCK_BDVAddr64Disp12)
1266       ResTy = parseBDVAddr64(Operands);
1267     else if (Kind == MCK_PCRel32)
1268       ResTy = parsePCRel32(Operands);
1269     else if (Kind == MCK_PCRel16)
1270       ResTy = parsePCRel16(Operands);
1271     else {
1272       // Only remaining operand kind is an immediate.
1273       const MCExpr *Expr;
1274       SMLoc StartLoc = Parser.getTok().getLoc();
1275
1276       // Expect immediate expression.
1277       if (Parser.parseExpression(Expr))
1278         return Error(StartLoc, "unexpected token in directive");
1279
1280       SMLoc EndLoc =
1281         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1282
1283       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1284       ResTy = MatchOperand_Success;
1285     }
1286
1287     if (ResTy != MatchOperand_Success)
1288       return true;
1289   }
1290
1291   // Build the instruction with the parsed operands.
1292   MCInst Inst = MCInstBuilder(Entry->Opcode);
1293
1294   for (size_t i = 0; i < Operands.size(); i++) {
1295     MCParsedAsmOperand &Operand = *Operands[i];
1296     MatchClassKind Kind = Entry->OperandKinds[i];
1297
1298     // Verify operand.
1299     unsigned Res = validateOperandClass(Operand, Kind);
1300     if (Res != Match_Success)
1301       return Error(Operand.getStartLoc(), "unexpected operand type");
1302
1303     // Add operands to instruction.
1304     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1305     if (ZOperand.isReg())
1306       ZOperand.addRegOperands(Inst, 1);
1307     else if (ZOperand.isMem(BDMem))
1308       ZOperand.addBDAddrOperands(Inst, 2);
1309     else if (ZOperand.isMem(BDXMem))
1310       ZOperand.addBDXAddrOperands(Inst, 3);
1311     else if (ZOperand.isMem(BDVMem))
1312       ZOperand.addBDVAddrOperands(Inst, 3);
1313     else if (ZOperand.isImm())
1314       ZOperand.addImmOperands(Inst, 1);
1315     else
1316       llvm_unreachable("unexpected operand type");
1317   }
1318
1319   // Emit as a regular instruction.
1320   Parser.getStreamer().emitInstruction(Inst, getSTI());
1321
1322   return false;
1323 }
1324
1325 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1326                                      SMLoc &EndLoc, bool RestoreOnFailure) {
1327   Register Reg;
1328   if (parseRegister(Reg, RestoreOnFailure))
1329     return true;
1330   if (Reg.Group == RegGR)
1331     RegNo = SystemZMC::GR64Regs[Reg.Num];
1332   else if (Reg.Group == RegFP)
1333     RegNo = SystemZMC::FP64Regs[Reg.Num];
1334   else if (Reg.Group == RegV)
1335     RegNo = SystemZMC::VR128Regs[Reg.Num];
1336   else if (Reg.Group == RegAR)
1337     RegNo = SystemZMC::AR32Regs[Reg.Num];
1338   else if (Reg.Group == RegCR)
1339     RegNo = SystemZMC::CR64Regs[Reg.Num];
1340   StartLoc = Reg.StartLoc;
1341   EndLoc = Reg.EndLoc;
1342   return false;
1343 }
1344
1345 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1346                                      SMLoc &EndLoc) {
1347   return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1348 }
1349
1350 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1351                                                         SMLoc &StartLoc,
1352                                                         SMLoc &EndLoc) {
1353   bool Result =
1354       ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1355   bool PendingErrors = getParser().hasPendingError();
1356   getParser().clearPendingErrors();
1357   if (PendingErrors)
1358     return MatchOperand_ParseFail;
1359   if (Result)
1360     return MatchOperand_NoMatch;
1361   return MatchOperand_Success;
1362 }
1363
1364 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1365                                         StringRef Name, SMLoc NameLoc,
1366                                         OperandVector &Operands) {
1367
1368   // Apply mnemonic aliases first, before doing anything else, in
1369   // case the target uses it.
1370   applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1371
1372   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1373
1374   // Read the remaining operands.
1375   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1376     // Read the first operand.
1377     if (parseOperand(Operands, Name)) {
1378       return true;
1379     }
1380
1381     // Read any subsequent operands.
1382     while (getLexer().is(AsmToken::Comma)) {
1383       Parser.Lex();
1384
1385       if (isParsingHLASM() && getLexer().is(AsmToken::Space))
1386         return Error(
1387             Parser.getTok().getLoc(),
1388             "No space allowed between comma that separates operand entries");
1389
1390       if (parseOperand(Operands, Name)) {
1391         return true;
1392       }
1393     }
1394
1395     // Under the HLASM variant, we could have the remark field
1396     // The remark field occurs after the operation entries
1397     // There is a space that separates the operation entries and the
1398     // remark field.
1399     if (isParsingHLASM() && getTok().is(AsmToken::Space)) {
1400       // We've confirmed that there is a Remark field.
1401       StringRef Remark(getLexer().LexUntilEndOfStatement());
1402       Parser.Lex();
1403
1404       // If there is nothing after the space, then there is nothing to emit
1405       // We could have a situation as this:
1406       // "  \n"
1407       // After lexing above, we will have
1408       // "\n"
1409       // This isn't an explicit remark field, so we don't have to output
1410       // this as a comment.
1411       if (Remark.size())
1412         // Output the entire Remarks Field as a comment
1413         getStreamer().AddComment(Remark);
1414     }
1415
1416     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1417       SMLoc Loc = getLexer().getLoc();
1418       return Error(Loc, "unexpected token in argument list");
1419     }
1420   }
1421
1422   // Consume the EndOfStatement.
1423   Parser.Lex();
1424   return false;
1425 }
1426
1427 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1428                                     StringRef Mnemonic) {
1429   // Check if the current operand has a custom associated parser, if so, try to
1430   // custom parse the operand, or fallback to the general approach.  Force all
1431   // features to be available during the operand check, or else we will fail to
1432   // find the custom parser, and then we will later get an InvalidOperand error
1433   // instead of a MissingFeature errror.
1434   FeatureBitset AvailableFeatures = getAvailableFeatures();
1435   FeatureBitset All;
1436   All.set();
1437   setAvailableFeatures(All);
1438   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1439   setAvailableFeatures(AvailableFeatures);
1440   if (ResTy == MatchOperand_Success)
1441     return false;
1442
1443   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1444   // there was a match, but an error occurred, in which case, just return that
1445   // the operand parsing failed.
1446   if (ResTy == MatchOperand_ParseFail)
1447     return true;
1448
1449   // Check for a register.  All real register operands should have used
1450   // a context-dependent parse routine, which gives the required register
1451   // class.  The code is here to mop up other cases, like those where
1452   // the instruction isn't recognized.
1453   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
1454     Register Reg;
1455     if (parseRegister(Reg))
1456       return true;
1457     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1458     return false;
1459   }
1460
1461   // The only other type of operand is an immediate or address.  As above,
1462   // real address operands should have used a context-dependent parse routine,
1463   // so we treat any plain expression as an immediate.
1464   SMLoc StartLoc = Parser.getTok().getLoc();
1465   Register Reg1, Reg2;
1466   bool HaveReg1, HaveReg2;
1467   const MCExpr *Expr;
1468   const MCExpr *Length;
1469   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1470                    /*HasLength*/ true, /*HasVectorIndex*/ true))
1471     return true;
1472   // If the register combination is not valid for any instruction, reject it.
1473   // Otherwise, fall back to reporting an unrecognized instruction.
1474   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1475       && parseAddressRegister(Reg1))
1476     return true;
1477   if (HaveReg2 && parseAddressRegister(Reg2))
1478     return true;
1479
1480   SMLoc EndLoc =
1481     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1482   if (HaveReg1 || HaveReg2 || Length)
1483     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1484   else
1485     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1486   return false;
1487 }
1488
1489 static std::string SystemZMnemonicSpellCheck(StringRef S,
1490                                              const FeatureBitset &FBS,
1491                                              unsigned VariantID = 0);
1492
1493 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1494                                                OperandVector &Operands,
1495                                                MCStreamer &Out,
1496                                                uint64_t &ErrorInfo,
1497                                                bool MatchingInlineAsm) {
1498   MCInst Inst;
1499   unsigned MatchResult;
1500
1501   unsigned Dialect = getMAIAssemblerDialect();
1502
1503   FeatureBitset MissingFeatures;
1504   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1505                                      MatchingInlineAsm, Dialect);
1506   switch (MatchResult) {
1507   case Match_Success:
1508     Inst.setLoc(IDLoc);
1509     Out.emitInstruction(Inst, getSTI());
1510     return false;
1511
1512   case Match_MissingFeature: {
1513     assert(MissingFeatures.any() && "Unknown missing feature!");
1514     // Special case the error message for the very common case where only
1515     // a single subtarget feature is missing
1516     std::string Msg = "instruction requires:";
1517     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1518       if (MissingFeatures[I]) {
1519         Msg += " ";
1520         Msg += getSubtargetFeatureName(I);
1521       }
1522     }
1523     return Error(IDLoc, Msg);
1524   }
1525
1526   case Match_InvalidOperand: {
1527     SMLoc ErrorLoc = IDLoc;
1528     if (ErrorInfo != ~0ULL) {
1529       if (ErrorInfo >= Operands.size())
1530         return Error(IDLoc, "too few operands for instruction");
1531
1532       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1533       if (ErrorLoc == SMLoc())
1534         ErrorLoc = IDLoc;
1535     }
1536     return Error(ErrorLoc, "invalid operand for instruction");
1537   }
1538
1539   case Match_MnemonicFail: {
1540     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1541     std::string Suggestion = SystemZMnemonicSpellCheck(
1542         ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1543     return Error(IDLoc, "invalid instruction" + Suggestion,
1544                  ((SystemZOperand &)*Operands[0]).getLocRange());
1545   }
1546   }
1547
1548   llvm_unreachable("Unexpected match type");
1549 }
1550
1551 OperandMatchResultTy
1552 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1553                              int64_t MaxVal, bool AllowTLS) {
1554   MCContext &Ctx = getContext();
1555   MCStreamer &Out = getStreamer();
1556   const MCExpr *Expr;
1557   SMLoc StartLoc = Parser.getTok().getLoc();
1558   if (getParser().parseExpression(Expr))
1559     return MatchOperand_NoMatch;
1560
1561   auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1562     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1563       int64_t Value = CE->getValue();
1564       if ((Value & 1) || Value < MinVal || Value > MaxVal)
1565         return true;
1566     }
1567     return false;
1568   };
1569
1570   // For consistency with the GNU assembler, treat immediates as offsets
1571   // from ".".
1572   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1573     if (isParsingHLASM()) {
1574       Error(StartLoc, "Expected PC-relative expression");
1575       return MatchOperand_ParseFail;
1576     }
1577     if (isOutOfRangeConstant(CE)) {
1578       Error(StartLoc, "offset out of range");
1579       return MatchOperand_ParseFail;
1580     }
1581     int64_t Value = CE->getValue();
1582     MCSymbol *Sym = Ctx.createTempSymbol();
1583     Out.emitLabel(Sym);
1584     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1585                                                  Ctx);
1586     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1587   }
1588
1589   // For consistency with the GNU assembler, conservatively assume that a
1590   // constant offset must by itself be within the given size range.
1591   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1592     if (isOutOfRangeConstant(BE->getLHS()) ||
1593         isOutOfRangeConstant(BE->getRHS())) {
1594       Error(StartLoc, "offset out of range");
1595       return MatchOperand_ParseFail;
1596     }
1597
1598   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1599   const MCExpr *Sym = nullptr;
1600   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1601     Parser.Lex();
1602
1603     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1604       Error(Parser.getTok().getLoc(), "unexpected token");
1605       return MatchOperand_ParseFail;
1606     }
1607
1608     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1609     StringRef Name = Parser.getTok().getString();
1610     if (Name == "tls_gdcall")
1611       Kind = MCSymbolRefExpr::VK_TLSGD;
1612     else if (Name == "tls_ldcall")
1613       Kind = MCSymbolRefExpr::VK_TLSLDM;
1614     else {
1615       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1616       return MatchOperand_ParseFail;
1617     }
1618     Parser.Lex();
1619
1620     if (Parser.getTok().isNot(AsmToken::Colon)) {
1621       Error(Parser.getTok().getLoc(), "unexpected token");
1622       return MatchOperand_ParseFail;
1623     }
1624     Parser.Lex();
1625
1626     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1627       Error(Parser.getTok().getLoc(), "unexpected token");
1628       return MatchOperand_ParseFail;
1629     }
1630
1631     StringRef Identifier = Parser.getTok().getString();
1632     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1633                                   Kind, Ctx);
1634     Parser.Lex();
1635   }
1636
1637   SMLoc EndLoc =
1638     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1639
1640   if (AllowTLS)
1641     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1642                                                     StartLoc, EndLoc));
1643   else
1644     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1645
1646   return MatchOperand_Success;
1647 }
1648
1649 bool SystemZAsmParser::isLabel(AsmToken &Token) {
1650   if (isParsingATT())
1651     return true;
1652
1653   // HLASM labels are ordinary symbols.
1654   // An HLASM label always starts at column 1.
1655   // An ordinary symbol syntax is laid out as follows:
1656   // Rules:
1657   // 1. Has to start with an "alphabetic character". Can be followed by up to
1658   //    62 alphanumeric characters. An "alphabetic character", in this scenario,
1659   //    is a letter from 'A' through 'Z', or from 'a' through 'z',
1660   //    or '$', '_', '#', or '@'
1661   // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1662   //    are all treated as the same symbol. However, the processing for the case
1663   //    folding will not be done in this function.
1664   StringRef RawLabel = Token.getString();
1665   SMLoc Loc = Token.getLoc();
1666
1667   // An HLASM label cannot be empty.
1668   if (!RawLabel.size())
1669     return !Error(Loc, "HLASM Label cannot be empty");
1670
1671   // An HLASM label cannot exceed greater than 63 characters.
1672   if (RawLabel.size() > 63)
1673     return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1674
1675   // A label must start with an "alphabetic character".
1676   if (!isHLASMAlpha(RawLabel[0]))
1677     return !Error(Loc, "HLASM Label has to start with an alphabetic "
1678                        "character or the underscore character");
1679
1680   // Now, we've established that the length is valid
1681   // and the first character is alphabetic.
1682   // Check whether remaining string is alphanumeric.
1683   for (unsigned I = 1; I < RawLabel.size(); ++I)
1684     if (!isHLASMAlnum(RawLabel[I]))
1685       return !Error(Loc, "HLASM Label has to be alphanumeric");
1686
1687   return true;
1688 }
1689
1690 // Force static initialization.
1691 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1692   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1693 }