| blob | 4a8476f7288a36273343470b06d959c04f5ffc52 |
1 //===----------------------------------------------------------------------===//
2 // Vector Instructions
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
6 // Pseudo instructions for VM512 modifications
7 //===----------------------------------------------------------------------===//
9 // LVM/SVM instructions using VM512
10 let hasSideEffects = 0, isCodeGenOnly = 1 in {
11 let Constraints = "$vx = $vd", DisableEncoding = "$vd" in {
12 def LVMyir_y : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz, VM512:$vd),
13 "# pseudo LVM $vx, $sy, $sz, $vd">;
14 def LVMyim_y : Pseudo<(outs VM512:$vx),
15 (ins uimm3:$sy, mimm:$sz, VM512:$vd),
16 "# pseudo LVM $vx, $sy, $sz, $vd">;
17 }
18 def LVMyir : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz),
19 "# pseudo LVM $vx, $sy, $sz">;
20 def LVMyim : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, mimm:$sz),
21 "# pseudo LVM $vx, $sy, $sz">;
22 def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy),
23 "# pseudo SVM $sx, $vz, $sy">;
24 }
26 // VFMK/VFMKW/VFMKS instructions using VM512
27 let hasSideEffects = 0, isCodeGenOnly = 1, DisableEncoding = "$vl" in {
28 def VFMKyal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),
29 "# pseudo-vfmk.at $vmx">;
30 def VFMKynal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),
31 "# pseudo-vfmk.af $vmx">;
32 def VFMKWyvl : Pseudo<(outs VM512:$vmx),
33 (ins CCOp:$cf, V64:$vz, I32:$vl),
34 "# pseudo-vfmk.w.$cf $vmx, $vz">;
35 def VFMKWyvyl : Pseudo<(outs VM512:$vmx),
36 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
37 "# pseudo-vfmk.w.$cf $vmx, $vz, $vm">;
38 def VFMKSyvl : Pseudo<(outs VM512:$vmx),
39 (ins CCOp:$cf, V64:$vz, I32:$vl),
40 "# pseudo-vfmk.s.$cf $vmx, $vz">;
41 def VFMKSyvyl : Pseudo<(outs VM512:$vmx),
42 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
43 "# pseudo-vfmk.s.$cf $vmx, $vz, $vm">;
44 }
46 // ANDM/ORM/XORM/EQVM/NNDM/NEGM instructions using VM512
47 let hasSideEffects = 0, isCodeGenOnly = 1 in {
48 def ANDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
49 "# andm $vmx, $vmy, $vmz">;
50 def ORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
51 "# orm $vmx, $vmy, $vmz">;
52 def XORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
53 "# xorm $vmx, $vmy, $vmz">;
54 def EQVMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
55 "# eqvm $vmx, $vmy, $vmz">;
56 def NNDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),
57 "# nndm $vmx, $vmy, $vmz">;
58 def NEGMy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy),
59 "# negm $vmx, $vmy">;
60 }
62 //===----------------------------------------------------------------------===//
63 // Instructions
64 //
65 // Define all vector instructions defined in SX-Aurora TSUBASA Architecture
66 // Guide here. As those mnemonics, we use mnemonics defined in Vector Engine
67 // Assembly Language Reference Manual.
68 //
69 // Some instructions can update existing data by following instructions
70 // sequence.
71 //
72 // lea %s0, 256
73 // lea %s1, 128
74 // lvl %s0
75 // vbrd %v0, 2 # v0 = { 2, 2, 2, ..., 2, 2, 2 }
76 // lvl %s1
77 // vbrd %v0, 3 # v0 = { 3, 3, 3, ..., 3, 2, 2, 2, ..., 2, 2, 2 }
78 //
79 // In order to represent above with a virtual register, we defines instructions
80 // with an additional base register and `_v` suffiex in mnemonic.
81 //
82 // lea t0, 256
83 // lea t1, 128
84 // lea t0
85 // vbrd tv0, 2
86 // lvl t1
87 // vbrd_v tv1, 2, tv0
88 //
89 // We also have some instructions uses VL register with an pseudo VL value
90 // with following suffixes in mnemonic.
91 //
92 // l: have an additional I32 register to represent the VL value.
93 // L: have an additional VL register to represent the VL value.
94 //===----------------------------------------------------------------------===//
96 //-----------------------------------------------------------------------------
97 // Section 8.9 - Vector Load/Store and Move Instructions
98 //-----------------------------------------------------------------------------
100 // Multiclass for VLD instructions
101 let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
102 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
103 string disEnc = ""> {
104 let DisableEncoding = disEnc in
105 def "" : RVM<opc, (outs RC:$vx), dag_in,
106 !strconcat(opcStr, " $vx, $sy, $sz")>;
107 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
108 isCodeGenOnly = 1 in
109 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
110 !strconcat(opcStr, " $vx, $sy, $sz")>;
111 }
112 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
113 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
114 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
115 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
116 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
117 }
118 }
119 let VE_VLIndex = 3 in
120 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
121 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
122 let cy = 0 in
123 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
124 let cz = 0 in
125 defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>;
126 let cy = 0, cz = 0 in
127 defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>;
128 }
129 multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {
130 let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;
131 let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;
132 }
134 // Section 8.9.1 - VLD (Vector Load)
135 defm VLD : VLDm<"vld", 0x81, V64>;
137 // Section 8.9.2 - VLDU (Vector Load Upper)
138 defm VLDU : VLDm<"vldu", 0x82, V64>;
140 // Section 8.9.3 - VLDL (Vector Load Lower)
141 defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>;
142 let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>;
144 // Section 8.9.4 - VLD2D (Vector Load 2D)
145 defm VLD2D : VLDm<"vld2d", 0xc1, V64>;
147 // Section 8.9.5 - VLDU2D (Vector Load Upper 2D)
148 defm VLDU2D : VLDm<"vldu2d", 0xc2, V64>;
150 // Section 8.9.6 - VLDL2D (Vector Load Lower 2D)
151 defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>;
152 let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>;
154 // Multiclass for VST instructions
155 let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
156 multiclass VSTbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
157 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
158 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
159 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
160 !strconcat(opcStr, argStr)>;
161 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
162 !strconcat(opcStr, argStr)>;
163 }
164 }
165 multiclass VSTmm<string opcStr, bits<8>opc, dag dag_in> {
166 defm "" : VSTbm<opcStr, " $vx, $sy, $sz", opc, dag_in>;
167 let m = ?, VE_VLWithMask = 1 in
168 defm m : VSTbm<opcStr, " $vx, $sy, $sz, $m", opc, !con(dag_in, (ins VM:$m))>;
169 }
170 let VE_VLIndex = 3 in
171 multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
172 defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>;
173 let cy = 0 in
174 defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>;
175 let cz = 0 in
176 defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>;
177 let cy = 0, cz = 0 in
178 defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>;
179 }
180 multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {
181 let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;
182 let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;
183 let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;
184 let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;
185 }
187 // Section 8.9.7 - VST (Vector Store)
188 defm VST : VSTm<"vst", 0x91, V64>;
190 // Section 8.9.8 - VST (Vector Store Upper)
191 defm VSTU : VSTm<"vstu", 0x92, V64>;
193 // Section 8.9.9 - VSTL (Vector Store Lower)
194 defm VSTL : VSTm<"vstl", 0x93, V64>;
196 // Section 8.9.10 - VST2D (Vector Store 2D)
197 defm VST2D : VSTm<"vst2d", 0xd1, V64>;
199 // Section 8.9.11 - VSTU2D (Vector Store Upper 2D)
200 defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;
202 // Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
203 defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;
205 // Multiclass for VGT instructions
206 let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
207 multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
208 dag dag_in, string disEnc = ""> {
209 let DisableEncoding = disEnc in
210 def "" : RVM<opc, (outs RC:$vx), dag_in,
211 !strconcat(opcStr, " $vx, ", argStr)>;
212 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
213 isCodeGenOnly = 1 in
214 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
215 !strconcat(opcStr, " $vx, ", argStr)>;
216 }
217 multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
218 dag dag_in> {
219 defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;
220 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
221 defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
222 "$vl,">;
223 defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
224 "$vl,">;
225 }
226 }
227 multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
228 dag dag_in> {
229 defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;
230 let m = ?, VE_VLWithMask = 1 in
231 defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;
232 }
233 let VE_VLIndex = 4 in
234 multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
235 dag dag_in> {
236 defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
237 !con(dag_in, (ins I64:$sy, I64:$sz))>;
238 let cy = 0 in
239 defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
240 !con(dag_in, (ins simm7:$sy, I64:$sz))>;
241 let cz = 0 in
242 defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
243 !con(dag_in, (ins I64:$sy, zero:$sz))>;
244 let cy = 0, cz = 0 in
245 defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
246 !con(dag_in, (ins simm7:$sy, zero:$sz))>;
247 }
248 multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
249 let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
250 let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
251 }
252 multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {
253 let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
254 let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
255 }
257 // Section 8.9.13 - VGT (Vector Gather)
258 defm VGT : VGTm<"vgt", 0xa1, V64>;
260 // Section 8.9.14 - VGTU (Vector Gather Upper)
261 defm VGTU : VGTm<"vgtu", 0xa2, V64>;
263 // Section 8.9.15 - VGTL (Vector Gather Lower)
264 defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;
265 let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;
266 def : MnemonicAlias<"vgtl", "vgtl.zx">;
267 def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">;
269 // Multiclass for VSC instructions
270 let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
271 multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
272 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
273 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
274 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
275 !strconcat(opcStr, argStr)>;
276 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
277 !strconcat(opcStr, argStr)>;
278 }
279 }
280 multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
281 defm "" : VSCbm<opcStr, argStr, opc, dag_in>;
282 let m = ?, VE_VLWithMask = 1 in
283 defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>;
284 }
285 let VE_VLIndex = 4 in
286 multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
287 dag dag_in> {
288 defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
289 !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;
290 let cy = 0 in
291 defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
292 !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;
293 let cz = 0 in
294 defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
295 !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;
296 let cy = 0, cz = 0 in
297 defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
298 !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;
299 }
300 multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {
301 let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
302 let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
303 }
304 multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {
305 let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
306 let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
307 let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
308 let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
309 }
311 // Section 8.9.16 - VSC (Vector Scatter)
312 defm VSC : VSCm<"vsc", 0xb1, V64>;
314 // Section 8.9.17 - VSCU (Vector Scatter Upper)
315 defm VSCU : VSCm<"vscu", 0xb2, V64>;
317 // Section 8.9.18 - VSCL (Vector Scatter Lower)
318 defm VSCL : VSCm<"vscl", 0xb3, V64>;
320 // Section 8.9.19 - PFCHV (Prefetch Vector)
321 let Uses = [VL] in
322 multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
323 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
324 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
325 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
326 !strconcat(opcStr, argStr)>;
327 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
328 !strconcat(opcStr, argStr)>;
329 }
330 }
331 let VE_VLIndex = 2 in
332 multiclass PFCHVm<string opcStr, bits<8>opc> {
333 defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>;
334 let cy = 0 in
335 defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>;
336 let cz = 0 in
337 defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>;
338 let cy = 0, cz = 0 in
339 defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>;
340 }
341 let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;
342 let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;
344 // Section 8.9.20 - LSV (Load S to V)
345 let sx = 0, vx = ?, hasSideEffects = 0 in
346 multiclass LSVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
347 dag dag_in> {
348 def "" : RR<opc, (outs RC:$vx), dag_in, !strconcat(opcStr, " ${vx}", argStr)>;
349 let Constraints = "$vx = $base", DisableEncoding = "$base",
350 isCodeGenOnly = 1 in
351 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
352 !strconcat(opcStr, " ${vx}", argStr)>;
353 }
354 multiclass LSVm<string opcStr, bits<8>opc, RegisterClass RC> {
355 defm rr : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, I64:$sz)>;
356 let cy = 0 in
357 defm ir : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, I64:$sz)>;
358 let cz = 0 in
359 defm rm : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, mimm:$sz)>;
360 let cy = 0, cz = 0 in
361 defm im : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, mimm:$sz)>;
362 }
363 defm LSV : LSVm<"lsv", 0x8e, V64>;
365 // Section 8.9.21 - LVS (Load V to S)
366 let cz = 0, sz = 0, vx = ?, hasSideEffects = 0 in
367 multiclass LVSm<string opcStr, bits<8>opc, RegisterClass RC> {
368 def vr : RR<opc, (outs I64:$sx), (ins RC:$vx, I64:$sy),
369 opcStr#" $sx, ${vx}(${sy})">;
370 let cy = 0 in
371 def vi : RR<opc, (outs I64:$sx), (ins RC:$vx, uimm7:$sy),
372 opcStr#" $sx, ${vx}(${sy})">;
373 }
374 defm LVS : LVSm<"lvs", 0x9e, V64>;
376 // Section 8.9.22 - LVM (Load VM)
377 let sx = 0, vx = ?, hasSideEffects = 0 in
378 multiclass LVMbm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM,
379 dag dag_in> {
380 def "" : RR<opc, (outs RCM:$vx), dag_in,
381 !strconcat(opcStr, " $vx, ", argStr)>;
382 let Constraints = "$vx = $base", DisableEncoding = "$base",
383 isCodeGenOnly = 1 in {
384 def _m : RR<opc, (outs RCM:$vx), !con(dag_in, (ins RCM:$base)),
385 !strconcat(opcStr, " $vx, ", argStr)>;
386 }
387 }
388 multiclass LVMom<string opcStr, bits<8>opc, RegisterClass RCM> {
389 defm rr : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, I64:$sz)>;
390 let cy = 0 in
391 defm ir : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, I64:$sz)>;
392 let cz = 0 in
393 defm rm : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, mimm:$sz)>;
394 let cy = 0, cz = 0 in
395 defm im : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, mimm:$sz)>;
396 }
397 multiclass LVMm<string opcStr, bits<8>opc, RegisterClass RCM> {
398 defm "" : LVMom<opcStr, opc, RCM>;
399 }
400 defm LVM : LVMm<"lvm", 0xb7, VM>;
402 // Section 8.9.23 - SVM (Save VM)
403 let cz = 0, sz = 0, vz = ?, hasSideEffects = 0 in
404 multiclass SVMm<string opcStr, bits<8>opc, RegisterClass RCM> {
405 def mr : RR<opc, (outs I64:$sx), (ins RCM:$vz, I64:$sy),
406 opcStr#" $sx, $vz, $sy">;
407 let cy = 0 in
408 def mi : RR<opc, (outs I64:$sx), (ins RCM:$vz, uimm2:$sy),
409 opcStr#" $sx, $vz, $sy">;
410 }
411 defm SVM : SVMm<"svm", 0xa7, VM>;
413 // Section 8.9.24 - VBRD (Vector Broadcast)
414 let vx = ?, hasSideEffects = 0, Uses = [VL] in
415 multiclass VBRDbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
416 dag dag_in, string disEnc = ""> {
417 let DisableEncoding = disEnc in
418 def "" : RV<opc, (outs RC:$vx), dag_in,
419 !strconcat(opcStr, " $vx, ", argStr)>;
420 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
421 isCodeGenOnly = 1 in
422 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
423 !strconcat(opcStr, " $vx, ", argStr)>;
424 }
425 multiclass VBRDlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
426 dag dag_in> {
427 defm "" : VBRDbm<opcStr, argStr, opc, RC, dag_in>;
428 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
429 defm l : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
430 "$vl,">;
431 defm L : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
432 "$vl,">;
433 }
434 }
435 multiclass VBRDmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
436 RegisterClass RCM, dag dag_in> {
437 defm "" : VBRDlm<opcStr, argStr, opc, RC, dag_in>;
438 let m = ?, VE_VLWithMask = 1 in
439 defm m : VBRDlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
440 }
441 let VE_VLIndex = 2 in
442 multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
443 RegisterClass RCM> {
444 defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>;
445 let cy = 0 in
446 defm i : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins simm7:$sy)>;
447 }
448 let cx = 0, cx2 = 0 in
449 defm VBRD : VBRDm<"vbrd", 0x8c, V64, I64, VM>;
450 let cx = 0, cx2 = 1 in
451 defm VBRDL : VBRDm<"vbrdl", 0x8c, V64, I32, VM>;
452 let cx = 1, cx2 = 0 in
453 defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>;
454 let cx = 1, cx2 = 1 in
455 defm PVBRD : VBRDm<"pvbrd", 0x8c, V64, I64, VM512>;
457 // Section 8.9.25 - VMV (Vector Move)
458 let vx = ?, vz = ?, hasSideEffects = 0, Uses = [VL] in
459 multiclass VMVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
460 dag dag_in, string disEnc = ""> {
461 let DisableEncoding = disEnc in
462 def "" : RV<opc, (outs RC:$vx), dag_in,
463 !strconcat(opcStr, " $vx, ", argStr)>;
464 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
465 isCodeGenOnly = 1 in
466 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
467 !strconcat(opcStr, " $vx, ", argStr)>;
468 }
469 multiclass VMVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
470 dag dag_in> {
471 defm "" : VMVbm<opcStr, argStr, opc, RC, dag_in>;
472 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
473 defm l : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
474 "$vl,">;
475 defm L : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
476 "$vl,">;
477 }
478 }
479 multiclass VMVmm<string opcStr, bits<8>opc, RegisterClass RC,
480 RegisterClass RCM, dag dag_in> {
481 defm "" : VMVlm<opcStr, "$sy, $vz", opc, RC, dag_in>;
482 let m = ?, VE_VLWithMask = 1 in
483 defm m : VMVlm<opcStr, "$sy, $vz, $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
484 }
485 let VE_VLIndex = 3 in
486 multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC,
487 RegisterClass RCM> {
488 defm rv : VMVmm<opcStr, opc, RC, RCM, (ins I64:$sy, RC:$vz)>;
489 let cy = 0 in
490 defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>;
491 }
492 defm VMV : VMVm<"vmv", 0x9c, V64, VM>;
494 //-----------------------------------------------------------------------------
495 // Section 8.10 - Vector Fixed-Point Arithmetic Instructions
496 //-----------------------------------------------------------------------------
498 // Multiclass for generic vector calculation
499 let vx = ?, hasSideEffects = 0, Uses = [VL] in
500 multiclass RVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
501 dag dag_in, string disEnc = ""> {
502 let DisableEncoding = disEnc in
503 def "" : RV<opc, (outs RC:$vx), dag_in,
504 !strconcat(opcStr, " $vx", argStr)>;
505 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
506 isCodeGenOnly = 1 in
507 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
508 !strconcat(opcStr, " $vx", argStr)>;
509 }
510 multiclass RVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
511 dag dag_in> {
512 defm "" : RVbm<opcStr, argStr, opc, RC, dag_in>;
513 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
514 defm l : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
515 "$vl,">;
516 defm L : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
517 "$vl,">;
518 }
519 }
520 multiclass RVmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
521 RegisterClass RCM, dag dag_in> {
522 defm "" : RVlm<opcStr, argStr, opc, RC, dag_in>;
523 let m = ?, VE_VLWithMask = 1 in
524 defm m : RVlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
525 }
526 // Generic RV multiclass with 2 arguments.
527 // e.g. VADD, VSUB, VMPY, and etc.
528 let VE_VLIndex = 3 in
529 multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
530 RegisterClass RCM, Operand SIMM = simm7> {
531 let cy = 0, sy = 0, vy = ?, vz = ? in
532 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
533 let cs = 1, vz = ? in
534 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
535 let cs = 1, cy = 0, vz = ? in
536 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;
537 }
538 // Special RV multiclass with 2 arguments using cs2.
539 // e.g. VDIV, VDVS, and VDVX.
540 let VE_VLIndex = 3 in
541 multiclass RVDIVm<string opcStr, bits<8>opc, RegisterClass VRC,
542 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {
543 let cy = 0, sy = 0, vy = ?, vz = ? in
544 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
545 let cs2 = 1, vy = ? in
546 defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>;
547 let cs2 = 1, cy = 0, vy = ? in
548 defm vi : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, SIMM:$sy)>;
549 let cs = 1, vz = ? in
550 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
551 let cs = 1, cy = 0, vz = ? in
552 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;
553 }
554 // Generic RV multiclass with 2 arguments for logical operations.
555 // e.g. VAND, VOR, VXOR, and etc.
556 let VE_VLIndex = 3 in
557 multiclass RVLm<string opcStr, bits<8>opc, RegisterClass ScaRC,
558 RegisterClass RC, RegisterClass RCM> {
559 let cy = 0, sy = 0, vy = ?, vz = ? in
560 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;
561 let cs = 1, vz = ? in
562 defm rv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins ScaRC:$sy, RC:$vz)>;
563 let cs = 1, cy = 0, vz = ? in
564 defm mv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins mimm:$sy, RC:$vz)>;
565 }
566 // Generic RV multiclass with 1 argument.
567 // e.g. VLDZ, VPCNT, and VBRV.
568 let VE_VLIndex = 2 in
569 multiclass RV1m<string opcStr, bits<8>opc, RegisterClass RC,
570 RegisterClass RCM> {
571 let cy = 0, sy = 0, vz = ? in
572 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;
573 }
574 // Generic RV multiclass with no argument.
575 // e.g. VSEQ.
576 let VE_VLIndex = 1 in
577 multiclass RV0m<string opcStr, bits<8>opc, RegisterClass RC,
578 RegisterClass RCM> {
579 let cy = 0, sy = 0 in
580 defm "" : RVmm<opcStr, "", opc, RC, RCM, (ins)>;
581 }
582 // Generic RV multiclass with 2 arguments for shift operations.
583 // e.g. VSLL, VSRL, VSLA, and etc.
584 let VE_VLIndex = 3 in
585 multiclass RVSm<string opcStr, bits<8>opc, RegisterClass ScaRC,
586 RegisterClass RC, RegisterClass RCM> {
587 let cy = 0, sy = 0, vy = ?, vz = ? in
588 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
589 let cs = 1, vz = ? in
590 defm vr : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, ScaRC:$sy)>;
591 let cs = 1, cy = 0, vz = ? in
592 defm vi : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, uimm7:$sy)>;
593 }
594 // Generic RV multiclass with 3 arguments for shift operations.
595 // e.g. VSLD and VSRD.
596 let VE_VLIndex = 4 in
597 multiclass RVSDm<string opcStr, bits<8>opc, RegisterClass RC,
598 RegisterClass RCM> {
599 let vy = ?, vz = ? in
600 defm vvr : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
601 (ins RC:$vy, RC:$vz, I64:$sy)>;
602 let cy = 0, vy = ?, vz = ? in
603 defm vvi : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
604 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
605 }
606 // Special RV multiclass with 3 arguments.
607 // e.g. VSFA
608 let VE_VLIndex = 4 in
609 multiclass RVSAm<string opcStr, bits<8>opc, RegisterClass RC,
610 RegisterClass RCM> {
611 let cz = 1, sz = ?, vz = ? in
612 defm vrr : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
613 (ins RC:$vz, I64:$sy, I64:$sz)>;
614 let cz = 0, sz = ?, vz = ? in
615 defm vrm : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
616 (ins RC:$vz, I64:$sy, mimm:$sz)>;
617 let cy = 0, cz = 1, sz = ?, vz = ? in
618 defm vir : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
619 (ins RC:$vz, uimm3:$sy, I64:$sz)>;
620 let cy = 0, cz = 0, sz = ?, vz = ? in
621 defm vim : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
622 (ins RC:$vz, uimm3:$sy, mimm:$sz)>;
623 }
624 // Generic RV multiclass with 1 argument using vy field.
625 // e.g. VFSQRT, VRCP, and VRSQRT.
626 let VE_VLIndex = 2 in
627 multiclass RVF1m<string opcStr, bits<8>opc, RegisterClass RC,
628 RegisterClass RCM> {
629 let cy = 0, sy = 0, vy = ? in
630 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;
631 }
632 // Special RV multiclass with 3 arguments using cs2.
633 // e.g. VFMAD, VFMSB, VFNMAD, and etc.
634 let VE_VLIndex = 4 in
635 multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
636 RegisterClass RCM, Operand SIMM = simm7> {
637 let cy = 0, sy = 0, vy = ?, vz = ?, vw = ? in
638 defm vvv : RVmm<opcStr, ", $vy, $vz, $vw", opc, VRC, RCM,
639 (ins VRC:$vy, VRC:$vz, VRC:$vw)>;
640 let cs2 = 1, vy = ?, vw = ? in
641 defm vrv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM,
642 (ins VRC:$vy, RC:$sy, VRC:$vw)>;
643 let cs2 = 1, cy = 0, vy = ?, vw = ? in
644 defm viv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM,
645 (ins VRC:$vy, SIMM:$sy, VRC:$vw)>;
646 let cs = 1, vz = ?, vw = ? in
647 defm rvv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM,
648 (ins RC:$sy, VRC:$vz, VRC:$vw)>;
649 let cs = 1, cy = 0, vz = ?, vw = ? in
650 defm ivv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM,
651 (ins SIMM:$sy, VRC:$vz, VRC:$vw)>;
652 }
653 // Special RV multiclass with 2 arguments for floating point conversions.
654 // e.g. VFIX and VFIXX
655 let hasSideEffects = 0, VE_VLIndex = 3 in
656 multiclass RVFIXm<string opcStr, bits<8> opc, RegisterClass RC,
657 RegisterClass RCM> {
658 let cy = 0, sy = 0, vy = ?, vz = ? in
659 defm v : RVmm<opcStr#"$vz", ", $vy", opc, RC, RCM, (ins RDOp:$vz, RC:$vy)>;
660 }
661 // Multiclass for generic iterative vector calculation
662 let vx = ?, hasSideEffects = 0, Uses = [VL] in
663 multiclass RVIbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
664 dag dag_in, string disEnc = ""> {
665 let DisableEncoding = disEnc in
666 def "" : RV<opc, (outs RC:$vx), dag_in,
667 !strconcat(opcStr, " $vx", argStr)>;
668 let isCodeGenOnly = 1, Constraints = "$vx = $base", DisableEncoding = disEnc#"$base" in
669 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
670 !strconcat(opcStr, " $vx", argStr)>;
671 }
672 multiclass RVIlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
673 dag dag_in> {
674 defm "" : RVIbm<opcStr, argStr, opc, RC, dag_in>;
675 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
676 defm l : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
677 "$vl,">;
678 defm L : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
679 "$vl,">;
680 }
681 }
682 // Generic RV multiclass for iterative operation with 2 argument.
683 // e.g. VFIA, VFIS, and VFIM
684 let VE_VLIndex = 3 in
685 multiclass RVI2m<string opcStr, bits<8>opc, RegisterClass VRC,
686 RegisterClass RC> {
687 let vy = ? in
688 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>;
689 let cy = 0, vy = ? in
690 defm vi : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, simm7fp:$sy)>;
691 }
692 // Generic RV multiclass for iterative operation with 3 argument.
693 // e.g. VFIAM, VFISM, VFIMA, and etc.
694 let VE_VLIndex = 4 in
695 multiclass RVI3m<string opcStr, bits<8>opc, RegisterClass VRC,
696 RegisterClass RC> {
697 let vy = ?, vz = ? in
698 defm vvr : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC,
699 (ins VRC:$vy, VRC:$vz, RC:$sy)>;
700 let cy = 0, vy = ?, vz = ? in
701 defm vvi : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC,
702 (ins VRC:$vy, VRC:$vz, simm7fp:$sy)>;
703 }
704 // special RV multiclass with 3 arguments for VSHF.
705 // e.g. VSHF
706 let vy = ?, vz = ?, VE_VLIndex = 4 in
707 multiclass RVSHFm<string opcStr, bits<8>opc, RegisterClass RC,
708 Operand SIMM = uimm4> {
709 defm vvr : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
710 (ins RC:$vy, RC:$vz, I64:$sy)>;
711 let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
712 (ins RC:$vy, RC:$vz, SIMM:$sy)>;
713 }
714 // Multiclass for generic mask calculation
715 let vx = ?, hasSideEffects = 0, Uses = [VL] in
716 multiclass RVMKbm<string opcStr, string argStr, bits<8>opc, dag dag_out,
717 dag dag_in> {
718 def "" : RV<opc, dag_out, dag_in, !strconcat(opcStr, argStr)>;
719 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
720 def l : RV<opc, dag_out, !con(dag_in, (ins I32:$vl)),
721 !strconcat(opcStr, argStr)>;
722 def L : RV<opc, dag_out, !con(dag_in, (ins VLS:$vl)),
723 !strconcat(opcStr, argStr)>;
724 }
725 }
726 multiclass RVMKlm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM,
727 dag dag_in> {
728 defm "" : RVMKbm<opcStr, " $vx"#argStr, opc, (outs RCM:$vx), dag_in>;
729 let m = ?, VE_VLWithMask = 1 in
730 defm m : RVMKbm<opcStr, " $vx"#argStr#", $m", opc, (outs RCM:$vx),
731 !con(dag_in, (ins RCM:$m))>;
732 }
733 // Generic RV multiclass for mask calculation with a condition.
734 // e.g. VFMK, VFMS, and VFMF
735 let cy = 0, sy = 0 in
736 multiclass RVMKom<string opcStr, bits<8> opc, RegisterClass RC,
737 RegisterClass RCM> {
738 let vy = ?, vz = ?, VE_VLIndex = 3 in
739 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
740 let vy = 15 /* AT */, VE_VLIndex = 1 in
741 defm a : RVMKlm<opcStr#"at", "", opc, RCM, (ins)>;
742 let vy = 0 /* AF */, VE_VLIndex = 1 in
743 defm na : RVMKlm<opcStr#"af", "", opc, RCM, (ins)>;
744 }
745 multiclass RVMKm<string opcStr, bits<8> opc, RegisterClass RC,
746 RegisterClass RCM> {
747 defm "" : RVMKom<opcStr, opc, RC, RCM>;
748 }
749 // Generic RV multiclass for mask calculation with 2 arguments.
750 // e.g. ANDM, ORM, XORM, and etc.
751 let cy = 0, sy = 0, vx = ?, vy = ?, vz = ?, hasSideEffects = 0 in
752 multiclass RVM2m<string opcStr, bits<8> opc, RegisterClass RCM> {
753 def mm : RV<opc, (outs RCM:$vx), (ins RCM:$vy, RCM:$vz),
754 !strconcat(opcStr, " $vx, $vy, $vz")>;
755 }
756 // Generic RV multiclass for mask calculation with 1 argument.
757 // e.g. NEGM
758 let cy = 0, sy = 0, vx = ?, vy = ?, hasSideEffects = 0 in
759 multiclass RVM1m<string opcStr, bits<8> opc, RegisterClass RCM> {
760 def m : RV<opc, (outs RCM:$vx), (ins RCM:$vy),
761 !strconcat(opcStr, " $vx, $vy")>;
762 }
763 // Generic RV multiclass for mask calculation with 1 argument.
764 // e.g. PCVM, LZVM, and TOVM
765 let cy = 0, sy = 0, vy = ?, hasSideEffects = 0, Uses = [VL] in
766 multiclass RVMSbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
767 def "" : RV<opc, (outs I64:$sx), dag_in,
768 !strconcat(opcStr, " $sx,", argStr)> {
769 bits<7> sx;
770 let Inst{54-48} = sx;
771 }
772 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
773 def l : RV<opc, (outs I64:$sx), !con(dag_in, (ins I32:$vl)),
774 !strconcat(opcStr, " $sx,", argStr)> {
775 bits<7> sx;
776 let Inst{54-48} = sx;
777 }
778 def L : RV<opc, (outs I64:$sx), !con(dag_in, (ins VLS:$vl)),
779 !strconcat(opcStr, " $sx,", argStr)> {
780 bits<7> sx;
781 let Inst{54-48} = sx;
782 }
783 }
784 }
785 let VE_VLIndex = 2 in
786 multiclass RVMSm<string opcStr, bits<8> opc, RegisterClass RCM> {
787 defm m : RVMSbm<opcStr, " $vy", opc, (ins RCM:$vy)>;
788 }
790 // Section 8.10.1 - VADD (Vector Add)
791 let cx = 0, cx2 = 0 in
792 defm VADDUL : RVm<"vaddu.l", 0xc8, V64, I64, VM>;
793 let cx = 0, cx2 = 1 in {
794 defm PVADDULO : RVm<"pvaddu.lo", 0xc8, V64, I32, VM>;
795 let isCodeGenOnly = 1 in
796 defm VADDUW : RVm<"vaddu.w", 0xc8, V64, I32, VM>;
797 }
798 let cx = 1, cx2 = 0 in
799 defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>;
800 let cx = 1, cx2 = 1 in
801 defm PVADDU : RVm<"pvaddu", 0xc8, V64, I64, VM512>;
802 def : MnemonicAlias<"vaddu.w", "pvaddu.lo">;
804 // Section 8.10.2 - VADS (Vector Add Single)
805 let cx = 0, cx2 = 0 in
806 defm VADDSWSX : RVm<"vadds.w.sx", 0xca, V64, I32, VM>;
807 let cx = 0, cx2 = 1 in {
808 defm PVADDSLO : RVm<"pvadds.lo", 0xca, V64, I32, VM>;
809 let isCodeGenOnly = 1 in
810 defm VADDSWZX : RVm<"vadds.w.zx", 0xca, V64, I32, VM>;
811 }
812 let cx = 1, cx2 = 0 in
813 defm PVADDSUP : RVm<"pvadds.up", 0xca, V64, I64, VM>;
814 let cx = 1, cx2 = 1 in
815 defm PVADDS : RVm<"pvadds", 0xca, V64, I64, VM512>;
816 def : MnemonicAlias<"pvadds.lo.sx", "vadds.w.sx">;
817 def : MnemonicAlias<"vadds.w.zx", "pvadds.lo">;
818 def : MnemonicAlias<"vadds.w", "pvadds.lo">;
819 def : MnemonicAlias<"pvadds.lo.zx", "pvadds.lo">;
821 // Section 8.10.3 - VADX (Vector Add)
822 defm VADDSL : RVm<"vadds.l", 0x8b, V64, I64, VM>;
824 // Section 8.10.4 - VSUB (Vector Subtract)
825 let cx = 0, cx2 = 0 in
826 defm VSUBUL : RVm<"vsubu.l", 0xd8, V64, I64, VM>;
827 let cx = 0, cx2 = 1 in {
828 defm PVSUBULO : RVm<"pvsubu.lo", 0xd8, V64, I32, VM>;
829 let isCodeGenOnly = 1 in
830 defm VSUBUW : RVm<"vsubu.w", 0xd8, V64, I32, VM>;
831 }
832 let cx = 1, cx2 = 0 in
833 defm PVSUBUUP : RVm<"pvsubu.up", 0xd8, V64, I64, VM>;
834 let cx = 1, cx2 = 1 in
835 defm PVSUBU : RVm<"pvsubu", 0xd8, V64, I64, VM512>;
836 def : MnemonicAlias<"vsubu.w", "pvsubu.lo">;
838 // Section 8.10.5 - VSBS (Vector Subtract Single)
839 let cx = 0, cx2 = 0 in
840 defm VSUBSWSX : RVm<"vsubs.w.sx", 0xda, V64, I32, VM>;
841 let cx = 0, cx2 = 1 in {
842 defm PVSUBSLO : RVm<"pvsubs.lo", 0xda, V64, I32, VM>;
843 let isCodeGenOnly = 1 in
844 defm VSUBSWZX : RVm<"vsubs.w.zx", 0xda, V64, I32, VM>;
845 }
846 let cx = 1, cx2 = 0 in
847 defm PVSUBSUP : RVm<"pvsubs.up", 0xda, V64, I64, VM>;
848 let cx = 1, cx2 = 1 in
849 defm PVSUBS : RVm<"pvsubs", 0xda, V64, I64, VM512>;
850 def : MnemonicAlias<"pvsubs.lo.sx", "vsubs.w.sx">;
851 def : MnemonicAlias<"vsubs.w.zx", "pvsubs.lo">;
852 def : MnemonicAlias<"vsubs.w", "pvsubs.lo">;
853 def : MnemonicAlias<"pvsubs.lo.zx", "pvsubs.lo">;
855 // Section 8.10.6 - VSBX (Vector Subtract)
856 defm VSUBSL : RVm<"vsubs.l", 0x9b, V64, I64, VM>;
858 // Section 8.10.7 - VMPY (Vector Multiply)
859 let cx2 = 0 in
860 defm VMULUL : RVm<"vmulu.l", 0xc9, V64, I64, VM>;
861 let cx2 = 1 in
862 defm VMULUW : RVm<"vmulu.w", 0xc9, V64, I32, VM>;
864 // Section 8.10.8 - VMPS (Vector Multiply Single)
865 let cx2 = 0 in
866 defm VMULSWSX : RVm<"vmuls.w.sx", 0xcb, V64, I32, VM>;
867 let cx2 = 1 in
868 defm VMULSWZX : RVm<"vmuls.w.zx", 0xcb, V64, I32, VM>;
869 def : MnemonicAlias<"vmuls.w", "vmuls.w.zx">;
871 // Section 8.10.9 - VMPX (Vector Multiply)
872 defm VMULSL : RVm<"vmuls.l", 0xdb, V64, I64, VM>;
874 // Section 8.10.10 - VMPD (Vector Multiply)
875 defm VMULSLW : RVm<"vmuls.l.w", 0xd9, V64, I32, VM>;
877 // Section 8.10.11 - VDIV (Vector Divide)
878 let cx2 = 0 in
879 defm VDIVUL : RVDIVm<"vdivu.l", 0xe9, V64, I64, VM>;
880 let cx2 = 1 in
881 defm VDIVUW : RVDIVm<"vdivu.w", 0xe9, V64, I32, VM>;
883 // Section 8.10.12 - VDVS (Vector Divide Single)
884 let cx2 = 0 in
885 defm VDIVSWSX : RVDIVm<"vdivs.w.sx", 0xeb, V64, I32, VM>;
886 let cx2 = 1 in
887 defm VDIVSWZX : RVDIVm<"vdivs.w.zx", 0xeb, V64, I32, VM>;
888 def : MnemonicAlias<"vdivs.w", "vdivs.w.zx">;
890 // Section 8.10.13 - VDVX (Vector Divide)
891 defm VDIVSL : RVDIVm<"vdivs.l", 0xfb, V64, I64, VM>;
893 // Section 8.10.14 - VCMP (Vector Compare)
894 let cx = 0, cx2 = 0 in
895 defm VCMPUL : RVm<"vcmpu.l", 0xb9, V64, I64, VM>;
896 let cx = 0, cx2 = 1 in {
897 defm PVCMPULO : RVm<"pvcmpu.lo", 0xb9, V64, I32, VM>;
898 let isCodeGenOnly = 1 in
899 defm VCMPUW : RVm<"vcmpu.w", 0xb9, V64, I32, VM>;
900 }
901 let cx = 1, cx2 = 0 in
902 defm PVCMPUUP : RVm<"pvcmpu.up", 0xb9, V64, I64, VM>;
903 let cx = 1, cx2 = 1 in
904 defm PVCMPU : RVm<"pvcmpu", 0xb9, V64, I64, VM512>;
905 def : MnemonicAlias<"vcmpu.w", "pvcmpu.lo">;
907 // Section 8.10.15 - VCPS (Vector Compare Single)
908 let cx = 0, cx2 = 0 in
909 defm VCMPSWSX : RVm<"vcmps.w.sx", 0xfa, V64, I32, VM>;
910 let cx = 0, cx2 = 1 in {
911 defm PVCMPSLO : RVm<"pvcmps.lo", 0xfa, V64, I32, VM>;
912 let isCodeGenOnly = 1 in
913 defm VCMPSWZX : RVm<"vcmps.w.zx", 0xfa, V64, I32, VM>;
914 }
915 let cx = 1, cx2 = 0 in
916 defm PVCMPSUP : RVm<"pvcmps.up", 0xfa, V64, I64, VM>;
917 let cx = 1, cx2 = 1 in
918 defm PVCMPS : RVm<"pvcmps", 0xfa, V64, I64, VM512>;
919 def : MnemonicAlias<"pvcmps.lo.sx", "vcmps.w.sx">;
920 def : MnemonicAlias<"vcmps.w.zx", "pvcmps.lo">;
921 def : MnemonicAlias<"vcmps.w", "pvcmps.lo">;
922 def : MnemonicAlias<"pvcmps.lo.zx", "pvcmps.lo">;
924 // Section 8.10.16 - VCPX (Vector Compare)
925 defm VCMPSL : RVm<"vcmps.l", 0xba, V64, I64, VM>;
927 // Section 8.10.17 - VCMS (Vector Compare and Select Maximum/Minimum Single)
928 let cx = 0, cx2 = 0 in
929 defm VMAXSWSX : RVm<"vmaxs.w.sx", 0x8a, V64, I32, VM>;
930 let cx = 0, cx2 = 1 in {
931 defm PVMAXSLO : RVm<"pvmaxs.lo", 0x8a, V64, I32, VM>;
932 let isCodeGenOnly = 1 in
933 defm VMAXSWZX : RVm<"vmaxs.w.zx", 0x8a, V64, I32, VM>;
934 }
935 let cx = 1, cx2 = 0 in
936 defm PVMAXSUP : RVm<"pvmaxs.up", 0x8a, V64, I64, VM>;
937 let cx = 1, cx2 = 1 in
938 defm PVMAXS : RVm<"pvmaxs", 0x8a, V64, I64, VM512>;
939 let cs2 = 1 in {
940 let cx = 0, cx2 = 0 in
941 defm VMINSWSX : RVm<"vmins.w.sx", 0x8a, V64, I32, VM>;
942 let cx = 0, cx2 = 1 in {
943 defm PVMINSLO : RVm<"pvmins.lo", 0x8a, V64, I32, VM>;
944 let isCodeGenOnly = 1 in
945 defm VMINSWZX : RVm<"vmins.w.zx", 0x8a, V64, I32, VM>;
946 }
947 let cx = 1, cx2 = 0 in
948 defm PVMINSUP : RVm<"pvmins.up", 0x8a, V64, I64, VM>;
949 let cx = 1, cx2 = 1 in
950 defm PVMINS : RVm<"pvmins", 0x8a, V64, I64, VM512>;
951 }
952 def : MnemonicAlias<"pvmaxs.lo.sx", "vmaxs.w.sx">;
953 def : MnemonicAlias<"vmaxs.w.zx", "pvmaxs.lo">;
954 def : MnemonicAlias<"vmaxs.w", "pvmaxs.lo">;
955 def : MnemonicAlias<"pvmaxs.lo.zx", "pvmaxs.lo">;
956 def : MnemonicAlias<"pvmins.lo.sx", "vmins.w.sx">;
957 def : MnemonicAlias<"vmins.w.zx", "pvmins.lo">;
958 def : MnemonicAlias<"vmins.w", "pvmins.lo">;
959 def : MnemonicAlias<"pvmins.lo.zx", "pvmins.lo">;
961 // Section 8.10.18 - VCMX (Vector Compare and Select Maximum/Minimum)
962 defm VMAXSL : RVm<"vmaxs.l", 0x9a, V64, I64, VM>;
963 let cs2 = 1 in
964 defm VMINSL : RVm<"vmins.l", 0x9a, V64, I64, VM>;
966 //-----------------------------------------------------------------------------
967 // Section 8.11 - Vector Logical Operation Instructions
968 //-----------------------------------------------------------------------------
970 // Section 8.11.1 - VAND (Vector And)
971 let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM>;
972 let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, I32, V64, VM>;
973 let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>;
974 let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, I64, V64, VM512>;
976 // Section 8.11.2 - VOR (Vector Or)
977 let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, I64, V64, VM>;
978 let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, I32, V64, VM>;
979 let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>;
980 let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, I64, V64, VM512>;
982 // Section 8.11.3 - VXOR (Vector Exclusive Or)
983 let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, I64, V64, VM>;
984 let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, I32, V64, VM>;
985 let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>;
986 let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, I64, V64, VM512>;
988 // Section 8.11.4 - VEQV (Vector Equivalence)
989 let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, I64, V64, VM>;
990 let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, I32, V64, VM>;
991 let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>;
992 let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, I64, V64, VM512>;
994 // Section 8.11.5 - VLDZ (Vector Leading Zero Count)
995 let cx = 0, cx2 = 0 in defm VLDZ : RV1m<"vldz", 0xe7, V64, VM>;
996 let cx = 0, cx2 = 1 in defm PVLDZLO : RV1m<"pvldz.lo", 0xe7, V64, VM>;
997 let cx = 1, cx2 = 0 in defm PVLDZUP : RV1m<"pvldz.up", 0xe7, V64, VM>;
998 let cx = 1, cx2 = 1 in defm PVLDZ : RV1m<"pvldz", 0xe7, V64, VM512>;
1000 // Section 8.11.6 - VPCNT (Vector Population Count)
1001 let cx = 0, cx2 = 0 in defm VPCNT : RV1m<"vpcnt", 0xac, V64, VM>;
1002 let cx = 0, cx2 = 1 in defm PVPCNTLO : RV1m<"pvpcnt.lo", 0xac, V64, VM>;
1003 let cx = 1, cx2 = 0 in defm PVPCNTUP : RV1m<"pvpcnt.up", 0xac, V64, VM>;
1004 let cx = 1, cx2 = 1 in defm PVPCNT : RV1m<"pvpcnt", 0xac, V64, VM512>;
1006 // Section 8.11.7 - VBRV (Vector Bit Reverse)
1007 let cx = 0, cx2 = 0 in defm VBRV : RV1m<"vbrv", 0xf7, V64, VM>;
1008 let cx = 0, cx2 = 1 in defm PVBRVLO : RV1m<"pvbrv.lo", 0xf7, V64, VM>;
1009 let cx = 1, cx2 = 0 in defm PVBRVUP : RV1m<"pvbrv.up", 0xf7, V64, VM>;
1010 let cx = 1, cx2 = 1 in defm PVBRV : RV1m<"pvbrv", 0xf7, V64, VM512>;
1012 // Section 8.11.8 - VSEQ (Vector Sequential Number)
1013 let cx = 0, cx2 = 0 in defm VSEQ : RV0m<"vseq", 0x99, V64, VM>;
1014 let cx = 0, cx2 = 1 in defm PVSEQLO : RV0m<"pvseq.lo", 0x99, V64, VM>;
1015 let cx = 1, cx2 = 0 in defm PVSEQUP : RV0m<"pvseq.up", 0x99, V64, VM>;
1016 let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512>;
1018 //-----------------------------------------------------------------------------
1019 // Section 8.12 - Vector Shift Operation Instructions
1020 //-----------------------------------------------------------------------------
1022 // Section 8.12.1 - VSLL (Vector Shift Left Logical)
1023 let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM>;
1024 let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM>;
1025 let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;
1026 let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512>;
1028 // Section 8.12.2 - VSLD (Vector Shift Left Double)
1029 defm VSLD : RVSDm<"vsld", 0xe4, V64, VM>;
1031 // Section 8.12.3 - VSRL (Vector Shift Right Logical)
1032 let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;
1033 let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM>;
1034 let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;
1035 let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512>;
1037 // Section 8.12.4 - VSRD (Vector Shift Right Double)
1038 defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>;
1040 // Section 8.12.5 - VSLA (Vector Shift Left Arithmetic)
1041 let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>;
1042 let cx = 0, cx2 = 1 in {
1043 defm PVSLALO : RVSm<"pvsla.lo", 0xe6, I32, V64, VM>;
1044 let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM>;
1045 }
1046 let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;
1047 let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512>;
1048 def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">;
1049 def : MnemonicAlias<"vsla.w.zx", "pvsla.lo">;
1050 def : MnemonicAlias<"vsla.w", "pvsla.lo">;
1051 def : MnemonicAlias<"pvsla.lo.zx", "pvsla.lo">;
1053 // Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic)
1054 defm VSLAL : RVSm<"vsla.l", 0xd4, I64, V64, VM>;
1056 // Section 8.12.7 - VSRA (Vector Shift Right Arithmetic)
1057 let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>;
1058 let cx = 0, cx2 = 1 in {
1059 defm PVSRALO : RVSm<"pvsra.lo", 0xf6, I32, V64, VM>;
1060 let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM>;
1061 }
1062 let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;
1063 let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512>;
1064 def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">;
1065 def : MnemonicAlias<"vsra.w.zx", "pvsra.lo">;
1066 def : MnemonicAlias<"vsra.w", "pvsra.lo">;
1067 def : MnemonicAlias<"pvsra.lo.zx", "pvsra.lo">;
1069 // Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic)
1070 defm VSRAL : RVSm<"vsra.l", 0xd5, I64, V64, VM>;
1072 // Section 8.12.9 - VSFA (Vector Shift Left and Add)
1073 defm VSFA : RVSAm<"vsfa", 0xd7, V64, VM>;
1075 //-----------------------------------------------------------------------------
1076 // Section 8.13 - Vector Floating-Point Arithmetic Instructions
1077 //-----------------------------------------------------------------------------
1079 // Section 8.13.1 - VFAD (Vector Floating Add)
1080 let cx = 0, cx2 = 0 in
1081 defm VFADDD : RVm<"vfadd.d", 0xcc, V64, I64, VM, simm7fp>;
1082 let cx = 0, cx2 = 1 in
1083 defm PVFADDLO : RVm<"pvfadd.lo", 0xcc, V64, I64, VM, simm7fp>;
1084 let cx = 1, cx2 = 0 in {
1085 defm PVFADDUP : RVm<"pvfadd.up", 0xcc, V64, F32, VM, simm7fp>;
1086 let isCodeGenOnly = 1 in
1087 defm VFADDS : RVm<"vfadd.s", 0xcc, V64, F32, VM, simm7fp>;
1088 }
1089 let cx = 1, cx2 = 1 in
1090 defm PVFADD : RVm<"pvfadd", 0xcc, V64, I64, VM512, simm7fp>;
1091 def : MnemonicAlias<"vfadd.s", "pvfadd.up">;
1093 // Section 8.13.2 - VFSB (Vector Floating Subtract)
1094 let cx = 0, cx2 = 0 in
1095 defm VFSUBD : RVm<"vfsub.d", 0xdc, V64, I64, VM, simm7fp>;
1096 let cx = 0, cx2 = 1 in
1097 defm PVFSUBLO : RVm<"pvfsub.lo", 0xdc, V64, I64, VM, simm7fp>;
1098 let cx = 1, cx2 = 0 in {
1099 defm PVFSUBUP : RVm<"pvfsub.up", 0xdc, V64, F32, VM, simm7fp>;
1100 let isCodeGenOnly = 1 in
1101 defm VFSUBS : RVm<"vfsub.s", 0xdc, V64, F32, VM, simm7fp>;
1102 }
1103 let cx = 1, cx2 = 1 in
1104 defm PVFSUB : RVm<"pvfsub", 0xdc, V64, I64, VM512, simm7fp>;
1105 def : MnemonicAlias<"vfsub.s", "pvfsub.up">;
1107 // Section 8.13.3 - VFMP (Vector Floating Multiply)
1108 let cx = 0, cx2 = 0 in
1109 defm VFMULD : RVm<"vfmul.d", 0xcd, V64, I64, VM, simm7fp>;
1110 let cx = 0, cx2 = 1 in
1111 defm PVFMULLO : RVm<"pvfmul.lo", 0xcd, V64, I64, VM, simm7fp>;
1112 let cx = 1, cx2 = 0 in {
1113 defm PVFMULUP : RVm<"pvfmul.up", 0xcd, V64, F32, VM, simm7fp>;
1114 let isCodeGenOnly = 1 in
1115 defm VFMULS : RVm<"vfmul.s", 0xcd, V64, F32, VM, simm7fp>;
1116 }
1117 let cx = 1, cx2 = 1 in
1118 defm PVFMUL : RVm<"pvfmul", 0xcd, V64, I64, VM512, simm7fp>;
1119 def : MnemonicAlias<"vfmul.s", "pvfmul.up">;
1121 // Section 8.13.4 - VFDV (Vector Floating Divide)
1122 defm VFDIVD : RVDIVm<"vfdiv.d", 0xdd, V64, I64, VM, simm7fp>;
1123 let cx = 1 in
1124 defm VFDIVS : RVDIVm<"vfdiv.s", 0xdd, V64, F32, VM, simm7fp>;
1126 // Section 8.13.5 - VFSQRT (Vector Floating Square Root)
1127 defm VFSQRTD : RVF1m<"vfsqrt.d", 0xed, V64, VM>;
1128 let cx = 1 in
1129 defm VFSQRTS : RVF1m<"vfsqrt.s", 0xed, V64, VM>;
1131 // Section 8.13.6 - VFCP (Vector Floating Compare)
1132 let cx = 0, cx2 = 0 in
1133 defm VFCMPD : RVm<"vfcmp.d", 0xfc, V64, I64, VM, simm7fp>;
1134 let cx = 0, cx2 = 1 in
1135 defm PVFCMPLO : RVm<"pvfcmp.lo", 0xfc, V64, I64, VM, simm7fp>;
1136 let cx = 1, cx2 = 0 in {
1137 defm PVFCMPUP : RVm<"pvfcmp.up", 0xfc, V64, F32, VM, simm7fp>;
1138 let isCodeGenOnly = 1 in
1139 defm VFCMPS : RVm<"vfcmp.s", 0xfc, V64, F32, VM, simm7fp>;
1140 }
1141 let cx = 1, cx2 = 1 in
1142 defm PVFCMP : RVm<"pvfcmp", 0xfc, V64, I64, VM512, simm7fp>;
1143 def : MnemonicAlias<"vfcmp.s", "pvfcmp.up">;
1145 // Section 8.13.7 - VFCM (Vector Floating Compare and Select Maximum/Minimum)
1146 let cx = 0, cx2 = 0 in
1147 defm VFMAXD : RVm<"vfmax.d", 0xbd, V64, I64, VM, simm7fp>;
1148 let cx = 0, cx2 = 1 in
1149 defm PVFMAXLO : RVm<"pvfmax.lo", 0xbd, V64, I64, VM, simm7fp>;
1150 let cx = 1, cx2 = 0 in {
1151 defm PVFMAXUP : RVm<"pvfmax.up", 0xbd, V64, F32, VM, simm7fp>;
1152 let isCodeGenOnly = 1 in
1153 defm VFMAXS : RVm<"vfmax.s", 0xbd, V64, F32, VM, simm7fp>;
1154 }
1155 let cx = 1, cx2 = 1 in
1156 defm PVFMAX : RVm<"pvfmax", 0xbd, V64, I64, VM512, simm7fp>;
1157 let cs2 = 1 in {
1158 let cx = 0, cx2 = 0 in
1159 defm VFMIND : RVm<"vfmin.d", 0xbd, V64, I64, VM, simm7fp>;
1160 let cx = 0, cx2 = 1 in
1161 defm PVFMINLO : RVm<"pvfmin.lo", 0xbd, V64, I64, VM, simm7fp>;
1162 let cx = 1, cx2 = 0 in {
1163 defm PVFMINUP : RVm<"pvfmin.up", 0xbd, V64, F32, VM, simm7fp>;
1164 let isCodeGenOnly = 1 in
1165 defm VFMINS : RVm<"vfmin.s", 0xbd, V64, F32, VM, simm7fp>;
1166 }
1167 let cx = 1, cx2 = 1 in
1168 defm PVFMIN : RVm<"pvfmin", 0xbd, V64, I64, VM512, simm7fp>;
1169 }
1170 def : MnemonicAlias<"vfmax.s", "pvfmax.up">;
1171 def : MnemonicAlias<"vfmin.s", "pvfmin.up">;
1173 // Section 8.13.8 - VFMAD (Vector Floating Fused Multiply Add)
1174 let cx = 0, cx2 = 0 in
1175 defm VFMADD : RVMm<"vfmad.d", 0xe2, V64, I64, VM, simm7fp>;
1176 let cx = 0, cx2 = 1 in
1177 defm PVFMADLO : RVMm<"pvfmad.lo", 0xe2, V64, I64, VM, simm7fp>;
1178 let cx = 1, cx2 = 0 in {
1179 defm PVFMADUP : RVMm<"pvfmad.up", 0xe2, V64, F32, VM, simm7fp>;
1180 let isCodeGenOnly = 1 in
1181 defm VFMADS : RVMm<"vfmad.s", 0xe2, V64, F32, VM, simm7fp>;
1182 }
1183 let cx = 1, cx2 = 1 in
1184 defm PVFMAD : RVMm<"pvfmad", 0xe2, V64, I64, VM512, simm7fp>;
1185 def : MnemonicAlias<"vfmad.s", "pvfmad.up">;
1187 // Section 8.13.9 - VFMSB (Vector Floating Fused Multiply Subtract)
1188 let cx = 0, cx2 = 0 in
1189 defm VFMSBD : RVMm<"vfmsb.d", 0xf2, V64, I64, VM, simm7fp>;
1190 let cx = 0, cx2 = 1 in
1191 defm PVFMSBLO : RVMm<"pvfmsb.lo", 0xf2, V64, I64, VM, simm7fp>;
1192 let cx = 1, cx2 = 0 in {
1193 defm PVFMSBUP : RVMm<"pvfmsb.up", 0xf2, V64, F32, VM, simm7fp>;
1194 let isCodeGenOnly = 1 in
1195 defm VFMSBS : RVMm<"vfmsb.s", 0xf2, V64, F32, VM, simm7fp>;
1196 }
1197 let cx = 1, cx2 = 1 in
1198 defm PVFMSB : RVMm<"pvfmsb", 0xf2, V64, I64, VM512, simm7fp>;
1199 def : MnemonicAlias<"vfmsb.s", "pvfmsb.up">;
1201 // Section 8.13.10 - VFNMAD (Vector Floating Fused Negative Multiply Add)
1202 let cx = 0, cx2 = 0 in
1203 defm VFNMADD : RVMm<"vfnmad.d", 0xe3, V64, I64, VM, simm7fp>;
1204 let cx = 0, cx2 = 1 in
1205 defm PVFNMADLO : RVMm<"pvfnmad.lo", 0xe3, V64, I64, VM, simm7fp>;
1206 let cx = 1, cx2 = 0 in {
1207 defm PVFNMADUP : RVMm<"pvfnmad.up", 0xe3, V64, F32, VM, simm7fp>;
1208 let isCodeGenOnly = 1 in
1209 defm VFNMADS : RVMm<"vfnmad.s", 0xe3, V64, F32, VM, simm7fp>;
1210 }
1211 let cx = 1, cx2 = 1 in
1212 defm PVFNMAD : RVMm<"pvfnmad", 0xe3, V64, I64, VM512, simm7fp>;
1213 def : MnemonicAlias<"vfnmad.s", "pvfnmad.up">;
1215 // Section 8.13.11 - VFNMSB (Vector Floating Fused Negative Multiply Subtract)
1216 let cx = 0, cx2 = 0 in
1217 defm VFNMSBD : RVMm<"vfnmsb.d", 0xf3, V64, I64, VM, simm7fp>;
1218 let cx = 0, cx2 = 1 in
1219 defm PVFNMSBLO : RVMm<"pvfnmsb.lo", 0xf3, V64, I64, VM, simm7fp>;
1220 let cx = 1, cx2 = 0 in {
1221 defm PVFNMSBUP : RVMm<"pvfnmsb.up", 0xf3, V64, F32, VM, simm7fp>;
1222 let isCodeGenOnly = 1 in
1223 defm VFNMSBS : RVMm<"vfnmsb.s", 0xf3, V64, F32, VM, simm7fp>;
1224 }
1225 let cx = 1, cx2 = 1 in
1226 defm PVFNMSB : RVMm<"pvfnmsb", 0xf3, V64, I64, VM512, simm7fp>;
1227 def : MnemonicAlias<"vfnmsb.s", "pvfnmsb.up">;
1229 // Section 8.13.12 - VRCP (Vector Floating Reciprocal)
1230 let cx = 0, cx2 = 0 in defm VRCPD : RVF1m<"vrcp.d", 0xe1, V64, VM>;
1231 let cx = 0, cx2 = 1 in defm PVRCPLO : RVF1m<"pvrcp.lo", 0xe1, V64, VM>;
1232 let cx = 1, cx2 = 0 in {
1233 defm PVRCPUP : RVF1m<"pvrcp.up", 0xe1, V64, VM>;
1234 let isCodeGenOnly = 1 in defm VRCPS : RVF1m<"vrcp.s", 0xe1, V64, VM>;
1235 }
1236 let cx = 1, cx2 = 1 in defm PVRCP : RVF1m<"pvrcp", 0xe1, V64, VM512>;
1237 def : MnemonicAlias<"vrcp.s", "pvrcp.up">;
1239 // Section 8.13.13 - VRSQRT (Vector Floating Reciprocal Square Root)
1240 let cx = 0, cx2 = 0 in defm VRSQRTD : RVF1m<"vrsqrt.d", 0xf1, V64, VM>;
1241 let cx = 0, cx2 = 1 in defm PVRSQRTLO : RVF1m<"pvrsqrt.lo", 0xf1, V64, VM>;
1242 let cx = 1, cx2 = 0 in {
1243 defm PVRSQRTUP : RVF1m<"pvrsqrt.up", 0xf1, V64, VM>;
1244 let isCodeGenOnly = 1 in
1245 defm VRSQRTS : RVF1m<"vrsqrt.s", 0xf1, V64, VM>;
1246 }
1247 let cx = 1, cx2 = 1 in
1248 defm PVRSQRT : RVF1m<"pvrsqrt", 0xf1, V64, VM512>;
1249 let cs2 = 1 in {
1250 let cx = 0, cx2 = 0 in
1251 defm VRSQRTDNEX : RVF1m<"vrsqrt.d.nex", 0xf1, V64, VM>;
1252 let cx = 0, cx2 = 1 in
1253 defm PVRSQRTLONEX : RVF1m<"pvrsqrt.lo.nex", 0xf1, V64, VM>;
1254 let cx = 1, cx2 = 0 in {
1255 defm PVRSQRTUPNEX : RVF1m<"pvrsqrt.up.nex", 0xf1, V64, VM>;
1256 let isCodeGenOnly = 1 in
1257 defm VRSQRTSNEX : RVF1m<"vrsqrt.s.nex", 0xf1, V64, VM>;
1258 }
1259 let cx = 1, cx2 = 1 in
1260 defm PVRSQRTNEX : RVF1m<"pvrsqrt.nex", 0xf1, V64, VM512>;
1261 }
1262 def : MnemonicAlias<"vrsqrt.s", "pvrsqrt.up">;
1263 def : MnemonicAlias<"vrsqrt.s.nex", "pvrsqrt.up.nex">;
1265 // Section 8.13.14 - VFIX (Vector Convert to Fixed Pointer)
1266 let cx = 0, cx2 = 0, cs2 = 0 in
1267 defm VCVTWDSX : RVFIXm<"vcvt.w.d.sx", 0xe8, V64, VM>;
1268 let cx = 0, cx2 = 1, cs2 = 0 in
1269 defm VCVTWDZX : RVFIXm<"vcvt.w.d.zx", 0xe8, V64, VM>;
1270 let cx = 1, cx2 = 0, cs2 = 0 in
1271 defm VCVTWSSX : RVFIXm<"vcvt.w.s.sx", 0xe8, V64, VM>;
1272 let cx = 1, cx2 = 1, cs2 = 0 in
1273 defm VCVTWSZX : RVFIXm<"vcvt.w.s.zx", 0xe8, V64, VM>;
1274 let cx = 0, cx2 = 1, cs2 = 1 in
1275 defm PVCVTWSLO : RVFIXm<"pvcvt.w.s.lo", 0xe8, V64, VM>;
1276 let cx = 1, cx2 = 0, cs2 = 1 in
1277 defm PVCVTWSUP : RVFIXm<"pvcvt.w.s.up", 0xe8, V64, VM>;
1278 let cx = 1, cx2 = 1, cs2 = 1 in
1279 defm PVCVTWS : RVFIXm<"pvcvt.w.s", 0xe8, V64, VM512>;
1281 // Section 8.13.15 - VFIXX (Vector Convert to Fixed Pointer)
1282 defm VCVTLD : RVFIXm<"vcvt.l.d", 0xa8, V64, VM>;
1284 // Section 8.13.16 - VFLT (Vector Convert to Floating Pointer)
1285 let cx = 0, cx2 = 0, cs2 = 0 in
1286 defm VCVTDW : RVF1m<"vcvt.d.w", 0xf8, V64, VM>;
1287 let cx = 1, cx2 = 0, cs2 = 0 in
1288 defm VCVTSW : RVF1m<"vcvt.s.w", 0xf8, V64, VM>;
1289 let cx = 0, cx2 = 1, cs2 = 1 in
1290 defm PVCVTSWLO : RVF1m<"pvcvt.s.w.lo", 0xf8, V64, VM>;
1291 let cx = 1, cx2 = 0, cs2 = 1 in
1292 defm PVCVTSWUP : RVF1m<"pvcvt.s.w.up", 0xf8, V64, VM>;
1293 let cx = 1, cx2 = 1, cs2 = 1 in
1294 defm PVCVTSW : RVF1m<"pvcvt.s.w", 0xf8, V64, VM512>;
1296 // Section 8.13.17 - VFLTX (Vector Convert to Floating Pointer)
1297 defm VCVTDL : RVF1m<"vcvt.d.l", 0xb8, V64, VM>;
1299 // Section 8.13.18 - VCVS (Vector Convert to Single-format)
1300 defm VCVTSD : RVF1m<"vcvt.s.d", 0x9f, V64, VM>;
1302 // Section 8.13.19 - VCVD (Vector Convert to Double-format)
1303 defm VCVTDS : RVF1m<"vcvt.d.s", 0x8f, V64, VM>;
1305 //-----------------------------------------------------------------------------
1306 // Section 8.14 - Vector Reduction Instructions
1307 //-----------------------------------------------------------------------------
1309 // Section 8.14.1 - VSUMS (Vector Sum Single)
1310 defm VSUMWSX : RVF1m<"vsum.w.sx", 0xea, V64, VM>;
1311 let cx2 = 1 in defm VSUMWZX : RVF1m<"vsum.w.zx", 0xea, V64, VM>;
1313 // Section 8.14.2 - VSUMX (Vector Sum)
1314 defm VSUML : RVF1m<"vsum.l", 0xaa, V64, VM>;
1316 // Section 8.14.3 - VFSUM (Vector Floating Sum)
1317 defm VFSUMD : RVF1m<"vfsum.d", 0xec, V64, VM>;
1318 let cx = 1 in defm VFSUMS : RVF1m<"vfsum.s", 0xec, V64, VM>;
1320 // Section 8.14.4 - VMAXS (Vector Maximum/Minimum Single)
1321 let cx2 = 0 in defm VRMAXSWFSTSX : RVF1m<"vrmaxs.w.fst.sx", 0xbb, V64, VM>;
1322 let cx2 = 1 in defm VRMAXSWFSTZX : RVF1m<"vrmaxs.w.fst.zx", 0xbb, V64, VM>;
1323 let cs = 1 in {
1324 let cx2 = 0 in
1325 defm VRMAXSWLSTSX : RVF1m<"vrmaxs.w.lst.sx", 0xbb, V64, VM>;
1326 let cx2 = 1 in
1327 defm VRMAXSWLSTZX : RVF1m<"vrmaxs.w.lst.zx", 0xbb, V64, VM>;
1328 }
1329 let cs2 = 1 in {
1330 let cx2 = 0 in
1331 defm VRMINSWFSTSX : RVF1m<"vrmins.w.fst.sx", 0xbb, V64, VM>;
1332 let cx2 = 1 in
1333 defm VRMINSWFSTZX : RVF1m<"vrmins.w.fst.zx", 0xbb, V64, VM>;
1334 let cs = 1 in {
1335 let cx2 = 0 in
1336 defm VRMINSWLSTSX : RVF1m<"vrmins.w.lst.sx", 0xbb, V64, VM>;
1337 let cx2 = 1 in
1338 defm VRMINSWLSTZX : RVF1m<"vrmins.w.lst.zx", 0xbb, V64, VM>;
1339 }
1340 }
1342 // Section 8.14.5 - VMAXX (Vector Maximum/Minimum)
1343 let cs = 0 in defm VRMAXSLFST : RVF1m<"vrmaxs.l.fst", 0xab, V64, VM>;
1344 let cs = 1 in defm VRMAXSLLST : RVF1m<"vrmaxs.l.lst", 0xab, V64, VM>;
1345 let cs2 = 1 in {
1346 let cs = 0 in defm VRMINSLFST : RVF1m<"vrmins.l.fst", 0xab, V64, VM>;
1347 let cs = 1 in defm VRMINSLLST : RVF1m<"vrmins.l.lst", 0xab, V64, VM>;
1348 }
1350 // Section 8.14.6 - VFMAX (Vector Floating Maximum/Minimum)
1351 let cs = 0 in defm VFRMAXDFST : RVF1m<"vfrmax.d.fst", 0xad, V64, VM>;
1352 let cs = 1 in defm VFRMAXDLST : RVF1m<"vfrmax.d.lst", 0xad, V64, VM>;
1353 let cs2 = 1 in {
1354 let cs = 0 in defm VFRMINDFST : RVF1m<"vfrmin.d.fst", 0xad, V64, VM>;
1355 let cs = 1 in defm VFRMINDLST : RVF1m<"vfrmin.d.lst", 0xad, V64, VM>;
1356 }
1357 let cx = 1 in {
1358 let cs = 0 in defm VFRMAXSFST : RVF1m<"vfrmax.s.fst", 0xad, V64, VM>;
1359 let cs = 1 in defm VFRMAXSLST : RVF1m<"vfrmax.s.lst", 0xad, V64, VM>;
1360 let cs2 = 1 in {
1361 let cs = 0 in defm VFRMINSFST : RVF1m<"vfrmin.s.fst", 0xad, V64, VM>;
1362 let cs = 1 in defm VFRMINSLST : RVF1m<"vfrmin.s.lst", 0xad, V64, VM>;
1363 }
1364 }
1366 // Section 8.14.7 - VRAND (Vector Reduction And)
1367 defm VRAND : RVF1m<"vrand", 0x88, V64, VM>;
1369 // Section 8.14.8 - VROR (Vector Reduction Or)
1370 defm VROR : RVF1m<"vror", 0x98, V64, VM>;
1372 // Section 8.14.9 - VRXOR (Vector Reduction Exclusive Or)
1373 defm VRXOR : RVF1m<"vrxor", 0x89, V64, VM>;
1375 //-----------------------------------------------------------------------------
1376 // Section 8.15 - Vector Iterative Operation Instructions
1377 //-----------------------------------------------------------------------------
1379 // Section 8.15.1 - VFIA (Vector Floating Iteration Add)
1380 let cx = 0 in defm VFIAD : RVI2m<"vfia.d", 0xce, V64, I64>;
1381 let cx = 1 in defm VFIAS : RVI2m<"vfia.s", 0xce, V64, F32>;
1383 // Section 8.15.2 - VFIS (Vector Floating Iteration Subtract)
1384 let cx = 0 in defm VFISD : RVI2m<"vfis.d", 0xde, V64, I64>;
1385 let cx = 1 in defm VFISS : RVI2m<"vfis.s", 0xde, V64, F32>;
1387 // Section 8.15.3 - VFIM (Vector Floating Iteration Multiply)
1388 let cx = 0 in defm VFIMD : RVI2m<"vfim.d", 0xcf, V64, I64>;
1389 let cx = 1 in defm VFIMS : RVI2m<"vfim.s", 0xcf, V64, F32>;
1391 // Section 8.15.4 - VFIAM (Vector Floating Iteration Add and Multiply)
1392 let cx = 0 in defm VFIAMD : RVI3m<"vfiam.d", 0xee, V64, I64>;
1393 let cx = 1 in defm VFIAMS : RVI3m<"vfiam.s", 0xee, V64, F32>;
1395 // Section 8.15.5 - VFISM (Vector Floating Iteration Subtract and Multiply)
1396 let cx = 0 in defm VFISMD : RVI3m<"vfism.d", 0xfe, V64, I64>;
1397 let cx = 1 in defm VFISMS : RVI3m<"vfism.s", 0xfe, V64, F32>;
1399 // Section 8.15.6 - VFIMA (Vector Floating Iteration Multiply and Add)
1400 let cx = 0 in defm VFIMAD : RVI3m<"vfima.d", 0xef, V64, I64>;
1401 let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>;
1403 // Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract)
1404 let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>;
1405 let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>;
1407 //-----------------------------------------------------------------------------
1408 // Section 8.16 - Vector Merger Operation Instructions
1409 //-----------------------------------------------------------------------------
1411 // Section 8.16.1 - VMRG (Vector Merge)
1412 let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>;
1413 // FIXME: vmrg.w should be called as pvmrg, but following assembly manual.
1414 let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>;
1415 def : MnemonicAlias<"vmrg.l", "vmrg">;
1417 // Section 8.16.2 - VSHF (Vector Shuffle)
1418 defm VSHF : RVSHFm<"vshf", 0xbc, V64>;
1420 // Section 8.16.3 - VCP (Vector Compress)
1421 defm VCP : RV1m<"vcp", 0x8d, V64, VM>;
1423 // Section 8.16.4 - VEX (Vector Expand)
1424 defm VEX : RV1m<"vex", 0x9d, V64, VM>;
1426 //-----------------------------------------------------------------------------
1427 // Section 8.17 - Vector Mask Operation Instructions
1428 //-----------------------------------------------------------------------------
1430 // Section 8.17.1 - VFMK (Vector Form Mask)
1431 defm VFMKL : RVMKm<"vfmk.l.", 0xb4, V64, VM>;
1432 def : MnemonicAlias<"vfmk.l", "vfmk.l.at">;
1434 // Section 8.17.2 - VFMS (Vector Form Mask Single)
1435 defm VFMKW : RVMKm<"vfmk.w.", 0xb5, V64, VM>;
1436 let isCodeGenOnly = 1 in defm PVFMKWLO : RVMKm<"vfmk.w.", 0xb5, V64, VM>;
1437 let cx = 1 in defm PVFMKWUP : RVMKm<"pvfmk.w.up.", 0xb5, V64, VM>;
1438 def : MnemonicAlias<"vfmk.w", "vfmk.w.at">;
1439 def : MnemonicAlias<"pvfmk.w.up", "pvfmk.w.up.at">;
1440 def : MnemonicAlias<"pvfmk.w.lo", "vfmk.w.at">;
1441 foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at" ] in {
1442 def : MnemonicAlias<"pvfmk.w.lo."#CC, "vfmk.w."#CC>;
1443 }
1445 // Section 8.17.3 - VFMF (Vector Form Mask Floating Point)
1446 defm VFMKD : RVMKm<"vfmk.d.", 0xb6, V64, VM>;
1447 let cx2 = 1 in defm PVFMKSLO : RVMKm<"pvfmk.s.lo.", 0xb6, V64, VM>;
1448 let cx = 1 in {
1449 defm PVFMKSUP : RVMKm<"pvfmk.s.up.", 0xb6, V64, VM>;
1450 let isCodeGenOnly = 1 in defm VFMKS : RVMKm<"vfmk.s.", 0xb6, V64, VM>;
1451 }
1452 def : MnemonicAlias<"vfmk.d", "vfmk.d.at">;
1453 def : MnemonicAlias<"pvfmk.s.lo", "pvfmk.s.lo.at">;
1454 def : MnemonicAlias<"pvfmk.s.up", "pvfmk.s.up.at">;
1455 def : MnemonicAlias<"vfmk.s", "pvfmk.s.up.at">;
1456 foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at", "num", "nan",
1457 "gtnan", "ltnan", "nenan", "eqnan", "genan", "lenan" ] in {
1458 def : MnemonicAlias<"vfmk.s."#CC, "pvfmk.s.up."#CC>;
1459 }
1461 // Section 8.17.4 - ANDM (And VM)
1462 defm ANDM : RVM2m<"andm", 0x84, VM>;
1464 // Section 8.17.5 - ORM (Or VM)
1465 defm ORM : RVM2m<"orm", 0x85, VM>;
1467 // Section 8.17.6 - XORM (Exclusive Or VM)
1468 defm XORM : RVM2m<"xorm", 0x86, VM>;
1470 // Section 8.17.7 - EQVM (Equivalence VM)
1471 defm EQVM : RVM2m<"eqvm", 0x87, VM>;
1473 // Section 8.17.8 - NNDM (Negate And VM)
1474 defm NNDM : RVM2m<"nndm", 0x94, VM>;
1476 // Section 8.17.9 - NEGM (Negate VM)
1477 defm NEGM : RVM1m<"negm", 0x95, VM>;
1479 // Section 8.17.10 - PCVM (Population Count of VM)
1480 defm PCVM : RVMSm<"pcvm", 0xa4, VM>;
1482 // Section 8.17.11 - LZVM (Leading Zero of VM)
1483 defm LZVM : RVMSm<"lzvm", 0xa5, VM>;
1485 // Section 8.17.12 - TOVM (Trailing One of VM)
1486 defm TOVM : RVMSm<"tovm", 0xa6, VM>;
1488 //-----------------------------------------------------------------------------
1489 // Section 8.18 - Vector Control Instructions
1490 //-----------------------------------------------------------------------------
1492 // Section 8.18.1 - LVL (Load VL)
1493 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VL] in {
1494 def LVLr : RR<0xbf, (outs), (ins I64:$sy), "lvl $sy">;
1495 let cy = 0 in def LVLi : RR<0xbf, (outs), (ins simm7:$sy), "lvl $sy">;
1496 }
1498 // Section 8.18.2 - SVL (Save VL)
1499 let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0, Uses = [VL] in
1500 def SVL : RR<0x2f, (outs I64:$sx), (ins), "svl $sx">;
1502 // Section 8.18.3 - SMVL (Save Maximum Vector Length)
1503 let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
1504 def SMVL : RR<0x2e, (outs I64:$sx), (ins), "smvl $sx">;
1506 // Section 8.18.4 - LVIX (Load Vector Data Index)
1507 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VIX] in {
1508 def LVIXr : RR<0xaf, (outs), (ins I64:$sy), "lvix $sy">;
1509 let cy = 0 in def LVIXi : RR<0xaf, (outs), (ins uimm6:$sy), "lvix $sy">;
1510 }